falcon.c 78 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2006-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/bitops.h>
  11. #include <linux/delay.h>
  12. #include <linux/pci.h>
  13. #include <linux/module.h>
  14. #include <linux/seq_file.h>
  15. #include "net_driver.h"
  16. #include "bitfield.h"
  17. #include "efx.h"
  18. #include "mac.h"
  19. #include "gmii.h"
  20. #include "spi.h"
  21. #include "falcon.h"
  22. #include "falcon_hwdefs.h"
  23. #include "falcon_io.h"
  24. #include "mdio_10g.h"
  25. #include "phy.h"
  26. #include "boards.h"
  27. #include "workarounds.h"
  28. /* Falcon hardware control.
  29. * Falcon is the internal codename for the SFC4000 controller that is
  30. * present in SFE400X evaluation boards
  31. */
  32. /**
  33. * struct falcon_nic_data - Falcon NIC state
  34. * @next_buffer_table: First available buffer table id
  35. * @pci_dev2: The secondary PCI device if present
  36. */
  37. struct falcon_nic_data {
  38. unsigned next_buffer_table;
  39. struct pci_dev *pci_dev2;
  40. };
  41. /**************************************************************************
  42. *
  43. * Configurable values
  44. *
  45. **************************************************************************
  46. */
  47. static int disable_dma_stats;
  48. /* This is set to 16 for a good reason. In summary, if larger than
  49. * 16, the descriptor cache holds more than a default socket
  50. * buffer's worth of packets (for UDP we can only have at most one
  51. * socket buffer's worth outstanding). This combined with the fact
  52. * that we only get 1 TX event per descriptor cache means the NIC
  53. * goes idle.
  54. */
  55. #define TX_DC_ENTRIES 16
  56. #define TX_DC_ENTRIES_ORDER 0
  57. #define TX_DC_BASE 0x130000
  58. #define RX_DC_ENTRIES 64
  59. #define RX_DC_ENTRIES_ORDER 2
  60. #define RX_DC_BASE 0x100000
  61. /* RX FIFO XOFF watermark
  62. *
  63. * When the amount of the RX FIFO increases used increases past this
  64. * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
  65. * This also has an effect on RX/TX arbitration
  66. */
  67. static int rx_xoff_thresh_bytes = -1;
  68. module_param(rx_xoff_thresh_bytes, int, 0644);
  69. MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
  70. /* RX FIFO XON watermark
  71. *
  72. * When the amount of the RX FIFO used decreases below this
  73. * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
  74. * This also has an effect on RX/TX arbitration
  75. */
  76. static int rx_xon_thresh_bytes = -1;
  77. module_param(rx_xon_thresh_bytes, int, 0644);
  78. MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
  79. /* TX descriptor ring size - min 512 max 4k */
  80. #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
  81. #define FALCON_TXD_RING_SIZE 1024
  82. #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
  83. /* RX descriptor ring size - min 512 max 4k */
  84. #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
  85. #define FALCON_RXD_RING_SIZE 1024
  86. #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
  87. /* Event queue size - max 32k */
  88. #define FALCON_EVQ_ORDER EVQ_SIZE_4K
  89. #define FALCON_EVQ_SIZE 4096
  90. #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
  91. /* Max number of internal errors. After this resets will not be performed */
  92. #define FALCON_MAX_INT_ERRORS 4
  93. /* Maximum period that we wait for flush events. If the flush event
  94. * doesn't arrive in this period of time then we check if the queue
  95. * was disabled anyway. */
  96. #define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
  97. /**************************************************************************
  98. *
  99. * Falcon constants
  100. *
  101. **************************************************************************
  102. */
  103. /* DMA address mask (up to 46-bit, avoiding compiler warnings)
  104. *
  105. * Note that it is possible to have a platform with 64-bit longs and
  106. * 32-bit DMA addresses, or vice versa. EFX_DMA_MASK takes care of the
  107. * platform DMA mask.
  108. */
  109. #if BITS_PER_LONG == 64
  110. #define FALCON_DMA_MASK EFX_DMA_MASK(0x00003fffffffffffUL)
  111. #else
  112. #define FALCON_DMA_MASK EFX_DMA_MASK(0x00003fffffffffffULL)
  113. #endif
  114. /* TX DMA length mask (13-bit) */
  115. #define FALCON_TX_DMA_MASK (4096 - 1)
  116. /* Size and alignment of special buffers (4KB) */
  117. #define FALCON_BUF_SIZE 4096
  118. /* Dummy SRAM size code */
  119. #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
  120. /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
  121. #define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
  122. #define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
  123. #define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
  124. #define PCI_EXP_LNKSTA_LNK_WID 0x3f0
  125. #define PCI_EXP_LNKSTA_LNK_WID_LBN 4
  126. #define FALCON_IS_DUAL_FUNC(efx) \
  127. (FALCON_REV(efx) < FALCON_REV_B0)
  128. /**************************************************************************
  129. *
  130. * Falcon hardware access
  131. *
  132. **************************************************************************/
  133. /* Read the current event from the event queue */
  134. static inline efx_qword_t *falcon_event(struct efx_channel *channel,
  135. unsigned int index)
  136. {
  137. return (((efx_qword_t *) (channel->eventq.addr)) + index);
  138. }
  139. /* See if an event is present
  140. *
  141. * We check both the high and low dword of the event for all ones. We
  142. * wrote all ones when we cleared the event, and no valid event can
  143. * have all ones in either its high or low dwords. This approach is
  144. * robust against reordering.
  145. *
  146. * Note that using a single 64-bit comparison is incorrect; even
  147. * though the CPU read will be atomic, the DMA write may not be.
  148. */
  149. static inline int falcon_event_present(efx_qword_t *event)
  150. {
  151. return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
  152. EFX_DWORD_IS_ALL_ONES(event->dword[1])));
  153. }
  154. /**************************************************************************
  155. *
  156. * I2C bus - this is a bit-bashing interface using GPIO pins
  157. * Note that it uses the output enables to tristate the outputs
  158. * SDA is the data pin and SCL is the clock
  159. *
  160. **************************************************************************
  161. */
  162. static void falcon_setsdascl(struct efx_i2c_interface *i2c)
  163. {
  164. efx_oword_t reg;
  165. falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
  166. EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, (i2c->scl ? 0 : 1));
  167. EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, (i2c->sda ? 0 : 1));
  168. falcon_write(i2c->efx, &reg, GPIO_CTL_REG_KER);
  169. }
  170. static int falcon_getsda(struct efx_i2c_interface *i2c)
  171. {
  172. efx_oword_t reg;
  173. falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
  174. return EFX_OWORD_FIELD(reg, GPIO3_IN);
  175. }
  176. static int falcon_getscl(struct efx_i2c_interface *i2c)
  177. {
  178. efx_oword_t reg;
  179. falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
  180. return EFX_DWORD_FIELD(reg, GPIO0_IN);
  181. }
  182. static struct efx_i2c_bit_operations falcon_i2c_bit_operations = {
  183. .setsda = falcon_setsdascl,
  184. .setscl = falcon_setsdascl,
  185. .getsda = falcon_getsda,
  186. .getscl = falcon_getscl,
  187. .udelay = 100,
  188. .mdelay = 10,
  189. };
  190. /**************************************************************************
  191. *
  192. * Falcon special buffer handling
  193. * Special buffers are used for event queues and the TX and RX
  194. * descriptor rings.
  195. *
  196. *************************************************************************/
  197. /*
  198. * Initialise a Falcon special buffer
  199. *
  200. * This will define a buffer (previously allocated via
  201. * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
  202. * it to be used for event queues, descriptor rings etc.
  203. */
  204. static int
  205. falcon_init_special_buffer(struct efx_nic *efx,
  206. struct efx_special_buffer *buffer)
  207. {
  208. efx_qword_t buf_desc;
  209. int index;
  210. dma_addr_t dma_addr;
  211. int i;
  212. EFX_BUG_ON_PARANOID(!buffer->addr);
  213. /* Write buffer descriptors to NIC */
  214. for (i = 0; i < buffer->entries; i++) {
  215. index = buffer->index + i;
  216. dma_addr = buffer->dma_addr + (i * 4096);
  217. EFX_LOG(efx, "mapping special buffer %d at %llx\n",
  218. index, (unsigned long long)dma_addr);
  219. EFX_POPULATE_QWORD_4(buf_desc,
  220. IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
  221. BUF_ADR_REGION, 0,
  222. BUF_ADR_FBUF, (dma_addr >> 12),
  223. BUF_OWNER_ID_FBUF, 0);
  224. falcon_write_sram(efx, &buf_desc, index);
  225. }
  226. return 0;
  227. }
  228. /* Unmaps a buffer from Falcon and clears the buffer table entries */
  229. static void
  230. falcon_fini_special_buffer(struct efx_nic *efx,
  231. struct efx_special_buffer *buffer)
  232. {
  233. efx_oword_t buf_tbl_upd;
  234. unsigned int start = buffer->index;
  235. unsigned int end = (buffer->index + buffer->entries - 1);
  236. if (!buffer->entries)
  237. return;
  238. EFX_LOG(efx, "unmapping special buffers %d-%d\n",
  239. buffer->index, buffer->index + buffer->entries - 1);
  240. EFX_POPULATE_OWORD_4(buf_tbl_upd,
  241. BUF_UPD_CMD, 0,
  242. BUF_CLR_CMD, 1,
  243. BUF_CLR_END_ID, end,
  244. BUF_CLR_START_ID, start);
  245. falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
  246. }
  247. /*
  248. * Allocate a new Falcon special buffer
  249. *
  250. * This allocates memory for a new buffer, clears it and allocates a
  251. * new buffer ID range. It does not write into Falcon's buffer table.
  252. *
  253. * This call will allocate 4KB buffers, since Falcon can't use 8KB
  254. * buffers for event queues and descriptor rings.
  255. */
  256. static int falcon_alloc_special_buffer(struct efx_nic *efx,
  257. struct efx_special_buffer *buffer,
  258. unsigned int len)
  259. {
  260. struct falcon_nic_data *nic_data = efx->nic_data;
  261. len = ALIGN(len, FALCON_BUF_SIZE);
  262. buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
  263. &buffer->dma_addr);
  264. if (!buffer->addr)
  265. return -ENOMEM;
  266. buffer->len = len;
  267. buffer->entries = len / FALCON_BUF_SIZE;
  268. BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
  269. /* All zeros is a potentially valid event so memset to 0xff */
  270. memset(buffer->addr, 0xff, len);
  271. /* Select new buffer ID */
  272. buffer->index = nic_data->next_buffer_table;
  273. nic_data->next_buffer_table += buffer->entries;
  274. EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
  275. "(virt %p phys %lx)\n", buffer->index,
  276. buffer->index + buffer->entries - 1,
  277. (unsigned long long)buffer->dma_addr, len,
  278. buffer->addr, virt_to_phys(buffer->addr));
  279. return 0;
  280. }
  281. static void falcon_free_special_buffer(struct efx_nic *efx,
  282. struct efx_special_buffer *buffer)
  283. {
  284. if (!buffer->addr)
  285. return;
  286. EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
  287. "(virt %p phys %lx)\n", buffer->index,
  288. buffer->index + buffer->entries - 1,
  289. (unsigned long long)buffer->dma_addr, buffer->len,
  290. buffer->addr, virt_to_phys(buffer->addr));
  291. pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
  292. buffer->dma_addr);
  293. buffer->addr = NULL;
  294. buffer->entries = 0;
  295. }
  296. /**************************************************************************
  297. *
  298. * Falcon generic buffer handling
  299. * These buffers are used for interrupt status and MAC stats
  300. *
  301. **************************************************************************/
  302. static int falcon_alloc_buffer(struct efx_nic *efx,
  303. struct efx_buffer *buffer, unsigned int len)
  304. {
  305. buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
  306. &buffer->dma_addr);
  307. if (!buffer->addr)
  308. return -ENOMEM;
  309. buffer->len = len;
  310. memset(buffer->addr, 0, len);
  311. return 0;
  312. }
  313. static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
  314. {
  315. if (buffer->addr) {
  316. pci_free_consistent(efx->pci_dev, buffer->len,
  317. buffer->addr, buffer->dma_addr);
  318. buffer->addr = NULL;
  319. }
  320. }
  321. /**************************************************************************
  322. *
  323. * Falcon TX path
  324. *
  325. **************************************************************************/
  326. /* Returns a pointer to the specified transmit descriptor in the TX
  327. * descriptor queue belonging to the specified channel.
  328. */
  329. static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
  330. unsigned int index)
  331. {
  332. return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
  333. }
  334. /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
  335. static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
  336. {
  337. unsigned write_ptr;
  338. efx_dword_t reg;
  339. write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
  340. EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
  341. falcon_writel_page(tx_queue->efx, &reg,
  342. TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
  343. }
  344. /* For each entry inserted into the software descriptor ring, create a
  345. * descriptor in the hardware TX descriptor ring (in host memory), and
  346. * write a doorbell.
  347. */
  348. void falcon_push_buffers(struct efx_tx_queue *tx_queue)
  349. {
  350. struct efx_tx_buffer *buffer;
  351. efx_qword_t *txd;
  352. unsigned write_ptr;
  353. BUG_ON(tx_queue->write_count == tx_queue->insert_count);
  354. do {
  355. write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
  356. buffer = &tx_queue->buffer[write_ptr];
  357. txd = falcon_tx_desc(tx_queue, write_ptr);
  358. ++tx_queue->write_count;
  359. /* Create TX descriptor ring entry */
  360. EFX_POPULATE_QWORD_5(*txd,
  361. TX_KER_PORT, 0,
  362. TX_KER_CONT, buffer->continuation,
  363. TX_KER_BYTE_CNT, buffer->len,
  364. TX_KER_BUF_REGION, 0,
  365. TX_KER_BUF_ADR, buffer->dma_addr);
  366. } while (tx_queue->write_count != tx_queue->insert_count);
  367. wmb(); /* Ensure descriptors are written before they are fetched */
  368. falcon_notify_tx_desc(tx_queue);
  369. }
  370. /* Allocate hardware resources for a TX queue */
  371. int falcon_probe_tx(struct efx_tx_queue *tx_queue)
  372. {
  373. struct efx_nic *efx = tx_queue->efx;
  374. return falcon_alloc_special_buffer(efx, &tx_queue->txd,
  375. FALCON_TXD_RING_SIZE *
  376. sizeof(efx_qword_t));
  377. }
  378. int falcon_init_tx(struct efx_tx_queue *tx_queue)
  379. {
  380. efx_oword_t tx_desc_ptr;
  381. struct efx_nic *efx = tx_queue->efx;
  382. int rc;
  383. /* Pin TX descriptor ring */
  384. rc = falcon_init_special_buffer(efx, &tx_queue->txd);
  385. if (rc)
  386. return rc;
  387. /* Push TX descriptor ring to card */
  388. EFX_POPULATE_OWORD_10(tx_desc_ptr,
  389. TX_DESCQ_EN, 1,
  390. TX_ISCSI_DDIG_EN, 0,
  391. TX_ISCSI_HDIG_EN, 0,
  392. TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
  393. TX_DESCQ_EVQ_ID, tx_queue->channel->evqnum,
  394. TX_DESCQ_OWNER_ID, 0,
  395. TX_DESCQ_LABEL, tx_queue->queue,
  396. TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
  397. TX_DESCQ_TYPE, 0,
  398. TX_NON_IP_DROP_DIS_B0, 1);
  399. if (FALCON_REV(efx) >= FALCON_REV_B0) {
  400. int csum = !(efx->net_dev->features & NETIF_F_IP_CSUM);
  401. EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, csum);
  402. EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, csum);
  403. }
  404. falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
  405. tx_queue->queue);
  406. if (FALCON_REV(efx) < FALCON_REV_B0) {
  407. efx_oword_t reg;
  408. BUG_ON(tx_queue->queue >= 128); /* HW limit */
  409. falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
  410. if (efx->net_dev->features & NETIF_F_IP_CSUM)
  411. clear_bit_le(tx_queue->queue, (void *)&reg);
  412. else
  413. set_bit_le(tx_queue->queue, (void *)&reg);
  414. falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
  415. }
  416. return 0;
  417. }
  418. static int falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
  419. {
  420. struct efx_nic *efx = tx_queue->efx;
  421. struct efx_channel *channel = &efx->channel[0];
  422. efx_oword_t tx_flush_descq;
  423. unsigned int read_ptr, i;
  424. /* Post a flush command */
  425. EFX_POPULATE_OWORD_2(tx_flush_descq,
  426. TX_FLUSH_DESCQ_CMD, 1,
  427. TX_FLUSH_DESCQ, tx_queue->queue);
  428. falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
  429. msleep(FALCON_FLUSH_TIMEOUT);
  430. if (EFX_WORKAROUND_7803(efx))
  431. return 0;
  432. /* Look for a flush completed event */
  433. read_ptr = channel->eventq_read_ptr;
  434. for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
  435. efx_qword_t *event = falcon_event(channel, read_ptr);
  436. int ev_code, ev_sub_code, ev_queue;
  437. if (!falcon_event_present(event))
  438. break;
  439. ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
  440. ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
  441. ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_TX_DESCQ_ID);
  442. if ((ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) &&
  443. (ev_queue == tx_queue->queue)) {
  444. EFX_LOG(efx, "tx queue %d flush command succesful\n",
  445. tx_queue->queue);
  446. return 0;
  447. }
  448. read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
  449. }
  450. if (EFX_WORKAROUND_11557(efx)) {
  451. efx_oword_t reg;
  452. int enabled;
  453. falcon_read_table(efx, &reg, efx->type->txd_ptr_tbl_base,
  454. tx_queue->queue);
  455. enabled = EFX_OWORD_FIELD(reg, TX_DESCQ_EN);
  456. if (!enabled) {
  457. EFX_LOG(efx, "tx queue %d disabled without a "
  458. "flush event seen\n", tx_queue->queue);
  459. return 0;
  460. }
  461. }
  462. EFX_ERR(efx, "tx queue %d flush command timed out\n", tx_queue->queue);
  463. return -ETIMEDOUT;
  464. }
  465. void falcon_fini_tx(struct efx_tx_queue *tx_queue)
  466. {
  467. struct efx_nic *efx = tx_queue->efx;
  468. efx_oword_t tx_desc_ptr;
  469. /* Stop the hardware using the queue */
  470. if (falcon_flush_tx_queue(tx_queue))
  471. EFX_ERR(efx, "failed to flush tx queue %d\n", tx_queue->queue);
  472. /* Remove TX descriptor ring from card */
  473. EFX_ZERO_OWORD(tx_desc_ptr);
  474. falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
  475. tx_queue->queue);
  476. /* Unpin TX descriptor ring */
  477. falcon_fini_special_buffer(efx, &tx_queue->txd);
  478. }
  479. /* Free buffers backing TX queue */
  480. void falcon_remove_tx(struct efx_tx_queue *tx_queue)
  481. {
  482. falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
  483. }
  484. /**************************************************************************
  485. *
  486. * Falcon RX path
  487. *
  488. **************************************************************************/
  489. /* Returns a pointer to the specified descriptor in the RX descriptor queue */
  490. static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
  491. unsigned int index)
  492. {
  493. return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
  494. }
  495. /* This creates an entry in the RX descriptor queue */
  496. static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
  497. unsigned index)
  498. {
  499. struct efx_rx_buffer *rx_buf;
  500. efx_qword_t *rxd;
  501. rxd = falcon_rx_desc(rx_queue, index);
  502. rx_buf = efx_rx_buffer(rx_queue, index);
  503. EFX_POPULATE_QWORD_3(*rxd,
  504. RX_KER_BUF_SIZE,
  505. rx_buf->len -
  506. rx_queue->efx->type->rx_buffer_padding,
  507. RX_KER_BUF_REGION, 0,
  508. RX_KER_BUF_ADR, rx_buf->dma_addr);
  509. }
  510. /* This writes to the RX_DESC_WPTR register for the specified receive
  511. * descriptor ring.
  512. */
  513. void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
  514. {
  515. efx_dword_t reg;
  516. unsigned write_ptr;
  517. while (rx_queue->notified_count != rx_queue->added_count) {
  518. falcon_build_rx_desc(rx_queue,
  519. rx_queue->notified_count &
  520. FALCON_RXD_RING_MASK);
  521. ++rx_queue->notified_count;
  522. }
  523. wmb();
  524. write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
  525. EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
  526. falcon_writel_page(rx_queue->efx, &reg,
  527. RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
  528. }
  529. int falcon_probe_rx(struct efx_rx_queue *rx_queue)
  530. {
  531. struct efx_nic *efx = rx_queue->efx;
  532. return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
  533. FALCON_RXD_RING_SIZE *
  534. sizeof(efx_qword_t));
  535. }
  536. int falcon_init_rx(struct efx_rx_queue *rx_queue)
  537. {
  538. efx_oword_t rx_desc_ptr;
  539. struct efx_nic *efx = rx_queue->efx;
  540. int rc;
  541. int is_b0 = FALCON_REV(efx) >= FALCON_REV_B0;
  542. int iscsi_digest_en = is_b0;
  543. EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
  544. rx_queue->queue, rx_queue->rxd.index,
  545. rx_queue->rxd.index + rx_queue->rxd.entries - 1);
  546. /* Pin RX descriptor ring */
  547. rc = falcon_init_special_buffer(efx, &rx_queue->rxd);
  548. if (rc)
  549. return rc;
  550. /* Push RX descriptor ring to card */
  551. EFX_POPULATE_OWORD_10(rx_desc_ptr,
  552. RX_ISCSI_DDIG_EN, iscsi_digest_en,
  553. RX_ISCSI_HDIG_EN, iscsi_digest_en,
  554. RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
  555. RX_DESCQ_EVQ_ID, rx_queue->channel->evqnum,
  556. RX_DESCQ_OWNER_ID, 0,
  557. RX_DESCQ_LABEL, rx_queue->queue,
  558. RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
  559. RX_DESCQ_TYPE, 0 /* kernel queue */ ,
  560. /* For >=B0 this is scatter so disable */
  561. RX_DESCQ_JUMBO, !is_b0,
  562. RX_DESCQ_EN, 1);
  563. falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
  564. rx_queue->queue);
  565. return 0;
  566. }
  567. static int falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
  568. {
  569. struct efx_nic *efx = rx_queue->efx;
  570. struct efx_channel *channel = &efx->channel[0];
  571. unsigned int read_ptr, i;
  572. efx_oword_t rx_flush_descq;
  573. /* Post a flush command */
  574. EFX_POPULATE_OWORD_2(rx_flush_descq,
  575. RX_FLUSH_DESCQ_CMD, 1,
  576. RX_FLUSH_DESCQ, rx_queue->queue);
  577. falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
  578. msleep(FALCON_FLUSH_TIMEOUT);
  579. if (EFX_WORKAROUND_7803(efx))
  580. return 0;
  581. /* Look for a flush completed event */
  582. read_ptr = channel->eventq_read_ptr;
  583. for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
  584. efx_qword_t *event = falcon_event(channel, read_ptr);
  585. int ev_code, ev_sub_code, ev_queue, ev_failed;
  586. if (!falcon_event_present(event))
  587. break;
  588. ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
  589. ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
  590. ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_DESCQ_ID);
  591. ev_failed = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_FLUSH_FAIL);
  592. if ((ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) &&
  593. (ev_queue == rx_queue->queue)) {
  594. if (ev_failed) {
  595. EFX_INFO(efx, "rx queue %d flush command "
  596. "failed\n", rx_queue->queue);
  597. return -EAGAIN;
  598. } else {
  599. EFX_LOG(efx, "rx queue %d flush command "
  600. "succesful\n", rx_queue->queue);
  601. return 0;
  602. }
  603. }
  604. read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
  605. }
  606. if (EFX_WORKAROUND_11557(efx)) {
  607. efx_oword_t reg;
  608. int enabled;
  609. falcon_read_table(efx, &reg, efx->type->rxd_ptr_tbl_base,
  610. rx_queue->queue);
  611. enabled = EFX_OWORD_FIELD(reg, RX_DESCQ_EN);
  612. if (!enabled) {
  613. EFX_LOG(efx, "rx queue %d disabled without a "
  614. "flush event seen\n", rx_queue->queue);
  615. return 0;
  616. }
  617. }
  618. EFX_ERR(efx, "rx queue %d flush command timed out\n", rx_queue->queue);
  619. return -ETIMEDOUT;
  620. }
  621. void falcon_fini_rx(struct efx_rx_queue *rx_queue)
  622. {
  623. efx_oword_t rx_desc_ptr;
  624. struct efx_nic *efx = rx_queue->efx;
  625. int i, rc;
  626. /* Try and flush the rx queue. This may need to be repeated */
  627. for (i = 0; i < 5; i++) {
  628. rc = falcon_flush_rx_queue(rx_queue);
  629. if (rc == -EAGAIN)
  630. continue;
  631. break;
  632. }
  633. if (rc)
  634. EFX_ERR(efx, "failed to flush rx queue %d\n", rx_queue->queue);
  635. /* Remove RX descriptor ring from card */
  636. EFX_ZERO_OWORD(rx_desc_ptr);
  637. falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
  638. rx_queue->queue);
  639. /* Unpin RX descriptor ring */
  640. falcon_fini_special_buffer(efx, &rx_queue->rxd);
  641. }
  642. /* Free buffers backing RX queue */
  643. void falcon_remove_rx(struct efx_rx_queue *rx_queue)
  644. {
  645. falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
  646. }
  647. /**************************************************************************
  648. *
  649. * Falcon event queue processing
  650. * Event queues are processed by per-channel tasklets.
  651. *
  652. **************************************************************************/
  653. /* Update a channel's event queue's read pointer (RPTR) register
  654. *
  655. * This writes the EVQ_RPTR_REG register for the specified channel's
  656. * event queue.
  657. *
  658. * Note that EVQ_RPTR_REG contains the index of the "last read" event,
  659. * whereas channel->eventq_read_ptr contains the index of the "next to
  660. * read" event.
  661. */
  662. void falcon_eventq_read_ack(struct efx_channel *channel)
  663. {
  664. efx_dword_t reg;
  665. struct efx_nic *efx = channel->efx;
  666. EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
  667. falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
  668. channel->evqnum);
  669. }
  670. /* Use HW to insert a SW defined event */
  671. void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
  672. {
  673. efx_oword_t drv_ev_reg;
  674. EFX_POPULATE_OWORD_2(drv_ev_reg,
  675. DRV_EV_QID, channel->evqnum,
  676. DRV_EV_DATA,
  677. EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
  678. falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
  679. }
  680. /* Handle a transmit completion event
  681. *
  682. * Falcon batches TX completion events; the message we receive is of
  683. * the form "complete all TX events up to this index".
  684. */
  685. static inline void falcon_handle_tx_event(struct efx_channel *channel,
  686. efx_qword_t *event)
  687. {
  688. unsigned int tx_ev_desc_ptr;
  689. unsigned int tx_ev_q_label;
  690. struct efx_tx_queue *tx_queue;
  691. struct efx_nic *efx = channel->efx;
  692. if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
  693. /* Transmit completion */
  694. tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
  695. tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
  696. tx_queue = &efx->tx_queue[tx_ev_q_label];
  697. efx_xmit_done(tx_queue, tx_ev_desc_ptr);
  698. } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
  699. /* Rewrite the FIFO write pointer */
  700. tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
  701. tx_queue = &efx->tx_queue[tx_ev_q_label];
  702. if (NET_DEV_REGISTERED(efx))
  703. netif_tx_lock(efx->net_dev);
  704. falcon_notify_tx_desc(tx_queue);
  705. if (NET_DEV_REGISTERED(efx))
  706. netif_tx_unlock(efx->net_dev);
  707. } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
  708. EFX_WORKAROUND_10727(efx)) {
  709. efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
  710. } else {
  711. EFX_ERR(efx, "channel %d unexpected TX event "
  712. EFX_QWORD_FMT"\n", channel->channel,
  713. EFX_QWORD_VAL(*event));
  714. }
  715. }
  716. /* Check received packet's destination MAC address. */
  717. static int check_dest_mac(struct efx_rx_queue *rx_queue,
  718. const efx_qword_t *event)
  719. {
  720. struct efx_rx_buffer *rx_buf;
  721. struct efx_nic *efx = rx_queue->efx;
  722. int rx_ev_desc_ptr;
  723. struct ethhdr *eh;
  724. if (efx->promiscuous)
  725. return 1;
  726. rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
  727. rx_buf = efx_rx_buffer(rx_queue, rx_ev_desc_ptr);
  728. eh = (struct ethhdr *)rx_buf->data;
  729. if (memcmp(eh->h_dest, efx->net_dev->dev_addr, ETH_ALEN))
  730. return 0;
  731. return 1;
  732. }
  733. /* Detect errors included in the rx_evt_pkt_ok bit. */
  734. static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
  735. const efx_qword_t *event,
  736. unsigned *rx_ev_pkt_ok,
  737. int *discard, int byte_count)
  738. {
  739. struct efx_nic *efx = rx_queue->efx;
  740. unsigned rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
  741. unsigned rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
  742. unsigned rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
  743. unsigned rx_ev_pkt_type, rx_ev_other_err, rx_ev_pause_frm;
  744. unsigned rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
  745. int snap, non_ip;
  746. rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
  747. rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
  748. rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
  749. rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
  750. rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
  751. RX_EV_BUF_OWNER_ID_ERR);
  752. rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
  753. rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
  754. RX_EV_IP_HDR_CHKSUM_ERR);
  755. rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
  756. RX_EV_TCP_UDP_CHKSUM_ERR);
  757. rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
  758. rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
  759. rx_ev_drib_nib = ((FALCON_REV(efx) >= FALCON_REV_B0) ?
  760. 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
  761. rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
  762. /* Every error apart from tobe_disc and pause_frm */
  763. rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
  764. rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
  765. rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
  766. snap = (rx_ev_pkt_type == RX_EV_PKT_TYPE_LLC_DECODE) ||
  767. (rx_ev_pkt_type == RX_EV_PKT_TYPE_VLAN_LLC_DECODE);
  768. non_ip = (rx_ev_hdr_type == RX_EV_HDR_TYPE_NON_IP_DECODE);
  769. /* SFC bug 5475/8970: The Falcon XMAC incorrectly calculates the
  770. * length field of an LLC frame, which sets TOBE_DISC. We could set
  771. * PASS_LEN_ERR, but we want the MAC to filter out short frames (to
  772. * protect the RX block).
  773. *
  774. * bug5475 - LLC/SNAP: Falcon identifies SNAP packets.
  775. * bug8970 - LLC/noSNAP: Falcon does not provide an LLC flag.
  776. * LLC can't encapsulate IP, so by definition
  777. * these packets are NON_IP.
  778. *
  779. * Unicast mismatch will also cause TOBE_DISC, so the driver needs
  780. * to check this.
  781. */
  782. if (EFX_WORKAROUND_5475(efx) && rx_ev_tobe_disc && (snap || non_ip)) {
  783. /* If all the other flags are zero then we can state the
  784. * entire packet is ok, which will flag to the kernel not
  785. * to recalculate checksums.
  786. */
  787. if (!(non_ip | rx_ev_other_err | rx_ev_pause_frm))
  788. *rx_ev_pkt_ok = 1;
  789. rx_ev_tobe_disc = 0;
  790. /* TOBE_DISC is set for unicast mismatch. But given that
  791. * we can't trust TOBE_DISC here, we must validate the dest
  792. * MAC address ourselves.
  793. */
  794. if (!rx_ev_mcast_pkt && !check_dest_mac(rx_queue, event))
  795. rx_ev_tobe_disc = 1;
  796. }
  797. /* Count errors that are not in MAC stats. */
  798. if (rx_ev_frm_trunc)
  799. ++rx_queue->channel->n_rx_frm_trunc;
  800. else if (rx_ev_tobe_disc)
  801. ++rx_queue->channel->n_rx_tobe_disc;
  802. else if (rx_ev_ip_hdr_chksum_err)
  803. ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
  804. else if (rx_ev_tcp_udp_chksum_err)
  805. ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
  806. if (rx_ev_ip_frag_err)
  807. ++rx_queue->channel->n_rx_ip_frag_err;
  808. /* The frame must be discarded if any of these are true. */
  809. *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
  810. rx_ev_tobe_disc | rx_ev_pause_frm);
  811. /* TOBE_DISC is expected on unicast mismatches; don't print out an
  812. * error message. FRM_TRUNC indicates RXDP dropped the packet due
  813. * to a FIFO overflow.
  814. */
  815. #ifdef EFX_ENABLE_DEBUG
  816. if (rx_ev_other_err) {
  817. EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
  818. EFX_QWORD_FMT "%s%s%s%s%s%s%s%s%s\n",
  819. rx_queue->queue, EFX_QWORD_VAL(*event),
  820. rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
  821. rx_ev_ip_hdr_chksum_err ?
  822. " [IP_HDR_CHKSUM_ERR]" : "",
  823. rx_ev_tcp_udp_chksum_err ?
  824. " [TCP_UDP_CHKSUM_ERR]" : "",
  825. rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
  826. rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
  827. rx_ev_drib_nib ? " [DRIB_NIB]" : "",
  828. rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
  829. rx_ev_pause_frm ? " [PAUSE]" : "",
  830. snap ? " [SNAP/LLC]" : "");
  831. }
  832. #endif
  833. if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
  834. efx->phy_type == PHY_TYPE_10XPRESS))
  835. tenxpress_crc_err(efx);
  836. }
  837. /* Handle receive events that are not in-order. */
  838. static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
  839. unsigned index)
  840. {
  841. struct efx_nic *efx = rx_queue->efx;
  842. unsigned expected, dropped;
  843. expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
  844. dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
  845. FALCON_RXD_RING_MASK);
  846. EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
  847. dropped, index, expected);
  848. efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
  849. RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
  850. }
  851. /* Handle a packet received event
  852. *
  853. * Falcon silicon gives a "discard" flag if it's a unicast packet with the
  854. * wrong destination address
  855. * Also "is multicast" and "matches multicast filter" flags can be used to
  856. * discard non-matching multicast packets.
  857. */
  858. static inline int falcon_handle_rx_event(struct efx_channel *channel,
  859. const efx_qword_t *event)
  860. {
  861. unsigned int rx_ev_q_label, rx_ev_desc_ptr, rx_ev_byte_cnt;
  862. unsigned int rx_ev_pkt_ok, rx_ev_hdr_type, rx_ev_mcast_pkt;
  863. unsigned expected_ptr;
  864. int discard = 0, checksummed;
  865. struct efx_rx_queue *rx_queue;
  866. struct efx_nic *efx = channel->efx;
  867. /* Basic packet information */
  868. rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
  869. rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
  870. rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
  871. WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
  872. WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
  873. rx_ev_q_label = EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL);
  874. rx_queue = &efx->rx_queue[rx_ev_q_label];
  875. rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
  876. expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
  877. if (unlikely(rx_ev_desc_ptr != expected_ptr)) {
  878. falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
  879. return rx_ev_q_label;
  880. }
  881. if (likely(rx_ev_pkt_ok)) {
  882. /* If packet is marked as OK and packet type is TCP/IPv4 or
  883. * UDP/IPv4, then we can rely on the hardware checksum.
  884. */
  885. checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
  886. } else {
  887. falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
  888. &discard, rx_ev_byte_cnt);
  889. checksummed = 0;
  890. }
  891. /* Detect multicast packets that didn't match the filter */
  892. rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
  893. if (rx_ev_mcast_pkt) {
  894. unsigned int rx_ev_mcast_hash_match =
  895. EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
  896. if (unlikely(!rx_ev_mcast_hash_match))
  897. discard = 1;
  898. }
  899. /* Handle received packet */
  900. efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
  901. checksummed, discard);
  902. return rx_ev_q_label;
  903. }
  904. /* Global events are basically PHY events */
  905. static void falcon_handle_global_event(struct efx_channel *channel,
  906. efx_qword_t *event)
  907. {
  908. struct efx_nic *efx = channel->efx;
  909. int is_phy_event = 0, handled = 0;
  910. /* Check for interrupt on either port. Some boards have a
  911. * single PHY wired to the interrupt line for port 1. */
  912. if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
  913. EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
  914. EFX_QWORD_FIELD(*event, XG_PHY_INTR))
  915. is_phy_event = 1;
  916. if ((FALCON_REV(efx) >= FALCON_REV_B0) &&
  917. EFX_OWORD_FIELD(*event, XG_MNT_INTR_B0))
  918. is_phy_event = 1;
  919. if (is_phy_event) {
  920. efx->phy_op->clear_interrupt(efx);
  921. queue_work(efx->workqueue, &efx->reconfigure_work);
  922. handled = 1;
  923. }
  924. if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
  925. EFX_ERR(efx, "channel %d seen global RX_RESET "
  926. "event. Resetting.\n", channel->channel);
  927. atomic_inc(&efx->rx_reset);
  928. efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
  929. RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
  930. handled = 1;
  931. }
  932. if (!handled)
  933. EFX_ERR(efx, "channel %d unknown global event "
  934. EFX_QWORD_FMT "\n", channel->channel,
  935. EFX_QWORD_VAL(*event));
  936. }
  937. static void falcon_handle_driver_event(struct efx_channel *channel,
  938. efx_qword_t *event)
  939. {
  940. struct efx_nic *efx = channel->efx;
  941. unsigned int ev_sub_code;
  942. unsigned int ev_sub_data;
  943. ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
  944. ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
  945. switch (ev_sub_code) {
  946. case TX_DESCQ_FLS_DONE_EV_DECODE:
  947. EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
  948. channel->channel, ev_sub_data);
  949. break;
  950. case RX_DESCQ_FLS_DONE_EV_DECODE:
  951. EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
  952. channel->channel, ev_sub_data);
  953. break;
  954. case EVQ_INIT_DONE_EV_DECODE:
  955. EFX_LOG(efx, "channel %d EVQ %d initialised\n",
  956. channel->channel, ev_sub_data);
  957. break;
  958. case SRM_UPD_DONE_EV_DECODE:
  959. EFX_TRACE(efx, "channel %d SRAM update done\n",
  960. channel->channel);
  961. break;
  962. case WAKE_UP_EV_DECODE:
  963. EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
  964. channel->channel, ev_sub_data);
  965. break;
  966. case TIMER_EV_DECODE:
  967. EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
  968. channel->channel, ev_sub_data);
  969. break;
  970. case RX_RECOVERY_EV_DECODE:
  971. EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
  972. "Resetting.\n", channel->channel);
  973. atomic_inc(&efx->rx_reset);
  974. efx_schedule_reset(efx,
  975. EFX_WORKAROUND_6555(efx) ?
  976. RESET_TYPE_RX_RECOVERY :
  977. RESET_TYPE_DISABLE);
  978. break;
  979. case RX_DSC_ERROR_EV_DECODE:
  980. EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
  981. " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
  982. efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
  983. break;
  984. case TX_DSC_ERROR_EV_DECODE:
  985. EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
  986. " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
  987. efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
  988. break;
  989. default:
  990. EFX_TRACE(efx, "channel %d unknown driver event code %d "
  991. "data %04x\n", channel->channel, ev_sub_code,
  992. ev_sub_data);
  993. break;
  994. }
  995. }
  996. int falcon_process_eventq(struct efx_channel *channel, int *rx_quota)
  997. {
  998. unsigned int read_ptr;
  999. efx_qword_t event, *p_event;
  1000. int ev_code;
  1001. int rxq;
  1002. int rxdmaqs = 0;
  1003. read_ptr = channel->eventq_read_ptr;
  1004. do {
  1005. p_event = falcon_event(channel, read_ptr);
  1006. event = *p_event;
  1007. if (!falcon_event_present(&event))
  1008. /* End of events */
  1009. break;
  1010. EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
  1011. channel->channel, EFX_QWORD_VAL(event));
  1012. /* Clear this event by marking it all ones */
  1013. EFX_SET_QWORD(*p_event);
  1014. ev_code = EFX_QWORD_FIELD(event, EV_CODE);
  1015. switch (ev_code) {
  1016. case RX_IP_EV_DECODE:
  1017. rxq = falcon_handle_rx_event(channel, &event);
  1018. rxdmaqs |= (1 << rxq);
  1019. (*rx_quota)--;
  1020. break;
  1021. case TX_IP_EV_DECODE:
  1022. falcon_handle_tx_event(channel, &event);
  1023. break;
  1024. case DRV_GEN_EV_DECODE:
  1025. channel->eventq_magic
  1026. = EFX_QWORD_FIELD(event, EVQ_MAGIC);
  1027. EFX_LOG(channel->efx, "channel %d received generated "
  1028. "event "EFX_QWORD_FMT"\n", channel->channel,
  1029. EFX_QWORD_VAL(event));
  1030. break;
  1031. case GLOBAL_EV_DECODE:
  1032. falcon_handle_global_event(channel, &event);
  1033. break;
  1034. case DRIVER_EV_DECODE:
  1035. falcon_handle_driver_event(channel, &event);
  1036. break;
  1037. default:
  1038. EFX_ERR(channel->efx, "channel %d unknown event type %d"
  1039. " (data " EFX_QWORD_FMT ")\n", channel->channel,
  1040. ev_code, EFX_QWORD_VAL(event));
  1041. }
  1042. /* Increment read pointer */
  1043. read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
  1044. } while (*rx_quota);
  1045. channel->eventq_read_ptr = read_ptr;
  1046. return rxdmaqs;
  1047. }
  1048. void falcon_set_int_moderation(struct efx_channel *channel)
  1049. {
  1050. efx_dword_t timer_cmd;
  1051. struct efx_nic *efx = channel->efx;
  1052. /* Set timer register */
  1053. if (channel->irq_moderation) {
  1054. /* Round to resolution supported by hardware. The value we
  1055. * program is based at 0. So actual interrupt moderation
  1056. * achieved is ((x + 1) * res).
  1057. */
  1058. unsigned int res = 5;
  1059. channel->irq_moderation -= (channel->irq_moderation % res);
  1060. if (channel->irq_moderation < res)
  1061. channel->irq_moderation = res;
  1062. EFX_POPULATE_DWORD_2(timer_cmd,
  1063. TIMER_MODE, TIMER_MODE_INT_HLDOFF,
  1064. TIMER_VAL,
  1065. (channel->irq_moderation / res) - 1);
  1066. } else {
  1067. EFX_POPULATE_DWORD_2(timer_cmd,
  1068. TIMER_MODE, TIMER_MODE_DIS,
  1069. TIMER_VAL, 0);
  1070. }
  1071. falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
  1072. channel->evqnum);
  1073. }
  1074. /* Allocate buffer table entries for event queue */
  1075. int falcon_probe_eventq(struct efx_channel *channel)
  1076. {
  1077. struct efx_nic *efx = channel->efx;
  1078. unsigned int evq_size;
  1079. evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
  1080. return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
  1081. }
  1082. int falcon_init_eventq(struct efx_channel *channel)
  1083. {
  1084. efx_oword_t evq_ptr;
  1085. struct efx_nic *efx = channel->efx;
  1086. int rc;
  1087. EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
  1088. channel->channel, channel->eventq.index,
  1089. channel->eventq.index + channel->eventq.entries - 1);
  1090. /* Pin event queue buffer */
  1091. rc = falcon_init_special_buffer(efx, &channel->eventq);
  1092. if (rc)
  1093. return rc;
  1094. /* Fill event queue with all ones (i.e. empty events) */
  1095. memset(channel->eventq.addr, 0xff, channel->eventq.len);
  1096. /* Push event queue to card */
  1097. EFX_POPULATE_OWORD_3(evq_ptr,
  1098. EVQ_EN, 1,
  1099. EVQ_SIZE, FALCON_EVQ_ORDER,
  1100. EVQ_BUF_BASE_ID, channel->eventq.index);
  1101. falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
  1102. channel->evqnum);
  1103. falcon_set_int_moderation(channel);
  1104. return 0;
  1105. }
  1106. void falcon_fini_eventq(struct efx_channel *channel)
  1107. {
  1108. efx_oword_t eventq_ptr;
  1109. struct efx_nic *efx = channel->efx;
  1110. /* Remove event queue from card */
  1111. EFX_ZERO_OWORD(eventq_ptr);
  1112. falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
  1113. channel->evqnum);
  1114. /* Unpin event queue */
  1115. falcon_fini_special_buffer(efx, &channel->eventq);
  1116. }
  1117. /* Free buffers backing event queue */
  1118. void falcon_remove_eventq(struct efx_channel *channel)
  1119. {
  1120. falcon_free_special_buffer(channel->efx, &channel->eventq);
  1121. }
  1122. /* Generates a test event on the event queue. A subsequent call to
  1123. * process_eventq() should pick up the event and place the value of
  1124. * "magic" into channel->eventq_magic;
  1125. */
  1126. void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
  1127. {
  1128. efx_qword_t test_event;
  1129. EFX_POPULATE_QWORD_2(test_event,
  1130. EV_CODE, DRV_GEN_EV_DECODE,
  1131. EVQ_MAGIC, magic);
  1132. falcon_generate_event(channel, &test_event);
  1133. }
  1134. /**************************************************************************
  1135. *
  1136. * Falcon hardware interrupts
  1137. * The hardware interrupt handler does very little work; all the event
  1138. * queue processing is carried out by per-channel tasklets.
  1139. *
  1140. **************************************************************************/
  1141. /* Enable/disable/generate Falcon interrupts */
  1142. static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
  1143. int force)
  1144. {
  1145. efx_oword_t int_en_reg_ker;
  1146. EFX_POPULATE_OWORD_2(int_en_reg_ker,
  1147. KER_INT_KER, force,
  1148. DRV_INT_EN_KER, enabled);
  1149. falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
  1150. }
  1151. void falcon_enable_interrupts(struct efx_nic *efx)
  1152. {
  1153. efx_oword_t int_adr_reg_ker;
  1154. struct efx_channel *channel;
  1155. EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
  1156. wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
  1157. /* Program address */
  1158. EFX_POPULATE_OWORD_2(int_adr_reg_ker,
  1159. NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
  1160. INT_ADR_KER, efx->irq_status.dma_addr);
  1161. falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
  1162. /* Enable interrupts */
  1163. falcon_interrupts(efx, 1, 0);
  1164. /* Force processing of all the channels to get the EVQ RPTRs up to
  1165. date */
  1166. efx_for_each_channel_with_interrupt(channel, efx)
  1167. efx_schedule_channel(channel);
  1168. }
  1169. void falcon_disable_interrupts(struct efx_nic *efx)
  1170. {
  1171. /* Disable interrupts */
  1172. falcon_interrupts(efx, 0, 0);
  1173. }
  1174. /* Generate a Falcon test interrupt
  1175. * Interrupt must already have been enabled, otherwise nasty things
  1176. * may happen.
  1177. */
  1178. void falcon_generate_interrupt(struct efx_nic *efx)
  1179. {
  1180. falcon_interrupts(efx, 1, 1);
  1181. }
  1182. /* Acknowledge a legacy interrupt from Falcon
  1183. *
  1184. * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
  1185. *
  1186. * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
  1187. * BIU. Interrupt acknowledge is read sensitive so must write instead
  1188. * (then read to ensure the BIU collector is flushed)
  1189. *
  1190. * NB most hardware supports MSI interrupts
  1191. */
  1192. static inline void falcon_irq_ack_a1(struct efx_nic *efx)
  1193. {
  1194. efx_dword_t reg;
  1195. EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
  1196. falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
  1197. falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
  1198. }
  1199. /* Process a fatal interrupt
  1200. * Disable bus mastering ASAP and schedule a reset
  1201. */
  1202. static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
  1203. {
  1204. struct falcon_nic_data *nic_data = efx->nic_data;
  1205. efx_oword_t *int_ker = (efx_oword_t *) efx->irq_status.addr;
  1206. efx_oword_t fatal_intr;
  1207. int error, mem_perr;
  1208. static int n_int_errors;
  1209. falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
  1210. error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
  1211. EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
  1212. EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
  1213. EFX_OWORD_VAL(fatal_intr),
  1214. error ? "disabling bus mastering" : "no recognised error");
  1215. if (error == 0)
  1216. goto out;
  1217. /* If this is a memory parity error dump which blocks are offending */
  1218. mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
  1219. if (mem_perr) {
  1220. efx_oword_t reg;
  1221. falcon_read(efx, &reg, MEM_STAT_REG_KER);
  1222. EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
  1223. EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
  1224. }
  1225. /* Disable DMA bus mastering on both devices */
  1226. pci_disable_device(efx->pci_dev);
  1227. if (FALCON_IS_DUAL_FUNC(efx))
  1228. pci_disable_device(nic_data->pci_dev2);
  1229. if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
  1230. EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
  1231. efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
  1232. } else {
  1233. EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
  1234. "NIC will be disabled\n");
  1235. efx_schedule_reset(efx, RESET_TYPE_DISABLE);
  1236. }
  1237. out:
  1238. return IRQ_HANDLED;
  1239. }
  1240. /* Handle a legacy interrupt from Falcon
  1241. * Acknowledges the interrupt and schedule event queue processing.
  1242. */
  1243. static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
  1244. {
  1245. struct efx_nic *efx = (struct efx_nic *)dev_id;
  1246. efx_oword_t *int_ker = (efx_oword_t *) efx->irq_status.addr;
  1247. struct efx_channel *channel;
  1248. efx_dword_t reg;
  1249. u32 queues;
  1250. int syserr;
  1251. /* Read the ISR which also ACKs the interrupts */
  1252. falcon_readl(efx, &reg, INT_ISR0_B0);
  1253. queues = EFX_EXTRACT_DWORD(reg, 0, 31);
  1254. /* Check to see if we have a serious error condition */
  1255. syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
  1256. if (unlikely(syserr))
  1257. return falcon_fatal_interrupt(efx);
  1258. if (queues == 0)
  1259. return IRQ_NONE;
  1260. efx->last_irq_cpu = raw_smp_processor_id();
  1261. EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
  1262. irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
  1263. /* Schedule processing of any interrupting queues */
  1264. channel = &efx->channel[0];
  1265. while (queues) {
  1266. if (queues & 0x01)
  1267. efx_schedule_channel(channel);
  1268. channel++;
  1269. queues >>= 1;
  1270. }
  1271. return IRQ_HANDLED;
  1272. }
  1273. static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
  1274. {
  1275. struct efx_nic *efx = (struct efx_nic *)dev_id;
  1276. efx_oword_t *int_ker = (efx_oword_t *) efx->irq_status.addr;
  1277. struct efx_channel *channel;
  1278. int syserr;
  1279. int queues;
  1280. /* Check to see if this is our interrupt. If it isn't, we
  1281. * exit without having touched the hardware.
  1282. */
  1283. if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
  1284. EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
  1285. raw_smp_processor_id());
  1286. return IRQ_NONE;
  1287. }
  1288. efx->last_irq_cpu = raw_smp_processor_id();
  1289. EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
  1290. irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
  1291. /* Check to see if we have a serious error condition */
  1292. syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
  1293. if (unlikely(syserr))
  1294. return falcon_fatal_interrupt(efx);
  1295. /* Determine interrupting queues, clear interrupt status
  1296. * register and acknowledge the device interrupt.
  1297. */
  1298. BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
  1299. queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
  1300. EFX_ZERO_OWORD(*int_ker);
  1301. wmb(); /* Ensure the vector is cleared before interrupt ack */
  1302. falcon_irq_ack_a1(efx);
  1303. /* Schedule processing of any interrupting queues */
  1304. channel = &efx->channel[0];
  1305. while (queues) {
  1306. if (queues & 0x01)
  1307. efx_schedule_channel(channel);
  1308. channel++;
  1309. queues >>= 1;
  1310. }
  1311. return IRQ_HANDLED;
  1312. }
  1313. /* Handle an MSI interrupt from Falcon
  1314. *
  1315. * Handle an MSI hardware interrupt. This routine schedules event
  1316. * queue processing. No interrupt acknowledgement cycle is necessary.
  1317. * Also, we never need to check that the interrupt is for us, since
  1318. * MSI interrupts cannot be shared.
  1319. */
  1320. static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
  1321. {
  1322. struct efx_channel *channel = (struct efx_channel *)dev_id;
  1323. struct efx_nic *efx = channel->efx;
  1324. efx_oword_t *int_ker = (efx_oword_t *) efx->irq_status.addr;
  1325. int syserr;
  1326. efx->last_irq_cpu = raw_smp_processor_id();
  1327. EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
  1328. irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
  1329. /* Check to see if we have a serious error condition */
  1330. syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
  1331. if (unlikely(syserr))
  1332. return falcon_fatal_interrupt(efx);
  1333. /* Schedule processing of the channel */
  1334. efx_schedule_channel(channel);
  1335. return IRQ_HANDLED;
  1336. }
  1337. /* Setup RSS indirection table.
  1338. * This maps from the hash value of the packet to RXQ
  1339. */
  1340. static void falcon_setup_rss_indir_table(struct efx_nic *efx)
  1341. {
  1342. int i = 0;
  1343. unsigned long offset;
  1344. efx_dword_t dword;
  1345. if (FALCON_REV(efx) < FALCON_REV_B0)
  1346. return;
  1347. for (offset = RX_RSS_INDIR_TBL_B0;
  1348. offset < RX_RSS_INDIR_TBL_B0 + 0x800;
  1349. offset += 0x10) {
  1350. EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
  1351. i % efx->rss_queues);
  1352. falcon_writel(efx, &dword, offset);
  1353. i++;
  1354. }
  1355. }
  1356. /* Hook interrupt handler(s)
  1357. * Try MSI and then legacy interrupts.
  1358. */
  1359. int falcon_init_interrupt(struct efx_nic *efx)
  1360. {
  1361. struct efx_channel *channel;
  1362. int rc;
  1363. if (!EFX_INT_MODE_USE_MSI(efx)) {
  1364. irq_handler_t handler;
  1365. if (FALCON_REV(efx) >= FALCON_REV_B0)
  1366. handler = falcon_legacy_interrupt_b0;
  1367. else
  1368. handler = falcon_legacy_interrupt_a1;
  1369. rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
  1370. efx->name, efx);
  1371. if (rc) {
  1372. EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
  1373. efx->pci_dev->irq);
  1374. goto fail1;
  1375. }
  1376. return 0;
  1377. }
  1378. /* Hook MSI or MSI-X interrupt */
  1379. efx_for_each_channel_with_interrupt(channel, efx) {
  1380. rc = request_irq(channel->irq, falcon_msi_interrupt,
  1381. IRQF_PROBE_SHARED, /* Not shared */
  1382. efx->name, channel);
  1383. if (rc) {
  1384. EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
  1385. goto fail2;
  1386. }
  1387. }
  1388. return 0;
  1389. fail2:
  1390. efx_for_each_channel_with_interrupt(channel, efx)
  1391. free_irq(channel->irq, channel);
  1392. fail1:
  1393. return rc;
  1394. }
  1395. void falcon_fini_interrupt(struct efx_nic *efx)
  1396. {
  1397. struct efx_channel *channel;
  1398. efx_oword_t reg;
  1399. /* Disable MSI/MSI-X interrupts */
  1400. efx_for_each_channel_with_interrupt(channel, efx)
  1401. if (channel->irq)
  1402. free_irq(channel->irq, channel);
  1403. /* ACK legacy interrupt */
  1404. if (FALCON_REV(efx) >= FALCON_REV_B0)
  1405. falcon_read(efx, &reg, INT_ISR0_B0);
  1406. else
  1407. falcon_irq_ack_a1(efx);
  1408. /* Disable legacy interrupt */
  1409. if (efx->legacy_irq)
  1410. free_irq(efx->legacy_irq, efx);
  1411. }
  1412. /**************************************************************************
  1413. *
  1414. * EEPROM/flash
  1415. *
  1416. **************************************************************************
  1417. */
  1418. #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
  1419. /* Wait for SPI command completion */
  1420. static int falcon_spi_wait(struct efx_nic *efx)
  1421. {
  1422. efx_oword_t reg;
  1423. int cmd_en, timer_active;
  1424. int count;
  1425. count = 0;
  1426. do {
  1427. falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
  1428. cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
  1429. timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
  1430. if (!cmd_en && !timer_active)
  1431. return 0;
  1432. udelay(10);
  1433. } while (++count < 10000); /* wait upto 100msec */
  1434. EFX_ERR(efx, "timed out waiting for SPI\n");
  1435. return -ETIMEDOUT;
  1436. }
  1437. static int
  1438. falcon_spi_read(struct efx_nic *efx, int device_id, unsigned int command,
  1439. unsigned int address, unsigned int addr_len,
  1440. void *data, unsigned int len)
  1441. {
  1442. efx_oword_t reg;
  1443. int rc;
  1444. BUG_ON(len > FALCON_SPI_MAX_LEN);
  1445. /* Check SPI not currently being accessed */
  1446. rc = falcon_spi_wait(efx);
  1447. if (rc)
  1448. return rc;
  1449. /* Program address register */
  1450. EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
  1451. falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
  1452. /* Issue read command */
  1453. EFX_POPULATE_OWORD_7(reg,
  1454. EE_SPI_HCMD_CMD_EN, 1,
  1455. EE_SPI_HCMD_SF_SEL, device_id,
  1456. EE_SPI_HCMD_DABCNT, len,
  1457. EE_SPI_HCMD_READ, EE_SPI_READ,
  1458. EE_SPI_HCMD_DUBCNT, 0,
  1459. EE_SPI_HCMD_ADBCNT, addr_len,
  1460. EE_SPI_HCMD_ENC, command);
  1461. falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
  1462. /* Wait for read to complete */
  1463. rc = falcon_spi_wait(efx);
  1464. if (rc)
  1465. return rc;
  1466. /* Read data */
  1467. falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
  1468. memcpy(data, &reg, len);
  1469. return 0;
  1470. }
  1471. /**************************************************************************
  1472. *
  1473. * MAC wrapper
  1474. *
  1475. **************************************************************************
  1476. */
  1477. void falcon_drain_tx_fifo(struct efx_nic *efx)
  1478. {
  1479. efx_oword_t temp;
  1480. int count;
  1481. if ((FALCON_REV(efx) < FALCON_REV_B0) ||
  1482. (efx->loopback_mode != LOOPBACK_NONE))
  1483. return;
  1484. falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
  1485. /* There is no point in draining more than once */
  1486. if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
  1487. return;
  1488. /* MAC stats will fail whilst the TX fifo is draining. Serialise
  1489. * the drain sequence with the statistics fetch */
  1490. spin_lock(&efx->stats_lock);
  1491. EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
  1492. falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
  1493. /* Reset the MAC and EM block. */
  1494. falcon_read(efx, &temp, GLB_CTL_REG_KER);
  1495. EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
  1496. EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
  1497. EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
  1498. falcon_write(efx, &temp, GLB_CTL_REG_KER);
  1499. count = 0;
  1500. while (1) {
  1501. falcon_read(efx, &temp, GLB_CTL_REG_KER);
  1502. if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
  1503. !EFX_OWORD_FIELD(temp, RST_XGRX) &&
  1504. !EFX_OWORD_FIELD(temp, RST_EM)) {
  1505. EFX_LOG(efx, "Completed MAC reset after %d loops\n",
  1506. count);
  1507. break;
  1508. }
  1509. if (count > 20) {
  1510. EFX_ERR(efx, "MAC reset failed\n");
  1511. break;
  1512. }
  1513. count++;
  1514. udelay(10);
  1515. }
  1516. spin_unlock(&efx->stats_lock);
  1517. /* If we've reset the EM block and the link is up, then
  1518. * we'll have to kick the XAUI link so the PHY can recover */
  1519. if (efx->link_up && EFX_WORKAROUND_5147(efx))
  1520. falcon_reset_xaui(efx);
  1521. }
  1522. void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
  1523. {
  1524. efx_oword_t temp;
  1525. if (FALCON_REV(efx) < FALCON_REV_B0)
  1526. return;
  1527. /* Isolate the MAC -> RX */
  1528. falcon_read(efx, &temp, RX_CFG_REG_KER);
  1529. EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
  1530. falcon_write(efx, &temp, RX_CFG_REG_KER);
  1531. if (!efx->link_up)
  1532. falcon_drain_tx_fifo(efx);
  1533. }
  1534. void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
  1535. {
  1536. efx_oword_t reg;
  1537. int link_speed;
  1538. unsigned int tx_fc;
  1539. if (efx->link_options & GM_LPA_10000)
  1540. link_speed = 0x3;
  1541. else if (efx->link_options & GM_LPA_1000)
  1542. link_speed = 0x2;
  1543. else if (efx->link_options & GM_LPA_100)
  1544. link_speed = 0x1;
  1545. else
  1546. link_speed = 0x0;
  1547. /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
  1548. * as advertised. Disable to ensure packets are not
  1549. * indefinitely held and TX queue can be flushed at any point
  1550. * while the link is down. */
  1551. EFX_POPULATE_OWORD_5(reg,
  1552. MAC_XOFF_VAL, 0xffff /* max pause time */,
  1553. MAC_BCAD_ACPT, 1,
  1554. MAC_UC_PROM, efx->promiscuous,
  1555. MAC_LINK_STATUS, 1, /* always set */
  1556. MAC_SPEED, link_speed);
  1557. /* On B0, MAC backpressure can be disabled and packets get
  1558. * discarded. */
  1559. if (FALCON_REV(efx) >= FALCON_REV_B0) {
  1560. EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
  1561. !efx->link_up);
  1562. }
  1563. falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
  1564. /* Restore the multicast hash registers. */
  1565. falcon_set_multicast_hash(efx);
  1566. /* Transmission of pause frames when RX crosses the threshold is
  1567. * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
  1568. * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
  1569. tx_fc = (efx->flow_control & EFX_FC_TX) ? 1 : 0;
  1570. falcon_read(efx, &reg, RX_CFG_REG_KER);
  1571. EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
  1572. /* Unisolate the MAC -> RX */
  1573. if (FALCON_REV(efx) >= FALCON_REV_B0)
  1574. EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
  1575. falcon_write(efx, &reg, RX_CFG_REG_KER);
  1576. }
  1577. int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
  1578. {
  1579. efx_oword_t reg;
  1580. u32 *dma_done;
  1581. int i;
  1582. if (disable_dma_stats)
  1583. return 0;
  1584. /* Statistics fetch will fail if the MAC is in TX drain */
  1585. if (FALCON_REV(efx) >= FALCON_REV_B0) {
  1586. efx_oword_t temp;
  1587. falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
  1588. if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
  1589. return 0;
  1590. }
  1591. dma_done = (efx->stats_buffer.addr + done_offset);
  1592. *dma_done = FALCON_STATS_NOT_DONE;
  1593. wmb(); /* ensure done flag is clear */
  1594. /* Initiate DMA transfer of stats */
  1595. EFX_POPULATE_OWORD_2(reg,
  1596. MAC_STAT_DMA_CMD, 1,
  1597. MAC_STAT_DMA_ADR,
  1598. efx->stats_buffer.dma_addr);
  1599. falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
  1600. /* Wait for transfer to complete */
  1601. for (i = 0; i < 400; i++) {
  1602. if (*(volatile u32 *)dma_done == FALCON_STATS_DONE)
  1603. return 0;
  1604. udelay(10);
  1605. }
  1606. EFX_ERR(efx, "timed out waiting for statistics\n");
  1607. return -ETIMEDOUT;
  1608. }
  1609. /**************************************************************************
  1610. *
  1611. * PHY access via GMII
  1612. *
  1613. **************************************************************************
  1614. */
  1615. /* Use the top bit of the MII PHY id to indicate the PHY type
  1616. * (1G/10G), with the remaining bits as the actual PHY id.
  1617. *
  1618. * This allows us to avoid leaking information from the mii_if_info
  1619. * structure into other data structures.
  1620. */
  1621. #define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
  1622. #define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
  1623. #define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
  1624. #define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
  1625. #define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
  1626. /* Packing the clause 45 port and device fields into a single value */
  1627. #define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
  1628. #define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
  1629. #define MD_DEV_ADR_COMP_LBN 0
  1630. #define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
  1631. /* Wait for GMII access to complete */
  1632. static int falcon_gmii_wait(struct efx_nic *efx)
  1633. {
  1634. efx_dword_t md_stat;
  1635. int count;
  1636. for (count = 0; count < 1000; count++) { /* wait upto 10ms */
  1637. falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
  1638. if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
  1639. if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
  1640. EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
  1641. EFX_ERR(efx, "error from GMII access "
  1642. EFX_DWORD_FMT"\n",
  1643. EFX_DWORD_VAL(md_stat));
  1644. return -EIO;
  1645. }
  1646. return 0;
  1647. }
  1648. udelay(10);
  1649. }
  1650. EFX_ERR(efx, "timed out waiting for GMII\n");
  1651. return -ETIMEDOUT;
  1652. }
  1653. /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
  1654. static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
  1655. int addr, int value)
  1656. {
  1657. struct efx_nic *efx = (struct efx_nic *)net_dev->priv;
  1658. unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
  1659. efx_oword_t reg;
  1660. /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
  1661. * chosen so that the only current user, Falcon, can take the
  1662. * packed value and use them directly.
  1663. * Fail to build if this assumption is broken.
  1664. */
  1665. BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
  1666. BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
  1667. BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
  1668. BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
  1669. if (phy_id2 == PHY_ADDR_INVALID)
  1670. return;
  1671. /* See falcon_mdio_read for an explanation. */
  1672. if (!(phy_id & FALCON_PHY_ID_10G)) {
  1673. int mmd = ffs(efx->phy_op->mmds) - 1;
  1674. EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
  1675. phy_id2 = mdio_clause45_pack(phy_id2, mmd)
  1676. & FALCON_PHY_ID_ID_MASK;
  1677. }
  1678. EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
  1679. addr, value);
  1680. spin_lock_bh(&efx->phy_lock);
  1681. /* Check MII not currently being accessed */
  1682. if (falcon_gmii_wait(efx) != 0)
  1683. goto out;
  1684. /* Write the address/ID register */
  1685. EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
  1686. falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
  1687. EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
  1688. falcon_write(efx, &reg, MD_ID_REG_KER);
  1689. /* Write data */
  1690. EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
  1691. falcon_write(efx, &reg, MD_TXD_REG_KER);
  1692. EFX_POPULATE_OWORD_2(reg,
  1693. MD_WRC, 1,
  1694. MD_GC, 0);
  1695. falcon_write(efx, &reg, MD_CS_REG_KER);
  1696. /* Wait for data to be written */
  1697. if (falcon_gmii_wait(efx) != 0) {
  1698. /* Abort the write operation */
  1699. EFX_POPULATE_OWORD_2(reg,
  1700. MD_WRC, 0,
  1701. MD_GC, 1);
  1702. falcon_write(efx, &reg, MD_CS_REG_KER);
  1703. udelay(10);
  1704. }
  1705. out:
  1706. spin_unlock_bh(&efx->phy_lock);
  1707. }
  1708. /* Reads a GMII register from a PHY connected to Falcon. If no value
  1709. * could be read, -1 will be returned. */
  1710. static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
  1711. {
  1712. struct efx_nic *efx = (struct efx_nic *)net_dev->priv;
  1713. unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
  1714. efx_oword_t reg;
  1715. int value = -1;
  1716. if (phy_addr == PHY_ADDR_INVALID)
  1717. return -1;
  1718. /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
  1719. * but the generic Linux code does not make any distinction or have
  1720. * any state for this.
  1721. * We spot the case where someone tried to talk 22 to a 45 PHY and
  1722. * redirect the request to the lowest numbered MMD as a clause45
  1723. * request. This is enough to allow simple queries like id and link
  1724. * state to succeed. TODO: We may need to do more in future.
  1725. */
  1726. if (!(phy_id & FALCON_PHY_ID_10G)) {
  1727. int mmd = ffs(efx->phy_op->mmds) - 1;
  1728. EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
  1729. phy_addr = mdio_clause45_pack(phy_addr, mmd)
  1730. & FALCON_PHY_ID_ID_MASK;
  1731. }
  1732. spin_lock_bh(&efx->phy_lock);
  1733. /* Check MII not currently being accessed */
  1734. if (falcon_gmii_wait(efx) != 0)
  1735. goto out;
  1736. EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
  1737. falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
  1738. EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
  1739. falcon_write(efx, &reg, MD_ID_REG_KER);
  1740. /* Request data to be read */
  1741. EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
  1742. falcon_write(efx, &reg, MD_CS_REG_KER);
  1743. /* Wait for data to become available */
  1744. value = falcon_gmii_wait(efx);
  1745. if (value == 0) {
  1746. falcon_read(efx, &reg, MD_RXD_REG_KER);
  1747. value = EFX_OWORD_FIELD(reg, MD_RXD);
  1748. EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
  1749. phy_id, addr, value);
  1750. } else {
  1751. /* Abort the read operation */
  1752. EFX_POPULATE_OWORD_2(reg,
  1753. MD_RIC, 0,
  1754. MD_GC, 1);
  1755. falcon_write(efx, &reg, MD_CS_REG_KER);
  1756. EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
  1757. "error %d\n", phy_id, addr, value);
  1758. }
  1759. out:
  1760. spin_unlock_bh(&efx->phy_lock);
  1761. return value;
  1762. }
  1763. static void falcon_init_mdio(struct mii_if_info *gmii)
  1764. {
  1765. gmii->mdio_read = falcon_mdio_read;
  1766. gmii->mdio_write = falcon_mdio_write;
  1767. gmii->phy_id_mask = FALCON_PHY_ID_MASK;
  1768. gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
  1769. }
  1770. static int falcon_probe_phy(struct efx_nic *efx)
  1771. {
  1772. switch (efx->phy_type) {
  1773. case PHY_TYPE_10XPRESS:
  1774. efx->phy_op = &falcon_tenxpress_phy_ops;
  1775. break;
  1776. case PHY_TYPE_XFP:
  1777. efx->phy_op = &falcon_xfp_phy_ops;
  1778. break;
  1779. default:
  1780. EFX_ERR(efx, "Unknown PHY type %d\n",
  1781. efx->phy_type);
  1782. return -1;
  1783. }
  1784. efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
  1785. return 0;
  1786. }
  1787. /* This call is responsible for hooking in the MAC and PHY operations */
  1788. int falcon_probe_port(struct efx_nic *efx)
  1789. {
  1790. int rc;
  1791. /* Hook in PHY operations table */
  1792. rc = falcon_probe_phy(efx);
  1793. if (rc)
  1794. return rc;
  1795. /* Set up GMII structure for PHY */
  1796. efx->mii.supports_gmii = 1;
  1797. falcon_init_mdio(&efx->mii);
  1798. /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
  1799. if (FALCON_REV(efx) >= FALCON_REV_B0)
  1800. efx->flow_control = EFX_FC_RX | EFX_FC_TX;
  1801. else
  1802. efx->flow_control = EFX_FC_RX;
  1803. /* Allocate buffer for stats */
  1804. rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
  1805. FALCON_MAC_STATS_SIZE);
  1806. if (rc)
  1807. return rc;
  1808. EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
  1809. (unsigned long long)efx->stats_buffer.dma_addr,
  1810. efx->stats_buffer.addr,
  1811. virt_to_phys(efx->stats_buffer.addr));
  1812. return 0;
  1813. }
  1814. void falcon_remove_port(struct efx_nic *efx)
  1815. {
  1816. falcon_free_buffer(efx, &efx->stats_buffer);
  1817. }
  1818. /**************************************************************************
  1819. *
  1820. * Multicast filtering
  1821. *
  1822. **************************************************************************
  1823. */
  1824. void falcon_set_multicast_hash(struct efx_nic *efx)
  1825. {
  1826. union efx_multicast_hash *mc_hash = &efx->multicast_hash;
  1827. /* Broadcast packets go through the multicast hash filter.
  1828. * ether_crc_le() of the broadcast address is 0xbe2612ff
  1829. * so we always add bit 0xff to the mask.
  1830. */
  1831. set_bit_le(0xff, mc_hash->byte);
  1832. falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
  1833. falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
  1834. }
  1835. /**************************************************************************
  1836. *
  1837. * Device reset
  1838. *
  1839. **************************************************************************
  1840. */
  1841. /* Resets NIC to known state. This routine must be called in process
  1842. * context and is allowed to sleep. */
  1843. int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
  1844. {
  1845. struct falcon_nic_data *nic_data = efx->nic_data;
  1846. efx_oword_t glb_ctl_reg_ker;
  1847. int rc;
  1848. EFX_LOG(efx, "performing hardware reset (%d)\n", method);
  1849. /* Initiate device reset */
  1850. if (method == RESET_TYPE_WORLD) {
  1851. rc = pci_save_state(efx->pci_dev);
  1852. if (rc) {
  1853. EFX_ERR(efx, "failed to backup PCI state of primary "
  1854. "function prior to hardware reset\n");
  1855. goto fail1;
  1856. }
  1857. if (FALCON_IS_DUAL_FUNC(efx)) {
  1858. rc = pci_save_state(nic_data->pci_dev2);
  1859. if (rc) {
  1860. EFX_ERR(efx, "failed to backup PCI state of "
  1861. "secondary function prior to "
  1862. "hardware reset\n");
  1863. goto fail2;
  1864. }
  1865. }
  1866. EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
  1867. EXT_PHY_RST_DUR, 0x7,
  1868. SWRST, 1);
  1869. } else {
  1870. int reset_phy = (method == RESET_TYPE_INVISIBLE ?
  1871. EXCLUDE_FROM_RESET : 0);
  1872. EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
  1873. EXT_PHY_RST_CTL, reset_phy,
  1874. PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
  1875. PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
  1876. PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
  1877. EE_RST_CTL, EXCLUDE_FROM_RESET,
  1878. EXT_PHY_RST_DUR, 0x7 /* 10ms */,
  1879. SWRST, 1);
  1880. }
  1881. falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
  1882. EFX_LOG(efx, "waiting for hardware reset\n");
  1883. schedule_timeout_uninterruptible(HZ / 20);
  1884. /* Restore PCI configuration if needed */
  1885. if (method == RESET_TYPE_WORLD) {
  1886. if (FALCON_IS_DUAL_FUNC(efx)) {
  1887. rc = pci_restore_state(nic_data->pci_dev2);
  1888. if (rc) {
  1889. EFX_ERR(efx, "failed to restore PCI config for "
  1890. "the secondary function\n");
  1891. goto fail3;
  1892. }
  1893. }
  1894. rc = pci_restore_state(efx->pci_dev);
  1895. if (rc) {
  1896. EFX_ERR(efx, "failed to restore PCI config for the "
  1897. "primary function\n");
  1898. goto fail4;
  1899. }
  1900. EFX_LOG(efx, "successfully restored PCI config\n");
  1901. }
  1902. /* Assert that reset complete */
  1903. falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
  1904. if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
  1905. rc = -ETIMEDOUT;
  1906. EFX_ERR(efx, "timed out waiting for hardware reset\n");
  1907. goto fail5;
  1908. }
  1909. EFX_LOG(efx, "hardware reset complete\n");
  1910. return 0;
  1911. /* pci_save_state() and pci_restore_state() MUST be called in pairs */
  1912. fail2:
  1913. fail3:
  1914. pci_restore_state(efx->pci_dev);
  1915. fail1:
  1916. fail4:
  1917. fail5:
  1918. return rc;
  1919. }
  1920. /* Zeroes out the SRAM contents. This routine must be called in
  1921. * process context and is allowed to sleep.
  1922. */
  1923. static int falcon_reset_sram(struct efx_nic *efx)
  1924. {
  1925. efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
  1926. int count;
  1927. /* Set the SRAM wake/sleep GPIO appropriately. */
  1928. falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
  1929. EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
  1930. EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
  1931. falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
  1932. /* Initiate SRAM reset */
  1933. EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
  1934. SRAM_OOB_BT_INIT_EN, 1,
  1935. SRM_NUM_BANKS_AND_BANK_SIZE, 0);
  1936. falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
  1937. /* Wait for SRAM reset to complete */
  1938. count = 0;
  1939. do {
  1940. EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
  1941. /* SRAM reset is slow; expect around 16ms */
  1942. schedule_timeout_uninterruptible(HZ / 50);
  1943. /* Check for reset complete */
  1944. falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
  1945. if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
  1946. EFX_LOG(efx, "SRAM reset complete\n");
  1947. return 0;
  1948. }
  1949. } while (++count < 20); /* wait upto 0.4 sec */
  1950. EFX_ERR(efx, "timed out waiting for SRAM reset\n");
  1951. return -ETIMEDOUT;
  1952. }
  1953. /* Extract non-volatile configuration */
  1954. static int falcon_probe_nvconfig(struct efx_nic *efx)
  1955. {
  1956. struct falcon_nvconfig *nvconfig;
  1957. efx_oword_t nic_stat;
  1958. int device_id;
  1959. unsigned addr_len;
  1960. size_t offset, len;
  1961. int magic_num, struct_ver, board_rev;
  1962. int rc;
  1963. /* Find the boot device. */
  1964. falcon_read(efx, &nic_stat, NIC_STAT_REG);
  1965. if (EFX_OWORD_FIELD(nic_stat, SF_PRST)) {
  1966. device_id = EE_SPI_FLASH;
  1967. addr_len = 3;
  1968. } else if (EFX_OWORD_FIELD(nic_stat, EE_PRST)) {
  1969. device_id = EE_SPI_EEPROM;
  1970. addr_len = 2;
  1971. } else {
  1972. return -ENODEV;
  1973. }
  1974. nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
  1975. /* Read the whole configuration structure into memory. */
  1976. for (offset = 0; offset < sizeof(*nvconfig); offset += len) {
  1977. len = min(sizeof(*nvconfig) - offset,
  1978. (size_t) FALCON_SPI_MAX_LEN);
  1979. rc = falcon_spi_read(efx, device_id, SPI_READ,
  1980. NVCONFIG_BASE + offset, addr_len,
  1981. (char *)nvconfig + offset, len);
  1982. if (rc)
  1983. goto out;
  1984. }
  1985. /* Read the MAC addresses */
  1986. memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
  1987. /* Read the board configuration. */
  1988. magic_num = le16_to_cpu(nvconfig->board_magic_num);
  1989. struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
  1990. if (magic_num != NVCONFIG_BOARD_MAGIC_NUM || struct_ver < 2) {
  1991. EFX_ERR(efx, "Non volatile memory bad magic=%x ver=%x "
  1992. "therefore using defaults\n", magic_num, struct_ver);
  1993. efx->phy_type = PHY_TYPE_NONE;
  1994. efx->mii.phy_id = PHY_ADDR_INVALID;
  1995. board_rev = 0;
  1996. } else {
  1997. struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
  1998. efx->phy_type = v2->port0_phy_type;
  1999. efx->mii.phy_id = v2->port0_phy_addr;
  2000. board_rev = le16_to_cpu(v2->board_revision);
  2001. }
  2002. EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
  2003. efx_set_board_info(efx, board_rev);
  2004. out:
  2005. kfree(nvconfig);
  2006. return rc;
  2007. }
  2008. /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
  2009. * count, port speed). Set workaround and feature flags accordingly.
  2010. */
  2011. static int falcon_probe_nic_variant(struct efx_nic *efx)
  2012. {
  2013. efx_oword_t altera_build;
  2014. falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
  2015. if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
  2016. EFX_ERR(efx, "Falcon FPGA not supported\n");
  2017. return -ENODEV;
  2018. }
  2019. switch (FALCON_REV(efx)) {
  2020. case FALCON_REV_A0:
  2021. case 0xff:
  2022. EFX_ERR(efx, "Falcon rev A0 not supported\n");
  2023. return -ENODEV;
  2024. case FALCON_REV_A1:{
  2025. efx_oword_t nic_stat;
  2026. falcon_read(efx, &nic_stat, NIC_STAT_REG);
  2027. if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
  2028. EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
  2029. return -ENODEV;
  2030. }
  2031. if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
  2032. EFX_ERR(efx, "1G mode not supported\n");
  2033. return -ENODEV;
  2034. }
  2035. break;
  2036. }
  2037. case FALCON_REV_B0:
  2038. break;
  2039. default:
  2040. EFX_ERR(efx, "Unknown Falcon rev %d\n", FALCON_REV(efx));
  2041. return -ENODEV;
  2042. }
  2043. return 0;
  2044. }
  2045. int falcon_probe_nic(struct efx_nic *efx)
  2046. {
  2047. struct falcon_nic_data *nic_data;
  2048. int rc;
  2049. /* Initialise I2C interface state */
  2050. efx->i2c.efx = efx;
  2051. efx->i2c.op = &falcon_i2c_bit_operations;
  2052. efx->i2c.sda = 1;
  2053. efx->i2c.scl = 1;
  2054. /* Allocate storage for hardware specific data */
  2055. nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
  2056. efx->nic_data = (void *) nic_data;
  2057. /* Determine number of ports etc. */
  2058. rc = falcon_probe_nic_variant(efx);
  2059. if (rc)
  2060. goto fail1;
  2061. /* Probe secondary function if expected */
  2062. if (FALCON_IS_DUAL_FUNC(efx)) {
  2063. struct pci_dev *dev = pci_dev_get(efx->pci_dev);
  2064. while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
  2065. dev))) {
  2066. if (dev->bus == efx->pci_dev->bus &&
  2067. dev->devfn == efx->pci_dev->devfn + 1) {
  2068. nic_data->pci_dev2 = dev;
  2069. break;
  2070. }
  2071. }
  2072. if (!nic_data->pci_dev2) {
  2073. EFX_ERR(efx, "failed to find secondary function\n");
  2074. rc = -ENODEV;
  2075. goto fail2;
  2076. }
  2077. }
  2078. /* Now we can reset the NIC */
  2079. rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
  2080. if (rc) {
  2081. EFX_ERR(efx, "failed to reset NIC\n");
  2082. goto fail3;
  2083. }
  2084. /* Allocate memory for INT_KER */
  2085. rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
  2086. if (rc)
  2087. goto fail4;
  2088. BUG_ON(efx->irq_status.dma_addr & 0x0f);
  2089. EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
  2090. (unsigned long long)efx->irq_status.dma_addr,
  2091. efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
  2092. /* Read in the non-volatile configuration */
  2093. rc = falcon_probe_nvconfig(efx);
  2094. if (rc)
  2095. goto fail5;
  2096. return 0;
  2097. fail5:
  2098. falcon_free_buffer(efx, &efx->irq_status);
  2099. fail4:
  2100. fail3:
  2101. if (nic_data->pci_dev2) {
  2102. pci_dev_put(nic_data->pci_dev2);
  2103. nic_data->pci_dev2 = NULL;
  2104. }
  2105. fail2:
  2106. fail1:
  2107. kfree(efx->nic_data);
  2108. return rc;
  2109. }
  2110. /* This call performs hardware-specific global initialisation, such as
  2111. * defining the descriptor cache sizes and number of RSS channels.
  2112. * It does not set up any buffers, descriptor rings or event queues.
  2113. */
  2114. int falcon_init_nic(struct efx_nic *efx)
  2115. {
  2116. struct falcon_nic_data *data;
  2117. efx_oword_t temp;
  2118. unsigned thresh;
  2119. int rc;
  2120. data = (struct falcon_nic_data *)efx->nic_data;
  2121. /* Set up the address region register. This is only needed
  2122. * for the B0 FPGA, but since we are just pushing in the
  2123. * reset defaults this may as well be unconditional. */
  2124. EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
  2125. ADR_REGION1, (1 << 16),
  2126. ADR_REGION2, (2 << 16),
  2127. ADR_REGION3, (3 << 16));
  2128. falcon_write(efx, &temp, ADR_REGION_REG_KER);
  2129. /* Use on-chip SRAM */
  2130. falcon_read(efx, &temp, NIC_STAT_REG);
  2131. EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
  2132. falcon_write(efx, &temp, NIC_STAT_REG);
  2133. /* Set buffer table mode */
  2134. EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
  2135. falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
  2136. rc = falcon_reset_sram(efx);
  2137. if (rc)
  2138. return rc;
  2139. /* Set positions of descriptor caches in SRAM. */
  2140. EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
  2141. falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
  2142. EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
  2143. falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
  2144. /* Set TX descriptor cache size. */
  2145. BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
  2146. EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
  2147. falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
  2148. /* Set RX descriptor cache size. Set low watermark to size-8, as
  2149. * this allows most efficient prefetching.
  2150. */
  2151. BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
  2152. EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
  2153. falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
  2154. EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
  2155. falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
  2156. /* Clear the parity enables on the TX data fifos as
  2157. * they produce false parity errors because of timing issues
  2158. */
  2159. if (EFX_WORKAROUND_5129(efx)) {
  2160. falcon_read(efx, &temp, SPARE_REG_KER);
  2161. EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
  2162. falcon_write(efx, &temp, SPARE_REG_KER);
  2163. }
  2164. /* Enable all the genuinely fatal interrupts. (They are still
  2165. * masked by the overall interrupt mask, controlled by
  2166. * falcon_interrupts()).
  2167. *
  2168. * Note: All other fatal interrupts are enabled
  2169. */
  2170. EFX_POPULATE_OWORD_3(temp,
  2171. ILL_ADR_INT_KER_EN, 1,
  2172. RBUF_OWN_INT_KER_EN, 1,
  2173. TBUF_OWN_INT_KER_EN, 1);
  2174. EFX_INVERT_OWORD(temp);
  2175. falcon_write(efx, &temp, FATAL_INTR_REG_KER);
  2176. /* Set number of RSS queues for receive path. */
  2177. falcon_read(efx, &temp, RX_FILTER_CTL_REG);
  2178. if (FALCON_REV(efx) >= FALCON_REV_B0)
  2179. EFX_SET_OWORD_FIELD(temp, NUM_KER, 0);
  2180. else
  2181. EFX_SET_OWORD_FIELD(temp, NUM_KER, efx->rss_queues - 1);
  2182. if (EFX_WORKAROUND_7244(efx)) {
  2183. EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
  2184. EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
  2185. EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
  2186. EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
  2187. }
  2188. falcon_write(efx, &temp, RX_FILTER_CTL_REG);
  2189. falcon_setup_rss_indir_table(efx);
  2190. /* Setup RX. Wait for descriptor is broken and must
  2191. * be disabled. RXDP recovery shouldn't be needed, but is.
  2192. */
  2193. falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
  2194. EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
  2195. EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
  2196. if (EFX_WORKAROUND_5583(efx))
  2197. EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
  2198. falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
  2199. /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
  2200. * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
  2201. */
  2202. falcon_read(efx, &temp, TX_CFG2_REG_KER);
  2203. EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
  2204. EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
  2205. EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
  2206. EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
  2207. EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
  2208. /* Enable SW_EV to inherit in char driver - assume harmless here */
  2209. EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
  2210. /* Prefetch threshold 2 => fetch when descriptor cache half empty */
  2211. EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
  2212. /* Squash TX of packets of 16 bytes or less */
  2213. if (FALCON_REV(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
  2214. EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
  2215. falcon_write(efx, &temp, TX_CFG2_REG_KER);
  2216. /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
  2217. * descriptors (which is bad).
  2218. */
  2219. falcon_read(efx, &temp, TX_CFG_REG_KER);
  2220. EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
  2221. falcon_write(efx, &temp, TX_CFG_REG_KER);
  2222. /* RX config */
  2223. falcon_read(efx, &temp, RX_CFG_REG_KER);
  2224. EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
  2225. if (EFX_WORKAROUND_7575(efx))
  2226. EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
  2227. (3 * 4096) / 32);
  2228. if (FALCON_REV(efx) >= FALCON_REV_B0)
  2229. EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
  2230. /* RX FIFO flow control thresholds */
  2231. thresh = ((rx_xon_thresh_bytes >= 0) ?
  2232. rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
  2233. EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
  2234. thresh = ((rx_xoff_thresh_bytes >= 0) ?
  2235. rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
  2236. EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
  2237. /* RX control FIFO thresholds [32 entries] */
  2238. EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 25);
  2239. EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 20);
  2240. falcon_write(efx, &temp, RX_CFG_REG_KER);
  2241. /* Set destination of both TX and RX Flush events */
  2242. if (FALCON_REV(efx) >= FALCON_REV_B0) {
  2243. EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
  2244. falcon_write(efx, &temp, DP_CTRL_REG);
  2245. }
  2246. return 0;
  2247. }
  2248. void falcon_remove_nic(struct efx_nic *efx)
  2249. {
  2250. struct falcon_nic_data *nic_data = efx->nic_data;
  2251. falcon_free_buffer(efx, &efx->irq_status);
  2252. (void) falcon_reset_hw(efx, RESET_TYPE_ALL);
  2253. /* Release the second function after the reset */
  2254. if (nic_data->pci_dev2) {
  2255. pci_dev_put(nic_data->pci_dev2);
  2256. nic_data->pci_dev2 = NULL;
  2257. }
  2258. /* Tear down the private nic state */
  2259. kfree(efx->nic_data);
  2260. efx->nic_data = NULL;
  2261. }
  2262. void falcon_update_nic_stats(struct efx_nic *efx)
  2263. {
  2264. efx_oword_t cnt;
  2265. falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
  2266. efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
  2267. }
  2268. /**************************************************************************
  2269. *
  2270. * Revision-dependent attributes used by efx.c
  2271. *
  2272. **************************************************************************
  2273. */
  2274. struct efx_nic_type falcon_a_nic_type = {
  2275. .mem_bar = 2,
  2276. .mem_map_size = 0x20000,
  2277. .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
  2278. .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
  2279. .buf_tbl_base = BUF_TBL_KER_A1,
  2280. .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
  2281. .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
  2282. .txd_ring_mask = FALCON_TXD_RING_MASK,
  2283. .rxd_ring_mask = FALCON_RXD_RING_MASK,
  2284. .evq_size = FALCON_EVQ_SIZE,
  2285. .max_dma_mask = FALCON_DMA_MASK,
  2286. .tx_dma_mask = FALCON_TX_DMA_MASK,
  2287. .bug5391_mask = 0xf,
  2288. .rx_xoff_thresh = 2048,
  2289. .rx_xon_thresh = 512,
  2290. .rx_buffer_padding = 0x24,
  2291. .max_interrupt_mode = EFX_INT_MODE_MSI,
  2292. .phys_addr_channels = 4,
  2293. };
  2294. struct efx_nic_type falcon_b_nic_type = {
  2295. .mem_bar = 2,
  2296. /* Map everything up to and including the RSS indirection
  2297. * table. Don't map MSI-X table, MSI-X PBA since Linux
  2298. * requires that they not be mapped. */
  2299. .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
  2300. .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
  2301. .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
  2302. .buf_tbl_base = BUF_TBL_KER_B0,
  2303. .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
  2304. .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
  2305. .txd_ring_mask = FALCON_TXD_RING_MASK,
  2306. .rxd_ring_mask = FALCON_RXD_RING_MASK,
  2307. .evq_size = FALCON_EVQ_SIZE,
  2308. .max_dma_mask = FALCON_DMA_MASK,
  2309. .tx_dma_mask = FALCON_TX_DMA_MASK,
  2310. .bug5391_mask = 0,
  2311. .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
  2312. .rx_xon_thresh = 27648, /* ~3*max MTU */
  2313. .rx_buffer_padding = 0,
  2314. .max_interrupt_mode = EFX_INT_MODE_MSIX,
  2315. .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
  2316. * interrupt handler only supports 32
  2317. * channels */
  2318. };