s2io.h 32 KB

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  1. /************************************************************************
  2. * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
  3. * Copyright(c) 2002-2007 Neterion Inc.
  4. * This software may be used and distributed according to the terms of
  5. * the GNU General Public License (GPL), incorporated herein by reference.
  6. * Drivers based on or derived from this code fall under the GPL and must
  7. * retain the authorship, copyright and license notice. This file is not
  8. * a complete program and may only be used when the entire operating
  9. * system is licensed under the GPL.
  10. * See the file COPYING in this distribution for more information.
  11. ************************************************************************/
  12. #ifndef _S2IO_H
  13. #define _S2IO_H
  14. #define TBD 0
  15. #define s2BIT(loc) (0x8000000000000000ULL >> (loc))
  16. #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
  17. #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
  18. #ifndef BOOL
  19. #define BOOL int
  20. #endif
  21. #ifndef TRUE
  22. #define TRUE 1
  23. #define FALSE 0
  24. #endif
  25. #undef SUCCESS
  26. #define SUCCESS 0
  27. #define FAILURE -1
  28. #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
  29. #define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
  30. #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
  31. #define S2IO_BIT_RESET 1
  32. #define S2IO_BIT_SET 2
  33. #define CHECKBIT(value, nbit) (value & (1 << nbit))
  34. /* Maximum time to flicker LED when asked to identify NIC using ethtool */
  35. #define MAX_FLICKER_TIME 60000 /* 60 Secs */
  36. /* Maximum outstanding splits to be configured into xena. */
  37. enum {
  38. XENA_ONE_SPLIT_TRANSACTION = 0,
  39. XENA_TWO_SPLIT_TRANSACTION = 1,
  40. XENA_THREE_SPLIT_TRANSACTION = 2,
  41. XENA_FOUR_SPLIT_TRANSACTION = 3,
  42. XENA_EIGHT_SPLIT_TRANSACTION = 4,
  43. XENA_TWELVE_SPLIT_TRANSACTION = 5,
  44. XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
  45. XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
  46. };
  47. #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
  48. /* OS concerned variables and constants */
  49. #define WATCH_DOG_TIMEOUT 15*HZ
  50. #define EFILL 0x1234
  51. #define ALIGN_SIZE 127
  52. #define PCIX_COMMAND_REGISTER 0x62
  53. /*
  54. * Debug related variables.
  55. */
  56. /* different debug levels. */
  57. #define ERR_DBG 0
  58. #define INIT_DBG 1
  59. #define INFO_DBG 2
  60. #define TX_DBG 3
  61. #define INTR_DBG 4
  62. /* Global variable that defines the present debug level of the driver. */
  63. static int debug_level = ERR_DBG;
  64. /* DEBUG message print. */
  65. #define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
  66. #ifndef DMA_ERROR_CODE
  67. #define DMA_ERROR_CODE (~(dma_addr_t)0x0)
  68. #endif
  69. /* Protocol assist features of the NIC */
  70. #define L3_CKSUM_OK 0xFFFF
  71. #define L4_CKSUM_OK 0xFFFF
  72. #define S2IO_JUMBO_SIZE 9600
  73. /* Driver statistics maintained by driver */
  74. struct swStat {
  75. unsigned long long single_ecc_errs;
  76. unsigned long long double_ecc_errs;
  77. unsigned long long parity_err_cnt;
  78. unsigned long long serious_err_cnt;
  79. unsigned long long soft_reset_cnt;
  80. unsigned long long fifo_full_cnt;
  81. unsigned long long ring_full_cnt[8];
  82. /* LRO statistics */
  83. unsigned long long clubbed_frms_cnt;
  84. unsigned long long sending_both;
  85. unsigned long long outof_sequence_pkts;
  86. unsigned long long flush_max_pkts;
  87. unsigned long long sum_avg_pkts_aggregated;
  88. unsigned long long num_aggregations;
  89. /* Other statistics */
  90. unsigned long long mem_alloc_fail_cnt;
  91. unsigned long long pci_map_fail_cnt;
  92. unsigned long long watchdog_timer_cnt;
  93. unsigned long long mem_allocated;
  94. unsigned long long mem_freed;
  95. unsigned long long link_up_cnt;
  96. unsigned long long link_down_cnt;
  97. unsigned long long link_up_time;
  98. unsigned long long link_down_time;
  99. /* Transfer Code statistics */
  100. unsigned long long tx_buf_abort_cnt;
  101. unsigned long long tx_desc_abort_cnt;
  102. unsigned long long tx_parity_err_cnt;
  103. unsigned long long tx_link_loss_cnt;
  104. unsigned long long tx_list_proc_err_cnt;
  105. unsigned long long rx_parity_err_cnt;
  106. unsigned long long rx_abort_cnt;
  107. unsigned long long rx_parity_abort_cnt;
  108. unsigned long long rx_rda_fail_cnt;
  109. unsigned long long rx_unkn_prot_cnt;
  110. unsigned long long rx_fcs_err_cnt;
  111. unsigned long long rx_buf_size_err_cnt;
  112. unsigned long long rx_rxd_corrupt_cnt;
  113. unsigned long long rx_unkn_err_cnt;
  114. /* Error/alarm statistics*/
  115. unsigned long long tda_err_cnt;
  116. unsigned long long pfc_err_cnt;
  117. unsigned long long pcc_err_cnt;
  118. unsigned long long tti_err_cnt;
  119. unsigned long long lso_err_cnt;
  120. unsigned long long tpa_err_cnt;
  121. unsigned long long sm_err_cnt;
  122. unsigned long long mac_tmac_err_cnt;
  123. unsigned long long mac_rmac_err_cnt;
  124. unsigned long long xgxs_txgxs_err_cnt;
  125. unsigned long long xgxs_rxgxs_err_cnt;
  126. unsigned long long rc_err_cnt;
  127. unsigned long long prc_pcix_err_cnt;
  128. unsigned long long rpa_err_cnt;
  129. unsigned long long rda_err_cnt;
  130. unsigned long long rti_err_cnt;
  131. unsigned long long mc_err_cnt;
  132. };
  133. /* Xpak releated alarm and warnings */
  134. struct xpakStat {
  135. u64 alarm_transceiver_temp_high;
  136. u64 alarm_transceiver_temp_low;
  137. u64 alarm_laser_bias_current_high;
  138. u64 alarm_laser_bias_current_low;
  139. u64 alarm_laser_output_power_high;
  140. u64 alarm_laser_output_power_low;
  141. u64 warn_transceiver_temp_high;
  142. u64 warn_transceiver_temp_low;
  143. u64 warn_laser_bias_current_high;
  144. u64 warn_laser_bias_current_low;
  145. u64 warn_laser_output_power_high;
  146. u64 warn_laser_output_power_low;
  147. u64 xpak_regs_stat;
  148. u32 xpak_timer_count;
  149. };
  150. /* The statistics block of Xena */
  151. struct stat_block {
  152. /* Tx MAC statistics counters. */
  153. __le32 tmac_data_octets;
  154. __le32 tmac_frms;
  155. __le64 tmac_drop_frms;
  156. __le32 tmac_bcst_frms;
  157. __le32 tmac_mcst_frms;
  158. __le64 tmac_pause_ctrl_frms;
  159. __le32 tmac_ucst_frms;
  160. __le32 tmac_ttl_octets;
  161. __le32 tmac_any_err_frms;
  162. __le32 tmac_nucst_frms;
  163. __le64 tmac_ttl_less_fb_octets;
  164. __le64 tmac_vld_ip_octets;
  165. __le32 tmac_drop_ip;
  166. __le32 tmac_vld_ip;
  167. __le32 tmac_rst_tcp;
  168. __le32 tmac_icmp;
  169. __le64 tmac_tcp;
  170. __le32 reserved_0;
  171. __le32 tmac_udp;
  172. /* Rx MAC Statistics counters. */
  173. __le32 rmac_data_octets;
  174. __le32 rmac_vld_frms;
  175. __le64 rmac_fcs_err_frms;
  176. __le64 rmac_drop_frms;
  177. __le32 rmac_vld_bcst_frms;
  178. __le32 rmac_vld_mcst_frms;
  179. __le32 rmac_out_rng_len_err_frms;
  180. __le32 rmac_in_rng_len_err_frms;
  181. __le64 rmac_long_frms;
  182. __le64 rmac_pause_ctrl_frms;
  183. __le64 rmac_unsup_ctrl_frms;
  184. __le32 rmac_accepted_ucst_frms;
  185. __le32 rmac_ttl_octets;
  186. __le32 rmac_discarded_frms;
  187. __le32 rmac_accepted_nucst_frms;
  188. __le32 reserved_1;
  189. __le32 rmac_drop_events;
  190. __le64 rmac_ttl_less_fb_octets;
  191. __le64 rmac_ttl_frms;
  192. __le64 reserved_2;
  193. __le32 rmac_usized_frms;
  194. __le32 reserved_3;
  195. __le32 rmac_frag_frms;
  196. __le32 rmac_osized_frms;
  197. __le32 reserved_4;
  198. __le32 rmac_jabber_frms;
  199. __le64 rmac_ttl_64_frms;
  200. __le64 rmac_ttl_65_127_frms;
  201. __le64 reserved_5;
  202. __le64 rmac_ttl_128_255_frms;
  203. __le64 rmac_ttl_256_511_frms;
  204. __le64 reserved_6;
  205. __le64 rmac_ttl_512_1023_frms;
  206. __le64 rmac_ttl_1024_1518_frms;
  207. __le32 rmac_ip;
  208. __le32 reserved_7;
  209. __le64 rmac_ip_octets;
  210. __le32 rmac_drop_ip;
  211. __le32 rmac_hdr_err_ip;
  212. __le32 reserved_8;
  213. __le32 rmac_icmp;
  214. __le64 rmac_tcp;
  215. __le32 rmac_err_drp_udp;
  216. __le32 rmac_udp;
  217. __le64 rmac_xgmii_err_sym;
  218. __le64 rmac_frms_q0;
  219. __le64 rmac_frms_q1;
  220. __le64 rmac_frms_q2;
  221. __le64 rmac_frms_q3;
  222. __le64 rmac_frms_q4;
  223. __le64 rmac_frms_q5;
  224. __le64 rmac_frms_q6;
  225. __le64 rmac_frms_q7;
  226. __le16 rmac_full_q3;
  227. __le16 rmac_full_q2;
  228. __le16 rmac_full_q1;
  229. __le16 rmac_full_q0;
  230. __le16 rmac_full_q7;
  231. __le16 rmac_full_q6;
  232. __le16 rmac_full_q5;
  233. __le16 rmac_full_q4;
  234. __le32 reserved_9;
  235. __le32 rmac_pause_cnt;
  236. __le64 rmac_xgmii_data_err_cnt;
  237. __le64 rmac_xgmii_ctrl_err_cnt;
  238. __le32 rmac_err_tcp;
  239. __le32 rmac_accepted_ip;
  240. /* PCI/PCI-X Read transaction statistics. */
  241. __le32 new_rd_req_cnt;
  242. __le32 rd_req_cnt;
  243. __le32 rd_rtry_cnt;
  244. __le32 new_rd_req_rtry_cnt;
  245. /* PCI/PCI-X Write/Read transaction statistics. */
  246. __le32 wr_req_cnt;
  247. __le32 wr_rtry_rd_ack_cnt;
  248. __le32 new_wr_req_rtry_cnt;
  249. __le32 new_wr_req_cnt;
  250. __le32 wr_disc_cnt;
  251. __le32 wr_rtry_cnt;
  252. /* PCI/PCI-X Write / DMA Transaction statistics. */
  253. __le32 txp_wr_cnt;
  254. __le32 rd_rtry_wr_ack_cnt;
  255. __le32 txd_wr_cnt;
  256. __le32 txd_rd_cnt;
  257. __le32 rxd_wr_cnt;
  258. __le32 rxd_rd_cnt;
  259. __le32 rxf_wr_cnt;
  260. __le32 txf_rd_cnt;
  261. /* Tx MAC statistics overflow counters. */
  262. __le32 tmac_data_octets_oflow;
  263. __le32 tmac_frms_oflow;
  264. __le32 tmac_bcst_frms_oflow;
  265. __le32 tmac_mcst_frms_oflow;
  266. __le32 tmac_ucst_frms_oflow;
  267. __le32 tmac_ttl_octets_oflow;
  268. __le32 tmac_any_err_frms_oflow;
  269. __le32 tmac_nucst_frms_oflow;
  270. __le64 tmac_vlan_frms;
  271. __le32 tmac_drop_ip_oflow;
  272. __le32 tmac_vld_ip_oflow;
  273. __le32 tmac_rst_tcp_oflow;
  274. __le32 tmac_icmp_oflow;
  275. __le32 tpa_unknown_protocol;
  276. __le32 tmac_udp_oflow;
  277. __le32 reserved_10;
  278. __le32 tpa_parse_failure;
  279. /* Rx MAC Statistics overflow counters. */
  280. __le32 rmac_data_octets_oflow;
  281. __le32 rmac_vld_frms_oflow;
  282. __le32 rmac_vld_bcst_frms_oflow;
  283. __le32 rmac_vld_mcst_frms_oflow;
  284. __le32 rmac_accepted_ucst_frms_oflow;
  285. __le32 rmac_ttl_octets_oflow;
  286. __le32 rmac_discarded_frms_oflow;
  287. __le32 rmac_accepted_nucst_frms_oflow;
  288. __le32 rmac_usized_frms_oflow;
  289. __le32 rmac_drop_events_oflow;
  290. __le32 rmac_frag_frms_oflow;
  291. __le32 rmac_osized_frms_oflow;
  292. __le32 rmac_ip_oflow;
  293. __le32 rmac_jabber_frms_oflow;
  294. __le32 rmac_icmp_oflow;
  295. __le32 rmac_drop_ip_oflow;
  296. __le32 rmac_err_drp_udp_oflow;
  297. __le32 rmac_udp_oflow;
  298. __le32 reserved_11;
  299. __le32 rmac_pause_cnt_oflow;
  300. __le64 rmac_ttl_1519_4095_frms;
  301. __le64 rmac_ttl_4096_8191_frms;
  302. __le64 rmac_ttl_8192_max_frms;
  303. __le64 rmac_ttl_gt_max_frms;
  304. __le64 rmac_osized_alt_frms;
  305. __le64 rmac_jabber_alt_frms;
  306. __le64 rmac_gt_max_alt_frms;
  307. __le64 rmac_vlan_frms;
  308. __le32 rmac_len_discard;
  309. __le32 rmac_fcs_discard;
  310. __le32 rmac_pf_discard;
  311. __le32 rmac_da_discard;
  312. __le32 rmac_red_discard;
  313. __le32 rmac_rts_discard;
  314. __le32 reserved_12;
  315. __le32 rmac_ingm_full_discard;
  316. __le32 reserved_13;
  317. __le32 rmac_accepted_ip_oflow;
  318. __le32 reserved_14;
  319. __le32 link_fault_cnt;
  320. u8 buffer[20];
  321. struct swStat sw_stat;
  322. struct xpakStat xpak_stat;
  323. };
  324. /* Default value for 'vlan_strip_tag' configuration parameter */
  325. #define NO_STRIP_IN_PROMISC 2
  326. /*
  327. * Structures representing different init time configuration
  328. * parameters of the NIC.
  329. */
  330. #define MAX_TX_FIFOS 8
  331. #define MAX_RX_RINGS 8
  332. #define FIFO_DEFAULT_NUM 5
  333. #define FIFO_UDP_MAX_NUM 2 /* 0 - even, 1 -odd ports */
  334. #define FIFO_OTHER_MAX_NUM 1
  335. #define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
  336. #define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
  337. #define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
  338. #define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
  339. /* FIFO mappings for all possible number of fifos configured */
  340. static int fifo_map[][MAX_TX_FIFOS] = {
  341. {0, 0, 0, 0, 0, 0, 0, 0},
  342. {0, 0, 0, 0, 1, 1, 1, 1},
  343. {0, 0, 0, 1, 1, 1, 2, 2},
  344. {0, 0, 1, 1, 2, 2, 3, 3},
  345. {0, 0, 1, 1, 2, 2, 3, 4},
  346. {0, 0, 1, 1, 2, 3, 4, 5},
  347. {0, 0, 1, 2, 3, 4, 5, 6},
  348. {0, 1, 2, 3, 4, 5, 6, 7},
  349. };
  350. static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
  351. /* Maintains Per FIFO related information. */
  352. struct tx_fifo_config {
  353. #define MAX_AVAILABLE_TXDS 8192
  354. u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
  355. /* Priority definition */
  356. #define TX_FIFO_PRI_0 0 /*Highest */
  357. #define TX_FIFO_PRI_1 1
  358. #define TX_FIFO_PRI_2 2
  359. #define TX_FIFO_PRI_3 3
  360. #define TX_FIFO_PRI_4 4
  361. #define TX_FIFO_PRI_5 5
  362. #define TX_FIFO_PRI_6 6
  363. #define TX_FIFO_PRI_7 7 /*lowest */
  364. u8 fifo_priority; /* specifies pointer level for FIFO */
  365. /* user should not set twos fifos with same pri */
  366. u8 f_no_snoop;
  367. #define NO_SNOOP_TXD 0x01
  368. #define NO_SNOOP_TXD_BUFFER 0x02
  369. };
  370. /* Maintains per Ring related information */
  371. struct rx_ring_config {
  372. u32 num_rxd; /*No of RxDs per Rx Ring */
  373. #define RX_RING_PRI_0 0 /* highest */
  374. #define RX_RING_PRI_1 1
  375. #define RX_RING_PRI_2 2
  376. #define RX_RING_PRI_3 3
  377. #define RX_RING_PRI_4 4
  378. #define RX_RING_PRI_5 5
  379. #define RX_RING_PRI_6 6
  380. #define RX_RING_PRI_7 7 /* lowest */
  381. u8 ring_priority; /*Specifies service priority of ring */
  382. /* OSM should not set any two rings with same priority */
  383. u8 ring_org; /*Organization of ring */
  384. #define RING_ORG_BUFF1 0x01
  385. #define RX_RING_ORG_BUFF3 0x03
  386. #define RX_RING_ORG_BUFF5 0x05
  387. u8 f_no_snoop;
  388. #define NO_SNOOP_RXD 0x01
  389. #define NO_SNOOP_RXD_BUFFER 0x02
  390. };
  391. /* This structure provides contains values of the tunable parameters
  392. * of the H/W
  393. */
  394. struct config_param {
  395. /* Tx Side */
  396. u32 tx_fifo_num; /*Number of Tx FIFOs */
  397. /* 0-No steering, 1-Priority steering, 2-Default fifo map */
  398. #define NO_STEERING 0
  399. #define TX_PRIORITY_STEERING 0x1
  400. #define TX_DEFAULT_STEERING 0x2
  401. u8 tx_steering_type;
  402. u8 fifo_mapping[MAX_TX_FIFOS];
  403. struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
  404. u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
  405. u64 tx_intr_type;
  406. #define INTA 0
  407. #define MSI_X 2
  408. u8 intr_type;
  409. u8 napi;
  410. /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
  411. /* Rx Side */
  412. u32 rx_ring_num; /*Number of receive rings */
  413. #define MAX_RX_BLOCKS_PER_RING 150
  414. struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
  415. #define HEADER_ETHERNET_II_802_3_SIZE 14
  416. #define HEADER_802_2_SIZE 3
  417. #define HEADER_SNAP_SIZE 5
  418. #define HEADER_VLAN_SIZE 4
  419. #define MIN_MTU 46
  420. #define MAX_PYLD 1500
  421. #define MAX_MTU (MAX_PYLD+18)
  422. #define MAX_MTU_VLAN (MAX_PYLD+22)
  423. #define MAX_PYLD_JUMBO 9600
  424. #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
  425. #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
  426. u16 bus_speed;
  427. int max_mc_addr; /* xena=64 herc=256 */
  428. int max_mac_addr; /* xena=16 herc=64 */
  429. int mc_start_offset; /* xena=16 herc=64 */
  430. u8 multiq;
  431. };
  432. /* Structure representing MAC Addrs */
  433. struct mac_addr {
  434. u8 mac_addr[ETH_ALEN];
  435. };
  436. /* Structure that represent every FIFO element in the BAR1
  437. * Address location.
  438. */
  439. struct TxFIFO_element {
  440. u64 TxDL_Pointer;
  441. u64 List_Control;
  442. #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
  443. #define TX_FIFO_FIRST_LIST s2BIT(14)
  444. #define TX_FIFO_LAST_LIST s2BIT(15)
  445. #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
  446. #define TX_FIFO_SPECIAL_FUNC s2BIT(23)
  447. #define TX_FIFO_DS_NO_SNOOP s2BIT(31)
  448. #define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
  449. };
  450. /* Tx descriptor structure */
  451. struct TxD {
  452. u64 Control_1;
  453. /* bit mask */
  454. #define TXD_LIST_OWN_XENA s2BIT(7)
  455. #define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
  456. #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
  457. #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
  458. #define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
  459. #define TXD_GATHER_CODE_FIRST s2BIT(22)
  460. #define TXD_GATHER_CODE_LAST s2BIT(23)
  461. #define TXD_TCP_LSO_EN s2BIT(30)
  462. #define TXD_UDP_COF_EN s2BIT(31)
  463. #define TXD_UFO_EN s2BIT(31) | s2BIT(30)
  464. #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
  465. #define TXD_UFO_MSS(val) vBIT(val,34,14)
  466. #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
  467. u64 Control_2;
  468. #define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
  469. #define TXD_TX_CKO_IPV4_EN s2BIT(5)
  470. #define TXD_TX_CKO_TCP_EN s2BIT(6)
  471. #define TXD_TX_CKO_UDP_EN s2BIT(7)
  472. #define TXD_VLAN_ENABLE s2BIT(15)
  473. #define TXD_VLAN_TAG(val) vBIT(val,16,16)
  474. #define TXD_INT_NUMBER(val) vBIT(val,34,6)
  475. #define TXD_INT_TYPE_PER_LIST s2BIT(47)
  476. #define TXD_INT_TYPE_UTILZ s2BIT(46)
  477. #define TXD_SET_MARKER vBIT(0x6,0,4)
  478. u64 Buffer_Pointer;
  479. u64 Host_Control; /* reserved for host */
  480. };
  481. /* Structure to hold the phy and virt addr of every TxDL. */
  482. struct list_info_hold {
  483. dma_addr_t list_phy_addr;
  484. void *list_virt_addr;
  485. };
  486. /* Rx descriptor structure for 1 buffer mode */
  487. struct RxD_t {
  488. u64 Host_Control; /* reserved for host */
  489. u64 Control_1;
  490. #define RXD_OWN_XENA s2BIT(7)
  491. #define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
  492. #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
  493. #define RXD_FRAME_VLAN_TAG s2BIT(24)
  494. #define RXD_FRAME_PROTO_IPV4 s2BIT(27)
  495. #define RXD_FRAME_PROTO_IPV6 s2BIT(28)
  496. #define RXD_FRAME_IP_FRAG s2BIT(29)
  497. #define RXD_FRAME_PROTO_TCP s2BIT(30)
  498. #define RXD_FRAME_PROTO_UDP s2BIT(31)
  499. #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
  500. #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
  501. #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
  502. u64 Control_2;
  503. #define THE_RXD_MARK 0x3
  504. #define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
  505. #define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
  506. #define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
  507. #define SET_VLAN_TAG(val) vBIT(val,48,16)
  508. #define SET_NUM_TAG(val) vBIT(val,16,32)
  509. };
  510. /* Rx descriptor structure for 1 buffer mode */
  511. struct RxD1 {
  512. struct RxD_t h;
  513. #define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
  514. #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
  515. #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
  516. (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
  517. u64 Buffer0_ptr;
  518. };
  519. /* Rx descriptor structure for 3 or 2 buffer mode */
  520. struct RxD3 {
  521. struct RxD_t h;
  522. #define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
  523. #define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
  524. #define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
  525. #define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
  526. #define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
  527. #define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
  528. #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
  529. (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
  530. #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
  531. (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
  532. #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
  533. (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
  534. #define BUF0_LEN 40
  535. #define BUF1_LEN 1
  536. u64 Buffer0_ptr;
  537. u64 Buffer1_ptr;
  538. u64 Buffer2_ptr;
  539. };
  540. /* Structure that represents the Rx descriptor block which contains
  541. * 128 Rx descriptors.
  542. */
  543. struct RxD_block {
  544. #define MAX_RXDS_PER_BLOCK_1 127
  545. struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
  546. u64 reserved_0;
  547. #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
  548. u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
  549. * Rxd in this blk */
  550. u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
  551. u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
  552. * the upper 32 bits should
  553. * be 0 */
  554. };
  555. #define SIZE_OF_BLOCK 4096
  556. #define RXD_MODE_1 0 /* One Buffer mode */
  557. #define RXD_MODE_3B 1 /* Two Buffer mode */
  558. /* Structure to hold virtual addresses of Buf0 and Buf1 in
  559. * 2buf mode. */
  560. struct buffAdd {
  561. void *ba_0_org;
  562. void *ba_1_org;
  563. void *ba_0;
  564. void *ba_1;
  565. };
  566. /* Structure which stores all the MAC control parameters */
  567. /* This structure stores the offset of the RxD in the ring
  568. * from which the Rx Interrupt processor can start picking
  569. * up the RxDs for processing.
  570. */
  571. struct rx_curr_get_info {
  572. u32 block_index;
  573. u32 offset;
  574. u32 ring_len;
  575. };
  576. struct rx_curr_put_info {
  577. u32 block_index;
  578. u32 offset;
  579. u32 ring_len;
  580. };
  581. /* This structure stores the offset of the TxDl in the FIFO
  582. * from which the Tx Interrupt processor can start picking
  583. * up the TxDLs for send complete interrupt processing.
  584. */
  585. struct tx_curr_get_info {
  586. u32 offset;
  587. u32 fifo_len;
  588. };
  589. struct tx_curr_put_info {
  590. u32 offset;
  591. u32 fifo_len;
  592. };
  593. struct rxd_info {
  594. void *virt_addr;
  595. dma_addr_t dma_addr;
  596. };
  597. /* Structure that holds the Phy and virt addresses of the Blocks */
  598. struct rx_block_info {
  599. void *block_virt_addr;
  600. dma_addr_t block_dma_addr;
  601. struct rxd_info *rxds;
  602. };
  603. /* Data structure to represent a LRO session */
  604. struct lro {
  605. struct sk_buff *parent;
  606. struct sk_buff *last_frag;
  607. u8 *l2h;
  608. struct iphdr *iph;
  609. struct tcphdr *tcph;
  610. u32 tcp_next_seq;
  611. __be32 tcp_ack;
  612. int total_len;
  613. int frags_len;
  614. int sg_num;
  615. int in_use;
  616. __be16 window;
  617. u16 vlan_tag;
  618. u32 cur_tsval;
  619. __be32 cur_tsecr;
  620. u8 saw_ts;
  621. } ____cacheline_aligned;
  622. /* Ring specific structure */
  623. struct ring_info {
  624. /* The ring number */
  625. int ring_no;
  626. /* per-ring buffer counter */
  627. u32 rx_bufs_left;
  628. #define MAX_LRO_SESSIONS 32
  629. struct lro lro0_n[MAX_LRO_SESSIONS];
  630. u8 lro;
  631. /* copy of sp->rxd_mode flag */
  632. int rxd_mode;
  633. /* Number of rxds per block for the rxd_mode */
  634. int rxd_count;
  635. /* copy of sp pointer */
  636. struct s2io_nic *nic;
  637. /* copy of sp->dev pointer */
  638. struct net_device *dev;
  639. /* copy of sp->pdev pointer */
  640. struct pci_dev *pdev;
  641. /*
  642. * Place holders for the virtual and physical addresses of
  643. * all the Rx Blocks
  644. */
  645. struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
  646. int block_count;
  647. int pkt_cnt;
  648. /*
  649. * Put pointer info which indictes which RxD has to be replenished
  650. * with a new buffer.
  651. */
  652. struct rx_curr_put_info rx_curr_put_info;
  653. /*
  654. * Get pointer info which indictes which is the last RxD that was
  655. * processed by the driver.
  656. */
  657. struct rx_curr_get_info rx_curr_get_info;
  658. /* interface MTU value */
  659. unsigned mtu;
  660. /* Buffer Address store. */
  661. struct buffAdd **ba;
  662. /* per-Ring statistics */
  663. unsigned long rx_packets;
  664. unsigned long rx_bytes;
  665. } ____cacheline_aligned;
  666. /* Fifo specific structure */
  667. struct fifo_info {
  668. /* FIFO number */
  669. int fifo_no;
  670. /* Maximum TxDs per TxDL */
  671. int max_txds;
  672. /* Place holder of all the TX List's Phy and Virt addresses. */
  673. struct list_info_hold *list_info;
  674. /*
  675. * Current offset within the tx FIFO where driver would write
  676. * new Tx frame
  677. */
  678. struct tx_curr_put_info tx_curr_put_info;
  679. /*
  680. * Current offset within tx FIFO from where the driver would start freeing
  681. * the buffers
  682. */
  683. struct tx_curr_get_info tx_curr_get_info;
  684. #define FIFO_QUEUE_START 0
  685. #define FIFO_QUEUE_STOP 1
  686. int queue_state;
  687. /* copy of sp->dev pointer */
  688. struct net_device *dev;
  689. /* copy of multiq status */
  690. u8 multiq;
  691. /* Per fifo lock */
  692. spinlock_t tx_lock;
  693. /* Per fifo UFO in band structure */
  694. u64 *ufo_in_band_v;
  695. struct s2io_nic *nic;
  696. } ____cacheline_aligned;
  697. /* Information related to the Tx and Rx FIFOs and Rings of Xena
  698. * is maintained in this structure.
  699. */
  700. struct mac_info {
  701. /* tx side stuff */
  702. /* logical pointer of start of each Tx FIFO */
  703. struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
  704. /* Fifo specific structure */
  705. struct fifo_info fifos[MAX_TX_FIFOS];
  706. /* Save virtual address of TxD page with zero DMA addr(if any) */
  707. void *zerodma_virt_addr;
  708. /* rx side stuff */
  709. /* Ring specific structure */
  710. struct ring_info rings[MAX_RX_RINGS];
  711. u16 rmac_pause_time;
  712. u16 mc_pause_threshold_q0q3;
  713. u16 mc_pause_threshold_q4q7;
  714. void *stats_mem; /* orignal pointer to allocated mem */
  715. dma_addr_t stats_mem_phy; /* Physical address of the stat block */
  716. u32 stats_mem_sz;
  717. struct stat_block *stats_info; /* Logical address of the stat block */
  718. };
  719. /* structure representing the user defined MAC addresses */
  720. struct usr_addr {
  721. char addr[ETH_ALEN];
  722. int usage_cnt;
  723. };
  724. /* Default Tunable parameters of the NIC. */
  725. #define DEFAULT_FIFO_0_LEN 4096
  726. #define DEFAULT_FIFO_1_7_LEN 512
  727. #define SMALL_BLK_CNT 30
  728. #define LARGE_BLK_CNT 100
  729. /*
  730. * Structure to keep track of the MSI-X vectors and the corresponding
  731. * argument registered against each vector
  732. */
  733. #define MAX_REQUESTED_MSI_X 17
  734. struct s2io_msix_entry
  735. {
  736. u16 vector;
  737. u16 entry;
  738. void *arg;
  739. u8 type;
  740. #define MSIX_FIFO_TYPE 1
  741. #define MSIX_RING_TYPE 2
  742. u8 in_use;
  743. #define MSIX_REGISTERED_SUCCESS 0xAA
  744. };
  745. struct msix_info_st {
  746. u64 addr;
  747. u64 data;
  748. };
  749. /* These flags represent the devices temporary state */
  750. enum s2io_device_state_t
  751. {
  752. __S2IO_STATE_LINK_TASK=0,
  753. __S2IO_STATE_CARD_UP
  754. };
  755. /* Structure representing one instance of the NIC */
  756. struct s2io_nic {
  757. int rxd_mode;
  758. /*
  759. * Count of packets to be processed in a given iteration, it will be indicated
  760. * by the quota field of the device structure when NAPI is enabled.
  761. */
  762. int pkts_to_process;
  763. struct net_device *dev;
  764. struct napi_struct napi;
  765. struct mac_info mac_control;
  766. struct config_param config;
  767. struct pci_dev *pdev;
  768. void __iomem *bar0;
  769. void __iomem *bar1;
  770. #define MAX_MAC_SUPPORTED 16
  771. #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
  772. struct mac_addr def_mac_addr[256];
  773. struct net_device_stats stats;
  774. int high_dma_flag;
  775. int device_enabled_once;
  776. char name[60];
  777. /* Timer that handles I/O errors/exceptions */
  778. struct timer_list alarm_timer;
  779. /* Space to back up the PCI config space */
  780. u32 config_space[256 / sizeof(u32)];
  781. #define PROMISC 1
  782. #define ALL_MULTI 2
  783. #define MAX_ADDRS_SUPPORTED 64
  784. u16 usr_addr_count;
  785. u16 mc_addr_count;
  786. struct usr_addr usr_addrs[256];
  787. u16 m_cast_flg;
  788. u16 all_multi_pos;
  789. u16 promisc_flg;
  790. /* Id timer, used to blink NIC to physically identify NIC. */
  791. struct timer_list id_timer;
  792. /* Restart timer, used to restart NIC if the device is stuck and
  793. * a schedule task that will set the correct Link state once the
  794. * NIC's PHY has stabilized after a state change.
  795. */
  796. struct work_struct rst_timer_task;
  797. struct work_struct set_link_task;
  798. /* Flag that can be used to turn on or turn off the Rx checksum
  799. * offload feature.
  800. */
  801. int rx_csum;
  802. /* Below variables are used for fifo selection to transmit a packet */
  803. u16 fifo_selector[MAX_TX_FIFOS];
  804. /* Total fifos for tcp packets */
  805. u8 total_tcp_fifos;
  806. /*
  807. * Beginning index of udp for udp packets
  808. * Value will be equal to
  809. * (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM)
  810. */
  811. u8 udp_fifo_idx;
  812. u8 total_udp_fifos;
  813. /*
  814. * Beginning index of fifo for all other packets
  815. * Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM)
  816. */
  817. u8 other_fifo_idx;
  818. /* after blink, the adapter must be restored with original
  819. * values.
  820. */
  821. u64 adapt_ctrl_org;
  822. /* Last known link state. */
  823. u16 last_link_state;
  824. #define LINK_DOWN 1
  825. #define LINK_UP 2
  826. int task_flag;
  827. unsigned long long start_time;
  828. struct vlan_group *vlgrp;
  829. #define MSIX_FLG 0xA5
  830. struct msix_entry *entries;
  831. int msi_detected;
  832. wait_queue_head_t msi_wait;
  833. struct s2io_msix_entry *s2io_entries;
  834. char desc[MAX_REQUESTED_MSI_X][25];
  835. int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
  836. struct msix_info_st msix_info[0x3f];
  837. #define XFRAME_I_DEVICE 1
  838. #define XFRAME_II_DEVICE 2
  839. u8 device_type;
  840. unsigned long clubbed_frms_cnt;
  841. unsigned long sending_both;
  842. u8 lro;
  843. u16 lro_max_aggr_per_sess;
  844. volatile unsigned long state;
  845. u64 general_int_mask;
  846. #define VPD_STRING_LEN 80
  847. u8 product_name[VPD_STRING_LEN];
  848. u8 serial_num[VPD_STRING_LEN];
  849. };
  850. #define RESET_ERROR 1;
  851. #define CMD_ERROR 2;
  852. /* OS related system calls */
  853. #ifndef readq
  854. static inline u64 readq(void __iomem *addr)
  855. {
  856. u64 ret = 0;
  857. ret = readl(addr + 4);
  858. ret <<= 32;
  859. ret |= readl(addr);
  860. return ret;
  861. }
  862. #endif
  863. #ifndef writeq
  864. static inline void writeq(u64 val, void __iomem *addr)
  865. {
  866. writel((u32) (val), addr);
  867. writel((u32) (val >> 32), (addr + 4));
  868. }
  869. #endif
  870. /*
  871. * Some registers have to be written in a particular order to
  872. * expect correct hardware operation. The macro SPECIAL_REG_WRITE
  873. * is used to perform such ordered writes. Defines UF (Upper First)
  874. * and LF (Lower First) will be used to specify the required write order.
  875. */
  876. #define UF 1
  877. #define LF 2
  878. static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
  879. {
  880. u32 ret;
  881. if (order == LF) {
  882. writel((u32) (val), addr);
  883. ret = readl(addr);
  884. writel((u32) (val >> 32), (addr + 4));
  885. ret = readl(addr + 4);
  886. } else {
  887. writel((u32) (val >> 32), (addr + 4));
  888. ret = readl(addr + 4);
  889. writel((u32) (val), addr);
  890. ret = readl(addr);
  891. }
  892. }
  893. /* Interrupt related values of Xena */
  894. #define ENABLE_INTRS 1
  895. #define DISABLE_INTRS 2
  896. /* Highest level interrupt blocks */
  897. #define TX_PIC_INTR (0x0001<<0)
  898. #define TX_DMA_INTR (0x0001<<1)
  899. #define TX_MAC_INTR (0x0001<<2)
  900. #define TX_XGXS_INTR (0x0001<<3)
  901. #define TX_TRAFFIC_INTR (0x0001<<4)
  902. #define RX_PIC_INTR (0x0001<<5)
  903. #define RX_DMA_INTR (0x0001<<6)
  904. #define RX_MAC_INTR (0x0001<<7)
  905. #define RX_XGXS_INTR (0x0001<<8)
  906. #define RX_TRAFFIC_INTR (0x0001<<9)
  907. #define MC_INTR (0x0001<<10)
  908. #define ENA_ALL_INTRS ( TX_PIC_INTR | \
  909. TX_DMA_INTR | \
  910. TX_MAC_INTR | \
  911. TX_XGXS_INTR | \
  912. TX_TRAFFIC_INTR | \
  913. RX_PIC_INTR | \
  914. RX_DMA_INTR | \
  915. RX_MAC_INTR | \
  916. RX_XGXS_INTR | \
  917. RX_TRAFFIC_INTR | \
  918. MC_INTR )
  919. /* Interrupt masks for the general interrupt mask register */
  920. #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
  921. #define TXPIC_INT_M s2BIT(0)
  922. #define TXDMA_INT_M s2BIT(1)
  923. #define TXMAC_INT_M s2BIT(2)
  924. #define TXXGXS_INT_M s2BIT(3)
  925. #define TXTRAFFIC_INT_M s2BIT(8)
  926. #define PIC_RX_INT_M s2BIT(32)
  927. #define RXDMA_INT_M s2BIT(33)
  928. #define RXMAC_INT_M s2BIT(34)
  929. #define MC_INT_M s2BIT(35)
  930. #define RXXGXS_INT_M s2BIT(36)
  931. #define RXTRAFFIC_INT_M s2BIT(40)
  932. /* PIC level Interrupts TODO*/
  933. /* DMA level Inressupts */
  934. #define TXDMA_PFC_INT_M s2BIT(0)
  935. #define TXDMA_PCC_INT_M s2BIT(2)
  936. /* PFC block interrupts */
  937. #define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
  938. /* PCC block interrupts. */
  939. #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
  940. PCC_FB_ECC Error. */
  941. #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
  942. /*
  943. * Prototype declaration.
  944. */
  945. static int __devinit s2io_init_nic(struct pci_dev *pdev,
  946. const struct pci_device_id *pre);
  947. static void __devexit s2io_rem_nic(struct pci_dev *pdev);
  948. static int init_shared_mem(struct s2io_nic *sp);
  949. static void free_shared_mem(struct s2io_nic *sp);
  950. static int init_nic(struct s2io_nic *nic);
  951. static void rx_intr_handler(struct ring_info *ring_data);
  952. static void tx_intr_handler(struct fifo_info *fifo_data);
  953. static void s2io_handle_errors(void * dev_id);
  954. static int s2io_starter(void);
  955. static void s2io_closer(void);
  956. static void s2io_tx_watchdog(struct net_device *dev);
  957. static void s2io_set_multicast(struct net_device *dev);
  958. static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
  959. static void s2io_link(struct s2io_nic * sp, int link);
  960. static void s2io_reset(struct s2io_nic * sp);
  961. static int s2io_poll(struct napi_struct *napi, int budget);
  962. static void s2io_init_pci(struct s2io_nic * sp);
  963. static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
  964. static void s2io_alarm_handle(unsigned long data);
  965. static irqreturn_t
  966. s2io_msix_ring_handle(int irq, void *dev_id);
  967. static irqreturn_t
  968. s2io_msix_fifo_handle(int irq, void *dev_id);
  969. static irqreturn_t s2io_isr(int irq, void *dev_id);
  970. static int verify_xena_quiescence(struct s2io_nic *sp);
  971. static const struct ethtool_ops netdev_ethtool_ops;
  972. static void s2io_set_link(struct work_struct *work);
  973. static int s2io_set_swapper(struct s2io_nic * sp);
  974. static void s2io_card_down(struct s2io_nic *nic);
  975. static int s2io_card_up(struct s2io_nic *nic);
  976. static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
  977. int bit_state);
  978. static int s2io_add_isr(struct s2io_nic * sp);
  979. static void s2io_rem_isr(struct s2io_nic * sp);
  980. static void restore_xmsi_data(struct s2io_nic *nic);
  981. static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
  982. static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
  983. static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
  984. static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
  985. static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
  986. static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
  987. static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
  988. u8 **tcp, u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
  989. struct s2io_nic *sp);
  990. static void clear_lro_session(struct lro *lro);
  991. static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag);
  992. static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
  993. static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
  994. struct sk_buff *skb, u32 tcp_len);
  995. static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
  996. static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
  997. pci_channel_state_t state);
  998. static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
  999. static void s2io_io_resume(struct pci_dev *pdev);
  1000. #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
  1001. #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
  1002. #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
  1003. #define S2IO_PARM_INT(X, def_val) \
  1004. static unsigned int X = def_val;\
  1005. module_param(X , uint, 0);
  1006. #endif /* _S2IO_H */