r6040.c 29 KB

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  1. /*
  2. * RDC R6040 Fast Ethernet MAC support
  3. *
  4. * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
  5. * Copyright (C) 2007
  6. * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
  7. * Florian Fainelli <florian@openwrt.org>
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version 2
  12. * of the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the
  21. * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  22. * Boston, MA 02110-1301, USA.
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/version.h>
  27. #include <linux/moduleparam.h>
  28. #include <linux/string.h>
  29. #include <linux/timer.h>
  30. #include <linux/errno.h>
  31. #include <linux/ioport.h>
  32. #include <linux/slab.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/pci.h>
  35. #include <linux/netdevice.h>
  36. #include <linux/etherdevice.h>
  37. #include <linux/skbuff.h>
  38. #include <linux/init.h>
  39. #include <linux/delay.h>
  40. #include <linux/mii.h>
  41. #include <linux/ethtool.h>
  42. #include <linux/crc32.h>
  43. #include <linux/spinlock.h>
  44. #include <linux/bitops.h>
  45. #include <linux/io.h>
  46. #include <linux/irq.h>
  47. #include <linux/uaccess.h>
  48. #include <asm/processor.h>
  49. #define DRV_NAME "r6040"
  50. #define DRV_VERSION "0.16"
  51. #define DRV_RELDATE "10Nov2007"
  52. /* PHY CHIP Address */
  53. #define PHY1_ADDR 1 /* For MAC1 */
  54. #define PHY2_ADDR 2 /* For MAC2 */
  55. #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
  56. #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
  57. /* Time in jiffies before concluding the transmitter is hung. */
  58. #define TX_TIMEOUT (6000 * HZ / 1000)
  59. /* RDC MAC I/O Size */
  60. #define R6040_IO_SIZE 256
  61. /* MAX RDC MAC */
  62. #define MAX_MAC 2
  63. /* MAC registers */
  64. #define MCR0 0x00 /* Control register 0 */
  65. #define MCR1 0x04 /* Control register 1 */
  66. #define MAC_RST 0x0001 /* Reset the MAC */
  67. #define MBCR 0x08 /* Bus control */
  68. #define MT_ICR 0x0C /* TX interrupt control */
  69. #define MR_ICR 0x10 /* RX interrupt control */
  70. #define MTPR 0x14 /* TX poll command register */
  71. #define MR_BSR 0x18 /* RX buffer size */
  72. #define MR_DCR 0x1A /* RX descriptor control */
  73. #define MLSR 0x1C /* Last status */
  74. #define MMDIO 0x20 /* MDIO control register */
  75. #define MDIO_WRITE 0x4000 /* MDIO write */
  76. #define MDIO_READ 0x2000 /* MDIO read */
  77. #define MMRD 0x24 /* MDIO read data register */
  78. #define MMWD 0x28 /* MDIO write data register */
  79. #define MTD_SA0 0x2C /* TX descriptor start address 0 */
  80. #define MTD_SA1 0x30 /* TX descriptor start address 1 */
  81. #define MRD_SA0 0x34 /* RX descriptor start address 0 */
  82. #define MRD_SA1 0x38 /* RX descriptor start address 1 */
  83. #define MISR 0x3C /* Status register */
  84. #define MIER 0x40 /* INT enable register */
  85. #define MSK_INT 0x0000 /* Mask off interrupts */
  86. #define ME_CISR 0x44 /* Event counter INT status */
  87. #define ME_CIER 0x48 /* Event counter INT enable */
  88. #define MR_CNT 0x50 /* Successfully received packet counter */
  89. #define ME_CNT0 0x52 /* Event counter 0 */
  90. #define ME_CNT1 0x54 /* Event counter 1 */
  91. #define ME_CNT2 0x56 /* Event counter 2 */
  92. #define ME_CNT3 0x58 /* Event counter 3 */
  93. #define MT_CNT 0x5A /* Successfully transmit packet counter */
  94. #define ME_CNT4 0x5C /* Event counter 4 */
  95. #define MP_CNT 0x5E /* Pause frame counter register */
  96. #define MAR0 0x60 /* Hash table 0 */
  97. #define MAR1 0x62 /* Hash table 1 */
  98. #define MAR2 0x64 /* Hash table 2 */
  99. #define MAR3 0x66 /* Hash table 3 */
  100. #define MID_0L 0x68 /* Multicast address MID0 Low */
  101. #define MID_0M 0x6A /* Multicast address MID0 Medium */
  102. #define MID_0H 0x6C /* Multicast address MID0 High */
  103. #define MID_1L 0x70 /* MID1 Low */
  104. #define MID_1M 0x72 /* MID1 Medium */
  105. #define MID_1H 0x74 /* MID1 High */
  106. #define MID_2L 0x78 /* MID2 Low */
  107. #define MID_2M 0x7A /* MID2 Medium */
  108. #define MID_2H 0x7C /* MID2 High */
  109. #define MID_3L 0x80 /* MID3 Low */
  110. #define MID_3M 0x82 /* MID3 Medium */
  111. #define MID_3H 0x84 /* MID3 High */
  112. #define PHY_CC 0x88 /* PHY status change configuration register */
  113. #define PHY_ST 0x8A /* PHY status register */
  114. #define MAC_SM 0xAC /* MAC status machine */
  115. #define MAC_ID 0xBE /* Identifier register */
  116. #define TX_DCNT 0x80 /* TX descriptor count */
  117. #define RX_DCNT 0x80 /* RX descriptor count */
  118. #define MAX_BUF_SIZE 0x600
  119. #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
  120. #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
  121. #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
  122. #define MCAST_MAX 4 /* Max number multicast addresses to filter */
  123. /* PHY settings */
  124. #define ICPLUS_PHY_ID 0x0243
  125. MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
  126. "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
  127. "Florian Fainelli <florian@openwrt.org>");
  128. MODULE_LICENSE("GPL");
  129. MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
  130. #define RX_INT 0x0001
  131. #define TX_INT 0x0010
  132. #define RX_NO_DESC_INT 0x0002
  133. #define INT_MASK (RX_INT | TX_INT)
  134. struct r6040_descriptor {
  135. u16 status, len; /* 0-3 */
  136. __le32 buf; /* 4-7 */
  137. __le32 ndesc; /* 8-B */
  138. u32 rev1; /* C-F */
  139. char *vbufp; /* 10-13 */
  140. struct r6040_descriptor *vndescp; /* 14-17 */
  141. struct sk_buff *skb_ptr; /* 18-1B */
  142. u32 rev2; /* 1C-1F */
  143. } __attribute__((aligned(32)));
  144. struct r6040_private {
  145. spinlock_t lock; /* driver lock */
  146. struct timer_list timer;
  147. struct pci_dev *pdev;
  148. struct r6040_descriptor *rx_insert_ptr;
  149. struct r6040_descriptor *rx_remove_ptr;
  150. struct r6040_descriptor *tx_insert_ptr;
  151. struct r6040_descriptor *tx_remove_ptr;
  152. struct r6040_descriptor *rx_ring;
  153. struct r6040_descriptor *tx_ring;
  154. dma_addr_t rx_ring_dma;
  155. dma_addr_t tx_ring_dma;
  156. u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
  157. u16 mcr0, mcr1;
  158. u16 switch_sig;
  159. struct net_device *dev;
  160. struct mii_if_info mii_if;
  161. struct napi_struct napi;
  162. void __iomem *base;
  163. };
  164. static char version[] __devinitdata = KERN_INFO DRV_NAME
  165. ": RDC R6040 NAPI net driver,"
  166. "version "DRV_VERSION " (" DRV_RELDATE ")\n";
  167. static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
  168. /* Read a word data from PHY Chip */
  169. static int phy_read(void __iomem *ioaddr, int phy_addr, int reg)
  170. {
  171. int limit = 2048;
  172. u16 cmd;
  173. iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
  174. /* Wait for the read bit to be cleared */
  175. while (limit--) {
  176. cmd = ioread16(ioaddr + MMDIO);
  177. if (cmd & MDIO_READ)
  178. break;
  179. }
  180. return ioread16(ioaddr + MMRD);
  181. }
  182. /* Write a word data from PHY Chip */
  183. static void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
  184. {
  185. int limit = 2048;
  186. u16 cmd;
  187. iowrite16(val, ioaddr + MMWD);
  188. /* Write the command to the MDIO bus */
  189. iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
  190. /* Wait for the write bit to be cleared */
  191. while (limit--) {
  192. cmd = ioread16(ioaddr + MMDIO);
  193. if (cmd & MDIO_WRITE)
  194. break;
  195. }
  196. }
  197. static int mdio_read(struct net_device *dev, int mii_id, int reg)
  198. {
  199. struct r6040_private *lp = netdev_priv(dev);
  200. void __iomem *ioaddr = lp->base;
  201. return (phy_read(ioaddr, lp->phy_addr, reg));
  202. }
  203. static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
  204. {
  205. struct r6040_private *lp = netdev_priv(dev);
  206. void __iomem *ioaddr = lp->base;
  207. phy_write(ioaddr, lp->phy_addr, reg, val);
  208. }
  209. static void r6040_free_txbufs(struct net_device *dev)
  210. {
  211. struct r6040_private *lp = netdev_priv(dev);
  212. int i;
  213. for (i = 0; i < TX_DCNT; i++) {
  214. if (lp->tx_insert_ptr->skb_ptr) {
  215. pci_unmap_single(lp->pdev,
  216. le32_to_cpu(lp->tx_insert_ptr->buf),
  217. MAX_BUF_SIZE, PCI_DMA_TODEVICE);
  218. dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
  219. lp->rx_insert_ptr->skb_ptr = NULL;
  220. }
  221. lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
  222. }
  223. }
  224. static void r6040_free_rxbufs(struct net_device *dev)
  225. {
  226. struct r6040_private *lp = netdev_priv(dev);
  227. int i;
  228. for (i = 0; i < RX_DCNT; i++) {
  229. if (lp->rx_insert_ptr->skb_ptr) {
  230. pci_unmap_single(lp->pdev,
  231. le32_to_cpu(lp->rx_insert_ptr->buf),
  232. MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  233. dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
  234. lp->rx_insert_ptr->skb_ptr = NULL;
  235. }
  236. lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
  237. }
  238. }
  239. static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
  240. dma_addr_t desc_dma, int size)
  241. {
  242. struct r6040_descriptor *desc = desc_ring;
  243. dma_addr_t mapping = desc_dma;
  244. while (size-- > 0) {
  245. mapping += sizeof(sizeof(*desc));
  246. desc->ndesc = cpu_to_le32(mapping);
  247. desc->vndescp = desc + 1;
  248. desc++;
  249. }
  250. desc--;
  251. desc->ndesc = cpu_to_le32(desc_dma);
  252. desc->vndescp = desc_ring;
  253. }
  254. /* Allocate skb buffer for rx descriptor */
  255. static void rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
  256. {
  257. struct r6040_descriptor *descptr;
  258. void __iomem *ioaddr = lp->base;
  259. descptr = lp->rx_insert_ptr;
  260. while (lp->rx_free_desc < RX_DCNT) {
  261. descptr->skb_ptr = netdev_alloc_skb(dev, MAX_BUF_SIZE);
  262. if (!descptr->skb_ptr)
  263. break;
  264. descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
  265. descptr->skb_ptr->data,
  266. MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
  267. descptr->status = 0x8000;
  268. descptr = descptr->vndescp;
  269. lp->rx_free_desc++;
  270. /* Trigger RX DMA */
  271. iowrite16(lp->mcr0 | 0x0002, ioaddr);
  272. }
  273. lp->rx_insert_ptr = descptr;
  274. }
  275. static void r6040_alloc_txbufs(struct net_device *dev)
  276. {
  277. struct r6040_private *lp = netdev_priv(dev);
  278. void __iomem *ioaddr = lp->base;
  279. lp->tx_free_desc = TX_DCNT;
  280. lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
  281. r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
  282. iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
  283. iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
  284. }
  285. static void r6040_alloc_rxbufs(struct net_device *dev)
  286. {
  287. struct r6040_private *lp = netdev_priv(dev);
  288. void __iomem *ioaddr = lp->base;
  289. lp->rx_free_desc = 0;
  290. lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
  291. r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
  292. rx_buf_alloc(lp, dev);
  293. iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
  294. iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
  295. }
  296. static void r6040_tx_timeout(struct net_device *dev)
  297. {
  298. struct r6040_private *priv = netdev_priv(dev);
  299. void __iomem *ioaddr = priv->base;
  300. printk(KERN_WARNING "%s: transmit timed out, status %4.4x, PHY status "
  301. "%4.4x\n",
  302. dev->name, ioread16(ioaddr + MIER),
  303. mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
  304. disable_irq(dev->irq);
  305. napi_disable(&priv->napi);
  306. spin_lock(&priv->lock);
  307. /* Clear all descriptors */
  308. r6040_free_txbufs(dev);
  309. r6040_free_rxbufs(dev);
  310. r6040_alloc_txbufs(dev);
  311. r6040_alloc_rxbufs(dev);
  312. /* Reset MAC */
  313. iowrite16(MAC_RST, ioaddr + MCR1);
  314. spin_unlock(&priv->lock);
  315. enable_irq(dev->irq);
  316. dev->stats.tx_errors++;
  317. netif_wake_queue(dev);
  318. }
  319. static struct net_device_stats *r6040_get_stats(struct net_device *dev)
  320. {
  321. struct r6040_private *priv = netdev_priv(dev);
  322. void __iomem *ioaddr = priv->base;
  323. unsigned long flags;
  324. spin_lock_irqsave(&priv->lock, flags);
  325. dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
  326. dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
  327. spin_unlock_irqrestore(&priv->lock, flags);
  328. return &dev->stats;
  329. }
  330. /* Stop RDC MAC and Free the allocated resource */
  331. static void r6040_down(struct net_device *dev)
  332. {
  333. struct r6040_private *lp = netdev_priv(dev);
  334. void __iomem *ioaddr = lp->base;
  335. struct pci_dev *pdev = lp->pdev;
  336. int limit = 2048;
  337. u16 *adrp;
  338. u16 cmd;
  339. /* Stop MAC */
  340. iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
  341. iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
  342. while (limit--) {
  343. cmd = ioread16(ioaddr + MCR1);
  344. if (cmd & 0x1)
  345. break;
  346. }
  347. /* Restore MAC Address to MIDx */
  348. adrp = (u16 *) dev->dev_addr;
  349. iowrite16(adrp[0], ioaddr + MID_0L);
  350. iowrite16(adrp[1], ioaddr + MID_0M);
  351. iowrite16(adrp[2], ioaddr + MID_0H);
  352. free_irq(dev->irq, dev);
  353. /* Free RX buffer */
  354. r6040_free_rxbufs(dev);
  355. /* Free TX buffer */
  356. r6040_free_txbufs(dev);
  357. /* Free Descriptor memory */
  358. pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
  359. pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
  360. }
  361. static int r6040_close(struct net_device *dev)
  362. {
  363. struct r6040_private *lp = netdev_priv(dev);
  364. /* deleted timer */
  365. del_timer_sync(&lp->timer);
  366. spin_lock_irq(&lp->lock);
  367. netif_stop_queue(dev);
  368. r6040_down(dev);
  369. spin_unlock_irq(&lp->lock);
  370. return 0;
  371. }
  372. /* Status of PHY CHIP */
  373. static int phy_mode_chk(struct net_device *dev)
  374. {
  375. struct r6040_private *lp = netdev_priv(dev);
  376. void __iomem *ioaddr = lp->base;
  377. int phy_dat;
  378. /* PHY Link Status Check */
  379. phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
  380. if (!(phy_dat & 0x4))
  381. phy_dat = 0x8000; /* Link Failed, full duplex */
  382. /* PHY Chip Auto-Negotiation Status */
  383. phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
  384. if (phy_dat & 0x0020) {
  385. /* Auto Negotiation Mode */
  386. phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
  387. phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
  388. if (phy_dat & 0x140)
  389. /* Force full duplex */
  390. phy_dat = 0x8000;
  391. else
  392. phy_dat = 0;
  393. } else {
  394. /* Force Mode */
  395. phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
  396. if (phy_dat & 0x100)
  397. phy_dat = 0x8000;
  398. else
  399. phy_dat = 0x0000;
  400. }
  401. return phy_dat;
  402. };
  403. static void r6040_set_carrier(struct mii_if_info *mii)
  404. {
  405. if (phy_mode_chk(mii->dev)) {
  406. /* autoneg is off: Link is always assumed to be up */
  407. if (!netif_carrier_ok(mii->dev))
  408. netif_carrier_on(mii->dev);
  409. } else
  410. phy_mode_chk(mii->dev);
  411. }
  412. static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  413. {
  414. struct r6040_private *lp = netdev_priv(dev);
  415. struct mii_ioctl_data *data = if_mii(rq);
  416. int rc;
  417. if (!netif_running(dev))
  418. return -EINVAL;
  419. spin_lock_irq(&lp->lock);
  420. rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
  421. spin_unlock_irq(&lp->lock);
  422. r6040_set_carrier(&lp->mii_if);
  423. return rc;
  424. }
  425. static int r6040_rx(struct net_device *dev, int limit)
  426. {
  427. struct r6040_private *priv = netdev_priv(dev);
  428. int count;
  429. void __iomem *ioaddr = priv->base;
  430. u16 err;
  431. for (count = 0; count < limit; ++count) {
  432. struct r6040_descriptor *descptr = priv->rx_remove_ptr;
  433. struct sk_buff *skb_ptr;
  434. /* Disable RX interrupt */
  435. iowrite16(ioread16(ioaddr + MIER) & (~RX_INT), ioaddr + MIER);
  436. descptr = priv->rx_remove_ptr;
  437. /* Check for errors */
  438. err = ioread16(ioaddr + MLSR);
  439. if (err & 0x0400)
  440. dev->stats.rx_errors++;
  441. /* RX FIFO over-run */
  442. if (err & 0x8000)
  443. dev->stats.rx_fifo_errors++;
  444. /* RX descriptor unavailable */
  445. if (err & 0x0080)
  446. dev->stats.rx_frame_errors++;
  447. /* Received packet with length over buffer lenght */
  448. if (err & 0x0020)
  449. dev->stats.rx_over_errors++;
  450. /* Received packet with too long or short */
  451. if (err & (0x0010 | 0x0008))
  452. dev->stats.rx_length_errors++;
  453. /* Received packet with CRC errors */
  454. if (err & 0x0004) {
  455. spin_lock(&priv->lock);
  456. dev->stats.rx_crc_errors++;
  457. spin_unlock(&priv->lock);
  458. }
  459. while (priv->rx_free_desc) {
  460. /* No RX packet */
  461. if (descptr->status & 0x8000)
  462. break;
  463. skb_ptr = descptr->skb_ptr;
  464. if (!skb_ptr) {
  465. printk(KERN_ERR "%s: Inconsistent RX"
  466. "descriptor chain\n",
  467. dev->name);
  468. break;
  469. }
  470. descptr->skb_ptr = NULL;
  471. skb_ptr->dev = priv->dev;
  472. /* Do not count the CRC */
  473. skb_put(skb_ptr, descptr->len - 4);
  474. pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
  475. MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  476. skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
  477. /* Send to upper layer */
  478. netif_receive_skb(skb_ptr);
  479. dev->last_rx = jiffies;
  480. dev->stats.rx_packets++;
  481. dev->stats.rx_bytes += descptr->len;
  482. /* To next descriptor */
  483. descptr = descptr->vndescp;
  484. priv->rx_free_desc--;
  485. }
  486. priv->rx_remove_ptr = descptr;
  487. }
  488. /* Allocate new RX buffer */
  489. if (priv->rx_free_desc < RX_DCNT)
  490. rx_buf_alloc(priv, priv->dev);
  491. return count;
  492. }
  493. static void r6040_tx(struct net_device *dev)
  494. {
  495. struct r6040_private *priv = netdev_priv(dev);
  496. struct r6040_descriptor *descptr;
  497. void __iomem *ioaddr = priv->base;
  498. struct sk_buff *skb_ptr;
  499. u16 err;
  500. spin_lock(&priv->lock);
  501. descptr = priv->tx_remove_ptr;
  502. while (priv->tx_free_desc < TX_DCNT) {
  503. /* Check for errors */
  504. err = ioread16(ioaddr + MLSR);
  505. if (err & 0x0200)
  506. dev->stats.rx_fifo_errors++;
  507. if (err & (0x2000 | 0x4000))
  508. dev->stats.tx_carrier_errors++;
  509. if (descptr->status & 0x8000)
  510. break; /* Not complete */
  511. skb_ptr = descptr->skb_ptr;
  512. pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
  513. skb_ptr->len, PCI_DMA_TODEVICE);
  514. /* Free buffer */
  515. dev_kfree_skb_irq(skb_ptr);
  516. descptr->skb_ptr = NULL;
  517. /* To next descriptor */
  518. descptr = descptr->vndescp;
  519. priv->tx_free_desc++;
  520. }
  521. priv->tx_remove_ptr = descptr;
  522. if (priv->tx_free_desc)
  523. netif_wake_queue(dev);
  524. spin_unlock(&priv->lock);
  525. }
  526. static int r6040_poll(struct napi_struct *napi, int budget)
  527. {
  528. struct r6040_private *priv =
  529. container_of(napi, struct r6040_private, napi);
  530. struct net_device *dev = priv->dev;
  531. void __iomem *ioaddr = priv->base;
  532. int work_done;
  533. work_done = r6040_rx(dev, budget);
  534. if (work_done < budget) {
  535. netif_rx_complete(dev, napi);
  536. /* Enable RX interrupt */
  537. iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
  538. }
  539. return work_done;
  540. }
  541. /* The RDC interrupt handler. */
  542. static irqreturn_t r6040_interrupt(int irq, void *dev_id)
  543. {
  544. struct net_device *dev = dev_id;
  545. struct r6040_private *lp = netdev_priv(dev);
  546. void __iomem *ioaddr = lp->base;
  547. u16 status;
  548. /* Mask off RDC MAC interrupt */
  549. iowrite16(MSK_INT, ioaddr + MIER);
  550. /* Read MISR status and clear */
  551. status = ioread16(ioaddr + MISR);
  552. if (status == 0x0000 || status == 0xffff)
  553. return IRQ_NONE;
  554. /* RX interrupt request */
  555. if (status & 0x01) {
  556. netif_rx_schedule(dev, &lp->napi);
  557. iowrite16(TX_INT, ioaddr + MIER);
  558. }
  559. /* TX interrupt request */
  560. if (status & 0x10)
  561. r6040_tx(dev);
  562. return IRQ_HANDLED;
  563. }
  564. #ifdef CONFIG_NET_POLL_CONTROLLER
  565. static void r6040_poll_controller(struct net_device *dev)
  566. {
  567. disable_irq(dev->irq);
  568. r6040_interrupt(dev->irq, dev);
  569. enable_irq(dev->irq);
  570. }
  571. #endif
  572. /* Init RDC MAC */
  573. static void r6040_up(struct net_device *dev)
  574. {
  575. struct r6040_private *lp = netdev_priv(dev);
  576. void __iomem *ioaddr = lp->base;
  577. /* Initialise and alloc RX/TX buffers */
  578. r6040_alloc_txbufs(dev);
  579. r6040_alloc_rxbufs(dev);
  580. /* Buffer Size Register */
  581. iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
  582. /* Read the PHY ID */
  583. lp->switch_sig = phy_read(ioaddr, 0, 2);
  584. if (lp->switch_sig == ICPLUS_PHY_ID) {
  585. phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
  586. lp->phy_mode = 0x8000;
  587. } else {
  588. /* PHY Mode Check */
  589. phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
  590. phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
  591. if (PHY_MODE == 0x3100)
  592. lp->phy_mode = phy_mode_chk(dev);
  593. else
  594. lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
  595. }
  596. /* MAC Bus Control Register */
  597. iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
  598. /* MAC TX/RX Enable */
  599. lp->mcr0 |= lp->phy_mode;
  600. iowrite16(lp->mcr0, ioaddr);
  601. /* set interrupt waiting time and packet numbers */
  602. iowrite16(0x0F06, ioaddr + MT_ICR);
  603. iowrite16(0x0F06, ioaddr + MR_ICR);
  604. /* improve performance (by RDC guys) */
  605. phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
  606. phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000));
  607. phy_write(ioaddr, 0, 19, 0x0000);
  608. phy_write(ioaddr, 0, 30, 0x01F0);
  609. /* Interrupt Mask Register */
  610. iowrite16(INT_MASK, ioaddr + MIER);
  611. }
  612. /*
  613. A periodic timer routine
  614. Polling PHY Chip Link Status
  615. */
  616. static void r6040_timer(unsigned long data)
  617. {
  618. struct net_device *dev = (struct net_device *)data;
  619. struct r6040_private *lp = netdev_priv(dev);
  620. void __iomem *ioaddr = lp->base;
  621. u16 phy_mode;
  622. /* Polling PHY Chip Status */
  623. if (PHY_MODE == 0x3100)
  624. phy_mode = phy_mode_chk(dev);
  625. else
  626. phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
  627. if (phy_mode != lp->phy_mode) {
  628. lp->phy_mode = phy_mode;
  629. lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
  630. iowrite16(lp->mcr0, ioaddr);
  631. printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
  632. }
  633. /* Timer active again */
  634. mod_timer(&lp->timer, jiffies + round_jiffies(HZ));
  635. }
  636. /* Read/set MAC address routines */
  637. static void r6040_mac_address(struct net_device *dev)
  638. {
  639. struct r6040_private *lp = netdev_priv(dev);
  640. void __iomem *ioaddr = lp->base;
  641. u16 *adrp;
  642. /* MAC operation register */
  643. iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
  644. iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
  645. iowrite16(0, ioaddr + MAC_SM);
  646. udelay(5000);
  647. /* Restore MAC Address */
  648. adrp = (u16 *) dev->dev_addr;
  649. iowrite16(adrp[0], ioaddr + MID_0L);
  650. iowrite16(adrp[1], ioaddr + MID_0M);
  651. iowrite16(adrp[2], ioaddr + MID_0H);
  652. }
  653. static int r6040_open(struct net_device *dev)
  654. {
  655. struct r6040_private *lp = netdev_priv(dev);
  656. int ret;
  657. /* Request IRQ and Register interrupt handler */
  658. ret = request_irq(dev->irq, &r6040_interrupt,
  659. IRQF_SHARED, dev->name, dev);
  660. if (ret)
  661. return ret;
  662. /* Set MAC address */
  663. r6040_mac_address(dev);
  664. /* Allocate Descriptor memory */
  665. lp->rx_ring =
  666. pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
  667. if (!lp->rx_ring)
  668. return -ENOMEM;
  669. lp->tx_ring =
  670. pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
  671. if (!lp->tx_ring) {
  672. pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
  673. lp->rx_ring_dma);
  674. return -ENOMEM;
  675. }
  676. r6040_up(dev);
  677. napi_enable(&lp->napi);
  678. netif_start_queue(dev);
  679. /* set and active a timer process */
  680. setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
  681. if (lp->switch_sig != ICPLUS_PHY_ID)
  682. mod_timer(&lp->timer, jiffies + HZ);
  683. return 0;
  684. }
  685. static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
  686. {
  687. struct r6040_private *lp = netdev_priv(dev);
  688. struct r6040_descriptor *descptr;
  689. void __iomem *ioaddr = lp->base;
  690. unsigned long flags;
  691. int ret = NETDEV_TX_OK;
  692. /* Critical Section */
  693. spin_lock_irqsave(&lp->lock, flags);
  694. /* TX resource check */
  695. if (!lp->tx_free_desc) {
  696. spin_unlock_irqrestore(&lp->lock, flags);
  697. netif_stop_queue(dev);
  698. printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
  699. ret = NETDEV_TX_BUSY;
  700. return ret;
  701. }
  702. /* Statistic Counter */
  703. dev->stats.tx_packets++;
  704. dev->stats.tx_bytes += skb->len;
  705. /* Set TX descriptor & Transmit it */
  706. lp->tx_free_desc--;
  707. descptr = lp->tx_insert_ptr;
  708. if (skb->len < MISR)
  709. descptr->len = MISR;
  710. else
  711. descptr->len = skb->len;
  712. descptr->skb_ptr = skb;
  713. descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
  714. skb->data, skb->len, PCI_DMA_TODEVICE));
  715. descptr->status = 0x8000;
  716. /* Trigger the MAC to check the TX descriptor */
  717. iowrite16(0x01, ioaddr + MTPR);
  718. lp->tx_insert_ptr = descptr->vndescp;
  719. /* If no tx resource, stop */
  720. if (!lp->tx_free_desc)
  721. netif_stop_queue(dev);
  722. dev->trans_start = jiffies;
  723. spin_unlock_irqrestore(&lp->lock, flags);
  724. return ret;
  725. }
  726. static void r6040_multicast_list(struct net_device *dev)
  727. {
  728. struct r6040_private *lp = netdev_priv(dev);
  729. void __iomem *ioaddr = lp->base;
  730. u16 *adrp;
  731. u16 reg;
  732. unsigned long flags;
  733. struct dev_mc_list *dmi = dev->mc_list;
  734. int i;
  735. /* MAC Address */
  736. adrp = (u16 *)dev->dev_addr;
  737. iowrite16(adrp[0], ioaddr + MID_0L);
  738. iowrite16(adrp[1], ioaddr + MID_0M);
  739. iowrite16(adrp[2], ioaddr + MID_0H);
  740. /* Promiscous Mode */
  741. spin_lock_irqsave(&lp->lock, flags);
  742. /* Clear AMCP & PROM bits */
  743. reg = ioread16(ioaddr) & ~0x0120;
  744. if (dev->flags & IFF_PROMISC) {
  745. reg |= 0x0020;
  746. lp->mcr0 |= 0x0020;
  747. }
  748. /* Too many multicast addresses
  749. * accept all traffic */
  750. else if ((dev->mc_count > MCAST_MAX)
  751. || (dev->flags & IFF_ALLMULTI))
  752. reg |= 0x0020;
  753. iowrite16(reg, ioaddr);
  754. spin_unlock_irqrestore(&lp->lock, flags);
  755. /* Build the hash table */
  756. if (dev->mc_count > MCAST_MAX) {
  757. u16 hash_table[4];
  758. u32 crc;
  759. for (i = 0; i < 4; i++)
  760. hash_table[i] = 0;
  761. for (i = 0; i < dev->mc_count; i++) {
  762. char *addrs = dmi->dmi_addr;
  763. dmi = dmi->next;
  764. if (!(*addrs & 1))
  765. continue;
  766. crc = ether_crc_le(6, addrs);
  767. crc >>= 26;
  768. hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
  769. }
  770. /* Write the index of the hash table */
  771. for (i = 0; i < 4; i++)
  772. iowrite16(hash_table[i] << 14, ioaddr + MCR1);
  773. /* Fill the MAC hash tables with their values */
  774. iowrite16(hash_table[0], ioaddr + MAR0);
  775. iowrite16(hash_table[1], ioaddr + MAR1);
  776. iowrite16(hash_table[2], ioaddr + MAR2);
  777. iowrite16(hash_table[3], ioaddr + MAR3);
  778. }
  779. /* Multicast Address 1~4 case */
  780. for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
  781. adrp = (u16 *)dmi->dmi_addr;
  782. iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
  783. iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
  784. iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
  785. dmi = dmi->next;
  786. }
  787. for (i = dev->mc_count; i < MCAST_MAX; i++) {
  788. iowrite16(0xffff, ioaddr + MID_0L + 8*i);
  789. iowrite16(0xffff, ioaddr + MID_0M + 8*i);
  790. iowrite16(0xffff, ioaddr + MID_0H + 8*i);
  791. }
  792. }
  793. static void netdev_get_drvinfo(struct net_device *dev,
  794. struct ethtool_drvinfo *info)
  795. {
  796. struct r6040_private *rp = netdev_priv(dev);
  797. strcpy(info->driver, DRV_NAME);
  798. strcpy(info->version, DRV_VERSION);
  799. strcpy(info->bus_info, pci_name(rp->pdev));
  800. }
  801. static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  802. {
  803. struct r6040_private *rp = netdev_priv(dev);
  804. int rc;
  805. spin_lock_irq(&rp->lock);
  806. rc = mii_ethtool_gset(&rp->mii_if, cmd);
  807. spin_unlock_irq(&rp->lock);
  808. return rc;
  809. }
  810. static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  811. {
  812. struct r6040_private *rp = netdev_priv(dev);
  813. int rc;
  814. spin_lock_irq(&rp->lock);
  815. rc = mii_ethtool_sset(&rp->mii_if, cmd);
  816. spin_unlock_irq(&rp->lock);
  817. r6040_set_carrier(&rp->mii_if);
  818. return rc;
  819. }
  820. static u32 netdev_get_link(struct net_device *dev)
  821. {
  822. struct r6040_private *rp = netdev_priv(dev);
  823. return mii_link_ok(&rp->mii_if);
  824. }
  825. static struct ethtool_ops netdev_ethtool_ops = {
  826. .get_drvinfo = netdev_get_drvinfo,
  827. .get_settings = netdev_get_settings,
  828. .set_settings = netdev_set_settings,
  829. .get_link = netdev_get_link,
  830. };
  831. static int __devinit r6040_init_one(struct pci_dev *pdev,
  832. const struct pci_device_id *ent)
  833. {
  834. struct net_device *dev;
  835. struct r6040_private *lp;
  836. void __iomem *ioaddr;
  837. int err, io_size = R6040_IO_SIZE;
  838. static int card_idx = -1;
  839. int bar = 0;
  840. long pioaddr;
  841. u16 *adrp;
  842. printk(KERN_INFO "%s\n", version);
  843. err = pci_enable_device(pdev);
  844. if (err)
  845. return err;
  846. /* this should always be supported */
  847. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  848. printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
  849. "not supported by the card\n");
  850. return -ENODEV;
  851. }
  852. if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
  853. printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
  854. "not supported by the card\n");
  855. return -ENODEV;
  856. }
  857. /* IO Size check */
  858. if (pci_resource_len(pdev, 0) < io_size) {
  859. printk(KERN_ERR "Insufficient PCI resources, aborting\n");
  860. return -EIO;
  861. }
  862. pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
  863. pci_set_master(pdev);
  864. dev = alloc_etherdev(sizeof(struct r6040_private));
  865. if (!dev) {
  866. printk(KERN_ERR "Failed to allocate etherdev\n");
  867. return -ENOMEM;
  868. }
  869. SET_NETDEV_DEV(dev, &pdev->dev);
  870. lp = netdev_priv(dev);
  871. lp->pdev = pdev;
  872. if (pci_request_regions(pdev, DRV_NAME)) {
  873. printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
  874. err = -ENODEV;
  875. goto err_out_disable;
  876. }
  877. ioaddr = pci_iomap(pdev, bar, io_size);
  878. if (!ioaddr) {
  879. printk(KERN_ERR "ioremap failed for device %s\n",
  880. pci_name(pdev));
  881. return -EIO;
  882. }
  883. /* Init system & device */
  884. lp->base = ioaddr;
  885. dev->irq = pdev->irq;
  886. spin_lock_init(&lp->lock);
  887. pci_set_drvdata(pdev, dev);
  888. /* Set MAC address */
  889. card_idx++;
  890. adrp = (u16 *)dev->dev_addr;
  891. adrp[0] = ioread16(ioaddr + MID_0L);
  892. adrp[1] = ioread16(ioaddr + MID_0M);
  893. adrp[2] = ioread16(ioaddr + MID_0H);
  894. /* Link new device into r6040_root_dev */
  895. lp->pdev = pdev;
  896. /* Init RDC private data */
  897. lp->mcr0 = 0x1002;
  898. lp->phy_addr = phy_table[card_idx];
  899. lp->switch_sig = 0;
  900. /* The RDC-specific entries in the device structure. */
  901. dev->open = &r6040_open;
  902. dev->hard_start_xmit = &r6040_start_xmit;
  903. dev->stop = &r6040_close;
  904. dev->get_stats = r6040_get_stats;
  905. dev->set_multicast_list = &r6040_multicast_list;
  906. dev->do_ioctl = &r6040_ioctl;
  907. dev->ethtool_ops = &netdev_ethtool_ops;
  908. dev->tx_timeout = &r6040_tx_timeout;
  909. dev->watchdog_timeo = TX_TIMEOUT;
  910. #ifdef CONFIG_NET_POLL_CONTROLLER
  911. dev->poll_controller = r6040_poll_controller;
  912. #endif
  913. netif_napi_add(dev, &lp->napi, r6040_poll, 64);
  914. lp->mii_if.dev = dev;
  915. lp->mii_if.mdio_read = mdio_read;
  916. lp->mii_if.mdio_write = mdio_write;
  917. lp->mii_if.phy_id = lp->phy_addr;
  918. lp->mii_if.phy_id_mask = 0x1f;
  919. lp->mii_if.reg_num_mask = 0x1f;
  920. /* Register net device. After this dev->name assign */
  921. err = register_netdev(dev);
  922. if (err) {
  923. printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
  924. goto err_out_res;
  925. }
  926. return 0;
  927. err_out_res:
  928. pci_release_regions(pdev);
  929. err_out_disable:
  930. pci_disable_device(pdev);
  931. pci_set_drvdata(pdev, NULL);
  932. free_netdev(dev);
  933. return err;
  934. }
  935. static void __devexit r6040_remove_one(struct pci_dev *pdev)
  936. {
  937. struct net_device *dev = pci_get_drvdata(pdev);
  938. unregister_netdev(dev);
  939. pci_release_regions(pdev);
  940. free_netdev(dev);
  941. pci_disable_device(pdev);
  942. pci_set_drvdata(pdev, NULL);
  943. }
  944. static struct pci_device_id r6040_pci_tbl[] = {
  945. { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
  946. { 0 }
  947. };
  948. MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
  949. static struct pci_driver r6040_driver = {
  950. .name = DRV_NAME,
  951. .id_table = r6040_pci_tbl,
  952. .probe = r6040_init_one,
  953. .remove = __devexit_p(r6040_remove_one),
  954. };
  955. static int __init r6040_init(void)
  956. {
  957. return pci_register_driver(&r6040_driver);
  958. }
  959. static void __exit r6040_cleanup(void)
  960. {
  961. pci_unregister_driver(&r6040_driver);
  962. }
  963. module_init(r6040_init);
  964. module_exit(r6040_cleanup);