netxen_nic_hw.c 32 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to access the Phantom hardware
  31. *
  32. */
  33. #include "netxen_nic.h"
  34. #include "netxen_nic_hw.h"
  35. #include "netxen_nic_phan_reg.h"
  36. #include <net/ip.h>
  37. struct netxen_recv_crb recv_crb_registers[] = {
  38. /*
  39. * Instance 0.
  40. */
  41. {
  42. /* rcv_desc_crb: */
  43. {
  44. {
  45. /* crb_rcv_producer_offset: */
  46. NETXEN_NIC_REG(0x100),
  47. /* crb_rcv_consumer_offset: */
  48. NETXEN_NIC_REG(0x104),
  49. /* crb_gloablrcv_ring: */
  50. NETXEN_NIC_REG(0x108),
  51. /* crb_rcv_ring_size */
  52. NETXEN_NIC_REG(0x10c),
  53. },
  54. /* Jumbo frames */
  55. {
  56. /* crb_rcv_producer_offset: */
  57. NETXEN_NIC_REG(0x110),
  58. /* crb_rcv_consumer_offset: */
  59. NETXEN_NIC_REG(0x114),
  60. /* crb_gloablrcv_ring: */
  61. NETXEN_NIC_REG(0x118),
  62. /* crb_rcv_ring_size */
  63. NETXEN_NIC_REG(0x11c),
  64. },
  65. /* LRO */
  66. {
  67. /* crb_rcv_producer_offset: */
  68. NETXEN_NIC_REG(0x120),
  69. /* crb_rcv_consumer_offset: */
  70. NETXEN_NIC_REG(0x124),
  71. /* crb_gloablrcv_ring: */
  72. NETXEN_NIC_REG(0x128),
  73. /* crb_rcv_ring_size */
  74. NETXEN_NIC_REG(0x12c),
  75. }
  76. },
  77. /* crb_rcvstatus_ring: */
  78. NETXEN_NIC_REG(0x130),
  79. /* crb_rcv_status_producer: */
  80. NETXEN_NIC_REG(0x134),
  81. /* crb_rcv_status_consumer: */
  82. NETXEN_NIC_REG(0x138),
  83. /* crb_rcvpeg_state: */
  84. NETXEN_NIC_REG(0x13c),
  85. /* crb_status_ring_size */
  86. NETXEN_NIC_REG(0x140),
  87. },
  88. /*
  89. * Instance 1,
  90. */
  91. {
  92. /* rcv_desc_crb: */
  93. {
  94. {
  95. /* crb_rcv_producer_offset: */
  96. NETXEN_NIC_REG(0x144),
  97. /* crb_rcv_consumer_offset: */
  98. NETXEN_NIC_REG(0x148),
  99. /* crb_globalrcv_ring: */
  100. NETXEN_NIC_REG(0x14c),
  101. /* crb_rcv_ring_size */
  102. NETXEN_NIC_REG(0x150),
  103. },
  104. /* Jumbo frames */
  105. {
  106. /* crb_rcv_producer_offset: */
  107. NETXEN_NIC_REG(0x154),
  108. /* crb_rcv_consumer_offset: */
  109. NETXEN_NIC_REG(0x158),
  110. /* crb_globalrcv_ring: */
  111. NETXEN_NIC_REG(0x15c),
  112. /* crb_rcv_ring_size */
  113. NETXEN_NIC_REG(0x160),
  114. },
  115. /* LRO */
  116. {
  117. /* crb_rcv_producer_offset: */
  118. NETXEN_NIC_REG(0x164),
  119. /* crb_rcv_consumer_offset: */
  120. NETXEN_NIC_REG(0x168),
  121. /* crb_globalrcv_ring: */
  122. NETXEN_NIC_REG(0x16c),
  123. /* crb_rcv_ring_size */
  124. NETXEN_NIC_REG(0x170),
  125. }
  126. },
  127. /* crb_rcvstatus_ring: */
  128. NETXEN_NIC_REG(0x174),
  129. /* crb_rcv_status_producer: */
  130. NETXEN_NIC_REG(0x178),
  131. /* crb_rcv_status_consumer: */
  132. NETXEN_NIC_REG(0x17c),
  133. /* crb_rcvpeg_state: */
  134. NETXEN_NIC_REG(0x180),
  135. /* crb_status_ring_size */
  136. NETXEN_NIC_REG(0x184),
  137. },
  138. /*
  139. * Instance 2,
  140. */
  141. {
  142. {
  143. {
  144. /* crb_rcv_producer_offset: */
  145. NETXEN_NIC_REG(0x1d8),
  146. /* crb_rcv_consumer_offset: */
  147. NETXEN_NIC_REG(0x1dc),
  148. /* crb_gloablrcv_ring: */
  149. NETXEN_NIC_REG(0x1f0),
  150. /* crb_rcv_ring_size */
  151. NETXEN_NIC_REG(0x1f4),
  152. },
  153. /* Jumbo frames */
  154. {
  155. /* crb_rcv_producer_offset: */
  156. NETXEN_NIC_REG(0x1f8),
  157. /* crb_rcv_consumer_offset: */
  158. NETXEN_NIC_REG(0x1fc),
  159. /* crb_gloablrcv_ring: */
  160. NETXEN_NIC_REG(0x200),
  161. /* crb_rcv_ring_size */
  162. NETXEN_NIC_REG(0x204),
  163. },
  164. /* LRO */
  165. {
  166. /* crb_rcv_producer_offset: */
  167. NETXEN_NIC_REG(0x208),
  168. /* crb_rcv_consumer_offset: */
  169. NETXEN_NIC_REG(0x20c),
  170. /* crb_gloablrcv_ring: */
  171. NETXEN_NIC_REG(0x210),
  172. /* crb_rcv_ring_size */
  173. NETXEN_NIC_REG(0x214),
  174. }
  175. },
  176. /* crb_rcvstatus_ring: */
  177. NETXEN_NIC_REG(0x218),
  178. /* crb_rcv_status_producer: */
  179. NETXEN_NIC_REG(0x21c),
  180. /* crb_rcv_status_consumer: */
  181. NETXEN_NIC_REG(0x220),
  182. /* crb_rcvpeg_state: */
  183. NETXEN_NIC_REG(0x224),
  184. /* crb_status_ring_size */
  185. NETXEN_NIC_REG(0x228),
  186. },
  187. /*
  188. * Instance 3,
  189. */
  190. {
  191. {
  192. {
  193. /* crb_rcv_producer_offset: */
  194. NETXEN_NIC_REG(0x22c),
  195. /* crb_rcv_consumer_offset: */
  196. NETXEN_NIC_REG(0x230),
  197. /* crb_gloablrcv_ring: */
  198. NETXEN_NIC_REG(0x234),
  199. /* crb_rcv_ring_size */
  200. NETXEN_NIC_REG(0x238),
  201. },
  202. /* Jumbo frames */
  203. {
  204. /* crb_rcv_producer_offset: */
  205. NETXEN_NIC_REG(0x23c),
  206. /* crb_rcv_consumer_offset: */
  207. NETXEN_NIC_REG(0x240),
  208. /* crb_gloablrcv_ring: */
  209. NETXEN_NIC_REG(0x244),
  210. /* crb_rcv_ring_size */
  211. NETXEN_NIC_REG(0x248),
  212. },
  213. /* LRO */
  214. {
  215. /* crb_rcv_producer_offset: */
  216. NETXEN_NIC_REG(0x24c),
  217. /* crb_rcv_consumer_offset: */
  218. NETXEN_NIC_REG(0x250),
  219. /* crb_gloablrcv_ring: */
  220. NETXEN_NIC_REG(0x254),
  221. /* crb_rcv_ring_size */
  222. NETXEN_NIC_REG(0x258),
  223. }
  224. },
  225. /* crb_rcvstatus_ring: */
  226. NETXEN_NIC_REG(0x25c),
  227. /* crb_rcv_status_producer: */
  228. NETXEN_NIC_REG(0x260),
  229. /* crb_rcv_status_consumer: */
  230. NETXEN_NIC_REG(0x264),
  231. /* crb_rcvpeg_state: */
  232. NETXEN_NIC_REG(0x268),
  233. /* crb_status_ring_size */
  234. NETXEN_NIC_REG(0x26c),
  235. },
  236. };
  237. static u64 ctx_addr_sig_regs[][3] = {
  238. {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
  239. {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
  240. {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
  241. {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
  242. };
  243. #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
  244. #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
  245. #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
  246. /* PCI Windowing for DDR regions. */
  247. #define ADDR_IN_RANGE(addr, low, high) \
  248. (((addr) <= (high)) && ((addr) >= (low)))
  249. #define NETXEN_FLASH_BASE (NETXEN_BOOTLD_START)
  250. #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
  251. #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
  252. #define NETXEN_MIN_MTU 64
  253. #define NETXEN_ETH_FCS_SIZE 4
  254. #define NETXEN_ENET_HEADER_SIZE 14
  255. #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
  256. #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
  257. #define NETXEN_NIU_HDRSIZE (0x1 << 6)
  258. #define NETXEN_NIU_TLRSIZE (0x1 << 5)
  259. #define lower32(x) ((u32)((x) & 0xffffffff))
  260. #define upper32(x) \
  261. ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
  262. #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
  263. #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
  264. #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
  265. #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
  266. #define NETXEN_NIC_WINDOW_MARGIN 0x100000
  267. static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
  268. unsigned long long addr);
  269. void netxen_free_hw_resources(struct netxen_adapter *adapter);
  270. int netxen_nic_set_mac(struct net_device *netdev, void *p)
  271. {
  272. struct netxen_adapter *adapter = netdev_priv(netdev);
  273. struct sockaddr *addr = p;
  274. if (netif_running(netdev))
  275. return -EBUSY;
  276. if (!is_valid_ether_addr(addr->sa_data))
  277. return -EADDRNOTAVAIL;
  278. DPRINTK(INFO, "valid ether addr\n");
  279. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  280. if (adapter->macaddr_set)
  281. adapter->macaddr_set(adapter, addr->sa_data);
  282. return 0;
  283. }
  284. /*
  285. * netxen_nic_set_multi - Multicast
  286. */
  287. void netxen_nic_set_multi(struct net_device *netdev)
  288. {
  289. struct netxen_adapter *adapter = netdev_priv(netdev);
  290. struct dev_mc_list *mc_ptr;
  291. mc_ptr = netdev->mc_list;
  292. if (netdev->flags & IFF_PROMISC) {
  293. if (adapter->set_promisc)
  294. adapter->set_promisc(adapter,
  295. NETXEN_NIU_PROMISC_MODE);
  296. } else {
  297. if (adapter->unset_promisc)
  298. adapter->unset_promisc(adapter,
  299. NETXEN_NIU_NON_PROMISC_MODE);
  300. }
  301. }
  302. /*
  303. * netxen_nic_change_mtu - Change the Maximum Transfer Unit
  304. * @returns 0 on success, negative on failure
  305. */
  306. int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
  307. {
  308. struct netxen_adapter *adapter = netdev_priv(netdev);
  309. int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
  310. if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
  311. printk(KERN_ERR "%s: %s %d is not supported.\n",
  312. netxen_nic_driver_name, netdev->name, mtu);
  313. return -EINVAL;
  314. }
  315. if (adapter->set_mtu)
  316. adapter->set_mtu(adapter, mtu);
  317. netdev->mtu = mtu;
  318. return 0;
  319. }
  320. /*
  321. * check if the firmware has been downloaded and ready to run and
  322. * setup the address for the descriptors in the adapter
  323. */
  324. int netxen_nic_hw_resources(struct netxen_adapter *adapter)
  325. {
  326. struct netxen_hardware_context *hw = &adapter->ahw;
  327. u32 state = 0;
  328. void *addr;
  329. int loops = 0, err = 0;
  330. int ctx, ring;
  331. struct netxen_recv_context *recv_ctx;
  332. struct netxen_rcv_desc_ctx *rcv_desc;
  333. int func_id = adapter->portnum;
  334. DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
  335. PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
  336. DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
  337. pci_base_offset(adapter, NETXEN_CRB_CAM));
  338. DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
  339. pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
  340. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  341. DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
  342. loops = 0;
  343. state = 0;
  344. /* Window 1 call */
  345. state = readl(NETXEN_CRB_NORMALIZE(adapter,
  346. recv_crb_registers[ctx].
  347. crb_rcvpeg_state));
  348. while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
  349. msleep(1);
  350. /* Window 1 call */
  351. state = readl(NETXEN_CRB_NORMALIZE(adapter,
  352. recv_crb_registers
  353. [ctx].
  354. crb_rcvpeg_state));
  355. loops++;
  356. }
  357. if (loops >= 20) {
  358. printk(KERN_ERR "Rcv Peg initialization not complete:"
  359. "%x.\n", state);
  360. err = -EIO;
  361. return err;
  362. }
  363. }
  364. adapter->intr_scheme = readl(
  365. NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW));
  366. printk(KERN_NOTICE "%s: FW capabilities:0x%x\n", netxen_nic_driver_name,
  367. adapter->intr_scheme);
  368. adapter->msi_mode = readl(
  369. NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW));
  370. DPRINTK(INFO, "Receive Peg ready too. starting stuff\n");
  371. addr = netxen_alloc(adapter->ahw.pdev,
  372. sizeof(struct netxen_ring_ctx) +
  373. sizeof(uint32_t),
  374. (dma_addr_t *) & adapter->ctx_desc_phys_addr,
  375. &adapter->ctx_desc_pdev);
  376. printk(KERN_INFO "ctx_desc_phys_addr: 0x%llx\n",
  377. (unsigned long long) adapter->ctx_desc_phys_addr);
  378. if (addr == NULL) {
  379. DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
  380. err = -ENOMEM;
  381. return err;
  382. }
  383. memset(addr, 0, sizeof(struct netxen_ring_ctx));
  384. adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
  385. adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
  386. adapter->ctx_desc->cmd_consumer_offset =
  387. cpu_to_le64(adapter->ctx_desc_phys_addr +
  388. sizeof(struct netxen_ring_ctx));
  389. adapter->cmd_consumer = (__le32 *) (((char *)addr) +
  390. sizeof(struct netxen_ring_ctx));
  391. addr = netxen_alloc(adapter->ahw.pdev,
  392. sizeof(struct cmd_desc_type0) *
  393. adapter->max_tx_desc_count,
  394. (dma_addr_t *) & hw->cmd_desc_phys_addr,
  395. &adapter->ahw.cmd_desc_pdev);
  396. printk(KERN_INFO "cmd_desc_phys_addr: 0x%llx\n",
  397. (unsigned long long) hw->cmd_desc_phys_addr);
  398. if (addr == NULL) {
  399. DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
  400. netxen_free_hw_resources(adapter);
  401. return -ENOMEM;
  402. }
  403. adapter->ctx_desc->cmd_ring_addr =
  404. cpu_to_le64(hw->cmd_desc_phys_addr);
  405. adapter->ctx_desc->cmd_ring_size =
  406. cpu_to_le32(adapter->max_tx_desc_count);
  407. hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
  408. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  409. recv_ctx = &adapter->recv_ctx[ctx];
  410. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  411. rcv_desc = &recv_ctx->rcv_desc[ring];
  412. addr = netxen_alloc(adapter->ahw.pdev,
  413. RCV_DESC_RINGSIZE,
  414. &rcv_desc->phys_addr,
  415. &rcv_desc->phys_pdev);
  416. if (addr == NULL) {
  417. DPRINTK(ERR, "bad return from "
  418. "pci_alloc_consistent\n");
  419. netxen_free_hw_resources(adapter);
  420. err = -ENOMEM;
  421. return err;
  422. }
  423. rcv_desc->desc_head = (struct rcv_desc *)addr;
  424. adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
  425. cpu_to_le64(rcv_desc->phys_addr);
  426. adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
  427. cpu_to_le32(rcv_desc->max_rx_desc_count);
  428. }
  429. addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
  430. &recv_ctx->rcv_status_desc_phys_addr,
  431. &recv_ctx->rcv_status_desc_pdev);
  432. if (addr == NULL) {
  433. DPRINTK(ERR, "bad return from"
  434. " pci_alloc_consistent\n");
  435. netxen_free_hw_resources(adapter);
  436. err = -ENOMEM;
  437. return err;
  438. }
  439. recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
  440. adapter->ctx_desc->sts_ring_addr =
  441. cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
  442. adapter->ctx_desc->sts_ring_size =
  443. cpu_to_le32(adapter->max_rx_desc_count);
  444. }
  445. /* Window = 1 */
  446. writel(lower32(adapter->ctx_desc_phys_addr),
  447. NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id)));
  448. writel(upper32(adapter->ctx_desc_phys_addr),
  449. NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id)));
  450. writel(NETXEN_CTX_SIGNATURE | func_id,
  451. NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id)));
  452. return err;
  453. }
  454. void netxen_free_hw_resources(struct netxen_adapter *adapter)
  455. {
  456. struct netxen_recv_context *recv_ctx;
  457. struct netxen_rcv_desc_ctx *rcv_desc;
  458. int ctx, ring;
  459. if (adapter->ctx_desc != NULL) {
  460. pci_free_consistent(adapter->ctx_desc_pdev,
  461. sizeof(struct netxen_ring_ctx) +
  462. sizeof(uint32_t),
  463. adapter->ctx_desc,
  464. adapter->ctx_desc_phys_addr);
  465. adapter->ctx_desc = NULL;
  466. }
  467. if (adapter->ahw.cmd_desc_head != NULL) {
  468. pci_free_consistent(adapter->ahw.cmd_desc_pdev,
  469. sizeof(struct cmd_desc_type0) *
  470. adapter->max_tx_desc_count,
  471. adapter->ahw.cmd_desc_head,
  472. adapter->ahw.cmd_desc_phys_addr);
  473. adapter->ahw.cmd_desc_head = NULL;
  474. }
  475. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  476. recv_ctx = &adapter->recv_ctx[ctx];
  477. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  478. rcv_desc = &recv_ctx->rcv_desc[ring];
  479. if (rcv_desc->desc_head != NULL) {
  480. pci_free_consistent(rcv_desc->phys_pdev,
  481. RCV_DESC_RINGSIZE,
  482. rcv_desc->desc_head,
  483. rcv_desc->phys_addr);
  484. rcv_desc->desc_head = NULL;
  485. }
  486. }
  487. if (recv_ctx->rcv_status_desc_head != NULL) {
  488. pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
  489. STATUS_DESC_RINGSIZE,
  490. recv_ctx->rcv_status_desc_head,
  491. recv_ctx->
  492. rcv_status_desc_phys_addr);
  493. recv_ctx->rcv_status_desc_head = NULL;
  494. }
  495. }
  496. }
  497. void netxen_tso_check(struct netxen_adapter *adapter,
  498. struct cmd_desc_type0 *desc, struct sk_buff *skb)
  499. {
  500. if (desc->mss) {
  501. desc->total_hdr_length = (sizeof(struct ethhdr) +
  502. ip_hdrlen(skb) + tcp_hdrlen(skb));
  503. netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
  504. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  505. if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
  506. netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
  507. } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
  508. netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
  509. } else {
  510. return;
  511. }
  512. }
  513. desc->tcp_hdr_offset = skb_transport_offset(skb);
  514. desc->ip_hdr_offset = skb_network_offset(skb);
  515. }
  516. int netxen_is_flash_supported(struct netxen_adapter *adapter)
  517. {
  518. const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
  519. int addr, val01, val02, i, j;
  520. /* if the flash size less than 4Mb, make huge war cry and die */
  521. for (j = 1; j < 4; j++) {
  522. addr = j * NETXEN_NIC_WINDOW_MARGIN;
  523. for (i = 0; i < ARRAY_SIZE(locs); i++) {
  524. if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
  525. && netxen_rom_fast_read(adapter, (addr + locs[i]),
  526. &val02) == 0) {
  527. if (val01 == val02)
  528. return -1;
  529. } else
  530. return -1;
  531. }
  532. }
  533. return 0;
  534. }
  535. static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
  536. int size, __le32 * buf)
  537. {
  538. int i, addr;
  539. __le32 *ptr32;
  540. u32 v;
  541. addr = base;
  542. ptr32 = buf;
  543. for (i = 0; i < size / sizeof(u32); i++) {
  544. if (netxen_rom_fast_read(adapter, addr, &v) == -1)
  545. return -1;
  546. *ptr32 = cpu_to_le32(v);
  547. ptr32++;
  548. addr += sizeof(u32);
  549. }
  550. if ((char *)buf + size > (char *)ptr32) {
  551. __le32 local;
  552. if (netxen_rom_fast_read(adapter, addr, &v) == -1)
  553. return -1;
  554. local = cpu_to_le32(v);
  555. memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
  556. }
  557. return 0;
  558. }
  559. int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
  560. {
  561. __le32 *pmac = (__le32 *) & mac[0];
  562. if (netxen_get_flash_block(adapter,
  563. NETXEN_USER_START +
  564. offsetof(struct netxen_new_user_info,
  565. mac_addr),
  566. FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
  567. return -1;
  568. }
  569. if (*mac == cpu_to_le64(~0ULL)) {
  570. if (netxen_get_flash_block(adapter,
  571. NETXEN_USER_START_OLD +
  572. offsetof(struct netxen_user_old_info,
  573. mac_addr),
  574. FLASH_NUM_PORTS * sizeof(u64),
  575. pmac) == -1)
  576. return -1;
  577. if (*mac == cpu_to_le64(~0ULL))
  578. return -1;
  579. }
  580. return 0;
  581. }
  582. /*
  583. * Changes the CRB window to the specified window.
  584. */
  585. void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
  586. {
  587. void __iomem *offset;
  588. u32 tmp;
  589. int count = 0;
  590. if (adapter->curr_window == wndw)
  591. return;
  592. switch(adapter->ahw.pci_func) {
  593. case 0:
  594. offset = PCI_OFFSET_SECOND_RANGE(adapter,
  595. NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
  596. break;
  597. case 1:
  598. offset = PCI_OFFSET_SECOND_RANGE(adapter,
  599. NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1));
  600. break;
  601. case 2:
  602. offset = PCI_OFFSET_SECOND_RANGE(adapter,
  603. NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2));
  604. break;
  605. case 3:
  606. offset = PCI_OFFSET_SECOND_RANGE(adapter,
  607. NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3));
  608. break;
  609. default:
  610. printk(KERN_INFO "Changing the window for PCI function "
  611. "%d\n", adapter->ahw.pci_func);
  612. offset = PCI_OFFSET_SECOND_RANGE(adapter,
  613. NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
  614. break;
  615. }
  616. /*
  617. * Move the CRB window.
  618. * We need to write to the "direct access" region of PCI
  619. * to avoid a race condition where the window register has
  620. * not been successfully written across CRB before the target
  621. * register address is received by PCI. The direct region bypasses
  622. * the CRB bus.
  623. */
  624. if (wndw & 0x1)
  625. wndw = NETXEN_WINDOW_ONE;
  626. writel(wndw, offset);
  627. /* MUST make sure window is set before we forge on... */
  628. while ((tmp = readl(offset)) != wndw) {
  629. printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
  630. "registered properly: 0x%08x.\n",
  631. netxen_nic_driver_name, __FUNCTION__, tmp);
  632. mdelay(1);
  633. if (count >= 10)
  634. break;
  635. count++;
  636. }
  637. if (wndw == NETXEN_WINDOW_ONE)
  638. adapter->curr_window = 1;
  639. else
  640. adapter->curr_window = 0;
  641. }
  642. int netxen_load_firmware(struct netxen_adapter *adapter)
  643. {
  644. int i;
  645. u32 data, size = 0;
  646. u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
  647. u64 off;
  648. void __iomem *addr;
  649. size = NETXEN_FIRMWARE_LEN;
  650. writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
  651. for (i = 0; i < size; i++) {
  652. int retries = 10;
  653. if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
  654. return -EIO;
  655. off = netxen_nic_pci_set_window(adapter, memaddr);
  656. addr = pci_base_offset(adapter, off);
  657. writel(data, addr);
  658. do {
  659. if (readl(addr) == data)
  660. break;
  661. msleep(100);
  662. writel(data, addr);
  663. } while (--retries);
  664. if (!retries) {
  665. printk(KERN_ERR "%s: firmware load aborted, write failed at 0x%x\n",
  666. netxen_nic_driver_name, memaddr);
  667. return -EIO;
  668. }
  669. flashaddr += 4;
  670. memaddr += 4;
  671. }
  672. udelay(100);
  673. /* make sure Casper is powered on */
  674. writel(0x3fff,
  675. NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
  676. writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
  677. return 0;
  678. }
  679. int
  680. netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
  681. int len)
  682. {
  683. void __iomem *addr;
  684. if (ADDR_IN_WINDOW1(off)) {
  685. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  686. } else { /* Window 0 */
  687. addr = pci_base_offset(adapter, off);
  688. netxen_nic_pci_change_crbwindow(adapter, 0);
  689. }
  690. DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
  691. " data %llx len %d\n",
  692. pci_base(adapter, off), off, addr,
  693. *(unsigned long long *)data, len);
  694. if (!addr) {
  695. netxen_nic_pci_change_crbwindow(adapter, 1);
  696. return 1;
  697. }
  698. switch (len) {
  699. case 1:
  700. writeb(*(u8 *) data, addr);
  701. break;
  702. case 2:
  703. writew(*(u16 *) data, addr);
  704. break;
  705. case 4:
  706. writel(*(u32 *) data, addr);
  707. break;
  708. case 8:
  709. writeq(*(u64 *) data, addr);
  710. break;
  711. default:
  712. DPRINTK(INFO,
  713. "writing data %lx to offset %llx, num words=%d\n",
  714. *(unsigned long *)data, off, (len >> 3));
  715. netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
  716. (len >> 3));
  717. break;
  718. }
  719. if (!ADDR_IN_WINDOW1(off))
  720. netxen_nic_pci_change_crbwindow(adapter, 1);
  721. return 0;
  722. }
  723. int
  724. netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
  725. int len)
  726. {
  727. void __iomem *addr;
  728. if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
  729. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  730. } else { /* Window 0 */
  731. addr = pci_base_offset(adapter, off);
  732. netxen_nic_pci_change_crbwindow(adapter, 0);
  733. }
  734. DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
  735. pci_base(adapter, off), off, addr);
  736. if (!addr) {
  737. netxen_nic_pci_change_crbwindow(adapter, 1);
  738. return 1;
  739. }
  740. switch (len) {
  741. case 1:
  742. *(u8 *) data = readb(addr);
  743. break;
  744. case 2:
  745. *(u16 *) data = readw(addr);
  746. break;
  747. case 4:
  748. *(u32 *) data = readl(addr);
  749. break;
  750. case 8:
  751. *(u64 *) data = readq(addr);
  752. break;
  753. default:
  754. netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
  755. (len >> 3));
  756. break;
  757. }
  758. DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
  759. if (!ADDR_IN_WINDOW1(off))
  760. netxen_nic_pci_change_crbwindow(adapter, 1);
  761. return 0;
  762. }
  763. void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
  764. { /* Only for window 1 */
  765. void __iomem *addr;
  766. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  767. DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
  768. pci_base(adapter, off), off, addr, val);
  769. writel(val, addr);
  770. }
  771. int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
  772. { /* Only for window 1 */
  773. void __iomem *addr;
  774. int val;
  775. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  776. DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
  777. pci_base(adapter, off), off, addr);
  778. val = readl(addr);
  779. writel(val, addr);
  780. return val;
  781. }
  782. /* Change the window to 0, write and change back to window 1. */
  783. void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
  784. {
  785. void __iomem *addr;
  786. netxen_nic_pci_change_crbwindow(adapter, 0);
  787. addr = pci_base_offset(adapter, index);
  788. writel(value, addr);
  789. netxen_nic_pci_change_crbwindow(adapter, 1);
  790. }
  791. /* Change the window to 0, read and change back to window 1. */
  792. void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
  793. {
  794. void __iomem *addr;
  795. addr = pci_base_offset(adapter, index);
  796. netxen_nic_pci_change_crbwindow(adapter, 0);
  797. *value = readl(addr);
  798. netxen_nic_pci_change_crbwindow(adapter, 1);
  799. }
  800. static int netxen_pci_set_window_warning_count;
  801. static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
  802. unsigned long long addr)
  803. {
  804. static int ddr_mn_window = -1;
  805. static int qdr_sn_window = -1;
  806. int window;
  807. if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
  808. /* DDR network side */
  809. addr -= NETXEN_ADDR_DDR_NET;
  810. window = (addr >> 25) & 0x3ff;
  811. if (ddr_mn_window != window) {
  812. ddr_mn_window = window;
  813. writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
  814. NETXEN_PCIX_PH_REG
  815. (PCIX_MN_WINDOW(adapter->ahw.pci_func))));
  816. /* MUST make sure window is set before we forge on... */
  817. readl(PCI_OFFSET_SECOND_RANGE(adapter,
  818. NETXEN_PCIX_PH_REG
  819. (PCIX_MN_WINDOW(adapter->ahw.pci_func))));
  820. }
  821. addr -= (window * NETXEN_WINDOW_ONE);
  822. addr += NETXEN_PCI_DDR_NET;
  823. } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
  824. addr -= NETXEN_ADDR_OCM0;
  825. addr += NETXEN_PCI_OCM0;
  826. } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
  827. addr -= NETXEN_ADDR_OCM1;
  828. addr += NETXEN_PCI_OCM1;
  829. } else
  830. if (ADDR_IN_RANGE
  831. (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
  832. /* QDR network side */
  833. addr -= NETXEN_ADDR_QDR_NET;
  834. window = (addr >> 22) & 0x3f;
  835. if (qdr_sn_window != window) {
  836. qdr_sn_window = window;
  837. writel((window << 22),
  838. PCI_OFFSET_SECOND_RANGE(adapter,
  839. NETXEN_PCIX_PH_REG
  840. (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
  841. /* MUST make sure window is set before we forge on... */
  842. readl(PCI_OFFSET_SECOND_RANGE(adapter,
  843. NETXEN_PCIX_PH_REG
  844. (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
  845. }
  846. addr -= (window * 0x400000);
  847. addr += NETXEN_PCI_QDR_NET;
  848. } else {
  849. /*
  850. * peg gdb frequently accesses memory that doesn't exist,
  851. * this limits the chit chat so debugging isn't slowed down.
  852. */
  853. if ((netxen_pci_set_window_warning_count++ < 8)
  854. || (netxen_pci_set_window_warning_count % 64 == 0))
  855. printk("%s: Warning:netxen_nic_pci_set_window()"
  856. " Unknown address range!\n",
  857. netxen_nic_driver_name);
  858. }
  859. return addr;
  860. }
  861. #if 0
  862. int
  863. netxen_nic_erase_pxe(struct netxen_adapter *adapter)
  864. {
  865. if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
  866. printk(KERN_ERR "%s: erase pxe failed\n",
  867. netxen_nic_driver_name);
  868. return -1;
  869. }
  870. return 0;
  871. }
  872. #endif /* 0 */
  873. int netxen_nic_get_board_info(struct netxen_adapter *adapter)
  874. {
  875. int rv = 0;
  876. int addr = NETXEN_BRDCFG_START;
  877. struct netxen_board_info *boardinfo;
  878. int index;
  879. u32 *ptr32;
  880. boardinfo = &adapter->ahw.boardcfg;
  881. ptr32 = (u32 *) boardinfo;
  882. for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
  883. index++) {
  884. if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
  885. return -EIO;
  886. }
  887. ptr32++;
  888. addr += sizeof(u32);
  889. }
  890. if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
  891. printk("%s: ERROR reading %s board config."
  892. " Read %x, expected %x\n", netxen_nic_driver_name,
  893. netxen_nic_driver_name,
  894. boardinfo->magic, NETXEN_BDINFO_MAGIC);
  895. rv = -1;
  896. }
  897. if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
  898. printk("%s: Unknown board config version."
  899. " Read %x, expected %x\n", netxen_nic_driver_name,
  900. boardinfo->header_version, NETXEN_BDINFO_VERSION);
  901. rv = -1;
  902. }
  903. DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
  904. switch ((netxen_brdtype_t) boardinfo->board_type) {
  905. case NETXEN_BRDTYPE_P2_SB35_4G:
  906. adapter->ahw.board_type = NETXEN_NIC_GBE;
  907. break;
  908. case NETXEN_BRDTYPE_P2_SB31_10G:
  909. case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
  910. case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
  911. case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
  912. adapter->ahw.board_type = NETXEN_NIC_XGBE;
  913. break;
  914. case NETXEN_BRDTYPE_P1_BD:
  915. case NETXEN_BRDTYPE_P1_SB:
  916. case NETXEN_BRDTYPE_P1_SMAX:
  917. case NETXEN_BRDTYPE_P1_SOCK:
  918. adapter->ahw.board_type = NETXEN_NIC_GBE;
  919. break;
  920. default:
  921. printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
  922. boardinfo->board_type);
  923. break;
  924. }
  925. return rv;
  926. }
  927. /* NIU access sections */
  928. int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
  929. {
  930. netxen_nic_write_w0(adapter,
  931. NETXEN_NIU_GB_MAX_FRAME_SIZE(
  932. physical_port[adapter->portnum]), new_mtu);
  933. return 0;
  934. }
  935. int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
  936. {
  937. new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
  938. if (physical_port[adapter->portnum] == 0)
  939. netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
  940. new_mtu);
  941. else
  942. netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
  943. new_mtu);
  944. return 0;
  945. }
  946. void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
  947. {
  948. netxen_niu_gbe_init_port(adapter, physical_port[adapter->portnum]);
  949. }
  950. void
  951. netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
  952. int data)
  953. {
  954. void __iomem *addr;
  955. if (ADDR_IN_WINDOW1(off)) {
  956. writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
  957. } else {
  958. netxen_nic_pci_change_crbwindow(adapter, 0);
  959. addr = pci_base_offset(adapter, off);
  960. writel(data, addr);
  961. netxen_nic_pci_change_crbwindow(adapter, 1);
  962. }
  963. }
  964. void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
  965. {
  966. __u32 status;
  967. __u32 autoneg;
  968. __u32 mode;
  969. netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
  970. if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
  971. if (adapter->phy_read
  972. && adapter->
  973. phy_read(adapter,
  974. NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
  975. &status) == 0) {
  976. if (netxen_get_phy_link(status)) {
  977. switch (netxen_get_phy_speed(status)) {
  978. case 0:
  979. adapter->link_speed = SPEED_10;
  980. break;
  981. case 1:
  982. adapter->link_speed = SPEED_100;
  983. break;
  984. case 2:
  985. adapter->link_speed = SPEED_1000;
  986. break;
  987. default:
  988. adapter->link_speed = -1;
  989. break;
  990. }
  991. switch (netxen_get_phy_duplex(status)) {
  992. case 0:
  993. adapter->link_duplex = DUPLEX_HALF;
  994. break;
  995. case 1:
  996. adapter->link_duplex = DUPLEX_FULL;
  997. break;
  998. default:
  999. adapter->link_duplex = -1;
  1000. break;
  1001. }
  1002. if (adapter->phy_read
  1003. && adapter->
  1004. phy_read(adapter,
  1005. NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
  1006. &autoneg) != 0)
  1007. adapter->link_autoneg = autoneg;
  1008. } else
  1009. goto link_down;
  1010. } else {
  1011. link_down:
  1012. adapter->link_speed = -1;
  1013. adapter->link_duplex = -1;
  1014. }
  1015. }
  1016. }
  1017. void netxen_nic_flash_print(struct netxen_adapter *adapter)
  1018. {
  1019. int valid = 1;
  1020. u32 fw_major = 0;
  1021. u32 fw_minor = 0;
  1022. u32 fw_build = 0;
  1023. char brd_name[NETXEN_MAX_SHORT_NAME];
  1024. char serial_num[32];
  1025. int i, addr;
  1026. __le32 *ptr32;
  1027. struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
  1028. if (board_info->magic != NETXEN_BDINFO_MAGIC) {
  1029. printk
  1030. ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
  1031. board_info->magic, NETXEN_BDINFO_MAGIC);
  1032. valid = 0;
  1033. }
  1034. if (board_info->header_version != NETXEN_BDINFO_VERSION) {
  1035. printk("NetXen Unknown board config version."
  1036. " Read %x, expected %x\n",
  1037. board_info->header_version, NETXEN_BDINFO_VERSION);
  1038. valid = 0;
  1039. }
  1040. if (valid) {
  1041. ptr32 = (u32 *)&serial_num;
  1042. addr = NETXEN_USER_START +
  1043. offsetof(struct netxen_new_user_info, serial_num);
  1044. for (i = 0; i < 8; i++) {
  1045. if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
  1046. printk("%s: ERROR reading %s board userarea.\n",
  1047. netxen_nic_driver_name,
  1048. netxen_nic_driver_name);
  1049. return;
  1050. }
  1051. ptr32++;
  1052. addr += sizeof(u32);
  1053. }
  1054. get_brd_name_by_type(board_info->board_type, brd_name);
  1055. printk("NetXen %s Board S/N %s Chip id 0x%x\n",
  1056. brd_name, serial_num, board_info->chip_id);
  1057. printk("NetXen %s Board #%d, Chip id 0x%x\n",
  1058. board_info->board_type == 0x0b ? "XGB" : "GBE",
  1059. board_info->board_num, board_info->chip_id);
  1060. fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
  1061. NETXEN_FW_VERSION_MAJOR));
  1062. fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
  1063. NETXEN_FW_VERSION_MINOR));
  1064. fw_build =
  1065. readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
  1066. printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
  1067. fw_build);
  1068. }
  1069. if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
  1070. printk(KERN_ERR "The mismatch in driver version and firmware "
  1071. "version major number\n"
  1072. "Driver version major number = %d \t"
  1073. "Firmware version major number = %d \n",
  1074. _NETXEN_NIC_LINUX_MAJOR, fw_major);
  1075. adapter->driver_mismatch = 1;
  1076. }
  1077. if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
  1078. fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
  1079. printk(KERN_ERR "The mismatch in driver version and firmware "
  1080. "version minor number\n"
  1081. "Driver version minor number = %d \t"
  1082. "Firmware version minor number = %d \n",
  1083. _NETXEN_NIC_LINUX_MINOR, fw_minor);
  1084. adapter->driver_mismatch = 1;
  1085. }
  1086. if (adapter->driver_mismatch)
  1087. printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
  1088. fw_major, fw_minor);
  1089. }