netxen_nic.h 33 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. */
  29. #ifndef _NETXEN_NIC_H_
  30. #define _NETXEN_NIC_H_
  31. #include <linux/module.h>
  32. #include <linux/kernel.h>
  33. #include <linux/types.h>
  34. #include <linux/compiler.h>
  35. #include <linux/slab.h>
  36. #include <linux/delay.h>
  37. #include <linux/init.h>
  38. #include <linux/ioport.h>
  39. #include <linux/pci.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/etherdevice.h>
  42. #include <linux/ip.h>
  43. #include <linux/in.h>
  44. #include <linux/tcp.h>
  45. #include <linux/skbuff.h>
  46. #include <linux/version.h>
  47. #include <linux/ethtool.h>
  48. #include <linux/mii.h>
  49. #include <linux/interrupt.h>
  50. #include <linux/timer.h>
  51. #include <linux/mm.h>
  52. #include <linux/mman.h>
  53. #include <asm/system.h>
  54. #include <asm/io.h>
  55. #include <asm/byteorder.h>
  56. #include <asm/uaccess.h>
  57. #include <asm/pgtable.h>
  58. #include "netxen_nic_hw.h"
  59. #define _NETXEN_NIC_LINUX_MAJOR 3
  60. #define _NETXEN_NIC_LINUX_MINOR 4
  61. #define _NETXEN_NIC_LINUX_SUBVERSION 18
  62. #define NETXEN_NIC_LINUX_VERSIONID "3.4.18"
  63. #define NETXEN_NUM_FLASH_SECTORS (64)
  64. #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
  65. #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
  66. * NETXEN_FLASH_SECTOR_SIZE)
  67. #define PHAN_VENDOR_ID 0x4040
  68. #define RCV_DESC_RINGSIZE \
  69. (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
  70. #define STATUS_DESC_RINGSIZE \
  71. (sizeof(struct status_desc)* adapter->max_rx_desc_count)
  72. #define LRO_DESC_RINGSIZE \
  73. (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
  74. #define TX_RINGSIZE \
  75. (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
  76. #define RCV_BUFFSIZE \
  77. (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count)
  78. #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
  79. #define NETXEN_NETDEV_STATUS 0x1
  80. #define NETXEN_RCV_PRODUCER_OFFSET 0
  81. #define NETXEN_RCV_PEG_DB_ID 2
  82. #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
  83. #define FLASH_SUCCESS 0
  84. #define ADDR_IN_WINDOW1(off) \
  85. ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
  86. /*
  87. * normalize a 64MB crb address to 32MB PCI window
  88. * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
  89. */
  90. #define NETXEN_CRB_NORMAL(reg) \
  91. ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
  92. #define NETXEN_CRB_NORMALIZE(adapter, reg) \
  93. pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
  94. #define DB_NORMALIZE(adapter, off) \
  95. (adapter->ahw.db_base + (off))
  96. #define NX_P2_C0 0x24
  97. #define NX_P2_C1 0x25
  98. #define FIRST_PAGE_GROUP_START 0
  99. #define FIRST_PAGE_GROUP_END 0x100000
  100. #define SECOND_PAGE_GROUP_START 0x6000000
  101. #define SECOND_PAGE_GROUP_END 0x68BC000
  102. #define THIRD_PAGE_GROUP_START 0x70E4000
  103. #define THIRD_PAGE_GROUP_END 0x8000000
  104. #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
  105. #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
  106. #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
  107. #define MAX_RX_BUFFER_LENGTH 1760
  108. #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
  109. #define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512)
  110. #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
  111. #define RX_JUMBO_DMA_MAP_LEN \
  112. (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
  113. #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
  114. #define NETXEN_ROM_ROUNDUP 0x80000000ULL
  115. /*
  116. * Maximum number of ring contexts
  117. */
  118. #define MAX_RING_CTX 1
  119. /* Opcodes to be used with the commands */
  120. enum {
  121. TX_ETHER_PKT = 0x01,
  122. /* The following opcodes are for IP checksum */
  123. TX_TCP_PKT,
  124. TX_UDP_PKT,
  125. TX_IP_PKT,
  126. TX_TCP_LSO,
  127. TX_IPSEC,
  128. TX_IPSEC_CMD
  129. };
  130. /* The following opcodes are for internal consumption. */
  131. #define NETXEN_CONTROL_OP 0x10
  132. #define PEGNET_REQUEST 0x11
  133. #define MAX_NUM_CARDS 4
  134. #define MAX_BUFFERS_PER_CMD 32
  135. /*
  136. * Following are the states of the Phantom. Phantom will set them and
  137. * Host will read to check if the fields are correct.
  138. */
  139. #define PHAN_INITIALIZE_START 0xff00
  140. #define PHAN_INITIALIZE_FAILED 0xffff
  141. #define PHAN_INITIALIZE_COMPLETE 0xff01
  142. /* Host writes the following to notify that it has done the init-handshake */
  143. #define PHAN_INITIALIZE_ACK 0xf00f
  144. #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */
  145. /* descriptor types */
  146. #define RCV_DESC_NORMAL 0x01
  147. #define RCV_DESC_JUMBO 0x02
  148. #define RCV_DESC_LRO 0x04
  149. #define RCV_DESC_NORMAL_CTXID 0
  150. #define RCV_DESC_JUMBO_CTXID 1
  151. #define RCV_DESC_LRO_CTXID 2
  152. #define RCV_DESC_TYPE(ID) \
  153. ((ID == RCV_DESC_JUMBO_CTXID) \
  154. ? RCV_DESC_JUMBO \
  155. : ((ID == RCV_DESC_LRO_CTXID) \
  156. ? RCV_DESC_LRO : \
  157. (RCV_DESC_NORMAL)))
  158. #define MAX_CMD_DESCRIPTORS 4096
  159. #define MAX_RCV_DESCRIPTORS 16384
  160. #define MAX_CMD_DESCRIPTORS_HOST (MAX_CMD_DESCRIPTORS / 4)
  161. #define MAX_RCV_DESCRIPTORS_1G (MAX_RCV_DESCRIPTORS / 4)
  162. #define MAX_JUMBO_RCV_DESCRIPTORS 1024
  163. #define MAX_LRO_RCV_DESCRIPTORS 64
  164. #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
  165. #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
  166. #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
  167. #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
  168. #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
  169. #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
  170. MAX_LRO_RCV_DESCRIPTORS)
  171. #define MIN_TX_COUNT 4096
  172. #define MIN_RX_COUNT 4096
  173. #define NETXEN_CTX_SIGNATURE 0xdee0
  174. #define NETXEN_RCV_PRODUCER(ringid) (ringid)
  175. #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
  176. #define PHAN_PEG_RCV_INITIALIZED 0xff01
  177. #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
  178. #define get_next_index(index, length) \
  179. (((index) + 1) & ((length) - 1))
  180. #define get_index_range(index,length,count) \
  181. (((index) + (count)) & ((length) - 1))
  182. #define MPORT_SINGLE_FUNCTION_MODE 0x1111
  183. #define MPORT_MULTI_FUNCTION_MODE 0x2222
  184. #include "netxen_nic_phan_reg.h"
  185. extern unsigned long long netxen_dma_mask;
  186. extern unsigned long last_schedule_time;
  187. /*
  188. * NetXen host-peg signal message structure
  189. *
  190. * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
  191. * Bit 2 : priv_id => must be 1
  192. * Bit 3-17 : count => for doorbell
  193. * Bit 18-27 : ctx_id => Context id
  194. * Bit 28-31 : opcode
  195. */
  196. typedef u32 netxen_ctx_msg;
  197. #define netxen_set_msg_peg_id(config_word, val) \
  198. ((config_word) &= ~3, (config_word) |= val & 3)
  199. #define netxen_set_msg_privid(config_word) \
  200. ((config_word) |= 1 << 2)
  201. #define netxen_set_msg_count(config_word, val) \
  202. ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
  203. #define netxen_set_msg_ctxid(config_word, val) \
  204. ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
  205. #define netxen_set_msg_opcode(config_word, val) \
  206. ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
  207. struct netxen_rcv_context {
  208. __le64 rcv_ring_addr;
  209. __le32 rcv_ring_size;
  210. __le32 rsrvd;
  211. };
  212. struct netxen_ring_ctx {
  213. /* one command ring */
  214. __le64 cmd_consumer_offset;
  215. __le64 cmd_ring_addr;
  216. __le32 cmd_ring_size;
  217. __le32 rsrvd;
  218. /* three receive rings */
  219. struct netxen_rcv_context rcv_ctx[3];
  220. /* one status ring */
  221. __le64 sts_ring_addr;
  222. __le32 sts_ring_size;
  223. __le32 ctx_id;
  224. } __attribute__ ((aligned(64)));
  225. /*
  226. * Following data structures describe the descriptors that will be used.
  227. * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
  228. * we are doing LSO (above the 1500 size packet) only.
  229. */
  230. /*
  231. * The size of reference handle been changed to 16 bits to pass the MSS fields
  232. * for the LSO packet
  233. */
  234. #define FLAGS_CHECKSUM_ENABLED 0x01
  235. #define FLAGS_LSO_ENABLED 0x02
  236. #define FLAGS_IPSEC_SA_ADD 0x04
  237. #define FLAGS_IPSEC_SA_DELETE 0x08
  238. #define FLAGS_VLAN_TAGGED 0x10
  239. #define netxen_set_cmd_desc_port(cmd_desc, var) \
  240. ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
  241. #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
  242. ((cmd_desc)->port_ctxid |= ((var) & 0xF0))
  243. #define netxen_set_cmd_desc_flags(cmd_desc, val) \
  244. (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
  245. ~cpu_to_le16(0x7f)) | cpu_to_le16((val) & 0x7f)
  246. #define netxen_set_cmd_desc_opcode(cmd_desc, val) \
  247. (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
  248. ~cpu_to_le16((u16)0x3f << 7)) | cpu_to_le16(((val) & 0x3f) << 7)
  249. #define netxen_set_cmd_desc_num_of_buff(cmd_desc, val) \
  250. (cmd_desc)->num_of_buffers_total_length = \
  251. ((cmd_desc)->num_of_buffers_total_length & \
  252. ~cpu_to_le32(0xff)) | cpu_to_le32((val) & 0xff)
  253. #define netxen_set_cmd_desc_totallength(cmd_desc, val) \
  254. (cmd_desc)->num_of_buffers_total_length = \
  255. ((cmd_desc)->num_of_buffers_total_length & \
  256. ~cpu_to_le32((u32)0xffffff << 8)) | \
  257. cpu_to_le32(((val) & 0xffffff) << 8)
  258. #define netxen_get_cmd_desc_opcode(cmd_desc) \
  259. ((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003f)
  260. #define netxen_get_cmd_desc_totallength(cmd_desc) \
  261. ((le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8) & 0xffffff)
  262. struct cmd_desc_type0 {
  263. u8 tcp_hdr_offset; /* For LSO only */
  264. u8 ip_hdr_offset; /* For LSO only */
  265. /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
  266. __le16 flags_opcode;
  267. /* Bit pattern: 0-7 total number of segments,
  268. 8-31 Total size of the packet */
  269. __le32 num_of_buffers_total_length;
  270. union {
  271. struct {
  272. __le32 addr_low_part2;
  273. __le32 addr_high_part2;
  274. };
  275. __le64 addr_buffer2;
  276. };
  277. __le16 reference_handle; /* changed to u16 to add mss */
  278. __le16 mss; /* passed by NDIS_PACKET for LSO */
  279. /* Bit pattern 0-3 port, 0-3 ctx id */
  280. u8 port_ctxid;
  281. u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
  282. __le16 conn_id; /* IPSec offoad only */
  283. union {
  284. struct {
  285. __le32 addr_low_part3;
  286. __le32 addr_high_part3;
  287. };
  288. __le64 addr_buffer3;
  289. };
  290. union {
  291. struct {
  292. __le32 addr_low_part1;
  293. __le32 addr_high_part1;
  294. };
  295. __le64 addr_buffer1;
  296. };
  297. __le16 buffer1_length;
  298. __le16 buffer2_length;
  299. __le16 buffer3_length;
  300. __le16 buffer4_length;
  301. union {
  302. struct {
  303. __le32 addr_low_part4;
  304. __le32 addr_high_part4;
  305. };
  306. __le64 addr_buffer4;
  307. };
  308. __le64 unused;
  309. } __attribute__ ((aligned(64)));
  310. /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
  311. struct rcv_desc {
  312. __le16 reference_handle;
  313. __le16 reserved;
  314. __le32 buffer_length; /* allocated buffer length (usually 2K) */
  315. __le64 addr_buffer;
  316. };
  317. /* opcode field in status_desc */
  318. #define RCV_NIC_PKT (0xA)
  319. #define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12)
  320. /* for status field in status_desc */
  321. #define STATUS_NEED_CKSUM (1)
  322. #define STATUS_CKSUM_OK (2)
  323. /* owner bits of status_desc */
  324. #define STATUS_OWNER_HOST (0x1)
  325. #define STATUS_OWNER_PHANTOM (0x2)
  326. #define NETXEN_PROT_IP (1)
  327. #define NETXEN_PROT_UNKNOWN (0)
  328. /* Note: sizeof(status_desc) should always be a mutliple of 2 */
  329. #define netxen_get_sts_desc_lro_cnt(status_desc) \
  330. ((status_desc)->lro & 0x7F)
  331. #define netxen_get_sts_desc_lro_last_frag(status_desc) \
  332. (((status_desc)->lro & 0x80) >> 7)
  333. #define netxen_get_sts_port(sts_data) \
  334. ((sts_data) & 0x0F)
  335. #define netxen_get_sts_status(sts_data) \
  336. (((sts_data) >> 4) & 0x0F)
  337. #define netxen_get_sts_type(sts_data) \
  338. (((sts_data) >> 8) & 0x0F)
  339. #define netxen_get_sts_totallength(sts_data) \
  340. (((sts_data) >> 12) & 0xFFFF)
  341. #define netxen_get_sts_refhandle(sts_data) \
  342. (((sts_data) >> 28) & 0xFFFF)
  343. #define netxen_get_sts_prot(sts_data) \
  344. (((sts_data) >> 44) & 0x0F)
  345. #define netxen_get_sts_opcode(sts_data) \
  346. (((sts_data) >> 58) & 0x03F)
  347. #define netxen_get_sts_owner(status_desc) \
  348. ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03)
  349. #define netxen_set_sts_owner(status_desc, val) { \
  350. (status_desc)->status_desc_data = \
  351. ((status_desc)->status_desc_data & \
  352. ~cpu_to_le64(0x3ULL << 56)) | \
  353. cpu_to_le64((u64)((val) & 0x3) << 56); \
  354. }
  355. struct status_desc {
  356. /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
  357. 28-43 reference_handle, 44-47 protocol, 48-52 unused
  358. 53-55 desc_cnt, 56-57 owner, 58-63 opcode
  359. */
  360. __le64 status_desc_data;
  361. __le32 hash_value;
  362. u8 hash_type;
  363. u8 msg_type;
  364. u8 unused;
  365. /* Bit pattern: 0-6 lro_count indicates frag sequence,
  366. 7 last_frag indicates last frag */
  367. u8 lro;
  368. } __attribute__ ((aligned(16)));
  369. enum {
  370. NETXEN_RCV_PEG_0 = 0,
  371. NETXEN_RCV_PEG_1
  372. };
  373. /* The version of the main data structure */
  374. #define NETXEN_BDINFO_VERSION 1
  375. /* Magic number to let user know flash is programmed */
  376. #define NETXEN_BDINFO_MAGIC 0x12345678
  377. /* Max number of Gig ports on a Phantom board */
  378. #define NETXEN_MAX_PORTS 4
  379. typedef enum {
  380. NETXEN_BRDTYPE_P1_BD = 0x0000,
  381. NETXEN_BRDTYPE_P1_SB = 0x0001,
  382. NETXEN_BRDTYPE_P1_SMAX = 0x0002,
  383. NETXEN_BRDTYPE_P1_SOCK = 0x0003,
  384. NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
  385. NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
  386. NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
  387. NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
  388. NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
  389. NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
  390. NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
  391. NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f
  392. } netxen_brdtype_t;
  393. typedef enum {
  394. NETXEN_BRDMFG_INVENTEC = 1
  395. } netxen_brdmfg;
  396. typedef enum {
  397. MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
  398. MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
  399. MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
  400. MEM_ORG_256Mbx4 = 0x3,
  401. MEM_ORG_256Mbx8 = 0x4,
  402. MEM_ORG_256Mbx16 = 0x5,
  403. MEM_ORG_512Mbx4 = 0x6,
  404. MEM_ORG_512Mbx8 = 0x7,
  405. MEM_ORG_512Mbx16 = 0x8,
  406. MEM_ORG_1Gbx4 = 0x9,
  407. MEM_ORG_1Gbx8 = 0xa,
  408. MEM_ORG_1Gbx16 = 0xb,
  409. MEM_ORG_2Gbx4 = 0xc,
  410. MEM_ORG_2Gbx8 = 0xd,
  411. MEM_ORG_2Gbx16 = 0xe,
  412. MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
  413. MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
  414. } netxen_mn_mem_org_t;
  415. typedef enum {
  416. MEM_ORG_512Kx36 = 0x0,
  417. MEM_ORG_1Mx36 = 0x1,
  418. MEM_ORG_2Mx36 = 0x2
  419. } netxen_sn_mem_org_t;
  420. typedef enum {
  421. MEM_DEPTH_4MB = 0x1,
  422. MEM_DEPTH_8MB = 0x2,
  423. MEM_DEPTH_16MB = 0x3,
  424. MEM_DEPTH_32MB = 0x4,
  425. MEM_DEPTH_64MB = 0x5,
  426. MEM_DEPTH_128MB = 0x6,
  427. MEM_DEPTH_256MB = 0x7,
  428. MEM_DEPTH_512MB = 0x8,
  429. MEM_DEPTH_1GB = 0x9,
  430. MEM_DEPTH_2GB = 0xa,
  431. MEM_DEPTH_4GB = 0xb,
  432. MEM_DEPTH_8GB = 0xc,
  433. MEM_DEPTH_16GB = 0xd,
  434. MEM_DEPTH_32GB = 0xe
  435. } netxen_mem_depth_t;
  436. struct netxen_board_info {
  437. u32 header_version;
  438. u32 board_mfg;
  439. u32 board_type;
  440. u32 board_num;
  441. u32 chip_id;
  442. u32 chip_minor;
  443. u32 chip_major;
  444. u32 chip_pkg;
  445. u32 chip_lot;
  446. u32 port_mask; /* available niu ports */
  447. u32 peg_mask; /* available pegs */
  448. u32 icache_ok; /* can we run with icache? */
  449. u32 dcache_ok; /* can we run with dcache? */
  450. u32 casper_ok;
  451. u32 mac_addr_lo_0;
  452. u32 mac_addr_lo_1;
  453. u32 mac_addr_lo_2;
  454. u32 mac_addr_lo_3;
  455. /* MN-related config */
  456. u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
  457. u32 mn_sync_shift_cclk;
  458. u32 mn_sync_shift_mclk;
  459. u32 mn_wb_en;
  460. u32 mn_crystal_freq; /* in MHz */
  461. u32 mn_speed; /* in MHz */
  462. u32 mn_org;
  463. u32 mn_depth;
  464. u32 mn_ranks_0; /* ranks per slot */
  465. u32 mn_ranks_1; /* ranks per slot */
  466. u32 mn_rd_latency_0;
  467. u32 mn_rd_latency_1;
  468. u32 mn_rd_latency_2;
  469. u32 mn_rd_latency_3;
  470. u32 mn_rd_latency_4;
  471. u32 mn_rd_latency_5;
  472. u32 mn_rd_latency_6;
  473. u32 mn_rd_latency_7;
  474. u32 mn_rd_latency_8;
  475. u32 mn_dll_val[18];
  476. u32 mn_mode_reg; /* MIU DDR Mode Register */
  477. u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
  478. u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
  479. u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
  480. u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
  481. /* SN-related config */
  482. u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
  483. u32 sn_pt_mode; /* pass through mode */
  484. u32 sn_ecc_en;
  485. u32 sn_wb_en;
  486. u32 sn_crystal_freq;
  487. u32 sn_speed;
  488. u32 sn_org;
  489. u32 sn_depth;
  490. u32 sn_dll_tap;
  491. u32 sn_rd_latency;
  492. u32 mac_addr_hi_0;
  493. u32 mac_addr_hi_1;
  494. u32 mac_addr_hi_2;
  495. u32 mac_addr_hi_3;
  496. u32 magic; /* indicates flash has been initialized */
  497. u32 mn_rdimm;
  498. u32 mn_dll_override;
  499. };
  500. #define FLASH_NUM_PORTS (4)
  501. struct netxen_flash_mac_addr {
  502. u32 flash_addr[32];
  503. };
  504. struct netxen_user_old_info {
  505. u8 flash_md5[16];
  506. u8 crbinit_md5[16];
  507. u8 brdcfg_md5[16];
  508. /* bootloader */
  509. u32 bootld_version;
  510. u32 bootld_size;
  511. u8 bootld_md5[16];
  512. /* image */
  513. u32 image_version;
  514. u32 image_size;
  515. u8 image_md5[16];
  516. /* primary image status */
  517. u32 primary_status;
  518. u32 secondary_present;
  519. /* MAC address , 4 ports */
  520. struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
  521. };
  522. #define FLASH_NUM_MAC_PER_PORT 32
  523. struct netxen_user_info {
  524. u8 flash_md5[16 * 64];
  525. /* bootloader */
  526. u32 bootld_version;
  527. u32 bootld_size;
  528. /* image */
  529. u32 image_version;
  530. u32 image_size;
  531. /* primary image status */
  532. u32 primary_status;
  533. u32 secondary_present;
  534. /* MAC address , 4 ports, 32 address per port */
  535. u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
  536. u32 sub_sys_id;
  537. u8 serial_num[32];
  538. /* Any user defined data */
  539. };
  540. /*
  541. * Flash Layout - new format.
  542. */
  543. struct netxen_new_user_info {
  544. u8 flash_md5[16 * 64];
  545. /* bootloader */
  546. u32 bootld_version;
  547. u32 bootld_size;
  548. /* image */
  549. u32 image_version;
  550. u32 image_size;
  551. /* primary image status */
  552. u32 primary_status;
  553. u32 secondary_present;
  554. /* MAC address , 4 ports, 32 address per port */
  555. u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
  556. u32 sub_sys_id;
  557. u8 serial_num[32];
  558. /* Any user defined data */
  559. };
  560. #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
  561. #define SECONDARY_IMAGE_ABSENT 0xffffffff
  562. #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
  563. #define PRIMARY_IMAGE_BAD 0xffffffff
  564. /* Flash memory map */
  565. typedef enum {
  566. NETXEN_CRBINIT_START = 0, /* Crbinit section */
  567. NETXEN_BRDCFG_START = 0x4000, /* board config */
  568. NETXEN_INITCODE_START = 0x6000, /* pegtune code */
  569. NETXEN_BOOTLD_START = 0x10000, /* bootld */
  570. NETXEN_IMAGE_START = 0x43000, /* compressed image */
  571. NETXEN_SECONDARY_START = 0x200000, /* backup images */
  572. NETXEN_PXE_START = 0x3E0000, /* user defined region */
  573. NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */
  574. NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */
  575. } netxen_flash_map_t;
  576. #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
  577. #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
  578. #define NETXEN_INIT_SECTOR (0)
  579. #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
  580. #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
  581. #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
  582. #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
  583. #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
  584. #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
  585. #define NETXEN_NUM_CONFIG_SECTORS (1)
  586. #define PFX "NetXen: "
  587. extern char netxen_nic_driver_name[];
  588. /* Note: Make sure to not call this before adapter->port is valid */
  589. #if !defined(NETXEN_DEBUG)
  590. #define DPRINTK(klevel, fmt, args...) do { \
  591. } while (0)
  592. #else
  593. #define DPRINTK(klevel, fmt, args...) do { \
  594. printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
  595. (adapter != NULL && adapter->netdev != NULL) ? \
  596. adapter->netdev->name : NULL, \
  597. ## args); } while(0)
  598. #endif
  599. /* Number of status descriptors to handle per interrupt */
  600. #define MAX_STATUS_HANDLE (128)
  601. /*
  602. * netxen_skb_frag{} is to contain mapping info for each SG list. This
  603. * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
  604. */
  605. struct netxen_skb_frag {
  606. u64 dma;
  607. u32 length;
  608. };
  609. #define _netxen_set_bits(config_word, start, bits, val) {\
  610. unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
  611. unsigned long long __tvalue = (val); \
  612. (config_word) &= ~__tmask; \
  613. (config_word) |= (((__tvalue) << (start)) & __tmask); \
  614. }
  615. #define _netxen_clear_bits(config_word, start, bits) {\
  616. unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
  617. (config_word) &= ~__tmask; \
  618. }
  619. /* Following defines are for the state of the buffers */
  620. #define NETXEN_BUFFER_FREE 0
  621. #define NETXEN_BUFFER_BUSY 1
  622. /*
  623. * There will be one netxen_buffer per skb packet. These will be
  624. * used to save the dma info for pci_unmap_page()
  625. */
  626. struct netxen_cmd_buffer {
  627. struct sk_buff *skb;
  628. struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
  629. u32 total_length;
  630. u32 mss;
  631. u16 port;
  632. u8 cmd;
  633. u8 frag_count;
  634. unsigned long time_stamp;
  635. u32 state;
  636. };
  637. /* In rx_buffer, we do not need multiple fragments as is a single buffer */
  638. struct netxen_rx_buffer {
  639. struct sk_buff *skb;
  640. u64 dma;
  641. u16 ref_handle;
  642. u16 state;
  643. u32 lro_expected_frags;
  644. u32 lro_current_frags;
  645. u32 lro_length;
  646. };
  647. /* Board types */
  648. #define NETXEN_NIC_GBE 0x01
  649. #define NETXEN_NIC_XGBE 0x02
  650. /*
  651. * One hardware_context{} per adapter
  652. * contains interrupt info as well shared hardware info.
  653. */
  654. struct netxen_hardware_context {
  655. struct pci_dev *pdev;
  656. void __iomem *pci_base0;
  657. void __iomem *pci_base1;
  658. void __iomem *pci_base2;
  659. unsigned long first_page_group_end;
  660. unsigned long first_page_group_start;
  661. void __iomem *db_base;
  662. unsigned long db_len;
  663. u8 revision_id;
  664. u16 board_type;
  665. u16 max_ports;
  666. struct netxen_board_info boardcfg;
  667. u32 xg_linkup;
  668. u32 qg_linksup;
  669. /* Address of cmd ring in Phantom */
  670. struct cmd_desc_type0 *cmd_desc_head;
  671. struct pci_dev *cmd_desc_pdev;
  672. dma_addr_t cmd_desc_phys_addr;
  673. struct netxen_adapter *adapter;
  674. int pci_func;
  675. };
  676. #define RCV_RING_LRO RCV_DESC_LRO
  677. #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
  678. #define ETHERNET_FCS_SIZE 4
  679. struct netxen_adapter_stats {
  680. u64 rcvdbadskb;
  681. u64 xmitcalled;
  682. u64 xmitedframes;
  683. u64 xmitfinished;
  684. u64 badskblen;
  685. u64 nocmddescriptor;
  686. u64 polled;
  687. u64 rxdropped;
  688. u64 txdropped;
  689. u64 csummed;
  690. u64 no_rcv;
  691. u64 rxbytes;
  692. u64 txbytes;
  693. u64 ints;
  694. };
  695. /*
  696. * Rcv Descriptor Context. One such per Rcv Descriptor. There may
  697. * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
  698. */
  699. struct netxen_rcv_desc_ctx {
  700. u32 flags;
  701. u32 producer;
  702. u32 rcv_pending; /* Num of bufs posted in phantom */
  703. dma_addr_t phys_addr;
  704. struct pci_dev *phys_pdev;
  705. struct rcv_desc *desc_head; /* address of rx ring in Phantom */
  706. u32 max_rx_desc_count;
  707. u32 dma_size;
  708. u32 skb_size;
  709. struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
  710. int begin_alloc;
  711. };
  712. /*
  713. * Receive context. There is one such structure per instance of the
  714. * receive processing. Any state information that is relevant to
  715. * the receive, and is must be in this structure. The global data may be
  716. * present elsewhere.
  717. */
  718. struct netxen_recv_context {
  719. struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS];
  720. u32 status_rx_producer;
  721. u32 status_rx_consumer;
  722. dma_addr_t rcv_status_desc_phys_addr;
  723. struct pci_dev *rcv_status_desc_pdev;
  724. struct status_desc *rcv_status_desc_head;
  725. };
  726. #define NETXEN_NIC_MSI_ENABLED 0x02
  727. #define NETXEN_DMA_MASK 0xfffffffe
  728. #define NETXEN_DB_MAPSIZE_BYTES 0x1000
  729. struct netxen_dummy_dma {
  730. void *addr;
  731. dma_addr_t phys_addr;
  732. };
  733. struct netxen_adapter {
  734. struct netxen_hardware_context ahw;
  735. struct netxen_adapter *master;
  736. struct net_device *netdev;
  737. struct pci_dev *pdev;
  738. struct napi_struct napi;
  739. struct net_device_stats net_stats;
  740. unsigned char mac_addr[ETH_ALEN];
  741. int mtu;
  742. int portnum;
  743. struct work_struct watchdog_task;
  744. struct timer_list watchdog_timer;
  745. struct work_struct tx_timeout_task;
  746. u32 curr_window;
  747. u32 cmd_producer;
  748. __le32 *cmd_consumer;
  749. u32 last_cmd_consumer;
  750. u32 max_tx_desc_count;
  751. u32 max_rx_desc_count;
  752. u32 max_jumbo_rx_desc_count;
  753. u32 max_lro_rx_desc_count;
  754. u32 flags;
  755. u32 irq;
  756. int driver_mismatch;
  757. u32 temp;
  758. struct netxen_adapter_stats stats;
  759. u16 portno;
  760. u16 link_speed;
  761. u16 link_duplex;
  762. u16 state;
  763. u16 link_autoneg;
  764. int rx_csum;
  765. int status;
  766. spinlock_t stats_lock;
  767. struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
  768. /*
  769. * Receive instances. These can be either one per port,
  770. * or one per peg, etc.
  771. */
  772. struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
  773. int is_up;
  774. struct netxen_dummy_dma dummy_dma;
  775. /* Context interface shared between card and host */
  776. struct netxen_ring_ctx *ctx_desc;
  777. struct pci_dev *ctx_desc_pdev;
  778. dma_addr_t ctx_desc_phys_addr;
  779. int intr_scheme;
  780. int msi_mode;
  781. int (*enable_phy_interrupts) (struct netxen_adapter *);
  782. int (*disable_phy_interrupts) (struct netxen_adapter *);
  783. void (*handle_phy_intr) (struct netxen_adapter *);
  784. int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
  785. int (*set_mtu) (struct netxen_adapter *, int);
  786. int (*set_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t);
  787. int (*unset_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t);
  788. int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
  789. int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
  790. int (*init_port) (struct netxen_adapter *, int);
  791. void (*init_niu) (struct netxen_adapter *);
  792. int (*stop_port) (struct netxen_adapter *);
  793. }; /* netxen_adapter structure */
  794. /*
  795. * NetXen dma watchdog control structure
  796. *
  797. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  798. * Bit 1 : disable_request => 1 req disable dma watchdog
  799. * Bit 2 : enable_request => 1 req enable dma watchdog
  800. * Bit 3-31 : unused
  801. */
  802. #define netxen_set_dma_watchdog_disable_req(config_word) \
  803. _netxen_set_bits(config_word, 1, 1, 1)
  804. #define netxen_set_dma_watchdog_enable_req(config_word) \
  805. _netxen_set_bits(config_word, 2, 1, 1)
  806. #define netxen_get_dma_watchdog_enabled(config_word) \
  807. ((config_word) & 0x1)
  808. #define netxen_get_dma_watchdog_disabled(config_word) \
  809. (((config_word) >> 1) & 0x1)
  810. /* Max number of xmit producer threads that can run simultaneously */
  811. #define MAX_XMIT_PRODUCERS 16
  812. #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
  813. ((adapter)->ahw.pci_base0 + (off))
  814. #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
  815. ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
  816. #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
  817. ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
  818. static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
  819. unsigned long off)
  820. {
  821. if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
  822. return (adapter->ahw.pci_base0 + off);
  823. } else if ((off < SECOND_PAGE_GROUP_END) &&
  824. (off >= SECOND_PAGE_GROUP_START)) {
  825. return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
  826. } else if ((off < THIRD_PAGE_GROUP_END) &&
  827. (off >= THIRD_PAGE_GROUP_START)) {
  828. return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
  829. }
  830. return NULL;
  831. }
  832. static inline void __iomem *pci_base(struct netxen_adapter *adapter,
  833. unsigned long off)
  834. {
  835. if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
  836. return adapter->ahw.pci_base0;
  837. } else if ((off < SECOND_PAGE_GROUP_END) &&
  838. (off >= SECOND_PAGE_GROUP_START)) {
  839. return adapter->ahw.pci_base1;
  840. } else if ((off < THIRD_PAGE_GROUP_END) &&
  841. (off >= THIRD_PAGE_GROUP_START)) {
  842. return adapter->ahw.pci_base2;
  843. }
  844. return NULL;
  845. }
  846. int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
  847. int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
  848. int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
  849. int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
  850. void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter);
  851. void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter);
  852. int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
  853. __u32 * readval);
  854. int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
  855. long reg, __u32 val);
  856. /* Functions available from netxen_nic_hw.c */
  857. int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
  858. int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
  859. void netxen_nic_init_niu_gb(struct netxen_adapter *adapter);
  860. void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw);
  861. void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
  862. int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
  863. void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
  864. void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value);
  865. int netxen_nic_get_board_info(struct netxen_adapter *adapter);
  866. int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
  867. int len);
  868. int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
  869. int len);
  870. void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
  871. unsigned long off, int data);
  872. /* Functions from netxen_nic_init.c */
  873. void netxen_free_adapter_offload(struct netxen_adapter *adapter);
  874. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
  875. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
  876. int netxen_load_firmware(struct netxen_adapter *adapter);
  877. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
  878. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
  879. int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  880. u8 *bytes, size_t size);
  881. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  882. u8 *bytes, size_t size);
  883. int netxen_flash_unlock(struct netxen_adapter *adapter);
  884. int netxen_backup_crbinit(struct netxen_adapter *adapter);
  885. int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
  886. int netxen_flash_erase_primary(struct netxen_adapter *adapter);
  887. void netxen_halt_pegs(struct netxen_adapter *adapter);
  888. int netxen_rom_se(struct netxen_adapter *adapter, int addr);
  889. /* Functions from netxen_nic_isr.c */
  890. void netxen_initialize_adapter_sw(struct netxen_adapter *adapter);
  891. void netxen_initialize_adapter_hw(struct netxen_adapter *adapter);
  892. void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
  893. struct pci_dev **used_dev);
  894. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
  895. int netxen_init_firmware(struct netxen_adapter *adapter);
  896. void netxen_free_hw_resources(struct netxen_adapter *adapter);
  897. void netxen_tso_check(struct netxen_adapter *adapter,
  898. struct cmd_desc_type0 *desc, struct sk_buff *skb);
  899. int netxen_nic_hw_resources(struct netxen_adapter *adapter);
  900. void netxen_nic_clear_stats(struct netxen_adapter *adapter);
  901. void netxen_watchdog_task(struct work_struct *work);
  902. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
  903. u32 ringid);
  904. int netxen_process_cmd_ring(struct netxen_adapter *adapter);
  905. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
  906. void netxen_nic_set_multi(struct net_device *netdev);
  907. int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
  908. int netxen_nic_set_mac(struct net_device *netdev, void *p);
  909. struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
  910. /*
  911. * NetXen Board information
  912. */
  913. #define NETXEN_MAX_SHORT_NAME 16
  914. struct netxen_brdinfo {
  915. netxen_brdtype_t brdtype; /* type of board */
  916. long ports; /* max no of physical ports */
  917. char short_name[NETXEN_MAX_SHORT_NAME];
  918. };
  919. static const struct netxen_brdinfo netxen_boards[] = {
  920. {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
  921. {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
  922. {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
  923. {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
  924. {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
  925. {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
  926. };
  927. #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
  928. static inline void get_brd_port_by_type(u32 type, int *ports)
  929. {
  930. int i, found = 0;
  931. for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
  932. if (netxen_boards[i].brdtype == type) {
  933. *ports = netxen_boards[i].ports;
  934. found = 1;
  935. break;
  936. }
  937. }
  938. if (!found)
  939. *ports = 0;
  940. }
  941. static inline void get_brd_name_by_type(u32 type, char *name)
  942. {
  943. int i, found = 0;
  944. for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
  945. if (netxen_boards[i].brdtype == type) {
  946. strcpy(name, netxen_boards[i].short_name);
  947. found = 1;
  948. break;
  949. }
  950. }
  951. if (!found)
  952. name = "Unknown";
  953. }
  954. static inline int
  955. dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
  956. {
  957. u32 ctrl;
  958. /* check if already inactive */
  959. if (netxen_nic_hw_read_wx(adapter,
  960. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
  961. printk(KERN_ERR "failed to read dma watchdog status\n");
  962. if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
  963. return 1;
  964. /* Send the disable request */
  965. netxen_set_dma_watchdog_disable_req(ctrl);
  966. netxen_crb_writelit_adapter(adapter,
  967. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
  968. return 0;
  969. }
  970. static inline int
  971. dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
  972. {
  973. u32 ctrl;
  974. if (netxen_nic_hw_read_wx(adapter,
  975. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
  976. printk(KERN_ERR "failed to read dma watchdog status\n");
  977. return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
  978. }
  979. static inline int
  980. dma_watchdog_wakeup(struct netxen_adapter *adapter)
  981. {
  982. u32 ctrl;
  983. if (netxen_nic_hw_read_wx(adapter,
  984. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
  985. printk(KERN_ERR "failed to read dma watchdog status\n");
  986. if (netxen_get_dma_watchdog_enabled(ctrl))
  987. return 1;
  988. /* send the wakeup request */
  989. netxen_set_dma_watchdog_enable_req(ctrl);
  990. netxen_crb_writelit_adapter(adapter,
  991. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
  992. return 0;
  993. }
  994. int netxen_is_flash_supported(struct netxen_adapter *adapter);
  995. int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]);
  996. extern void netxen_change_ringparam(struct netxen_adapter *adapter);
  997. extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
  998. int *valp);
  999. extern struct ethtool_ops netxen_nic_ethtool_ops;
  1000. extern int physical_port[]; /* physical port # from virtual port.*/
  1001. #endif /* __NETXEN_NIC_H_ */