ixgb_main.c 63 KB

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  1. /*******************************************************************************
  2. Intel PRO/10GbE Linux driver
  3. Copyright(c) 1999 - 2006 Intel Corporation.
  4. This program is free software; you can redistribute it and/or modify it
  5. under the terms and conditions of the GNU General Public License,
  6. version 2, as published by the Free Software Foundation.
  7. This program is distributed in the hope it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc.,
  13. 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  14. The full GNU General Public License is included in this distribution in
  15. the file called "COPYING".
  16. Contact Information:
  17. Linux NICS <linux.nics@intel.com>
  18. e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20. *******************************************************************************/
  21. #include "ixgb.h"
  22. char ixgb_driver_name[] = "ixgb";
  23. static char ixgb_driver_string[] = "Intel(R) PRO/10GbE Network Driver";
  24. #ifndef CONFIG_IXGB_NAPI
  25. #define DRIVERNAPI
  26. #else
  27. #define DRIVERNAPI "-NAPI"
  28. #endif
  29. #define DRV_VERSION "1.0.126-k4"DRIVERNAPI
  30. const char ixgb_driver_version[] = DRV_VERSION;
  31. static const char ixgb_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
  32. /* ixgb_pci_tbl - PCI Device ID Table
  33. *
  34. * Wildcard entries (PCI_ANY_ID) should come last
  35. * Last entry must be all 0s
  36. *
  37. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  38. * Class, Class Mask, private data (not used) }
  39. */
  40. static struct pci_device_id ixgb_pci_tbl[] = {
  41. {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX,
  42. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  43. {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX_CX4,
  44. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  45. {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX_SR,
  46. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  47. {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX_LR,
  48. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  49. /* required last entry */
  50. {0,}
  51. };
  52. MODULE_DEVICE_TABLE(pci, ixgb_pci_tbl);
  53. /* Local Function Prototypes */
  54. int ixgb_up(struct ixgb_adapter *adapter);
  55. void ixgb_down(struct ixgb_adapter *adapter, bool kill_watchdog);
  56. void ixgb_reset(struct ixgb_adapter *adapter);
  57. int ixgb_setup_tx_resources(struct ixgb_adapter *adapter);
  58. int ixgb_setup_rx_resources(struct ixgb_adapter *adapter);
  59. void ixgb_free_tx_resources(struct ixgb_adapter *adapter);
  60. void ixgb_free_rx_resources(struct ixgb_adapter *adapter);
  61. void ixgb_update_stats(struct ixgb_adapter *adapter);
  62. static int ixgb_init_module(void);
  63. static void ixgb_exit_module(void);
  64. static int ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  65. static void __devexit ixgb_remove(struct pci_dev *pdev);
  66. static int ixgb_sw_init(struct ixgb_adapter *adapter);
  67. static int ixgb_open(struct net_device *netdev);
  68. static int ixgb_close(struct net_device *netdev);
  69. static void ixgb_configure_tx(struct ixgb_adapter *adapter);
  70. static void ixgb_configure_rx(struct ixgb_adapter *adapter);
  71. static void ixgb_setup_rctl(struct ixgb_adapter *adapter);
  72. static void ixgb_clean_tx_ring(struct ixgb_adapter *adapter);
  73. static void ixgb_clean_rx_ring(struct ixgb_adapter *adapter);
  74. static void ixgb_set_multi(struct net_device *netdev);
  75. static void ixgb_watchdog(unsigned long data);
  76. static int ixgb_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
  77. static struct net_device_stats *ixgb_get_stats(struct net_device *netdev);
  78. static int ixgb_change_mtu(struct net_device *netdev, int new_mtu);
  79. static int ixgb_set_mac(struct net_device *netdev, void *p);
  80. static irqreturn_t ixgb_intr(int irq, void *data);
  81. static bool ixgb_clean_tx_irq(struct ixgb_adapter *adapter);
  82. #ifdef CONFIG_IXGB_NAPI
  83. static int ixgb_clean(struct napi_struct *napi, int budget);
  84. static bool ixgb_clean_rx_irq(struct ixgb_adapter *adapter,
  85. int *work_done, int work_to_do);
  86. #else
  87. static bool ixgb_clean_rx_irq(struct ixgb_adapter *adapter);
  88. #endif
  89. static void ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter);
  90. static void ixgb_tx_timeout(struct net_device *dev);
  91. static void ixgb_tx_timeout_task(struct work_struct *work);
  92. static void ixgb_vlan_rx_register(struct net_device *netdev,
  93. struct vlan_group *grp);
  94. static void ixgb_vlan_rx_add_vid(struct net_device *netdev, u16 vid);
  95. static void ixgb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid);
  96. static void ixgb_restore_vlan(struct ixgb_adapter *adapter);
  97. #ifdef CONFIG_NET_POLL_CONTROLLER
  98. /* for netdump / net console */
  99. static void ixgb_netpoll(struct net_device *dev);
  100. #endif
  101. static pci_ers_result_t ixgb_io_error_detected (struct pci_dev *pdev,
  102. enum pci_channel_state state);
  103. static pci_ers_result_t ixgb_io_slot_reset (struct pci_dev *pdev);
  104. static void ixgb_io_resume (struct pci_dev *pdev);
  105. static struct pci_error_handlers ixgb_err_handler = {
  106. .error_detected = ixgb_io_error_detected,
  107. .slot_reset = ixgb_io_slot_reset,
  108. .resume = ixgb_io_resume,
  109. };
  110. static struct pci_driver ixgb_driver = {
  111. .name = ixgb_driver_name,
  112. .id_table = ixgb_pci_tbl,
  113. .probe = ixgb_probe,
  114. .remove = __devexit_p(ixgb_remove),
  115. .err_handler = &ixgb_err_handler
  116. };
  117. MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
  118. MODULE_DESCRIPTION("Intel(R) PRO/10GbE Network Driver");
  119. MODULE_LICENSE("GPL");
  120. MODULE_VERSION(DRV_VERSION);
  121. #define DEFAULT_DEBUG_LEVEL_SHIFT 3
  122. static int debug = DEFAULT_DEBUG_LEVEL_SHIFT;
  123. module_param(debug, int, 0);
  124. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  125. /* some defines for controlling descriptor fetches in h/w */
  126. #define RXDCTL_WTHRESH_DEFAULT 15 /* chip writes back at this many or RXT0 */
  127. #define RXDCTL_PTHRESH_DEFAULT 0 /* chip considers prefech below
  128. * this */
  129. #define RXDCTL_HTHRESH_DEFAULT 0 /* chip will only prefetch if tail
  130. * is pushed this many descriptors
  131. * from head */
  132. /**
  133. * ixgb_init_module - Driver Registration Routine
  134. *
  135. * ixgb_init_module is the first routine called when the driver is
  136. * loaded. All it does is register with the PCI subsystem.
  137. **/
  138. static int __init
  139. ixgb_init_module(void)
  140. {
  141. printk(KERN_INFO "%s - version %s\n",
  142. ixgb_driver_string, ixgb_driver_version);
  143. printk(KERN_INFO "%s\n", ixgb_copyright);
  144. return pci_register_driver(&ixgb_driver);
  145. }
  146. module_init(ixgb_init_module);
  147. /**
  148. * ixgb_exit_module - Driver Exit Cleanup Routine
  149. *
  150. * ixgb_exit_module is called just before the driver is removed
  151. * from memory.
  152. **/
  153. static void __exit
  154. ixgb_exit_module(void)
  155. {
  156. pci_unregister_driver(&ixgb_driver);
  157. }
  158. module_exit(ixgb_exit_module);
  159. /**
  160. * ixgb_irq_disable - Mask off interrupt generation on the NIC
  161. * @adapter: board private structure
  162. **/
  163. static void
  164. ixgb_irq_disable(struct ixgb_adapter *adapter)
  165. {
  166. IXGB_WRITE_REG(&adapter->hw, IMC, ~0);
  167. IXGB_WRITE_FLUSH(&adapter->hw);
  168. synchronize_irq(adapter->pdev->irq);
  169. }
  170. /**
  171. * ixgb_irq_enable - Enable default interrupt generation settings
  172. * @adapter: board private structure
  173. **/
  174. static void
  175. ixgb_irq_enable(struct ixgb_adapter *adapter)
  176. {
  177. u32 val = IXGB_INT_RXT0 | IXGB_INT_RXDMT0 |
  178. IXGB_INT_TXDW | IXGB_INT_LSC;
  179. if (adapter->hw.subsystem_vendor_id == SUN_SUBVENDOR_ID)
  180. val |= IXGB_INT_GPI0;
  181. IXGB_WRITE_REG(&adapter->hw, IMS, val);
  182. IXGB_WRITE_FLUSH(&adapter->hw);
  183. }
  184. int
  185. ixgb_up(struct ixgb_adapter *adapter)
  186. {
  187. struct net_device *netdev = adapter->netdev;
  188. int err, irq_flags = IRQF_SHARED;
  189. int max_frame = netdev->mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
  190. struct ixgb_hw *hw = &adapter->hw;
  191. /* hardware has been reset, we need to reload some things */
  192. ixgb_rar_set(hw, netdev->dev_addr, 0);
  193. ixgb_set_multi(netdev);
  194. ixgb_restore_vlan(adapter);
  195. ixgb_configure_tx(adapter);
  196. ixgb_setup_rctl(adapter);
  197. ixgb_configure_rx(adapter);
  198. ixgb_alloc_rx_buffers(adapter);
  199. /* disable interrupts and get the hardware into a known state */
  200. IXGB_WRITE_REG(&adapter->hw, IMC, 0xffffffff);
  201. /* only enable MSI if bus is in PCI-X mode */
  202. if (IXGB_READ_REG(&adapter->hw, STATUS) & IXGB_STATUS_PCIX_MODE) {
  203. err = pci_enable_msi(adapter->pdev);
  204. if (!err) {
  205. adapter->have_msi = 1;
  206. irq_flags = 0;
  207. }
  208. /* proceed to try to request regular interrupt */
  209. }
  210. err = request_irq(adapter->pdev->irq, &ixgb_intr, irq_flags,
  211. netdev->name, netdev);
  212. if (err) {
  213. if (adapter->have_msi)
  214. pci_disable_msi(adapter->pdev);
  215. DPRINTK(PROBE, ERR,
  216. "Unable to allocate interrupt Error: %d\n", err);
  217. return err;
  218. }
  219. if((hw->max_frame_size != max_frame) ||
  220. (hw->max_frame_size !=
  221. (IXGB_READ_REG(hw, MFS) >> IXGB_MFS_SHIFT))) {
  222. hw->max_frame_size = max_frame;
  223. IXGB_WRITE_REG(hw, MFS, hw->max_frame_size << IXGB_MFS_SHIFT);
  224. if(hw->max_frame_size >
  225. IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH) {
  226. u32 ctrl0 = IXGB_READ_REG(hw, CTRL0);
  227. if(!(ctrl0 & IXGB_CTRL0_JFE)) {
  228. ctrl0 |= IXGB_CTRL0_JFE;
  229. IXGB_WRITE_REG(hw, CTRL0, ctrl0);
  230. }
  231. }
  232. }
  233. clear_bit(__IXGB_DOWN, &adapter->flags);
  234. #ifdef CONFIG_IXGB_NAPI
  235. napi_enable(&adapter->napi);
  236. #endif
  237. ixgb_irq_enable(adapter);
  238. mod_timer(&adapter->watchdog_timer, jiffies);
  239. return 0;
  240. }
  241. void
  242. ixgb_down(struct ixgb_adapter *adapter, bool kill_watchdog)
  243. {
  244. struct net_device *netdev = adapter->netdev;
  245. /* prevent the interrupt handler from restarting watchdog */
  246. set_bit(__IXGB_DOWN, &adapter->flags);
  247. #ifdef CONFIG_IXGB_NAPI
  248. napi_disable(&adapter->napi);
  249. #endif
  250. /* waiting for NAPI to complete can re-enable interrupts */
  251. ixgb_irq_disable(adapter);
  252. free_irq(adapter->pdev->irq, netdev);
  253. if (adapter->have_msi)
  254. pci_disable_msi(adapter->pdev);
  255. if(kill_watchdog)
  256. del_timer_sync(&adapter->watchdog_timer);
  257. adapter->link_speed = 0;
  258. adapter->link_duplex = 0;
  259. netif_carrier_off(netdev);
  260. netif_stop_queue(netdev);
  261. ixgb_reset(adapter);
  262. ixgb_clean_tx_ring(adapter);
  263. ixgb_clean_rx_ring(adapter);
  264. }
  265. void
  266. ixgb_reset(struct ixgb_adapter *adapter)
  267. {
  268. struct ixgb_hw *hw = &adapter->hw;
  269. ixgb_adapter_stop(hw);
  270. if (!ixgb_init_hw(hw))
  271. DPRINTK(PROBE, ERR, "ixgb_init_hw failed.\n");
  272. /* restore frame size information */
  273. IXGB_WRITE_REG(hw, MFS, hw->max_frame_size << IXGB_MFS_SHIFT);
  274. if (hw->max_frame_size >
  275. IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH) {
  276. u32 ctrl0 = IXGB_READ_REG(hw, CTRL0);
  277. if (!(ctrl0 & IXGB_CTRL0_JFE)) {
  278. ctrl0 |= IXGB_CTRL0_JFE;
  279. IXGB_WRITE_REG(hw, CTRL0, ctrl0);
  280. }
  281. }
  282. }
  283. /**
  284. * ixgb_probe - Device Initialization Routine
  285. * @pdev: PCI device information struct
  286. * @ent: entry in ixgb_pci_tbl
  287. *
  288. * Returns 0 on success, negative on failure
  289. *
  290. * ixgb_probe initializes an adapter identified by a pci_dev structure.
  291. * The OS initialization, configuring of the adapter private structure,
  292. * and a hardware reset occur.
  293. **/
  294. static int __devinit
  295. ixgb_probe(struct pci_dev *pdev,
  296. const struct pci_device_id *ent)
  297. {
  298. struct net_device *netdev = NULL;
  299. struct ixgb_adapter *adapter;
  300. static int cards_found = 0;
  301. unsigned long mmio_start;
  302. int mmio_len;
  303. int pci_using_dac;
  304. int i;
  305. int err;
  306. if((err = pci_enable_device(pdev)))
  307. return err;
  308. if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
  309. !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
  310. pci_using_dac = 1;
  311. } else {
  312. if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) ||
  313. (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
  314. printk(KERN_ERR
  315. "ixgb: No usable DMA configuration, aborting\n");
  316. goto err_dma_mask;
  317. }
  318. pci_using_dac = 0;
  319. }
  320. if((err = pci_request_regions(pdev, ixgb_driver_name)))
  321. goto err_request_regions;
  322. pci_set_master(pdev);
  323. netdev = alloc_etherdev(sizeof(struct ixgb_adapter));
  324. if(!netdev) {
  325. err = -ENOMEM;
  326. goto err_alloc_etherdev;
  327. }
  328. SET_NETDEV_DEV(netdev, &pdev->dev);
  329. pci_set_drvdata(pdev, netdev);
  330. adapter = netdev_priv(netdev);
  331. adapter->netdev = netdev;
  332. adapter->pdev = pdev;
  333. adapter->hw.back = adapter;
  334. adapter->msg_enable = netif_msg_init(debug, DEFAULT_DEBUG_LEVEL_SHIFT);
  335. mmio_start = pci_resource_start(pdev, BAR_0);
  336. mmio_len = pci_resource_len(pdev, BAR_0);
  337. adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
  338. if(!adapter->hw.hw_addr) {
  339. err = -EIO;
  340. goto err_ioremap;
  341. }
  342. for(i = BAR_1; i <= BAR_5; i++) {
  343. if(pci_resource_len(pdev, i) == 0)
  344. continue;
  345. if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
  346. adapter->hw.io_base = pci_resource_start(pdev, i);
  347. break;
  348. }
  349. }
  350. netdev->open = &ixgb_open;
  351. netdev->stop = &ixgb_close;
  352. netdev->hard_start_xmit = &ixgb_xmit_frame;
  353. netdev->get_stats = &ixgb_get_stats;
  354. netdev->set_multicast_list = &ixgb_set_multi;
  355. netdev->set_mac_address = &ixgb_set_mac;
  356. netdev->change_mtu = &ixgb_change_mtu;
  357. ixgb_set_ethtool_ops(netdev);
  358. netdev->tx_timeout = &ixgb_tx_timeout;
  359. netdev->watchdog_timeo = 5 * HZ;
  360. #ifdef CONFIG_IXGB_NAPI
  361. netif_napi_add(netdev, &adapter->napi, ixgb_clean, 64);
  362. #endif
  363. netdev->vlan_rx_register = ixgb_vlan_rx_register;
  364. netdev->vlan_rx_add_vid = ixgb_vlan_rx_add_vid;
  365. netdev->vlan_rx_kill_vid = ixgb_vlan_rx_kill_vid;
  366. #ifdef CONFIG_NET_POLL_CONTROLLER
  367. netdev->poll_controller = ixgb_netpoll;
  368. #endif
  369. strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
  370. netdev->mem_start = mmio_start;
  371. netdev->mem_end = mmio_start + mmio_len;
  372. netdev->base_addr = adapter->hw.io_base;
  373. adapter->bd_number = cards_found;
  374. adapter->link_speed = 0;
  375. adapter->link_duplex = 0;
  376. /* setup the private structure */
  377. if((err = ixgb_sw_init(adapter)))
  378. goto err_sw_init;
  379. netdev->features = NETIF_F_SG |
  380. NETIF_F_HW_CSUM |
  381. NETIF_F_HW_VLAN_TX |
  382. NETIF_F_HW_VLAN_RX |
  383. NETIF_F_HW_VLAN_FILTER;
  384. netdev->features |= NETIF_F_TSO;
  385. #ifdef NETIF_F_LLTX
  386. netdev->features |= NETIF_F_LLTX;
  387. #endif
  388. if(pci_using_dac)
  389. netdev->features |= NETIF_F_HIGHDMA;
  390. /* make sure the EEPROM is good */
  391. if(!ixgb_validate_eeprom_checksum(&adapter->hw)) {
  392. DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
  393. err = -EIO;
  394. goto err_eeprom;
  395. }
  396. ixgb_get_ee_mac_addr(&adapter->hw, netdev->dev_addr);
  397. memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
  398. if(!is_valid_ether_addr(netdev->perm_addr)) {
  399. DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
  400. err = -EIO;
  401. goto err_eeprom;
  402. }
  403. adapter->part_num = ixgb_get_ee_pba_number(&adapter->hw);
  404. init_timer(&adapter->watchdog_timer);
  405. adapter->watchdog_timer.function = &ixgb_watchdog;
  406. adapter->watchdog_timer.data = (unsigned long)adapter;
  407. INIT_WORK(&adapter->tx_timeout_task, ixgb_tx_timeout_task);
  408. strcpy(netdev->name, "eth%d");
  409. if((err = register_netdev(netdev)))
  410. goto err_register;
  411. /* we're going to reset, so assume we have no link for now */
  412. netif_carrier_off(netdev);
  413. netif_stop_queue(netdev);
  414. DPRINTK(PROBE, INFO, "Intel(R) PRO/10GbE Network Connection\n");
  415. ixgb_check_options(adapter);
  416. /* reset the hardware with the new settings */
  417. ixgb_reset(adapter);
  418. cards_found++;
  419. return 0;
  420. err_register:
  421. err_sw_init:
  422. err_eeprom:
  423. iounmap(adapter->hw.hw_addr);
  424. err_ioremap:
  425. free_netdev(netdev);
  426. err_alloc_etherdev:
  427. pci_release_regions(pdev);
  428. err_request_regions:
  429. err_dma_mask:
  430. pci_disable_device(pdev);
  431. return err;
  432. }
  433. /**
  434. * ixgb_remove - Device Removal Routine
  435. * @pdev: PCI device information struct
  436. *
  437. * ixgb_remove is called by the PCI subsystem to alert the driver
  438. * that it should release a PCI device. The could be caused by a
  439. * Hot-Plug event, or because the driver is going to be removed from
  440. * memory.
  441. **/
  442. static void __devexit
  443. ixgb_remove(struct pci_dev *pdev)
  444. {
  445. struct net_device *netdev = pci_get_drvdata(pdev);
  446. struct ixgb_adapter *adapter = netdev_priv(netdev);
  447. unregister_netdev(netdev);
  448. iounmap(adapter->hw.hw_addr);
  449. pci_release_regions(pdev);
  450. free_netdev(netdev);
  451. }
  452. /**
  453. * ixgb_sw_init - Initialize general software structures (struct ixgb_adapter)
  454. * @adapter: board private structure to initialize
  455. *
  456. * ixgb_sw_init initializes the Adapter private data structure.
  457. * Fields are initialized based on PCI device information and
  458. * OS network device settings (MTU size).
  459. **/
  460. static int __devinit
  461. ixgb_sw_init(struct ixgb_adapter *adapter)
  462. {
  463. struct ixgb_hw *hw = &adapter->hw;
  464. struct net_device *netdev = adapter->netdev;
  465. struct pci_dev *pdev = adapter->pdev;
  466. /* PCI config space info */
  467. hw->vendor_id = pdev->vendor;
  468. hw->device_id = pdev->device;
  469. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  470. hw->subsystem_id = pdev->subsystem_device;
  471. hw->max_frame_size = netdev->mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
  472. adapter->rx_buffer_len = hw->max_frame_size;
  473. if((hw->device_id == IXGB_DEVICE_ID_82597EX)
  474. || (hw->device_id == IXGB_DEVICE_ID_82597EX_CX4)
  475. || (hw->device_id == IXGB_DEVICE_ID_82597EX_LR)
  476. || (hw->device_id == IXGB_DEVICE_ID_82597EX_SR))
  477. hw->mac_type = ixgb_82597;
  478. else {
  479. /* should never have loaded on this device */
  480. DPRINTK(PROBE, ERR, "unsupported device id\n");
  481. }
  482. /* enable flow control to be programmed */
  483. hw->fc.send_xon = 1;
  484. spin_lock_init(&adapter->tx_lock);
  485. set_bit(__IXGB_DOWN, &adapter->flags);
  486. return 0;
  487. }
  488. /**
  489. * ixgb_open - Called when a network interface is made active
  490. * @netdev: network interface device structure
  491. *
  492. * Returns 0 on success, negative value on failure
  493. *
  494. * The open entry point is called when a network interface is made
  495. * active by the system (IFF_UP). At this point all resources needed
  496. * for transmit and receive operations are allocated, the interrupt
  497. * handler is registered with the OS, the watchdog timer is started,
  498. * and the stack is notified that the interface is ready.
  499. **/
  500. static int
  501. ixgb_open(struct net_device *netdev)
  502. {
  503. struct ixgb_adapter *adapter = netdev_priv(netdev);
  504. int err;
  505. /* allocate transmit descriptors */
  506. if((err = ixgb_setup_tx_resources(adapter)))
  507. goto err_setup_tx;
  508. /* allocate receive descriptors */
  509. if((err = ixgb_setup_rx_resources(adapter)))
  510. goto err_setup_rx;
  511. if((err = ixgb_up(adapter)))
  512. goto err_up;
  513. return 0;
  514. err_up:
  515. ixgb_free_rx_resources(adapter);
  516. err_setup_rx:
  517. ixgb_free_tx_resources(adapter);
  518. err_setup_tx:
  519. ixgb_reset(adapter);
  520. return err;
  521. }
  522. /**
  523. * ixgb_close - Disables a network interface
  524. * @netdev: network interface device structure
  525. *
  526. * Returns 0, this is not allowed to fail
  527. *
  528. * The close entry point is called when an interface is de-activated
  529. * by the OS. The hardware is still under the drivers control, but
  530. * needs to be disabled. A global MAC reset is issued to stop the
  531. * hardware, and all transmit and receive resources are freed.
  532. **/
  533. static int
  534. ixgb_close(struct net_device *netdev)
  535. {
  536. struct ixgb_adapter *adapter = netdev_priv(netdev);
  537. ixgb_down(adapter, true);
  538. ixgb_free_tx_resources(adapter);
  539. ixgb_free_rx_resources(adapter);
  540. return 0;
  541. }
  542. /**
  543. * ixgb_setup_tx_resources - allocate Tx resources (Descriptors)
  544. * @adapter: board private structure
  545. *
  546. * Return 0 on success, negative on failure
  547. **/
  548. int
  549. ixgb_setup_tx_resources(struct ixgb_adapter *adapter)
  550. {
  551. struct ixgb_desc_ring *txdr = &adapter->tx_ring;
  552. struct pci_dev *pdev = adapter->pdev;
  553. int size;
  554. size = sizeof(struct ixgb_buffer) * txdr->count;
  555. txdr->buffer_info = vmalloc(size);
  556. if(!txdr->buffer_info) {
  557. DPRINTK(PROBE, ERR,
  558. "Unable to allocate transmit descriptor ring memory\n");
  559. return -ENOMEM;
  560. }
  561. memset(txdr->buffer_info, 0, size);
  562. /* round up to nearest 4K */
  563. txdr->size = txdr->count * sizeof(struct ixgb_tx_desc);
  564. txdr->size = ALIGN(txdr->size, 4096);
  565. txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
  566. if(!txdr->desc) {
  567. vfree(txdr->buffer_info);
  568. DPRINTK(PROBE, ERR,
  569. "Unable to allocate transmit descriptor memory\n");
  570. return -ENOMEM;
  571. }
  572. memset(txdr->desc, 0, txdr->size);
  573. txdr->next_to_use = 0;
  574. txdr->next_to_clean = 0;
  575. return 0;
  576. }
  577. /**
  578. * ixgb_configure_tx - Configure 82597 Transmit Unit after Reset.
  579. * @adapter: board private structure
  580. *
  581. * Configure the Tx unit of the MAC after a reset.
  582. **/
  583. static void
  584. ixgb_configure_tx(struct ixgb_adapter *adapter)
  585. {
  586. u64 tdba = adapter->tx_ring.dma;
  587. u32 tdlen = adapter->tx_ring.count * sizeof(struct ixgb_tx_desc);
  588. u32 tctl;
  589. struct ixgb_hw *hw = &adapter->hw;
  590. /* Setup the Base and Length of the Tx Descriptor Ring
  591. * tx_ring.dma can be either a 32 or 64 bit value
  592. */
  593. IXGB_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
  594. IXGB_WRITE_REG(hw, TDBAH, (tdba >> 32));
  595. IXGB_WRITE_REG(hw, TDLEN, tdlen);
  596. /* Setup the HW Tx Head and Tail descriptor pointers */
  597. IXGB_WRITE_REG(hw, TDH, 0);
  598. IXGB_WRITE_REG(hw, TDT, 0);
  599. /* don't set up txdctl, it induces performance problems if configured
  600. * incorrectly */
  601. /* Set the Tx Interrupt Delay register */
  602. IXGB_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
  603. /* Program the Transmit Control Register */
  604. tctl = IXGB_TCTL_TCE | IXGB_TCTL_TXEN | IXGB_TCTL_TPDE;
  605. IXGB_WRITE_REG(hw, TCTL, tctl);
  606. /* Setup Transmit Descriptor Settings for this adapter */
  607. adapter->tx_cmd_type =
  608. IXGB_TX_DESC_TYPE
  609. | (adapter->tx_int_delay_enable ? IXGB_TX_DESC_CMD_IDE : 0);
  610. }
  611. /**
  612. * ixgb_setup_rx_resources - allocate Rx resources (Descriptors)
  613. * @adapter: board private structure
  614. *
  615. * Returns 0 on success, negative on failure
  616. **/
  617. int
  618. ixgb_setup_rx_resources(struct ixgb_adapter *adapter)
  619. {
  620. struct ixgb_desc_ring *rxdr = &adapter->rx_ring;
  621. struct pci_dev *pdev = adapter->pdev;
  622. int size;
  623. size = sizeof(struct ixgb_buffer) * rxdr->count;
  624. rxdr->buffer_info = vmalloc(size);
  625. if(!rxdr->buffer_info) {
  626. DPRINTK(PROBE, ERR,
  627. "Unable to allocate receive descriptor ring\n");
  628. return -ENOMEM;
  629. }
  630. memset(rxdr->buffer_info, 0, size);
  631. /* Round up to nearest 4K */
  632. rxdr->size = rxdr->count * sizeof(struct ixgb_rx_desc);
  633. rxdr->size = ALIGN(rxdr->size, 4096);
  634. rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
  635. if(!rxdr->desc) {
  636. vfree(rxdr->buffer_info);
  637. DPRINTK(PROBE, ERR,
  638. "Unable to allocate receive descriptors\n");
  639. return -ENOMEM;
  640. }
  641. memset(rxdr->desc, 0, rxdr->size);
  642. rxdr->next_to_clean = 0;
  643. rxdr->next_to_use = 0;
  644. return 0;
  645. }
  646. /**
  647. * ixgb_setup_rctl - configure the receive control register
  648. * @adapter: Board private structure
  649. **/
  650. static void
  651. ixgb_setup_rctl(struct ixgb_adapter *adapter)
  652. {
  653. u32 rctl;
  654. rctl = IXGB_READ_REG(&adapter->hw, RCTL);
  655. rctl &= ~(3 << IXGB_RCTL_MO_SHIFT);
  656. rctl |=
  657. IXGB_RCTL_BAM | IXGB_RCTL_RDMTS_1_2 |
  658. IXGB_RCTL_RXEN | IXGB_RCTL_CFF |
  659. (adapter->hw.mc_filter_type << IXGB_RCTL_MO_SHIFT);
  660. rctl |= IXGB_RCTL_SECRC;
  661. if (adapter->rx_buffer_len <= IXGB_RXBUFFER_2048)
  662. rctl |= IXGB_RCTL_BSIZE_2048;
  663. else if (adapter->rx_buffer_len <= IXGB_RXBUFFER_4096)
  664. rctl |= IXGB_RCTL_BSIZE_4096;
  665. else if (adapter->rx_buffer_len <= IXGB_RXBUFFER_8192)
  666. rctl |= IXGB_RCTL_BSIZE_8192;
  667. else if (adapter->rx_buffer_len <= IXGB_RXBUFFER_16384)
  668. rctl |= IXGB_RCTL_BSIZE_16384;
  669. IXGB_WRITE_REG(&adapter->hw, RCTL, rctl);
  670. }
  671. /**
  672. * ixgb_configure_rx - Configure 82597 Receive Unit after Reset.
  673. * @adapter: board private structure
  674. *
  675. * Configure the Rx unit of the MAC after a reset.
  676. **/
  677. static void
  678. ixgb_configure_rx(struct ixgb_adapter *adapter)
  679. {
  680. u64 rdba = adapter->rx_ring.dma;
  681. u32 rdlen = adapter->rx_ring.count * sizeof(struct ixgb_rx_desc);
  682. struct ixgb_hw *hw = &adapter->hw;
  683. u32 rctl;
  684. u32 rxcsum;
  685. u32 rxdctl;
  686. /* make sure receives are disabled while setting up the descriptors */
  687. rctl = IXGB_READ_REG(hw, RCTL);
  688. IXGB_WRITE_REG(hw, RCTL, rctl & ~IXGB_RCTL_RXEN);
  689. /* set the Receive Delay Timer Register */
  690. IXGB_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
  691. /* Setup the Base and Length of the Rx Descriptor Ring */
  692. IXGB_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
  693. IXGB_WRITE_REG(hw, RDBAH, (rdba >> 32));
  694. IXGB_WRITE_REG(hw, RDLEN, rdlen);
  695. /* Setup the HW Rx Head and Tail Descriptor Pointers */
  696. IXGB_WRITE_REG(hw, RDH, 0);
  697. IXGB_WRITE_REG(hw, RDT, 0);
  698. /* set up pre-fetching of receive buffers so we get some before we
  699. * run out (default hardware behavior is to run out before fetching
  700. * more). This sets up to fetch if HTHRESH rx descriptors are avail
  701. * and the descriptors in hw cache are below PTHRESH. This avoids
  702. * the hardware behavior of fetching <=512 descriptors in a single
  703. * burst that pre-empts all other activity, usually causing fifo
  704. * overflows. */
  705. /* use WTHRESH to burst write 16 descriptors or burst when RXT0 */
  706. rxdctl = RXDCTL_WTHRESH_DEFAULT << IXGB_RXDCTL_WTHRESH_SHIFT |
  707. RXDCTL_HTHRESH_DEFAULT << IXGB_RXDCTL_HTHRESH_SHIFT |
  708. RXDCTL_PTHRESH_DEFAULT << IXGB_RXDCTL_PTHRESH_SHIFT;
  709. IXGB_WRITE_REG(hw, RXDCTL, rxdctl);
  710. /* Enable Receive Checksum Offload for TCP and UDP */
  711. if (adapter->rx_csum) {
  712. rxcsum = IXGB_READ_REG(hw, RXCSUM);
  713. rxcsum |= IXGB_RXCSUM_TUOFL;
  714. IXGB_WRITE_REG(hw, RXCSUM, rxcsum);
  715. }
  716. /* Enable Receives */
  717. IXGB_WRITE_REG(hw, RCTL, rctl);
  718. }
  719. /**
  720. * ixgb_free_tx_resources - Free Tx Resources
  721. * @adapter: board private structure
  722. *
  723. * Free all transmit software resources
  724. **/
  725. void
  726. ixgb_free_tx_resources(struct ixgb_adapter *adapter)
  727. {
  728. struct pci_dev *pdev = adapter->pdev;
  729. ixgb_clean_tx_ring(adapter);
  730. vfree(adapter->tx_ring.buffer_info);
  731. adapter->tx_ring.buffer_info = NULL;
  732. pci_free_consistent(pdev, adapter->tx_ring.size,
  733. adapter->tx_ring.desc, adapter->tx_ring.dma);
  734. adapter->tx_ring.desc = NULL;
  735. }
  736. static void
  737. ixgb_unmap_and_free_tx_resource(struct ixgb_adapter *adapter,
  738. struct ixgb_buffer *buffer_info)
  739. {
  740. struct pci_dev *pdev = adapter->pdev;
  741. if (buffer_info->dma)
  742. pci_unmap_page(pdev, buffer_info->dma, buffer_info->length,
  743. PCI_DMA_TODEVICE);
  744. if (buffer_info->skb)
  745. dev_kfree_skb_any(buffer_info->skb);
  746. buffer_info->skb = NULL;
  747. buffer_info->dma = 0;
  748. buffer_info->time_stamp = 0;
  749. /* these fields must always be initialized in tx
  750. * buffer_info->length = 0;
  751. * buffer_info->next_to_watch = 0; */
  752. }
  753. /**
  754. * ixgb_clean_tx_ring - Free Tx Buffers
  755. * @adapter: board private structure
  756. **/
  757. static void
  758. ixgb_clean_tx_ring(struct ixgb_adapter *adapter)
  759. {
  760. struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
  761. struct ixgb_buffer *buffer_info;
  762. unsigned long size;
  763. unsigned int i;
  764. /* Free all the Tx ring sk_buffs */
  765. for(i = 0; i < tx_ring->count; i++) {
  766. buffer_info = &tx_ring->buffer_info[i];
  767. ixgb_unmap_and_free_tx_resource(adapter, buffer_info);
  768. }
  769. size = sizeof(struct ixgb_buffer) * tx_ring->count;
  770. memset(tx_ring->buffer_info, 0, size);
  771. /* Zero out the descriptor ring */
  772. memset(tx_ring->desc, 0, tx_ring->size);
  773. tx_ring->next_to_use = 0;
  774. tx_ring->next_to_clean = 0;
  775. IXGB_WRITE_REG(&adapter->hw, TDH, 0);
  776. IXGB_WRITE_REG(&adapter->hw, TDT, 0);
  777. }
  778. /**
  779. * ixgb_free_rx_resources - Free Rx Resources
  780. * @adapter: board private structure
  781. *
  782. * Free all receive software resources
  783. **/
  784. void
  785. ixgb_free_rx_resources(struct ixgb_adapter *adapter)
  786. {
  787. struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
  788. struct pci_dev *pdev = adapter->pdev;
  789. ixgb_clean_rx_ring(adapter);
  790. vfree(rx_ring->buffer_info);
  791. rx_ring->buffer_info = NULL;
  792. pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
  793. rx_ring->desc = NULL;
  794. }
  795. /**
  796. * ixgb_clean_rx_ring - Free Rx Buffers
  797. * @adapter: board private structure
  798. **/
  799. static void
  800. ixgb_clean_rx_ring(struct ixgb_adapter *adapter)
  801. {
  802. struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
  803. struct ixgb_buffer *buffer_info;
  804. struct pci_dev *pdev = adapter->pdev;
  805. unsigned long size;
  806. unsigned int i;
  807. /* Free all the Rx ring sk_buffs */
  808. for(i = 0; i < rx_ring->count; i++) {
  809. buffer_info = &rx_ring->buffer_info[i];
  810. if(buffer_info->skb) {
  811. pci_unmap_single(pdev,
  812. buffer_info->dma,
  813. buffer_info->length,
  814. PCI_DMA_FROMDEVICE);
  815. dev_kfree_skb(buffer_info->skb);
  816. buffer_info->skb = NULL;
  817. }
  818. }
  819. size = sizeof(struct ixgb_buffer) * rx_ring->count;
  820. memset(rx_ring->buffer_info, 0, size);
  821. /* Zero out the descriptor ring */
  822. memset(rx_ring->desc, 0, rx_ring->size);
  823. rx_ring->next_to_clean = 0;
  824. rx_ring->next_to_use = 0;
  825. IXGB_WRITE_REG(&adapter->hw, RDH, 0);
  826. IXGB_WRITE_REG(&adapter->hw, RDT, 0);
  827. }
  828. /**
  829. * ixgb_set_mac - Change the Ethernet Address of the NIC
  830. * @netdev: network interface device structure
  831. * @p: pointer to an address structure
  832. *
  833. * Returns 0 on success, negative on failure
  834. **/
  835. static int
  836. ixgb_set_mac(struct net_device *netdev, void *p)
  837. {
  838. struct ixgb_adapter *adapter = netdev_priv(netdev);
  839. struct sockaddr *addr = p;
  840. if(!is_valid_ether_addr(addr->sa_data))
  841. return -EADDRNOTAVAIL;
  842. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  843. ixgb_rar_set(&adapter->hw, addr->sa_data, 0);
  844. return 0;
  845. }
  846. /**
  847. * ixgb_set_multi - Multicast and Promiscuous mode set
  848. * @netdev: network interface device structure
  849. *
  850. * The set_multi entry point is called whenever the multicast address
  851. * list or the network interface flags are updated. This routine is
  852. * responsible for configuring the hardware for proper multicast,
  853. * promiscuous mode, and all-multi behavior.
  854. **/
  855. static void
  856. ixgb_set_multi(struct net_device *netdev)
  857. {
  858. struct ixgb_adapter *adapter = netdev_priv(netdev);
  859. struct ixgb_hw *hw = &adapter->hw;
  860. struct dev_mc_list *mc_ptr;
  861. u32 rctl;
  862. int i;
  863. /* Check for Promiscuous and All Multicast modes */
  864. rctl = IXGB_READ_REG(hw, RCTL);
  865. if(netdev->flags & IFF_PROMISC) {
  866. rctl |= (IXGB_RCTL_UPE | IXGB_RCTL_MPE);
  867. } else if(netdev->flags & IFF_ALLMULTI) {
  868. rctl |= IXGB_RCTL_MPE;
  869. rctl &= ~IXGB_RCTL_UPE;
  870. } else {
  871. rctl &= ~(IXGB_RCTL_UPE | IXGB_RCTL_MPE);
  872. }
  873. if(netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES) {
  874. rctl |= IXGB_RCTL_MPE;
  875. IXGB_WRITE_REG(hw, RCTL, rctl);
  876. } else {
  877. u8 mta[IXGB_MAX_NUM_MULTICAST_ADDRESSES *
  878. IXGB_ETH_LENGTH_OF_ADDRESS];
  879. IXGB_WRITE_REG(hw, RCTL, rctl);
  880. for(i = 0, mc_ptr = netdev->mc_list; mc_ptr;
  881. i++, mc_ptr = mc_ptr->next)
  882. memcpy(&mta[i * IXGB_ETH_LENGTH_OF_ADDRESS],
  883. mc_ptr->dmi_addr, IXGB_ETH_LENGTH_OF_ADDRESS);
  884. ixgb_mc_addr_list_update(hw, mta, netdev->mc_count, 0);
  885. }
  886. }
  887. /**
  888. * ixgb_watchdog - Timer Call-back
  889. * @data: pointer to netdev cast into an unsigned long
  890. **/
  891. static void
  892. ixgb_watchdog(unsigned long data)
  893. {
  894. struct ixgb_adapter *adapter = (struct ixgb_adapter *)data;
  895. struct net_device *netdev = adapter->netdev;
  896. struct ixgb_desc_ring *txdr = &adapter->tx_ring;
  897. ixgb_check_for_link(&adapter->hw);
  898. if (ixgb_check_for_bad_link(&adapter->hw)) {
  899. /* force the reset path */
  900. netif_stop_queue(netdev);
  901. }
  902. if(adapter->hw.link_up) {
  903. if(!netif_carrier_ok(netdev)) {
  904. DPRINTK(LINK, INFO,
  905. "NIC Link is Up 10000 Mbps Full Duplex\n");
  906. adapter->link_speed = 10000;
  907. adapter->link_duplex = FULL_DUPLEX;
  908. netif_carrier_on(netdev);
  909. netif_wake_queue(netdev);
  910. }
  911. } else {
  912. if(netif_carrier_ok(netdev)) {
  913. adapter->link_speed = 0;
  914. adapter->link_duplex = 0;
  915. DPRINTK(LINK, INFO, "NIC Link is Down\n");
  916. netif_carrier_off(netdev);
  917. netif_stop_queue(netdev);
  918. }
  919. }
  920. ixgb_update_stats(adapter);
  921. if(!netif_carrier_ok(netdev)) {
  922. if(IXGB_DESC_UNUSED(txdr) + 1 < txdr->count) {
  923. /* We've lost link, so the controller stops DMA,
  924. * but we've got queued Tx work that's never going
  925. * to get done, so reset controller to flush Tx.
  926. * (Do the reset outside of interrupt context). */
  927. schedule_work(&adapter->tx_timeout_task);
  928. }
  929. }
  930. /* Force detection of hung controller every watchdog period */
  931. adapter->detect_tx_hung = true;
  932. /* generate an interrupt to force clean up of any stragglers */
  933. IXGB_WRITE_REG(&adapter->hw, ICS, IXGB_INT_TXDW);
  934. /* Reset the timer */
  935. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  936. }
  937. #define IXGB_TX_FLAGS_CSUM 0x00000001
  938. #define IXGB_TX_FLAGS_VLAN 0x00000002
  939. #define IXGB_TX_FLAGS_TSO 0x00000004
  940. static int
  941. ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
  942. {
  943. struct ixgb_context_desc *context_desc;
  944. unsigned int i;
  945. u8 ipcss, ipcso, tucss, tucso, hdr_len;
  946. u16 ipcse, tucse, mss;
  947. int err;
  948. if (likely(skb_is_gso(skb))) {
  949. struct ixgb_buffer *buffer_info;
  950. struct iphdr *iph;
  951. if (skb_header_cloned(skb)) {
  952. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  953. if (err)
  954. return err;
  955. }
  956. hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  957. mss = skb_shinfo(skb)->gso_size;
  958. iph = ip_hdr(skb);
  959. iph->tot_len = 0;
  960. iph->check = 0;
  961. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  962. iph->daddr, 0,
  963. IPPROTO_TCP, 0);
  964. ipcss = skb_network_offset(skb);
  965. ipcso = (void *)&(iph->check) - (void *)skb->data;
  966. ipcse = skb_transport_offset(skb) - 1;
  967. tucss = skb_transport_offset(skb);
  968. tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
  969. tucse = 0;
  970. i = adapter->tx_ring.next_to_use;
  971. context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i);
  972. buffer_info = &adapter->tx_ring.buffer_info[i];
  973. WARN_ON(buffer_info->dma != 0);
  974. context_desc->ipcss = ipcss;
  975. context_desc->ipcso = ipcso;
  976. context_desc->ipcse = cpu_to_le16(ipcse);
  977. context_desc->tucss = tucss;
  978. context_desc->tucso = tucso;
  979. context_desc->tucse = cpu_to_le16(tucse);
  980. context_desc->mss = cpu_to_le16(mss);
  981. context_desc->hdr_len = hdr_len;
  982. context_desc->status = 0;
  983. context_desc->cmd_type_len = cpu_to_le32(
  984. IXGB_CONTEXT_DESC_TYPE
  985. | IXGB_CONTEXT_DESC_CMD_TSE
  986. | IXGB_CONTEXT_DESC_CMD_IP
  987. | IXGB_CONTEXT_DESC_CMD_TCP
  988. | IXGB_CONTEXT_DESC_CMD_IDE
  989. | (skb->len - (hdr_len)));
  990. if(++i == adapter->tx_ring.count) i = 0;
  991. adapter->tx_ring.next_to_use = i;
  992. return 1;
  993. }
  994. return 0;
  995. }
  996. static bool
  997. ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
  998. {
  999. struct ixgb_context_desc *context_desc;
  1000. unsigned int i;
  1001. u8 css, cso;
  1002. if(likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1003. struct ixgb_buffer *buffer_info;
  1004. css = skb_transport_offset(skb);
  1005. cso = css + skb->csum_offset;
  1006. i = adapter->tx_ring.next_to_use;
  1007. context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i);
  1008. buffer_info = &adapter->tx_ring.buffer_info[i];
  1009. WARN_ON(buffer_info->dma != 0);
  1010. context_desc->tucss = css;
  1011. context_desc->tucso = cso;
  1012. context_desc->tucse = 0;
  1013. /* zero out any previously existing data in one instruction */
  1014. *(u32 *)&(context_desc->ipcss) = 0;
  1015. context_desc->status = 0;
  1016. context_desc->hdr_len = 0;
  1017. context_desc->mss = 0;
  1018. context_desc->cmd_type_len =
  1019. cpu_to_le32(IXGB_CONTEXT_DESC_TYPE
  1020. | IXGB_TX_DESC_CMD_IDE);
  1021. if(++i == adapter->tx_ring.count) i = 0;
  1022. adapter->tx_ring.next_to_use = i;
  1023. return true;
  1024. }
  1025. return false;
  1026. }
  1027. #define IXGB_MAX_TXD_PWR 14
  1028. #define IXGB_MAX_DATA_PER_TXD (1<<IXGB_MAX_TXD_PWR)
  1029. static int
  1030. ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb,
  1031. unsigned int first)
  1032. {
  1033. struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
  1034. struct ixgb_buffer *buffer_info;
  1035. int len = skb->len;
  1036. unsigned int offset = 0, size, count = 0, i;
  1037. unsigned int mss = skb_shinfo(skb)->gso_size;
  1038. unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
  1039. unsigned int f;
  1040. len -= skb->data_len;
  1041. i = tx_ring->next_to_use;
  1042. while(len) {
  1043. buffer_info = &tx_ring->buffer_info[i];
  1044. size = min(len, IXGB_MAX_DATA_PER_TXD);
  1045. /* Workaround for premature desc write-backs
  1046. * in TSO mode. Append 4-byte sentinel desc */
  1047. if (unlikely(mss && !nr_frags && size == len && size > 8))
  1048. size -= 4;
  1049. buffer_info->length = size;
  1050. WARN_ON(buffer_info->dma != 0);
  1051. buffer_info->dma =
  1052. pci_map_single(adapter->pdev,
  1053. skb->data + offset,
  1054. size,
  1055. PCI_DMA_TODEVICE);
  1056. buffer_info->time_stamp = jiffies;
  1057. buffer_info->next_to_watch = 0;
  1058. len -= size;
  1059. offset += size;
  1060. count++;
  1061. if(++i == tx_ring->count) i = 0;
  1062. }
  1063. for(f = 0; f < nr_frags; f++) {
  1064. struct skb_frag_struct *frag;
  1065. frag = &skb_shinfo(skb)->frags[f];
  1066. len = frag->size;
  1067. offset = 0;
  1068. while(len) {
  1069. buffer_info = &tx_ring->buffer_info[i];
  1070. size = min(len, IXGB_MAX_DATA_PER_TXD);
  1071. /* Workaround for premature desc write-backs
  1072. * in TSO mode. Append 4-byte sentinel desc */
  1073. if (unlikely(mss && (f == (nr_frags - 1))
  1074. && size == len && size > 8))
  1075. size -= 4;
  1076. buffer_info->length = size;
  1077. buffer_info->dma =
  1078. pci_map_page(adapter->pdev,
  1079. frag->page,
  1080. frag->page_offset + offset,
  1081. size,
  1082. PCI_DMA_TODEVICE);
  1083. buffer_info->time_stamp = jiffies;
  1084. buffer_info->next_to_watch = 0;
  1085. len -= size;
  1086. offset += size;
  1087. count++;
  1088. if(++i == tx_ring->count) i = 0;
  1089. }
  1090. }
  1091. i = (i == 0) ? tx_ring->count - 1 : i - 1;
  1092. tx_ring->buffer_info[i].skb = skb;
  1093. tx_ring->buffer_info[first].next_to_watch = i;
  1094. return count;
  1095. }
  1096. static void
  1097. ixgb_tx_queue(struct ixgb_adapter *adapter, int count, int vlan_id,int tx_flags)
  1098. {
  1099. struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
  1100. struct ixgb_tx_desc *tx_desc = NULL;
  1101. struct ixgb_buffer *buffer_info;
  1102. u32 cmd_type_len = adapter->tx_cmd_type;
  1103. u8 status = 0;
  1104. u8 popts = 0;
  1105. unsigned int i;
  1106. if(tx_flags & IXGB_TX_FLAGS_TSO) {
  1107. cmd_type_len |= IXGB_TX_DESC_CMD_TSE;
  1108. popts |= (IXGB_TX_DESC_POPTS_IXSM | IXGB_TX_DESC_POPTS_TXSM);
  1109. }
  1110. if(tx_flags & IXGB_TX_FLAGS_CSUM)
  1111. popts |= IXGB_TX_DESC_POPTS_TXSM;
  1112. if(tx_flags & IXGB_TX_FLAGS_VLAN) {
  1113. cmd_type_len |= IXGB_TX_DESC_CMD_VLE;
  1114. }
  1115. i = tx_ring->next_to_use;
  1116. while(count--) {
  1117. buffer_info = &tx_ring->buffer_info[i];
  1118. tx_desc = IXGB_TX_DESC(*tx_ring, i);
  1119. tx_desc->buff_addr = cpu_to_le64(buffer_info->dma);
  1120. tx_desc->cmd_type_len =
  1121. cpu_to_le32(cmd_type_len | buffer_info->length);
  1122. tx_desc->status = status;
  1123. tx_desc->popts = popts;
  1124. tx_desc->vlan = cpu_to_le16(vlan_id);
  1125. if(++i == tx_ring->count) i = 0;
  1126. }
  1127. tx_desc->cmd_type_len |= cpu_to_le32(IXGB_TX_DESC_CMD_EOP
  1128. | IXGB_TX_DESC_CMD_RS );
  1129. /* Force memory writes to complete before letting h/w
  1130. * know there are new descriptors to fetch. (Only
  1131. * applicable for weak-ordered memory model archs,
  1132. * such as IA-64). */
  1133. wmb();
  1134. tx_ring->next_to_use = i;
  1135. IXGB_WRITE_REG(&adapter->hw, TDT, i);
  1136. }
  1137. static int __ixgb_maybe_stop_tx(struct net_device *netdev, int size)
  1138. {
  1139. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1140. struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
  1141. netif_stop_queue(netdev);
  1142. /* Herbert's original patch had:
  1143. * smp_mb__after_netif_stop_queue();
  1144. * but since that doesn't exist yet, just open code it. */
  1145. smp_mb();
  1146. /* We need to check again in a case another CPU has just
  1147. * made room available. */
  1148. if (likely(IXGB_DESC_UNUSED(tx_ring) < size))
  1149. return -EBUSY;
  1150. /* A reprieve! */
  1151. netif_start_queue(netdev);
  1152. ++adapter->restart_queue;
  1153. return 0;
  1154. }
  1155. static int ixgb_maybe_stop_tx(struct net_device *netdev,
  1156. struct ixgb_desc_ring *tx_ring, int size)
  1157. {
  1158. if (likely(IXGB_DESC_UNUSED(tx_ring) >= size))
  1159. return 0;
  1160. return __ixgb_maybe_stop_tx(netdev, size);
  1161. }
  1162. /* Tx Descriptors needed, worst case */
  1163. #define TXD_USE_COUNT(S) (((S) >> IXGB_MAX_TXD_PWR) + \
  1164. (((S) & (IXGB_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
  1165. #define DESC_NEEDED TXD_USE_COUNT(IXGB_MAX_DATA_PER_TXD) /* skb->date */ + \
  1166. MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1 /* for context */ \
  1167. + 1 /* one more needed for sentinel TSO workaround */
  1168. static int
  1169. ixgb_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  1170. {
  1171. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1172. unsigned int first;
  1173. unsigned int tx_flags = 0;
  1174. unsigned long flags;
  1175. int vlan_id = 0;
  1176. int tso;
  1177. if (test_bit(__IXGB_DOWN, &adapter->flags)) {
  1178. dev_kfree_skb(skb);
  1179. return NETDEV_TX_OK;
  1180. }
  1181. if(skb->len <= 0) {
  1182. dev_kfree_skb_any(skb);
  1183. return 0;
  1184. }
  1185. #ifdef NETIF_F_LLTX
  1186. if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
  1187. /* Collision - tell upper layer to requeue */
  1188. local_irq_restore(flags);
  1189. return NETDEV_TX_LOCKED;
  1190. }
  1191. #else
  1192. spin_lock_irqsave(&adapter->tx_lock, flags);
  1193. #endif
  1194. if (unlikely(ixgb_maybe_stop_tx(netdev, &adapter->tx_ring,
  1195. DESC_NEEDED))) {
  1196. netif_stop_queue(netdev);
  1197. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1198. return NETDEV_TX_BUSY;
  1199. }
  1200. #ifndef NETIF_F_LLTX
  1201. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1202. #endif
  1203. if(adapter->vlgrp && vlan_tx_tag_present(skb)) {
  1204. tx_flags |= IXGB_TX_FLAGS_VLAN;
  1205. vlan_id = vlan_tx_tag_get(skb);
  1206. }
  1207. first = adapter->tx_ring.next_to_use;
  1208. tso = ixgb_tso(adapter, skb);
  1209. if (tso < 0) {
  1210. dev_kfree_skb_any(skb);
  1211. #ifdef NETIF_F_LLTX
  1212. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1213. #endif
  1214. return NETDEV_TX_OK;
  1215. }
  1216. if (likely(tso))
  1217. tx_flags |= IXGB_TX_FLAGS_TSO;
  1218. else if(ixgb_tx_csum(adapter, skb))
  1219. tx_flags |= IXGB_TX_FLAGS_CSUM;
  1220. ixgb_tx_queue(adapter, ixgb_tx_map(adapter, skb, first), vlan_id,
  1221. tx_flags);
  1222. netdev->trans_start = jiffies;
  1223. #ifdef NETIF_F_LLTX
  1224. /* Make sure there is space in the ring for the next send. */
  1225. ixgb_maybe_stop_tx(netdev, &adapter->tx_ring, DESC_NEEDED);
  1226. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1227. #endif
  1228. return NETDEV_TX_OK;
  1229. }
  1230. /**
  1231. * ixgb_tx_timeout - Respond to a Tx Hang
  1232. * @netdev: network interface device structure
  1233. **/
  1234. static void
  1235. ixgb_tx_timeout(struct net_device *netdev)
  1236. {
  1237. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1238. /* Do the reset outside of interrupt context */
  1239. schedule_work(&adapter->tx_timeout_task);
  1240. }
  1241. static void
  1242. ixgb_tx_timeout_task(struct work_struct *work)
  1243. {
  1244. struct ixgb_adapter *adapter =
  1245. container_of(work, struct ixgb_adapter, tx_timeout_task);
  1246. adapter->tx_timeout_count++;
  1247. ixgb_down(adapter, true);
  1248. ixgb_up(adapter);
  1249. }
  1250. /**
  1251. * ixgb_get_stats - Get System Network Statistics
  1252. * @netdev: network interface device structure
  1253. *
  1254. * Returns the address of the device statistics structure.
  1255. * The statistics are actually updated from the timer callback.
  1256. **/
  1257. static struct net_device_stats *
  1258. ixgb_get_stats(struct net_device *netdev)
  1259. {
  1260. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1261. return &adapter->net_stats;
  1262. }
  1263. /**
  1264. * ixgb_change_mtu - Change the Maximum Transfer Unit
  1265. * @netdev: network interface device structure
  1266. * @new_mtu: new value for maximum frame size
  1267. *
  1268. * Returns 0 on success, negative on failure
  1269. **/
  1270. static int
  1271. ixgb_change_mtu(struct net_device *netdev, int new_mtu)
  1272. {
  1273. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1274. int max_frame = new_mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
  1275. int old_max_frame = netdev->mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
  1276. if((max_frame < IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH)
  1277. || (max_frame > IXGB_MAX_JUMBO_FRAME_SIZE + ENET_FCS_LENGTH)) {
  1278. DPRINTK(PROBE, ERR, "Invalid MTU setting %d\n", new_mtu);
  1279. return -EINVAL;
  1280. }
  1281. adapter->rx_buffer_len = max_frame;
  1282. netdev->mtu = new_mtu;
  1283. if ((old_max_frame != max_frame) && netif_running(netdev)) {
  1284. ixgb_down(adapter, true);
  1285. ixgb_up(adapter);
  1286. }
  1287. return 0;
  1288. }
  1289. /**
  1290. * ixgb_update_stats - Update the board statistics counters.
  1291. * @adapter: board private structure
  1292. **/
  1293. void
  1294. ixgb_update_stats(struct ixgb_adapter *adapter)
  1295. {
  1296. struct net_device *netdev = adapter->netdev;
  1297. struct pci_dev *pdev = adapter->pdev;
  1298. /* Prevent stats update while adapter is being reset */
  1299. if (pci_channel_offline(pdev))
  1300. return;
  1301. if((netdev->flags & IFF_PROMISC) || (netdev->flags & IFF_ALLMULTI) ||
  1302. (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES)) {
  1303. u64 multi = IXGB_READ_REG(&adapter->hw, MPRCL);
  1304. u32 bcast_l = IXGB_READ_REG(&adapter->hw, BPRCL);
  1305. u32 bcast_h = IXGB_READ_REG(&adapter->hw, BPRCH);
  1306. u64 bcast = ((u64)bcast_h << 32) | bcast_l;
  1307. multi |= ((u64)IXGB_READ_REG(&adapter->hw, MPRCH) << 32);
  1308. /* fix up multicast stats by removing broadcasts */
  1309. if(multi >= bcast)
  1310. multi -= bcast;
  1311. adapter->stats.mprcl += (multi & 0xFFFFFFFF);
  1312. adapter->stats.mprch += (multi >> 32);
  1313. adapter->stats.bprcl += bcast_l;
  1314. adapter->stats.bprch += bcast_h;
  1315. } else {
  1316. adapter->stats.mprcl += IXGB_READ_REG(&adapter->hw, MPRCL);
  1317. adapter->stats.mprch += IXGB_READ_REG(&adapter->hw, MPRCH);
  1318. adapter->stats.bprcl += IXGB_READ_REG(&adapter->hw, BPRCL);
  1319. adapter->stats.bprch += IXGB_READ_REG(&adapter->hw, BPRCH);
  1320. }
  1321. adapter->stats.tprl += IXGB_READ_REG(&adapter->hw, TPRL);
  1322. adapter->stats.tprh += IXGB_READ_REG(&adapter->hw, TPRH);
  1323. adapter->stats.gprcl += IXGB_READ_REG(&adapter->hw, GPRCL);
  1324. adapter->stats.gprch += IXGB_READ_REG(&adapter->hw, GPRCH);
  1325. adapter->stats.uprcl += IXGB_READ_REG(&adapter->hw, UPRCL);
  1326. adapter->stats.uprch += IXGB_READ_REG(&adapter->hw, UPRCH);
  1327. adapter->stats.vprcl += IXGB_READ_REG(&adapter->hw, VPRCL);
  1328. adapter->stats.vprch += IXGB_READ_REG(&adapter->hw, VPRCH);
  1329. adapter->stats.jprcl += IXGB_READ_REG(&adapter->hw, JPRCL);
  1330. adapter->stats.jprch += IXGB_READ_REG(&adapter->hw, JPRCH);
  1331. adapter->stats.gorcl += IXGB_READ_REG(&adapter->hw, GORCL);
  1332. adapter->stats.gorch += IXGB_READ_REG(&adapter->hw, GORCH);
  1333. adapter->stats.torl += IXGB_READ_REG(&adapter->hw, TORL);
  1334. adapter->stats.torh += IXGB_READ_REG(&adapter->hw, TORH);
  1335. adapter->stats.rnbc += IXGB_READ_REG(&adapter->hw, RNBC);
  1336. adapter->stats.ruc += IXGB_READ_REG(&adapter->hw, RUC);
  1337. adapter->stats.roc += IXGB_READ_REG(&adapter->hw, ROC);
  1338. adapter->stats.rlec += IXGB_READ_REG(&adapter->hw, RLEC);
  1339. adapter->stats.crcerrs += IXGB_READ_REG(&adapter->hw, CRCERRS);
  1340. adapter->stats.icbc += IXGB_READ_REG(&adapter->hw, ICBC);
  1341. adapter->stats.ecbc += IXGB_READ_REG(&adapter->hw, ECBC);
  1342. adapter->stats.mpc += IXGB_READ_REG(&adapter->hw, MPC);
  1343. adapter->stats.tptl += IXGB_READ_REG(&adapter->hw, TPTL);
  1344. adapter->stats.tpth += IXGB_READ_REG(&adapter->hw, TPTH);
  1345. adapter->stats.gptcl += IXGB_READ_REG(&adapter->hw, GPTCL);
  1346. adapter->stats.gptch += IXGB_READ_REG(&adapter->hw, GPTCH);
  1347. adapter->stats.bptcl += IXGB_READ_REG(&adapter->hw, BPTCL);
  1348. adapter->stats.bptch += IXGB_READ_REG(&adapter->hw, BPTCH);
  1349. adapter->stats.mptcl += IXGB_READ_REG(&adapter->hw, MPTCL);
  1350. adapter->stats.mptch += IXGB_READ_REG(&adapter->hw, MPTCH);
  1351. adapter->stats.uptcl += IXGB_READ_REG(&adapter->hw, UPTCL);
  1352. adapter->stats.uptch += IXGB_READ_REG(&adapter->hw, UPTCH);
  1353. adapter->stats.vptcl += IXGB_READ_REG(&adapter->hw, VPTCL);
  1354. adapter->stats.vptch += IXGB_READ_REG(&adapter->hw, VPTCH);
  1355. adapter->stats.jptcl += IXGB_READ_REG(&adapter->hw, JPTCL);
  1356. adapter->stats.jptch += IXGB_READ_REG(&adapter->hw, JPTCH);
  1357. adapter->stats.gotcl += IXGB_READ_REG(&adapter->hw, GOTCL);
  1358. adapter->stats.gotch += IXGB_READ_REG(&adapter->hw, GOTCH);
  1359. adapter->stats.totl += IXGB_READ_REG(&adapter->hw, TOTL);
  1360. adapter->stats.toth += IXGB_READ_REG(&adapter->hw, TOTH);
  1361. adapter->stats.dc += IXGB_READ_REG(&adapter->hw, DC);
  1362. adapter->stats.plt64c += IXGB_READ_REG(&adapter->hw, PLT64C);
  1363. adapter->stats.tsctc += IXGB_READ_REG(&adapter->hw, TSCTC);
  1364. adapter->stats.tsctfc += IXGB_READ_REG(&adapter->hw, TSCTFC);
  1365. adapter->stats.ibic += IXGB_READ_REG(&adapter->hw, IBIC);
  1366. adapter->stats.rfc += IXGB_READ_REG(&adapter->hw, RFC);
  1367. adapter->stats.lfc += IXGB_READ_REG(&adapter->hw, LFC);
  1368. adapter->stats.pfrc += IXGB_READ_REG(&adapter->hw, PFRC);
  1369. adapter->stats.pftc += IXGB_READ_REG(&adapter->hw, PFTC);
  1370. adapter->stats.mcfrc += IXGB_READ_REG(&adapter->hw, MCFRC);
  1371. adapter->stats.mcftc += IXGB_READ_REG(&adapter->hw, MCFTC);
  1372. adapter->stats.xonrxc += IXGB_READ_REG(&adapter->hw, XONRXC);
  1373. adapter->stats.xontxc += IXGB_READ_REG(&adapter->hw, XONTXC);
  1374. adapter->stats.xoffrxc += IXGB_READ_REG(&adapter->hw, XOFFRXC);
  1375. adapter->stats.xofftxc += IXGB_READ_REG(&adapter->hw, XOFFTXC);
  1376. adapter->stats.rjc += IXGB_READ_REG(&adapter->hw, RJC);
  1377. /* Fill out the OS statistics structure */
  1378. adapter->net_stats.rx_packets = adapter->stats.gprcl;
  1379. adapter->net_stats.tx_packets = adapter->stats.gptcl;
  1380. adapter->net_stats.rx_bytes = adapter->stats.gorcl;
  1381. adapter->net_stats.tx_bytes = adapter->stats.gotcl;
  1382. adapter->net_stats.multicast = adapter->stats.mprcl;
  1383. adapter->net_stats.collisions = 0;
  1384. /* ignore RLEC as it reports errors for padded (<64bytes) frames
  1385. * with a length in the type/len field */
  1386. adapter->net_stats.rx_errors =
  1387. /* adapter->stats.rnbc + */ adapter->stats.crcerrs +
  1388. adapter->stats.ruc +
  1389. adapter->stats.roc /*+ adapter->stats.rlec */ +
  1390. adapter->stats.icbc +
  1391. adapter->stats.ecbc + adapter->stats.mpc;
  1392. /* see above
  1393. * adapter->net_stats.rx_length_errors = adapter->stats.rlec;
  1394. */
  1395. adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
  1396. adapter->net_stats.rx_fifo_errors = adapter->stats.mpc;
  1397. adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
  1398. adapter->net_stats.rx_over_errors = adapter->stats.mpc;
  1399. adapter->net_stats.tx_errors = 0;
  1400. adapter->net_stats.rx_frame_errors = 0;
  1401. adapter->net_stats.tx_aborted_errors = 0;
  1402. adapter->net_stats.tx_carrier_errors = 0;
  1403. adapter->net_stats.tx_fifo_errors = 0;
  1404. adapter->net_stats.tx_heartbeat_errors = 0;
  1405. adapter->net_stats.tx_window_errors = 0;
  1406. }
  1407. #define IXGB_MAX_INTR 10
  1408. /**
  1409. * ixgb_intr - Interrupt Handler
  1410. * @irq: interrupt number
  1411. * @data: pointer to a network interface device structure
  1412. **/
  1413. static irqreturn_t
  1414. ixgb_intr(int irq, void *data)
  1415. {
  1416. struct net_device *netdev = data;
  1417. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1418. struct ixgb_hw *hw = &adapter->hw;
  1419. u32 icr = IXGB_READ_REG(hw, ICR);
  1420. #ifndef CONFIG_IXGB_NAPI
  1421. unsigned int i;
  1422. #endif
  1423. if(unlikely(!icr))
  1424. return IRQ_NONE; /* Not our interrupt */
  1425. if (unlikely(icr & (IXGB_INT_RXSEQ | IXGB_INT_LSC)))
  1426. if (!test_bit(__IXGB_DOWN, &adapter->flags))
  1427. mod_timer(&adapter->watchdog_timer, jiffies);
  1428. #ifdef CONFIG_IXGB_NAPI
  1429. if (netif_rx_schedule_prep(netdev, &adapter->napi)) {
  1430. /* Disable interrupts and register for poll. The flush
  1431. of the posted write is intentionally left out.
  1432. */
  1433. IXGB_WRITE_REG(&adapter->hw, IMC, ~0);
  1434. __netif_rx_schedule(netdev, &adapter->napi);
  1435. }
  1436. #else
  1437. /* yes, that is actually a & and it is meant to make sure that
  1438. * every pass through this for loop checks both receive and
  1439. * transmit queues for completed descriptors, intended to
  1440. * avoid starvation issues and assist tx/rx fairness. */
  1441. for(i = 0; i < IXGB_MAX_INTR; i++)
  1442. if(!ixgb_clean_rx_irq(adapter) &
  1443. !ixgb_clean_tx_irq(adapter))
  1444. break;
  1445. #endif
  1446. return IRQ_HANDLED;
  1447. }
  1448. #ifdef CONFIG_IXGB_NAPI
  1449. /**
  1450. * ixgb_clean - NAPI Rx polling callback
  1451. * @adapter: board private structure
  1452. **/
  1453. static int
  1454. ixgb_clean(struct napi_struct *napi, int budget)
  1455. {
  1456. struct ixgb_adapter *adapter = container_of(napi, struct ixgb_adapter, napi);
  1457. struct net_device *netdev = adapter->netdev;
  1458. int work_done = 0;
  1459. ixgb_clean_tx_irq(adapter);
  1460. ixgb_clean_rx_irq(adapter, &work_done, budget);
  1461. /* If budget not fully consumed, exit the polling mode */
  1462. if (work_done < budget) {
  1463. netif_rx_complete(netdev, napi);
  1464. ixgb_irq_enable(adapter);
  1465. }
  1466. return work_done;
  1467. }
  1468. #endif
  1469. /**
  1470. * ixgb_clean_tx_irq - Reclaim resources after transmit completes
  1471. * @adapter: board private structure
  1472. **/
  1473. static bool
  1474. ixgb_clean_tx_irq(struct ixgb_adapter *adapter)
  1475. {
  1476. struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
  1477. struct net_device *netdev = adapter->netdev;
  1478. struct ixgb_tx_desc *tx_desc, *eop_desc;
  1479. struct ixgb_buffer *buffer_info;
  1480. unsigned int i, eop;
  1481. bool cleaned = false;
  1482. i = tx_ring->next_to_clean;
  1483. eop = tx_ring->buffer_info[i].next_to_watch;
  1484. eop_desc = IXGB_TX_DESC(*tx_ring, eop);
  1485. while(eop_desc->status & IXGB_TX_DESC_STATUS_DD) {
  1486. for (cleaned = false; !cleaned; ) {
  1487. tx_desc = IXGB_TX_DESC(*tx_ring, i);
  1488. buffer_info = &tx_ring->buffer_info[i];
  1489. if (tx_desc->popts
  1490. & (IXGB_TX_DESC_POPTS_TXSM |
  1491. IXGB_TX_DESC_POPTS_IXSM))
  1492. adapter->hw_csum_tx_good++;
  1493. ixgb_unmap_and_free_tx_resource(adapter, buffer_info);
  1494. *(u32 *)&(tx_desc->status) = 0;
  1495. cleaned = (i == eop);
  1496. if(++i == tx_ring->count) i = 0;
  1497. }
  1498. eop = tx_ring->buffer_info[i].next_to_watch;
  1499. eop_desc = IXGB_TX_DESC(*tx_ring, eop);
  1500. }
  1501. tx_ring->next_to_clean = i;
  1502. if (unlikely(netif_queue_stopped(netdev))) {
  1503. spin_lock(&adapter->tx_lock);
  1504. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev) &&
  1505. (IXGB_DESC_UNUSED(tx_ring) >= DESC_NEEDED))
  1506. netif_wake_queue(netdev);
  1507. spin_unlock(&adapter->tx_lock);
  1508. }
  1509. if(adapter->detect_tx_hung) {
  1510. /* detect a transmit hang in hardware, this serializes the
  1511. * check with the clearing of time_stamp and movement of i */
  1512. adapter->detect_tx_hung = false;
  1513. if (tx_ring->buffer_info[eop].dma &&
  1514. time_after(jiffies, tx_ring->buffer_info[eop].time_stamp + HZ)
  1515. && !(IXGB_READ_REG(&adapter->hw, STATUS) &
  1516. IXGB_STATUS_TXOFF)) {
  1517. /* detected Tx unit hang */
  1518. DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
  1519. " TDH <%x>\n"
  1520. " TDT <%x>\n"
  1521. " next_to_use <%x>\n"
  1522. " next_to_clean <%x>\n"
  1523. "buffer_info[next_to_clean]\n"
  1524. " time_stamp <%lx>\n"
  1525. " next_to_watch <%x>\n"
  1526. " jiffies <%lx>\n"
  1527. " next_to_watch.status <%x>\n",
  1528. IXGB_READ_REG(&adapter->hw, TDH),
  1529. IXGB_READ_REG(&adapter->hw, TDT),
  1530. tx_ring->next_to_use,
  1531. tx_ring->next_to_clean,
  1532. tx_ring->buffer_info[eop].time_stamp,
  1533. eop,
  1534. jiffies,
  1535. eop_desc->status);
  1536. netif_stop_queue(netdev);
  1537. }
  1538. }
  1539. return cleaned;
  1540. }
  1541. /**
  1542. * ixgb_rx_checksum - Receive Checksum Offload for 82597.
  1543. * @adapter: board private structure
  1544. * @rx_desc: receive descriptor
  1545. * @sk_buff: socket buffer with received data
  1546. **/
  1547. static void
  1548. ixgb_rx_checksum(struct ixgb_adapter *adapter,
  1549. struct ixgb_rx_desc *rx_desc,
  1550. struct sk_buff *skb)
  1551. {
  1552. /* Ignore Checksum bit is set OR
  1553. * TCP Checksum has not been calculated
  1554. */
  1555. if((rx_desc->status & IXGB_RX_DESC_STATUS_IXSM) ||
  1556. (!(rx_desc->status & IXGB_RX_DESC_STATUS_TCPCS))) {
  1557. skb->ip_summed = CHECKSUM_NONE;
  1558. return;
  1559. }
  1560. /* At this point we know the hardware did the TCP checksum */
  1561. /* now look at the TCP checksum error bit */
  1562. if(rx_desc->errors & IXGB_RX_DESC_ERRORS_TCPE) {
  1563. /* let the stack verify checksum errors */
  1564. skb->ip_summed = CHECKSUM_NONE;
  1565. adapter->hw_csum_rx_error++;
  1566. } else {
  1567. /* TCP checksum is good */
  1568. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1569. adapter->hw_csum_rx_good++;
  1570. }
  1571. }
  1572. /**
  1573. * ixgb_clean_rx_irq - Send received data up the network stack,
  1574. * @adapter: board private structure
  1575. **/
  1576. static bool
  1577. #ifdef CONFIG_IXGB_NAPI
  1578. ixgb_clean_rx_irq(struct ixgb_adapter *adapter, int *work_done, int work_to_do)
  1579. #else
  1580. ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
  1581. #endif
  1582. {
  1583. struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
  1584. struct net_device *netdev = adapter->netdev;
  1585. struct pci_dev *pdev = adapter->pdev;
  1586. struct ixgb_rx_desc *rx_desc, *next_rxd;
  1587. struct ixgb_buffer *buffer_info, *next_buffer, *next2_buffer;
  1588. u32 length;
  1589. unsigned int i, j;
  1590. bool cleaned = false;
  1591. i = rx_ring->next_to_clean;
  1592. rx_desc = IXGB_RX_DESC(*rx_ring, i);
  1593. buffer_info = &rx_ring->buffer_info[i];
  1594. while(rx_desc->status & IXGB_RX_DESC_STATUS_DD) {
  1595. struct sk_buff *skb, *next_skb;
  1596. u8 status;
  1597. #ifdef CONFIG_IXGB_NAPI
  1598. if(*work_done >= work_to_do)
  1599. break;
  1600. (*work_done)++;
  1601. #endif
  1602. status = rx_desc->status;
  1603. skb = buffer_info->skb;
  1604. buffer_info->skb = NULL;
  1605. prefetch(skb->data);
  1606. if(++i == rx_ring->count) i = 0;
  1607. next_rxd = IXGB_RX_DESC(*rx_ring, i);
  1608. prefetch(next_rxd);
  1609. if((j = i + 1) == rx_ring->count) j = 0;
  1610. next2_buffer = &rx_ring->buffer_info[j];
  1611. prefetch(next2_buffer);
  1612. next_buffer = &rx_ring->buffer_info[i];
  1613. next_skb = next_buffer->skb;
  1614. prefetch(next_skb);
  1615. cleaned = true;
  1616. pci_unmap_single(pdev,
  1617. buffer_info->dma,
  1618. buffer_info->length,
  1619. PCI_DMA_FROMDEVICE);
  1620. length = le16_to_cpu(rx_desc->length);
  1621. if(unlikely(!(status & IXGB_RX_DESC_STATUS_EOP))) {
  1622. /* All receives must fit into a single buffer */
  1623. IXGB_DBG("Receive packet consumed multiple buffers "
  1624. "length<%x>\n", length);
  1625. dev_kfree_skb_irq(skb);
  1626. goto rxdesc_done;
  1627. }
  1628. if (unlikely(rx_desc->errors
  1629. & (IXGB_RX_DESC_ERRORS_CE | IXGB_RX_DESC_ERRORS_SE
  1630. | IXGB_RX_DESC_ERRORS_P |
  1631. IXGB_RX_DESC_ERRORS_RXE))) {
  1632. dev_kfree_skb_irq(skb);
  1633. goto rxdesc_done;
  1634. }
  1635. /* code added for copybreak, this should improve
  1636. * performance for small packets with large amounts
  1637. * of reassembly being done in the stack */
  1638. #define IXGB_CB_LENGTH 256
  1639. if (length < IXGB_CB_LENGTH) {
  1640. struct sk_buff *new_skb =
  1641. netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
  1642. if (new_skb) {
  1643. skb_reserve(new_skb, NET_IP_ALIGN);
  1644. skb_copy_to_linear_data_offset(new_skb,
  1645. -NET_IP_ALIGN,
  1646. (skb->data -
  1647. NET_IP_ALIGN),
  1648. (length +
  1649. NET_IP_ALIGN));
  1650. /* save the skb in buffer_info as good */
  1651. buffer_info->skb = skb;
  1652. skb = new_skb;
  1653. }
  1654. }
  1655. /* end copybreak code */
  1656. /* Good Receive */
  1657. skb_put(skb, length);
  1658. /* Receive Checksum Offload */
  1659. ixgb_rx_checksum(adapter, rx_desc, skb);
  1660. skb->protocol = eth_type_trans(skb, netdev);
  1661. #ifdef CONFIG_IXGB_NAPI
  1662. if(adapter->vlgrp && (status & IXGB_RX_DESC_STATUS_VP)) {
  1663. vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
  1664. le16_to_cpu(rx_desc->special) &
  1665. IXGB_RX_DESC_SPECIAL_VLAN_MASK);
  1666. } else {
  1667. netif_receive_skb(skb);
  1668. }
  1669. #else /* CONFIG_IXGB_NAPI */
  1670. if(adapter->vlgrp && (status & IXGB_RX_DESC_STATUS_VP)) {
  1671. vlan_hwaccel_rx(skb, adapter->vlgrp,
  1672. le16_to_cpu(rx_desc->special) &
  1673. IXGB_RX_DESC_SPECIAL_VLAN_MASK);
  1674. } else {
  1675. netif_rx(skb);
  1676. }
  1677. #endif /* CONFIG_IXGB_NAPI */
  1678. netdev->last_rx = jiffies;
  1679. rxdesc_done:
  1680. /* clean up descriptor, might be written over by hw */
  1681. rx_desc->status = 0;
  1682. /* use prefetched values */
  1683. rx_desc = next_rxd;
  1684. buffer_info = next_buffer;
  1685. }
  1686. rx_ring->next_to_clean = i;
  1687. ixgb_alloc_rx_buffers(adapter);
  1688. return cleaned;
  1689. }
  1690. /**
  1691. * ixgb_alloc_rx_buffers - Replace used receive buffers
  1692. * @adapter: address of board private structure
  1693. **/
  1694. static void
  1695. ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter)
  1696. {
  1697. struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
  1698. struct net_device *netdev = adapter->netdev;
  1699. struct pci_dev *pdev = adapter->pdev;
  1700. struct ixgb_rx_desc *rx_desc;
  1701. struct ixgb_buffer *buffer_info;
  1702. struct sk_buff *skb;
  1703. unsigned int i;
  1704. long cleancount;
  1705. i = rx_ring->next_to_use;
  1706. buffer_info = &rx_ring->buffer_info[i];
  1707. cleancount = IXGB_DESC_UNUSED(rx_ring);
  1708. /* leave three descriptors unused */
  1709. while(--cleancount > 2) {
  1710. /* recycle! its good for you */
  1711. skb = buffer_info->skb;
  1712. if (skb) {
  1713. skb_trim(skb, 0);
  1714. goto map_skb;
  1715. }
  1716. skb = netdev_alloc_skb(netdev, adapter->rx_buffer_len
  1717. + NET_IP_ALIGN);
  1718. if (unlikely(!skb)) {
  1719. /* Better luck next round */
  1720. adapter->alloc_rx_buff_failed++;
  1721. break;
  1722. }
  1723. /* Make buffer alignment 2 beyond a 16 byte boundary
  1724. * this will result in a 16 byte aligned IP header after
  1725. * the 14 byte MAC header is removed
  1726. */
  1727. skb_reserve(skb, NET_IP_ALIGN);
  1728. buffer_info->skb = skb;
  1729. buffer_info->length = adapter->rx_buffer_len;
  1730. map_skb:
  1731. buffer_info->dma = pci_map_single(pdev,
  1732. skb->data,
  1733. adapter->rx_buffer_len,
  1734. PCI_DMA_FROMDEVICE);
  1735. rx_desc = IXGB_RX_DESC(*rx_ring, i);
  1736. rx_desc->buff_addr = cpu_to_le64(buffer_info->dma);
  1737. /* guarantee DD bit not set now before h/w gets descriptor
  1738. * this is the rest of the workaround for h/w double
  1739. * writeback. */
  1740. rx_desc->status = 0;
  1741. if(++i == rx_ring->count) i = 0;
  1742. buffer_info = &rx_ring->buffer_info[i];
  1743. }
  1744. if (likely(rx_ring->next_to_use != i)) {
  1745. rx_ring->next_to_use = i;
  1746. if (unlikely(i-- == 0))
  1747. i = (rx_ring->count - 1);
  1748. /* Force memory writes to complete before letting h/w
  1749. * know there are new descriptors to fetch. (Only
  1750. * applicable for weak-ordered memory model archs, such
  1751. * as IA-64). */
  1752. wmb();
  1753. IXGB_WRITE_REG(&adapter->hw, RDT, i);
  1754. }
  1755. }
  1756. /**
  1757. * ixgb_vlan_rx_register - enables or disables vlan tagging/stripping.
  1758. *
  1759. * @param netdev network interface device structure
  1760. * @param grp indicates to enable or disable tagging/stripping
  1761. **/
  1762. static void
  1763. ixgb_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
  1764. {
  1765. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1766. u32 ctrl, rctl;
  1767. ixgb_irq_disable(adapter);
  1768. adapter->vlgrp = grp;
  1769. if(grp) {
  1770. /* enable VLAN tag insert/strip */
  1771. ctrl = IXGB_READ_REG(&adapter->hw, CTRL0);
  1772. ctrl |= IXGB_CTRL0_VME;
  1773. IXGB_WRITE_REG(&adapter->hw, CTRL0, ctrl);
  1774. /* enable VLAN receive filtering */
  1775. rctl = IXGB_READ_REG(&adapter->hw, RCTL);
  1776. rctl |= IXGB_RCTL_VFE;
  1777. rctl &= ~IXGB_RCTL_CFIEN;
  1778. IXGB_WRITE_REG(&adapter->hw, RCTL, rctl);
  1779. } else {
  1780. /* disable VLAN tag insert/strip */
  1781. ctrl = IXGB_READ_REG(&adapter->hw, CTRL0);
  1782. ctrl &= ~IXGB_CTRL0_VME;
  1783. IXGB_WRITE_REG(&adapter->hw, CTRL0, ctrl);
  1784. /* disable VLAN filtering */
  1785. rctl = IXGB_READ_REG(&adapter->hw, RCTL);
  1786. rctl &= ~IXGB_RCTL_VFE;
  1787. IXGB_WRITE_REG(&adapter->hw, RCTL, rctl);
  1788. }
  1789. /* don't enable interrupts unless we are UP */
  1790. if (adapter->netdev->flags & IFF_UP)
  1791. ixgb_irq_enable(adapter);
  1792. }
  1793. static void
  1794. ixgb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
  1795. {
  1796. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1797. u32 vfta, index;
  1798. /* add VID to filter table */
  1799. index = (vid >> 5) & 0x7F;
  1800. vfta = IXGB_READ_REG_ARRAY(&adapter->hw, VFTA, index);
  1801. vfta |= (1 << (vid & 0x1F));
  1802. ixgb_write_vfta(&adapter->hw, index, vfta);
  1803. }
  1804. static void
  1805. ixgb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
  1806. {
  1807. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1808. u32 vfta, index;
  1809. ixgb_irq_disable(adapter);
  1810. vlan_group_set_device(adapter->vlgrp, vid, NULL);
  1811. /* don't enable interrupts unless we are UP */
  1812. if (adapter->netdev->flags & IFF_UP)
  1813. ixgb_irq_enable(adapter);
  1814. /* remove VID from filter table */
  1815. index = (vid >> 5) & 0x7F;
  1816. vfta = IXGB_READ_REG_ARRAY(&adapter->hw, VFTA, index);
  1817. vfta &= ~(1 << (vid & 0x1F));
  1818. ixgb_write_vfta(&adapter->hw, index, vfta);
  1819. }
  1820. static void
  1821. ixgb_restore_vlan(struct ixgb_adapter *adapter)
  1822. {
  1823. ixgb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
  1824. if(adapter->vlgrp) {
  1825. u16 vid;
  1826. for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
  1827. if(!vlan_group_get_device(adapter->vlgrp, vid))
  1828. continue;
  1829. ixgb_vlan_rx_add_vid(adapter->netdev, vid);
  1830. }
  1831. }
  1832. }
  1833. #ifdef CONFIG_NET_POLL_CONTROLLER
  1834. /*
  1835. * Polling 'interrupt' - used by things like netconsole to send skbs
  1836. * without having to re-enable interrupts. It's not called while
  1837. * the interrupt routine is executing.
  1838. */
  1839. static void ixgb_netpoll(struct net_device *dev)
  1840. {
  1841. struct ixgb_adapter *adapter = netdev_priv(dev);
  1842. disable_irq(adapter->pdev->irq);
  1843. ixgb_intr(adapter->pdev->irq, dev);
  1844. enable_irq(adapter->pdev->irq);
  1845. }
  1846. #endif
  1847. /**
  1848. * ixgb_io_error_detected() - called when PCI error is detected
  1849. * @pdev pointer to pci device with error
  1850. * @state pci channel state after error
  1851. *
  1852. * This callback is called by the PCI subsystem whenever
  1853. * a PCI bus error is detected.
  1854. */
  1855. static pci_ers_result_t ixgb_io_error_detected (struct pci_dev *pdev,
  1856. enum pci_channel_state state)
  1857. {
  1858. struct net_device *netdev = pci_get_drvdata(pdev);
  1859. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1860. if(netif_running(netdev))
  1861. ixgb_down(adapter, true);
  1862. pci_disable_device(pdev);
  1863. /* Request a slot reset. */
  1864. return PCI_ERS_RESULT_NEED_RESET;
  1865. }
  1866. /**
  1867. * ixgb_io_slot_reset - called after the pci bus has been reset.
  1868. * @pdev pointer to pci device with error
  1869. *
  1870. * This callback is called after the PCI buss has been reset.
  1871. * Basically, this tries to restart the card from scratch.
  1872. * This is a shortened version of the device probe/discovery code,
  1873. * it resembles the first-half of the ixgb_probe() routine.
  1874. */
  1875. static pci_ers_result_t ixgb_io_slot_reset (struct pci_dev *pdev)
  1876. {
  1877. struct net_device *netdev = pci_get_drvdata(pdev);
  1878. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1879. if(pci_enable_device(pdev)) {
  1880. DPRINTK(PROBE, ERR, "Cannot re-enable PCI device after reset.\n");
  1881. return PCI_ERS_RESULT_DISCONNECT;
  1882. }
  1883. /* Perform card reset only on one instance of the card */
  1884. if (0 != PCI_FUNC (pdev->devfn))
  1885. return PCI_ERS_RESULT_RECOVERED;
  1886. pci_set_master(pdev);
  1887. netif_carrier_off(netdev);
  1888. netif_stop_queue(netdev);
  1889. ixgb_reset(adapter);
  1890. /* Make sure the EEPROM is good */
  1891. if(!ixgb_validate_eeprom_checksum(&adapter->hw)) {
  1892. DPRINTK(PROBE, ERR, "After reset, the EEPROM checksum is not valid.\n");
  1893. return PCI_ERS_RESULT_DISCONNECT;
  1894. }
  1895. ixgb_get_ee_mac_addr(&adapter->hw, netdev->dev_addr);
  1896. memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
  1897. if(!is_valid_ether_addr(netdev->perm_addr)) {
  1898. DPRINTK(PROBE, ERR, "After reset, invalid MAC address.\n");
  1899. return PCI_ERS_RESULT_DISCONNECT;
  1900. }
  1901. return PCI_ERS_RESULT_RECOVERED;
  1902. }
  1903. /**
  1904. * ixgb_io_resume - called when its OK to resume normal operations
  1905. * @pdev pointer to pci device with error
  1906. *
  1907. * The error recovery driver tells us that its OK to resume
  1908. * normal operation. Implementation resembles the second-half
  1909. * of the ixgb_probe() routine.
  1910. */
  1911. static void ixgb_io_resume (struct pci_dev *pdev)
  1912. {
  1913. struct net_device *netdev = pci_get_drvdata(pdev);
  1914. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1915. pci_set_master(pdev);
  1916. if(netif_running(netdev)) {
  1917. if(ixgb_up(adapter)) {
  1918. printk ("ixgb: can't bring device back up after reset\n");
  1919. return;
  1920. }
  1921. }
  1922. netif_device_attach(netdev);
  1923. mod_timer(&adapter->watchdog_timer, jiffies);
  1924. }
  1925. /* ixgb_main.c */