bnx2x_fw_defs.h 6.2 KB

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  1. /* bnx2x_fw_defs.h: Broadcom Everest network driver.
  2. *
  3. * Copyright (c) 2007-2008 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. */
  9. #define CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
  10. (0x1922 + (port * 0x40) + (index * 0x4))
  11. #define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
  12. (0x1900 + (port * 0x40))
  13. #define CSTORM_HC_BTR_OFFSET(port)\
  14. (0x1984 + (port * 0xc0))
  15. #define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
  16. (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
  17. #define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
  18. (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
  19. #define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
  20. (0x1400 + (port * 0x280) + (cpu_id * 0x28))
  21. #define CSTORM_STATS_FLAGS_OFFSET(port) (0x5108 + (port * 0x8))
  22. #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id)\
  23. (0x1510 + (port * 0x240) + (client_id * 0x20))
  24. #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
  25. (0x138a + (port * 0x28) + (index * 0x4))
  26. #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
  27. (0x1370 + (port * 0x28))
  28. #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
  29. (0x4b70 + (port * 0x8))
  30. #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function)\
  31. (0x1418 + (function * 0x30))
  32. #define TSTORM_HC_BTR_OFFSET(port)\
  33. (0x13c4 + (port * 0x18))
  34. #define TSTORM_INDIRECTION_TABLE_OFFSET(port)\
  35. (0x22c8 + (port * 0x80))
  36. #define TSTORM_INDIRECTION_TABLE_SIZE 0x80
  37. #define TSTORM_MAC_FILTER_CONFIG_OFFSET(port)\
  38. (0x1420 + (port * 0x30))
  39. #define TSTORM_RCQ_PROD_OFFSET(port, client_id)\
  40. (0x1508 + (port * 0x240) + (client_id * 0x20))
  41. #define TSTORM_STATS_FLAGS_OFFSET(port) (0x4b90 + (port * 0x8))
  42. #define USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
  43. (0x191a + (port * 0x28) + (index * 0x4))
  44. #define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
  45. (0x1900 + (port * 0x28))
  46. #define USTORM_HC_BTR_OFFSET(port)\
  47. (0x1954 + (port * 0xb8))
  48. #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port)\
  49. (0x5408 + (port * 0x8))
  50. #define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
  51. (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
  52. #define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
  53. (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
  54. #define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
  55. (0x1400 + (port * 0x280) + (cpu_id * 0x28))
  56. #define XSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
  57. #define XSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
  58. #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
  59. (0x141a + (port * 0x28) + (index * 0x4))
  60. #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
  61. (0x1400 + (port * 0x28))
  62. #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
  63. (0x5408 + (port * 0x8))
  64. #define XSTORM_HC_BTR_OFFSET(port)\
  65. (0x1454 + (port * 0x18))
  66. #define XSTORM_SPQ_PAGE_BASE_OFFSET(port)\
  67. (0x5328 + (port * 0x18))
  68. #define XSTORM_SPQ_PROD_OFFSET(port)\
  69. (0x5330 + (port * 0x18))
  70. #define XSTORM_STATS_FLAGS_OFFSET(port) (0x53f8 + (port * 0x8))
  71. #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
  72. /**
  73. * This file defines HSI constatnts for the ETH flow
  74. */
  75. /* hash types */
  76. #define DEFAULT_HASH_TYPE 0
  77. #define IPV4_HASH_TYPE 1
  78. #define TCP_IPV4_HASH_TYPE 2
  79. #define IPV6_HASH_TYPE 3
  80. #define TCP_IPV6_HASH_TYPE 4
  81. /* values of command IDs in the ramrod message */
  82. #define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
  83. #define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
  84. #define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
  85. #define RAMROD_CMD_ID_ETH_UPDATE (100)
  86. #define RAMROD_CMD_ID_ETH_HALT (105)
  87. #define RAMROD_CMD_ID_ETH_SET_MAC (110)
  88. #define RAMROD_CMD_ID_ETH_CFC_DEL (115)
  89. #define RAMROD_CMD_ID_ETH_PORT_DEL (120)
  90. #define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
  91. /* command values for set mac command */
  92. #define T_ETH_MAC_COMMAND_SET 0
  93. #define T_ETH_MAC_COMMAND_INVALIDATE 1
  94. #define T_ETH_INDIRECTION_TABLE_SIZE 128
  95. /* Maximal L2 clients supported */
  96. #define ETH_MAX_RX_CLIENTS (18)
  97. /**
  98. * This file defines HSI constatnts common to all microcode flows
  99. */
  100. /* Connection types */
  101. #define ETH_CONNECTION_TYPE 0
  102. #define PROTOCOL_STATE_BIT_OFFSET 6
  103. #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
  104. /* microcode fixed page page size 4K (chains and ring segments) */
  105. #define MC_PAGE_SIZE (4096)
  106. /* Host coalescing constants */
  107. /* IGU constants */
  108. #define IGU_PORT_BASE 0x0400
  109. #define IGU_ADDR_MSIX 0x0000
  110. #define IGU_ADDR_INT_ACK 0x0200
  111. #define IGU_ADDR_PROD_UPD 0x0201
  112. #define IGU_ADDR_ATTN_BITS_UPD 0x0202
  113. #define IGU_ADDR_ATTN_BITS_SET 0x0203
  114. #define IGU_ADDR_ATTN_BITS_CLR 0x0204
  115. #define IGU_ADDR_COALESCE_NOW 0x0205
  116. #define IGU_ADDR_SIMD_MASK 0x0206
  117. #define IGU_ADDR_SIMD_NOMASK 0x0207
  118. #define IGU_ADDR_MSI_CTL 0x0210
  119. #define IGU_ADDR_MSI_ADDR_LO 0x0211
  120. #define IGU_ADDR_MSI_ADDR_HI 0x0212
  121. #define IGU_ADDR_MSI_DATA 0x0213
  122. #define IGU_INT_ENABLE 0
  123. #define IGU_INT_DISABLE 1
  124. #define IGU_INT_NOP 2
  125. #define IGU_INT_NOP2 3
  126. /* index numbers */
  127. #define HC_USTORM_DEF_SB_NUM_INDICES 4
  128. #define HC_CSTORM_DEF_SB_NUM_INDICES 8
  129. #define HC_XSTORM_DEF_SB_NUM_INDICES 4
  130. #define HC_TSTORM_DEF_SB_NUM_INDICES 4
  131. #define HC_USTORM_SB_NUM_INDICES 4
  132. #define HC_CSTORM_SB_NUM_INDICES 4
  133. /* index values - which counterto update */
  134. #define HC_INDEX_U_ETH_RX_CQ_CONS 1
  135. #define HC_INDEX_C_ETH_TX_CQ_CONS 1
  136. #define HC_INDEX_DEF_X_SPQ_CONS 0
  137. #define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
  138. #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
  139. /* used by the driver to get the SB offset */
  140. #define USTORM_ID 0
  141. #define CSTORM_ID 1
  142. #define XSTORM_ID 2
  143. #define TSTORM_ID 3
  144. #define ATTENTION_ID 4
  145. /* max number of slow path commands per port */
  146. #define MAX_RAMRODS_PER_PORT (8)
  147. /* values for RX ETH CQE type field */
  148. #define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
  149. #define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
  150. /* MAC address list size */
  151. #define T_MAC_ADDRESS_LIST_SIZE (96)
  152. #define XSTORM_IP_ID_ROLL_HALF 0x8000
  153. #define XSTORM_IP_ID_ROLL_ALL 0
  154. #define FW_LOG_LIST_SIZE (50)
  155. #define NUM_OF_PROTOCOLS 4
  156. #define MAX_COS_NUMBER 16
  157. #define MAX_T_STAT_COUNTER_ID 18
  158. #define T_FAIR 1
  159. #define FAIR_MEM 2
  160. #define RS_PERIODIC_TIMEOUT_IN_SDM_TICS 25
  161. #define UNKNOWN_ADDRESS 0
  162. #define UNICAST_ADDRESS 1
  163. #define MULTICAST_ADDRESS 2
  164. #define BROADCAST_ADDRESS 3