acenic.c 86 KB

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  1. /*
  2. * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
  3. * and other Tigon based cards.
  4. *
  5. * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
  6. *
  7. * Thanks to Alteon and 3Com for providing hardware and documentation
  8. * enabling me to write this driver.
  9. *
  10. * A mailing list for discussing the use of this driver has been
  11. * setup, please subscribe to the lists if you have any questions
  12. * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
  13. * see how to subscribe.
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * Additional credits:
  21. * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
  22. * dump support. The trace dump support has not been
  23. * integrated yet however.
  24. * Troy Benjegerdes: Big Endian (PPC) patches.
  25. * Nate Stahl: Better out of memory handling and stats support.
  26. * Aman Singla: Nasty race between interrupt handler and tx code dealing
  27. * with 'testing the tx_ret_csm and setting tx_full'
  28. * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
  29. * infrastructure and Sparc support
  30. * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
  31. * driver under Linux/Sparc64
  32. * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
  33. * ETHTOOL_GDRVINFO support
  34. * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
  35. * handler and close() cleanup.
  36. * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
  37. * memory mapped IO is enabled to
  38. * make the driver work on RS/6000.
  39. * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
  40. * where the driver would disable
  41. * bus master mode if it had to disable
  42. * write and invalidate.
  43. * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
  44. * endian systems.
  45. * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
  46. * rx producer index when
  47. * flushing the Jumbo ring.
  48. * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
  49. * driver init path.
  50. * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
  51. */
  52. #include <linux/module.h>
  53. #include <linux/moduleparam.h>
  54. #include <linux/version.h>
  55. #include <linux/types.h>
  56. #include <linux/errno.h>
  57. #include <linux/ioport.h>
  58. #include <linux/pci.h>
  59. #include <linux/dma-mapping.h>
  60. #include <linux/kernel.h>
  61. #include <linux/netdevice.h>
  62. #include <linux/etherdevice.h>
  63. #include <linux/skbuff.h>
  64. #include <linux/init.h>
  65. #include <linux/delay.h>
  66. #include <linux/mm.h>
  67. #include <linux/highmem.h>
  68. #include <linux/sockios.h>
  69. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  70. #include <linux/if_vlan.h>
  71. #endif
  72. #ifdef SIOCETHTOOL
  73. #include <linux/ethtool.h>
  74. #endif
  75. #include <net/sock.h>
  76. #include <net/ip.h>
  77. #include <asm/system.h>
  78. #include <asm/io.h>
  79. #include <asm/irq.h>
  80. #include <asm/byteorder.h>
  81. #include <asm/uaccess.h>
  82. #define DRV_NAME "acenic"
  83. #undef INDEX_DEBUG
  84. #ifdef CONFIG_ACENIC_OMIT_TIGON_I
  85. #define ACE_IS_TIGON_I(ap) 0
  86. #define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
  87. #else
  88. #define ACE_IS_TIGON_I(ap) (ap->version == 1)
  89. #define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
  90. #endif
  91. #ifndef PCI_VENDOR_ID_ALTEON
  92. #define PCI_VENDOR_ID_ALTEON 0x12ae
  93. #endif
  94. #ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
  95. #define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
  96. #define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
  97. #endif
  98. #ifndef PCI_DEVICE_ID_3COM_3C985
  99. #define PCI_DEVICE_ID_3COM_3C985 0x0001
  100. #endif
  101. #ifndef PCI_VENDOR_ID_NETGEAR
  102. #define PCI_VENDOR_ID_NETGEAR 0x1385
  103. #define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
  104. #endif
  105. #ifndef PCI_DEVICE_ID_NETGEAR_GA620T
  106. #define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
  107. #endif
  108. /*
  109. * Farallon used the DEC vendor ID by mistake and they seem not
  110. * to care - stinky!
  111. */
  112. #ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
  113. #define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
  114. #endif
  115. #ifndef PCI_DEVICE_ID_FARALLON_PN9100T
  116. #define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
  117. #endif
  118. #ifndef PCI_VENDOR_ID_SGI
  119. #define PCI_VENDOR_ID_SGI 0x10a9
  120. #endif
  121. #ifndef PCI_DEVICE_ID_SGI_ACENIC
  122. #define PCI_DEVICE_ID_SGI_ACENIC 0x0009
  123. #endif
  124. static struct pci_device_id acenic_pci_tbl[] = {
  125. { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
  126. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  127. { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
  128. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  129. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
  130. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  131. { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
  132. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  133. { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
  134. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  135. /*
  136. * Farallon used the DEC vendor ID on their cards incorrectly,
  137. * then later Alteon's ID.
  138. */
  139. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
  140. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  141. { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
  142. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  143. { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
  144. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  145. { }
  146. };
  147. MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
  148. #define ace_sync_irq(irq) synchronize_irq(irq)
  149. #ifndef offset_in_page
  150. #define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
  151. #endif
  152. #define ACE_MAX_MOD_PARMS 8
  153. #define BOARD_IDX_STATIC 0
  154. #define BOARD_IDX_OVERFLOW -1
  155. #if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
  156. defined(NETIF_F_HW_VLAN_RX)
  157. #define ACENIC_DO_VLAN 1
  158. #define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
  159. #else
  160. #define ACENIC_DO_VLAN 0
  161. #define ACE_RCB_VLAN_FLAG 0
  162. #endif
  163. #include "acenic.h"
  164. /*
  165. * These must be defined before the firmware is included.
  166. */
  167. #define MAX_TEXT_LEN 96*1024
  168. #define MAX_RODATA_LEN 8*1024
  169. #define MAX_DATA_LEN 2*1024
  170. #include "acenic_firmware.h"
  171. #ifndef tigon2FwReleaseLocal
  172. #define tigon2FwReleaseLocal 0
  173. #endif
  174. /*
  175. * This driver currently supports Tigon I and Tigon II based cards
  176. * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
  177. * GA620. The driver should also work on the SGI, DEC and Farallon
  178. * versions of the card, however I have not been able to test that
  179. * myself.
  180. *
  181. * This card is really neat, it supports receive hardware checksumming
  182. * and jumbo frames (up to 9000 bytes) and does a lot of work in the
  183. * firmware. Also the programming interface is quite neat, except for
  184. * the parts dealing with the i2c eeprom on the card ;-)
  185. *
  186. * Using jumbo frames:
  187. *
  188. * To enable jumbo frames, simply specify an mtu between 1500 and 9000
  189. * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
  190. * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
  191. * interface number and <MTU> being the MTU value.
  192. *
  193. * Module parameters:
  194. *
  195. * When compiled as a loadable module, the driver allows for a number
  196. * of module parameters to be specified. The driver supports the
  197. * following module parameters:
  198. *
  199. * trace=<val> - Firmware trace level. This requires special traced
  200. * firmware to replace the firmware supplied with
  201. * the driver - for debugging purposes only.
  202. *
  203. * link=<val> - Link state. Normally you want to use the default link
  204. * parameters set by the driver. This can be used to
  205. * override these in case your switch doesn't negotiate
  206. * the link properly. Valid values are:
  207. * 0x0001 - Force half duplex link.
  208. * 0x0002 - Do not negotiate line speed with the other end.
  209. * 0x0010 - 10Mbit/sec link.
  210. * 0x0020 - 100Mbit/sec link.
  211. * 0x0040 - 1000Mbit/sec link.
  212. * 0x0100 - Do not negotiate flow control.
  213. * 0x0200 - Enable RX flow control Y
  214. * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
  215. * Default value is 0x0270, ie. enable link+flow
  216. * control negotiation. Negotiating the highest
  217. * possible link speed with RX flow control enabled.
  218. *
  219. * When disabling link speed negotiation, only one link
  220. * speed is allowed to be specified!
  221. *
  222. * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
  223. * to wait for more packets to arive before
  224. * interrupting the host, from the time the first
  225. * packet arrives.
  226. *
  227. * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
  228. * to wait for more packets to arive in the transmit ring,
  229. * before interrupting the host, after transmitting the
  230. * first packet in the ring.
  231. *
  232. * max_tx_desc=<val> - maximum number of transmit descriptors
  233. * (packets) transmitted before interrupting the host.
  234. *
  235. * max_rx_desc=<val> - maximum number of receive descriptors
  236. * (packets) received before interrupting the host.
  237. *
  238. * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
  239. * increments of the NIC's on board memory to be used for
  240. * transmit and receive buffers. For the 1MB NIC app. 800KB
  241. * is available, on the 1/2MB NIC app. 300KB is available.
  242. * 68KB will always be available as a minimum for both
  243. * directions. The default value is a 50/50 split.
  244. * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
  245. * operations, default (1) is to always disable this as
  246. * that is what Alteon does on NT. I have not been able
  247. * to measure any real performance differences with
  248. * this on my systems. Set <val>=0 if you want to
  249. * enable these operations.
  250. *
  251. * If you use more than one NIC, specify the parameters for the
  252. * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
  253. * run tracing on NIC #2 but not on NIC #1 and #3.
  254. *
  255. * TODO:
  256. *
  257. * - Proper multicast support.
  258. * - NIC dump support.
  259. * - More tuning parameters.
  260. *
  261. * The mini ring is not used under Linux and I am not sure it makes sense
  262. * to actually use it.
  263. *
  264. * New interrupt handler strategy:
  265. *
  266. * The old interrupt handler worked using the traditional method of
  267. * replacing an skbuff with a new one when a packet arrives. However
  268. * the rx rings do not need to contain a static number of buffer
  269. * descriptors, thus it makes sense to move the memory allocation out
  270. * of the main interrupt handler and do it in a bottom half handler
  271. * and only allocate new buffers when the number of buffers in the
  272. * ring is below a certain threshold. In order to avoid starving the
  273. * NIC under heavy load it is however necessary to force allocation
  274. * when hitting a minimum threshold. The strategy for alloction is as
  275. * follows:
  276. *
  277. * RX_LOW_BUF_THRES - allocate buffers in the bottom half
  278. * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
  279. * the buffers in the interrupt handler
  280. * RX_RING_THRES - maximum number of buffers in the rx ring
  281. * RX_MINI_THRES - maximum number of buffers in the mini ring
  282. * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
  283. *
  284. * One advantagous side effect of this allocation approach is that the
  285. * entire rx processing can be done without holding any spin lock
  286. * since the rx rings and registers are totally independent of the tx
  287. * ring and its registers. This of course includes the kmalloc's of
  288. * new skb's. Thus start_xmit can run in parallel with rx processing
  289. * and the memory allocation on SMP systems.
  290. *
  291. * Note that running the skb reallocation in a bottom half opens up
  292. * another can of races which needs to be handled properly. In
  293. * particular it can happen that the interrupt handler tries to run
  294. * the reallocation while the bottom half is either running on another
  295. * CPU or was interrupted on the same CPU. To get around this the
  296. * driver uses bitops to prevent the reallocation routines from being
  297. * reentered.
  298. *
  299. * TX handling can also be done without holding any spin lock, wheee
  300. * this is fun! since tx_ret_csm is only written to by the interrupt
  301. * handler. The case to be aware of is when shutting down the device
  302. * and cleaning up where it is necessary to make sure that
  303. * start_xmit() is not running while this is happening. Well DaveM
  304. * informs me that this case is already protected against ... bye bye
  305. * Mr. Spin Lock, it was nice to know you.
  306. *
  307. * TX interrupts are now partly disabled so the NIC will only generate
  308. * TX interrupts for the number of coal ticks, not for the number of
  309. * TX packets in the queue. This should reduce the number of TX only,
  310. * ie. when no RX processing is done, interrupts seen.
  311. */
  312. /*
  313. * Threshold values for RX buffer allocation - the low water marks for
  314. * when to start refilling the rings are set to 75% of the ring
  315. * sizes. It seems to make sense to refill the rings entirely from the
  316. * intrrupt handler once it gets below the panic threshold, that way
  317. * we don't risk that the refilling is moved to another CPU when the
  318. * one running the interrupt handler just got the slab code hot in its
  319. * cache.
  320. */
  321. #define RX_RING_SIZE 72
  322. #define RX_MINI_SIZE 64
  323. #define RX_JUMBO_SIZE 48
  324. #define RX_PANIC_STD_THRES 16
  325. #define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
  326. #define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
  327. #define RX_PANIC_MINI_THRES 12
  328. #define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
  329. #define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
  330. #define RX_PANIC_JUMBO_THRES 6
  331. #define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
  332. #define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
  333. /*
  334. * Size of the mini ring entries, basically these just should be big
  335. * enough to take TCP ACKs
  336. */
  337. #define ACE_MINI_SIZE 100
  338. #define ACE_MINI_BUFSIZE ACE_MINI_SIZE
  339. #define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
  340. #define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
  341. /*
  342. * There seems to be a magic difference in the effect between 995 and 996
  343. * but little difference between 900 and 995 ... no idea why.
  344. *
  345. * There is now a default set of tuning parameters which is set, depending
  346. * on whether or not the user enables Jumbo frames. It's assumed that if
  347. * Jumbo frames are enabled, the user wants optimal tuning for that case.
  348. */
  349. #define DEF_TX_COAL 400 /* 996 */
  350. #define DEF_TX_MAX_DESC 60 /* was 40 */
  351. #define DEF_RX_COAL 120 /* 1000 */
  352. #define DEF_RX_MAX_DESC 25
  353. #define DEF_TX_RATIO 21 /* 24 */
  354. #define DEF_JUMBO_TX_COAL 20
  355. #define DEF_JUMBO_TX_MAX_DESC 60
  356. #define DEF_JUMBO_RX_COAL 30
  357. #define DEF_JUMBO_RX_MAX_DESC 6
  358. #define DEF_JUMBO_TX_RATIO 21
  359. #if tigon2FwReleaseLocal < 20001118
  360. /*
  361. * Standard firmware and early modifications duplicate
  362. * IRQ load without this flag (coal timer is never reset).
  363. * Note that with this flag tx_coal should be less than
  364. * time to xmit full tx ring.
  365. * 400usec is not so bad for tx ring size of 128.
  366. */
  367. #define TX_COAL_INTS_ONLY 1 /* worth it */
  368. #else
  369. /*
  370. * With modified firmware, this is not necessary, but still useful.
  371. */
  372. #define TX_COAL_INTS_ONLY 1
  373. #endif
  374. #define DEF_TRACE 0
  375. #define DEF_STAT (2 * TICKS_PER_SEC)
  376. static int link_state[ACE_MAX_MOD_PARMS];
  377. static int trace[ACE_MAX_MOD_PARMS];
  378. static int tx_coal_tick[ACE_MAX_MOD_PARMS];
  379. static int rx_coal_tick[ACE_MAX_MOD_PARMS];
  380. static int max_tx_desc[ACE_MAX_MOD_PARMS];
  381. static int max_rx_desc[ACE_MAX_MOD_PARMS];
  382. static int tx_ratio[ACE_MAX_MOD_PARMS];
  383. static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
  384. MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
  385. MODULE_LICENSE("GPL");
  386. MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
  387. module_param_array_named(link, link_state, int, NULL, 0);
  388. module_param_array(trace, int, NULL, 0);
  389. module_param_array(tx_coal_tick, int, NULL, 0);
  390. module_param_array(max_tx_desc, int, NULL, 0);
  391. module_param_array(rx_coal_tick, int, NULL, 0);
  392. module_param_array(max_rx_desc, int, NULL, 0);
  393. module_param_array(tx_ratio, int, NULL, 0);
  394. MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
  395. MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
  396. MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
  397. MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
  398. MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
  399. MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
  400. MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
  401. static char version[] __devinitdata =
  402. "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
  403. " http://home.cern.ch/~jes/gige/acenic.html\n";
  404. static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
  405. static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
  406. static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
  407. static const struct ethtool_ops ace_ethtool_ops = {
  408. .get_settings = ace_get_settings,
  409. .set_settings = ace_set_settings,
  410. .get_drvinfo = ace_get_drvinfo,
  411. };
  412. static void ace_watchdog(struct net_device *dev);
  413. static int __devinit acenic_probe_one(struct pci_dev *pdev,
  414. const struct pci_device_id *id)
  415. {
  416. struct net_device *dev;
  417. struct ace_private *ap;
  418. static int boards_found;
  419. dev = alloc_etherdev(sizeof(struct ace_private));
  420. if (dev == NULL) {
  421. printk(KERN_ERR "acenic: Unable to allocate "
  422. "net_device structure!\n");
  423. return -ENOMEM;
  424. }
  425. SET_NETDEV_DEV(dev, &pdev->dev);
  426. ap = dev->priv;
  427. ap->pdev = pdev;
  428. ap->name = pci_name(pdev);
  429. dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
  430. #if ACENIC_DO_VLAN
  431. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  432. dev->vlan_rx_register = ace_vlan_rx_register;
  433. #endif
  434. dev->tx_timeout = &ace_watchdog;
  435. dev->watchdog_timeo = 5*HZ;
  436. dev->open = &ace_open;
  437. dev->stop = &ace_close;
  438. dev->hard_start_xmit = &ace_start_xmit;
  439. dev->get_stats = &ace_get_stats;
  440. dev->set_multicast_list = &ace_set_multicast_list;
  441. SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
  442. dev->set_mac_address = &ace_set_mac_addr;
  443. dev->change_mtu = &ace_change_mtu;
  444. /* we only display this string ONCE */
  445. if (!boards_found)
  446. printk(version);
  447. if (pci_enable_device(pdev))
  448. goto fail_free_netdev;
  449. /*
  450. * Enable master mode before we start playing with the
  451. * pci_command word since pci_set_master() will modify
  452. * it.
  453. */
  454. pci_set_master(pdev);
  455. pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
  456. /* OpenFirmware on Mac's does not set this - DOH.. */
  457. if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
  458. printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
  459. "access - was not enabled by BIOS/Firmware\n",
  460. ap->name);
  461. ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
  462. pci_write_config_word(ap->pdev, PCI_COMMAND,
  463. ap->pci_command);
  464. wmb();
  465. }
  466. pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
  467. if (ap->pci_latency <= 0x40) {
  468. ap->pci_latency = 0x40;
  469. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
  470. }
  471. /*
  472. * Remap the regs into kernel space - this is abuse of
  473. * dev->base_addr since it was means for I/O port
  474. * addresses but who gives a damn.
  475. */
  476. dev->base_addr = pci_resource_start(pdev, 0);
  477. ap->regs = ioremap(dev->base_addr, 0x4000);
  478. if (!ap->regs) {
  479. printk(KERN_ERR "%s: Unable to map I/O register, "
  480. "AceNIC %i will be disabled.\n",
  481. ap->name, boards_found);
  482. goto fail_free_netdev;
  483. }
  484. switch(pdev->vendor) {
  485. case PCI_VENDOR_ID_ALTEON:
  486. if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
  487. printk(KERN_INFO "%s: Farallon PN9100-T ",
  488. ap->name);
  489. } else {
  490. printk(KERN_INFO "%s: Alteon AceNIC ",
  491. ap->name);
  492. }
  493. break;
  494. case PCI_VENDOR_ID_3COM:
  495. printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
  496. break;
  497. case PCI_VENDOR_ID_NETGEAR:
  498. printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
  499. break;
  500. case PCI_VENDOR_ID_DEC:
  501. if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
  502. printk(KERN_INFO "%s: Farallon PN9000-SX ",
  503. ap->name);
  504. break;
  505. }
  506. case PCI_VENDOR_ID_SGI:
  507. printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
  508. break;
  509. default:
  510. printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
  511. break;
  512. }
  513. printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
  514. printk("irq %d\n", pdev->irq);
  515. #ifdef CONFIG_ACENIC_OMIT_TIGON_I
  516. if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
  517. printk(KERN_ERR "%s: Driver compiled without Tigon I"
  518. " support - NIC disabled\n", dev->name);
  519. goto fail_uninit;
  520. }
  521. #endif
  522. if (ace_allocate_descriptors(dev))
  523. goto fail_free_netdev;
  524. #ifdef MODULE
  525. if (boards_found >= ACE_MAX_MOD_PARMS)
  526. ap->board_idx = BOARD_IDX_OVERFLOW;
  527. else
  528. ap->board_idx = boards_found;
  529. #else
  530. ap->board_idx = BOARD_IDX_STATIC;
  531. #endif
  532. if (ace_init(dev))
  533. goto fail_free_netdev;
  534. if (register_netdev(dev)) {
  535. printk(KERN_ERR "acenic: device registration failed\n");
  536. goto fail_uninit;
  537. }
  538. ap->name = dev->name;
  539. if (ap->pci_using_dac)
  540. dev->features |= NETIF_F_HIGHDMA;
  541. pci_set_drvdata(pdev, dev);
  542. boards_found++;
  543. return 0;
  544. fail_uninit:
  545. ace_init_cleanup(dev);
  546. fail_free_netdev:
  547. free_netdev(dev);
  548. return -ENODEV;
  549. }
  550. static void __devexit acenic_remove_one(struct pci_dev *pdev)
  551. {
  552. struct net_device *dev = pci_get_drvdata(pdev);
  553. struct ace_private *ap = netdev_priv(dev);
  554. struct ace_regs __iomem *regs = ap->regs;
  555. short i;
  556. unregister_netdev(dev);
  557. writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
  558. if (ap->version >= 2)
  559. writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
  560. /*
  561. * This clears any pending interrupts
  562. */
  563. writel(1, &regs->Mb0Lo);
  564. readl(&regs->CpuCtrl); /* flush */
  565. /*
  566. * Make sure no other CPUs are processing interrupts
  567. * on the card before the buffers are being released.
  568. * Otherwise one might experience some `interesting'
  569. * effects.
  570. *
  571. * Then release the RX buffers - jumbo buffers were
  572. * already released in ace_close().
  573. */
  574. ace_sync_irq(dev->irq);
  575. for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
  576. struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
  577. if (skb) {
  578. struct ring_info *ringp;
  579. dma_addr_t mapping;
  580. ringp = &ap->skb->rx_std_skbuff[i];
  581. mapping = pci_unmap_addr(ringp, mapping);
  582. pci_unmap_page(ap->pdev, mapping,
  583. ACE_STD_BUFSIZE,
  584. PCI_DMA_FROMDEVICE);
  585. ap->rx_std_ring[i].size = 0;
  586. ap->skb->rx_std_skbuff[i].skb = NULL;
  587. dev_kfree_skb(skb);
  588. }
  589. }
  590. if (ap->version >= 2) {
  591. for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
  592. struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
  593. if (skb) {
  594. struct ring_info *ringp;
  595. dma_addr_t mapping;
  596. ringp = &ap->skb->rx_mini_skbuff[i];
  597. mapping = pci_unmap_addr(ringp,mapping);
  598. pci_unmap_page(ap->pdev, mapping,
  599. ACE_MINI_BUFSIZE,
  600. PCI_DMA_FROMDEVICE);
  601. ap->rx_mini_ring[i].size = 0;
  602. ap->skb->rx_mini_skbuff[i].skb = NULL;
  603. dev_kfree_skb(skb);
  604. }
  605. }
  606. }
  607. for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
  608. struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
  609. if (skb) {
  610. struct ring_info *ringp;
  611. dma_addr_t mapping;
  612. ringp = &ap->skb->rx_jumbo_skbuff[i];
  613. mapping = pci_unmap_addr(ringp, mapping);
  614. pci_unmap_page(ap->pdev, mapping,
  615. ACE_JUMBO_BUFSIZE,
  616. PCI_DMA_FROMDEVICE);
  617. ap->rx_jumbo_ring[i].size = 0;
  618. ap->skb->rx_jumbo_skbuff[i].skb = NULL;
  619. dev_kfree_skb(skb);
  620. }
  621. }
  622. ace_init_cleanup(dev);
  623. free_netdev(dev);
  624. }
  625. static struct pci_driver acenic_pci_driver = {
  626. .name = "acenic",
  627. .id_table = acenic_pci_tbl,
  628. .probe = acenic_probe_one,
  629. .remove = __devexit_p(acenic_remove_one),
  630. };
  631. static int __init acenic_init(void)
  632. {
  633. return pci_register_driver(&acenic_pci_driver);
  634. }
  635. static void __exit acenic_exit(void)
  636. {
  637. pci_unregister_driver(&acenic_pci_driver);
  638. }
  639. module_init(acenic_init);
  640. module_exit(acenic_exit);
  641. static void ace_free_descriptors(struct net_device *dev)
  642. {
  643. struct ace_private *ap = netdev_priv(dev);
  644. int size;
  645. if (ap->rx_std_ring != NULL) {
  646. size = (sizeof(struct rx_desc) *
  647. (RX_STD_RING_ENTRIES +
  648. RX_JUMBO_RING_ENTRIES +
  649. RX_MINI_RING_ENTRIES +
  650. RX_RETURN_RING_ENTRIES));
  651. pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
  652. ap->rx_ring_base_dma);
  653. ap->rx_std_ring = NULL;
  654. ap->rx_jumbo_ring = NULL;
  655. ap->rx_mini_ring = NULL;
  656. ap->rx_return_ring = NULL;
  657. }
  658. if (ap->evt_ring != NULL) {
  659. size = (sizeof(struct event) * EVT_RING_ENTRIES);
  660. pci_free_consistent(ap->pdev, size, ap->evt_ring,
  661. ap->evt_ring_dma);
  662. ap->evt_ring = NULL;
  663. }
  664. if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
  665. size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
  666. pci_free_consistent(ap->pdev, size, ap->tx_ring,
  667. ap->tx_ring_dma);
  668. }
  669. ap->tx_ring = NULL;
  670. if (ap->evt_prd != NULL) {
  671. pci_free_consistent(ap->pdev, sizeof(u32),
  672. (void *)ap->evt_prd, ap->evt_prd_dma);
  673. ap->evt_prd = NULL;
  674. }
  675. if (ap->rx_ret_prd != NULL) {
  676. pci_free_consistent(ap->pdev, sizeof(u32),
  677. (void *)ap->rx_ret_prd,
  678. ap->rx_ret_prd_dma);
  679. ap->rx_ret_prd = NULL;
  680. }
  681. if (ap->tx_csm != NULL) {
  682. pci_free_consistent(ap->pdev, sizeof(u32),
  683. (void *)ap->tx_csm, ap->tx_csm_dma);
  684. ap->tx_csm = NULL;
  685. }
  686. }
  687. static int ace_allocate_descriptors(struct net_device *dev)
  688. {
  689. struct ace_private *ap = netdev_priv(dev);
  690. int size;
  691. size = (sizeof(struct rx_desc) *
  692. (RX_STD_RING_ENTRIES +
  693. RX_JUMBO_RING_ENTRIES +
  694. RX_MINI_RING_ENTRIES +
  695. RX_RETURN_RING_ENTRIES));
  696. ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
  697. &ap->rx_ring_base_dma);
  698. if (ap->rx_std_ring == NULL)
  699. goto fail;
  700. ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
  701. ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
  702. ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
  703. size = (sizeof(struct event) * EVT_RING_ENTRIES);
  704. ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
  705. if (ap->evt_ring == NULL)
  706. goto fail;
  707. /*
  708. * Only allocate a host TX ring for the Tigon II, the Tigon I
  709. * has to use PCI registers for this ;-(
  710. */
  711. if (!ACE_IS_TIGON_I(ap)) {
  712. size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
  713. ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
  714. &ap->tx_ring_dma);
  715. if (ap->tx_ring == NULL)
  716. goto fail;
  717. }
  718. ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
  719. &ap->evt_prd_dma);
  720. if (ap->evt_prd == NULL)
  721. goto fail;
  722. ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
  723. &ap->rx_ret_prd_dma);
  724. if (ap->rx_ret_prd == NULL)
  725. goto fail;
  726. ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
  727. &ap->tx_csm_dma);
  728. if (ap->tx_csm == NULL)
  729. goto fail;
  730. return 0;
  731. fail:
  732. /* Clean up. */
  733. ace_init_cleanup(dev);
  734. return 1;
  735. }
  736. /*
  737. * Generic cleanup handling data allocated during init. Used when the
  738. * module is unloaded or if an error occurs during initialization
  739. */
  740. static void ace_init_cleanup(struct net_device *dev)
  741. {
  742. struct ace_private *ap;
  743. ap = netdev_priv(dev);
  744. ace_free_descriptors(dev);
  745. if (ap->info)
  746. pci_free_consistent(ap->pdev, sizeof(struct ace_info),
  747. ap->info, ap->info_dma);
  748. kfree(ap->skb);
  749. kfree(ap->trace_buf);
  750. if (dev->irq)
  751. free_irq(dev->irq, dev);
  752. iounmap(ap->regs);
  753. }
  754. /*
  755. * Commands are considered to be slow.
  756. */
  757. static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
  758. {
  759. u32 idx;
  760. idx = readl(&regs->CmdPrd);
  761. writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
  762. idx = (idx + 1) % CMD_RING_ENTRIES;
  763. writel(idx, &regs->CmdPrd);
  764. }
  765. static int __devinit ace_init(struct net_device *dev)
  766. {
  767. struct ace_private *ap;
  768. struct ace_regs __iomem *regs;
  769. struct ace_info *info = NULL;
  770. struct pci_dev *pdev;
  771. unsigned long myjif;
  772. u64 tmp_ptr;
  773. u32 tig_ver, mac1, mac2, tmp, pci_state;
  774. int board_idx, ecode = 0;
  775. short i;
  776. unsigned char cache_size;
  777. DECLARE_MAC_BUF(mac);
  778. ap = netdev_priv(dev);
  779. regs = ap->regs;
  780. board_idx = ap->board_idx;
  781. /*
  782. * aman@sgi.com - its useful to do a NIC reset here to
  783. * address the `Firmware not running' problem subsequent
  784. * to any crashes involving the NIC
  785. */
  786. writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
  787. readl(&regs->HostCtrl); /* PCI write posting */
  788. udelay(5);
  789. /*
  790. * Don't access any other registers before this point!
  791. */
  792. #ifdef __BIG_ENDIAN
  793. /*
  794. * This will most likely need BYTE_SWAP once we switch
  795. * to using __raw_writel()
  796. */
  797. writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
  798. &regs->HostCtrl);
  799. #else
  800. writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
  801. &regs->HostCtrl);
  802. #endif
  803. readl(&regs->HostCtrl); /* PCI write posting */
  804. /*
  805. * Stop the NIC CPU and clear pending interrupts
  806. */
  807. writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
  808. readl(&regs->CpuCtrl); /* PCI write posting */
  809. writel(0, &regs->Mb0Lo);
  810. tig_ver = readl(&regs->HostCtrl) >> 28;
  811. switch(tig_ver){
  812. #ifndef CONFIG_ACENIC_OMIT_TIGON_I
  813. case 4:
  814. case 5:
  815. printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
  816. tig_ver, tigonFwReleaseMajor, tigonFwReleaseMinor,
  817. tigonFwReleaseFix);
  818. writel(0, &regs->LocalCtrl);
  819. ap->version = 1;
  820. ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
  821. break;
  822. #endif
  823. case 6:
  824. printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
  825. tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor,
  826. tigon2FwReleaseFix);
  827. writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
  828. readl(&regs->CpuBCtrl); /* PCI write posting */
  829. /*
  830. * The SRAM bank size does _not_ indicate the amount
  831. * of memory on the card, it controls the _bank_ size!
  832. * Ie. a 1MB AceNIC will have two banks of 512KB.
  833. */
  834. writel(SRAM_BANK_512K, &regs->LocalCtrl);
  835. writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
  836. ap->version = 2;
  837. ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
  838. break;
  839. default:
  840. printk(KERN_WARNING " Unsupported Tigon version detected "
  841. "(%i)\n", tig_ver);
  842. ecode = -ENODEV;
  843. goto init_error;
  844. }
  845. /*
  846. * ModeStat _must_ be set after the SRAM settings as this change
  847. * seems to corrupt the ModeStat and possible other registers.
  848. * The SRAM settings survive resets and setting it to the same
  849. * value a second time works as well. This is what caused the
  850. * `Firmware not running' problem on the Tigon II.
  851. */
  852. #ifdef __BIG_ENDIAN
  853. writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
  854. ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
  855. #else
  856. writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
  857. ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
  858. #endif
  859. readl(&regs->ModeStat); /* PCI write posting */
  860. mac1 = 0;
  861. for(i = 0; i < 4; i++) {
  862. int t;
  863. mac1 = mac1 << 8;
  864. t = read_eeprom_byte(dev, 0x8c+i);
  865. if (t < 0) {
  866. ecode = -EIO;
  867. goto init_error;
  868. } else
  869. mac1 |= (t & 0xff);
  870. }
  871. mac2 = 0;
  872. for(i = 4; i < 8; i++) {
  873. int t;
  874. mac2 = mac2 << 8;
  875. t = read_eeprom_byte(dev, 0x8c+i);
  876. if (t < 0) {
  877. ecode = -EIO;
  878. goto init_error;
  879. } else
  880. mac2 |= (t & 0xff);
  881. }
  882. writel(mac1, &regs->MacAddrHi);
  883. writel(mac2, &regs->MacAddrLo);
  884. dev->dev_addr[0] = (mac1 >> 8) & 0xff;
  885. dev->dev_addr[1] = mac1 & 0xff;
  886. dev->dev_addr[2] = (mac2 >> 24) & 0xff;
  887. dev->dev_addr[3] = (mac2 >> 16) & 0xff;
  888. dev->dev_addr[4] = (mac2 >> 8) & 0xff;
  889. dev->dev_addr[5] = mac2 & 0xff;
  890. printk("MAC: %s\n", print_mac(mac, dev->dev_addr));
  891. /*
  892. * Looks like this is necessary to deal with on all architectures,
  893. * even this %$#%$# N440BX Intel based thing doesn't get it right.
  894. * Ie. having two NICs in the machine, one will have the cache
  895. * line set at boot time, the other will not.
  896. */
  897. pdev = ap->pdev;
  898. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
  899. cache_size <<= 2;
  900. if (cache_size != SMP_CACHE_BYTES) {
  901. printk(KERN_INFO " PCI cache line size set incorrectly "
  902. "(%i bytes) by BIOS/FW, ", cache_size);
  903. if (cache_size > SMP_CACHE_BYTES)
  904. printk("expecting %i\n", SMP_CACHE_BYTES);
  905. else {
  906. printk("correcting to %i\n", SMP_CACHE_BYTES);
  907. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
  908. SMP_CACHE_BYTES >> 2);
  909. }
  910. }
  911. pci_state = readl(&regs->PciState);
  912. printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
  913. "latency: %i clks\n",
  914. (pci_state & PCI_32BIT) ? 32 : 64,
  915. (pci_state & PCI_66MHZ) ? 66 : 33,
  916. ap->pci_latency);
  917. /*
  918. * Set the max DMA transfer size. Seems that for most systems
  919. * the performance is better when no MAX parameter is
  920. * set. However for systems enabling PCI write and invalidate,
  921. * DMA writes must be set to the L1 cache line size to get
  922. * optimal performance.
  923. *
  924. * The default is now to turn the PCI write and invalidate off
  925. * - that is what Alteon does for NT.
  926. */
  927. tmp = READ_CMD_MEM | WRITE_CMD_MEM;
  928. if (ap->version >= 2) {
  929. tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
  930. /*
  931. * Tuning parameters only supported for 8 cards
  932. */
  933. if (board_idx == BOARD_IDX_OVERFLOW ||
  934. dis_pci_mem_inval[board_idx]) {
  935. if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
  936. ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
  937. pci_write_config_word(pdev, PCI_COMMAND,
  938. ap->pci_command);
  939. printk(KERN_INFO " Disabling PCI memory "
  940. "write and invalidate\n");
  941. }
  942. } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
  943. printk(KERN_INFO " PCI memory write & invalidate "
  944. "enabled by BIOS, enabling counter measures\n");
  945. switch(SMP_CACHE_BYTES) {
  946. case 16:
  947. tmp |= DMA_WRITE_MAX_16;
  948. break;
  949. case 32:
  950. tmp |= DMA_WRITE_MAX_32;
  951. break;
  952. case 64:
  953. tmp |= DMA_WRITE_MAX_64;
  954. break;
  955. case 128:
  956. tmp |= DMA_WRITE_MAX_128;
  957. break;
  958. default:
  959. printk(KERN_INFO " Cache line size %i not "
  960. "supported, PCI write and invalidate "
  961. "disabled\n", SMP_CACHE_BYTES);
  962. ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
  963. pci_write_config_word(pdev, PCI_COMMAND,
  964. ap->pci_command);
  965. }
  966. }
  967. }
  968. #ifdef __sparc__
  969. /*
  970. * On this platform, we know what the best dma settings
  971. * are. We use 64-byte maximum bursts, because if we
  972. * burst larger than the cache line size (or even cross
  973. * a 64byte boundary in a single burst) the UltraSparc
  974. * PCI controller will disconnect at 64-byte multiples.
  975. *
  976. * Read-multiple will be properly enabled above, and when
  977. * set will give the PCI controller proper hints about
  978. * prefetching.
  979. */
  980. tmp &= ~DMA_READ_WRITE_MASK;
  981. tmp |= DMA_READ_MAX_64;
  982. tmp |= DMA_WRITE_MAX_64;
  983. #endif
  984. #ifdef __alpha__
  985. tmp &= ~DMA_READ_WRITE_MASK;
  986. tmp |= DMA_READ_MAX_128;
  987. /*
  988. * All the docs say MUST NOT. Well, I did.
  989. * Nothing terrible happens, if we load wrong size.
  990. * Bit w&i still works better!
  991. */
  992. tmp |= DMA_WRITE_MAX_128;
  993. #endif
  994. writel(tmp, &regs->PciState);
  995. #if 0
  996. /*
  997. * The Host PCI bus controller driver has to set FBB.
  998. * If all devices on that PCI bus support FBB, then the controller
  999. * can enable FBB support in the Host PCI Bus controller (or on
  1000. * the PCI-PCI bridge if that applies).
  1001. * -ggg
  1002. */
  1003. /*
  1004. * I have received reports from people having problems when this
  1005. * bit is enabled.
  1006. */
  1007. if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
  1008. printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
  1009. ap->pci_command |= PCI_COMMAND_FAST_BACK;
  1010. pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
  1011. }
  1012. #endif
  1013. /*
  1014. * Configure DMA attributes.
  1015. */
  1016. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  1017. ap->pci_using_dac = 1;
  1018. } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  1019. ap->pci_using_dac = 0;
  1020. } else {
  1021. ecode = -ENODEV;
  1022. goto init_error;
  1023. }
  1024. /*
  1025. * Initialize the generic info block and the command+event rings
  1026. * and the control blocks for the transmit and receive rings
  1027. * as they need to be setup once and for all.
  1028. */
  1029. if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
  1030. &ap->info_dma))) {
  1031. ecode = -EAGAIN;
  1032. goto init_error;
  1033. }
  1034. ap->info = info;
  1035. /*
  1036. * Get the memory for the skb rings.
  1037. */
  1038. if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
  1039. ecode = -EAGAIN;
  1040. goto init_error;
  1041. }
  1042. ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
  1043. DRV_NAME, dev);
  1044. if (ecode) {
  1045. printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
  1046. DRV_NAME, pdev->irq);
  1047. goto init_error;
  1048. } else
  1049. dev->irq = pdev->irq;
  1050. #ifdef INDEX_DEBUG
  1051. spin_lock_init(&ap->debug_lock);
  1052. ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
  1053. ap->last_std_rx = 0;
  1054. ap->last_mini_rx = 0;
  1055. #endif
  1056. memset(ap->info, 0, sizeof(struct ace_info));
  1057. memset(ap->skb, 0, sizeof(struct ace_skb));
  1058. ace_load_firmware(dev);
  1059. ap->fw_running = 0;
  1060. tmp_ptr = ap->info_dma;
  1061. writel(tmp_ptr >> 32, &regs->InfoPtrHi);
  1062. writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
  1063. memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
  1064. set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
  1065. info->evt_ctrl.flags = 0;
  1066. *(ap->evt_prd) = 0;
  1067. wmb();
  1068. set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
  1069. writel(0, &regs->EvtCsm);
  1070. set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
  1071. info->cmd_ctrl.flags = 0;
  1072. info->cmd_ctrl.max_len = 0;
  1073. for (i = 0; i < CMD_RING_ENTRIES; i++)
  1074. writel(0, &regs->CmdRng[i]);
  1075. writel(0, &regs->CmdPrd);
  1076. writel(0, &regs->CmdCsm);
  1077. tmp_ptr = ap->info_dma;
  1078. tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
  1079. set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
  1080. set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
  1081. info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
  1082. info->rx_std_ctrl.flags =
  1083. RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
  1084. memset(ap->rx_std_ring, 0,
  1085. RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
  1086. for (i = 0; i < RX_STD_RING_ENTRIES; i++)
  1087. ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
  1088. ap->rx_std_skbprd = 0;
  1089. atomic_set(&ap->cur_rx_bufs, 0);
  1090. set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
  1091. (ap->rx_ring_base_dma +
  1092. (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
  1093. info->rx_jumbo_ctrl.max_len = 0;
  1094. info->rx_jumbo_ctrl.flags =
  1095. RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
  1096. memset(ap->rx_jumbo_ring, 0,
  1097. RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
  1098. for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
  1099. ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
  1100. ap->rx_jumbo_skbprd = 0;
  1101. atomic_set(&ap->cur_jumbo_bufs, 0);
  1102. memset(ap->rx_mini_ring, 0,
  1103. RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
  1104. if (ap->version >= 2) {
  1105. set_aceaddr(&info->rx_mini_ctrl.rngptr,
  1106. (ap->rx_ring_base_dma +
  1107. (sizeof(struct rx_desc) *
  1108. (RX_STD_RING_ENTRIES +
  1109. RX_JUMBO_RING_ENTRIES))));
  1110. info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
  1111. info->rx_mini_ctrl.flags =
  1112. RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
  1113. for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
  1114. ap->rx_mini_ring[i].flags =
  1115. BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
  1116. } else {
  1117. set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
  1118. info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
  1119. info->rx_mini_ctrl.max_len = 0;
  1120. }
  1121. ap->rx_mini_skbprd = 0;
  1122. atomic_set(&ap->cur_mini_bufs, 0);
  1123. set_aceaddr(&info->rx_return_ctrl.rngptr,
  1124. (ap->rx_ring_base_dma +
  1125. (sizeof(struct rx_desc) *
  1126. (RX_STD_RING_ENTRIES +
  1127. RX_JUMBO_RING_ENTRIES +
  1128. RX_MINI_RING_ENTRIES))));
  1129. info->rx_return_ctrl.flags = 0;
  1130. info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
  1131. memset(ap->rx_return_ring, 0,
  1132. RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
  1133. set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
  1134. *(ap->rx_ret_prd) = 0;
  1135. writel(TX_RING_BASE, &regs->WinBase);
  1136. if (ACE_IS_TIGON_I(ap)) {
  1137. ap->tx_ring = (__force struct tx_desc *) regs->Window;
  1138. for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
  1139. * sizeof(struct tx_desc)) / sizeof(u32); i++)
  1140. writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
  1141. set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
  1142. } else {
  1143. memset(ap->tx_ring, 0,
  1144. MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
  1145. set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
  1146. }
  1147. info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
  1148. tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
  1149. /*
  1150. * The Tigon I does not like having the TX ring in host memory ;-(
  1151. */
  1152. if (!ACE_IS_TIGON_I(ap))
  1153. tmp |= RCB_FLG_TX_HOST_RING;
  1154. #if TX_COAL_INTS_ONLY
  1155. tmp |= RCB_FLG_COAL_INT_ONLY;
  1156. #endif
  1157. info->tx_ctrl.flags = tmp;
  1158. set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
  1159. /*
  1160. * Potential item for tuning parameter
  1161. */
  1162. #if 0 /* NO */
  1163. writel(DMA_THRESH_16W, &regs->DmaReadCfg);
  1164. writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
  1165. #else
  1166. writel(DMA_THRESH_8W, &regs->DmaReadCfg);
  1167. writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
  1168. #endif
  1169. writel(0, &regs->MaskInt);
  1170. writel(1, &regs->IfIdx);
  1171. #if 0
  1172. /*
  1173. * McKinley boxes do not like us fiddling with AssistState
  1174. * this early
  1175. */
  1176. writel(1, &regs->AssistState);
  1177. #endif
  1178. writel(DEF_STAT, &regs->TuneStatTicks);
  1179. writel(DEF_TRACE, &regs->TuneTrace);
  1180. ace_set_rxtx_parms(dev, 0);
  1181. if (board_idx == BOARD_IDX_OVERFLOW) {
  1182. printk(KERN_WARNING "%s: more than %i NICs detected, "
  1183. "ignoring module parameters!\n",
  1184. ap->name, ACE_MAX_MOD_PARMS);
  1185. } else if (board_idx >= 0) {
  1186. if (tx_coal_tick[board_idx])
  1187. writel(tx_coal_tick[board_idx],
  1188. &regs->TuneTxCoalTicks);
  1189. if (max_tx_desc[board_idx])
  1190. writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
  1191. if (rx_coal_tick[board_idx])
  1192. writel(rx_coal_tick[board_idx],
  1193. &regs->TuneRxCoalTicks);
  1194. if (max_rx_desc[board_idx])
  1195. writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
  1196. if (trace[board_idx])
  1197. writel(trace[board_idx], &regs->TuneTrace);
  1198. if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
  1199. writel(tx_ratio[board_idx], &regs->TxBufRat);
  1200. }
  1201. /*
  1202. * Default link parameters
  1203. */
  1204. tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
  1205. LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
  1206. if(ap->version >= 2)
  1207. tmp |= LNK_TX_FLOW_CTL_Y;
  1208. /*
  1209. * Override link default parameters
  1210. */
  1211. if ((board_idx >= 0) && link_state[board_idx]) {
  1212. int option = link_state[board_idx];
  1213. tmp = LNK_ENABLE;
  1214. if (option & 0x01) {
  1215. printk(KERN_INFO "%s: Setting half duplex link\n",
  1216. ap->name);
  1217. tmp &= ~LNK_FULL_DUPLEX;
  1218. }
  1219. if (option & 0x02)
  1220. tmp &= ~LNK_NEGOTIATE;
  1221. if (option & 0x10)
  1222. tmp |= LNK_10MB;
  1223. if (option & 0x20)
  1224. tmp |= LNK_100MB;
  1225. if (option & 0x40)
  1226. tmp |= LNK_1000MB;
  1227. if ((option & 0x70) == 0) {
  1228. printk(KERN_WARNING "%s: No media speed specified, "
  1229. "forcing auto negotiation\n", ap->name);
  1230. tmp |= LNK_NEGOTIATE | LNK_1000MB |
  1231. LNK_100MB | LNK_10MB;
  1232. }
  1233. if ((option & 0x100) == 0)
  1234. tmp |= LNK_NEG_FCTL;
  1235. else
  1236. printk(KERN_INFO "%s: Disabling flow control "
  1237. "negotiation\n", ap->name);
  1238. if (option & 0x200)
  1239. tmp |= LNK_RX_FLOW_CTL_Y;
  1240. if ((option & 0x400) && (ap->version >= 2)) {
  1241. printk(KERN_INFO "%s: Enabling TX flow control\n",
  1242. ap->name);
  1243. tmp |= LNK_TX_FLOW_CTL_Y;
  1244. }
  1245. }
  1246. ap->link = tmp;
  1247. writel(tmp, &regs->TuneLink);
  1248. if (ap->version >= 2)
  1249. writel(tmp, &regs->TuneFastLink);
  1250. if (ACE_IS_TIGON_I(ap))
  1251. writel(tigonFwStartAddr, &regs->Pc);
  1252. if (ap->version == 2)
  1253. writel(tigon2FwStartAddr, &regs->Pc);
  1254. writel(0, &regs->Mb0Lo);
  1255. /*
  1256. * Set tx_csm before we start receiving interrupts, otherwise
  1257. * the interrupt handler might think it is supposed to process
  1258. * tx ints before we are up and running, which may cause a null
  1259. * pointer access in the int handler.
  1260. */
  1261. ap->cur_rx = 0;
  1262. ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
  1263. wmb();
  1264. ace_set_txprd(regs, ap, 0);
  1265. writel(0, &regs->RxRetCsm);
  1266. /*
  1267. * Enable DMA engine now.
  1268. * If we do this sooner, Mckinley box pukes.
  1269. * I assume it's because Tigon II DMA engine wants to check
  1270. * *something* even before the CPU is started.
  1271. */
  1272. writel(1, &regs->AssistState); /* enable DMA */
  1273. /*
  1274. * Start the NIC CPU
  1275. */
  1276. writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
  1277. readl(&regs->CpuCtrl);
  1278. /*
  1279. * Wait for the firmware to spin up - max 3 seconds.
  1280. */
  1281. myjif = jiffies + 3 * HZ;
  1282. while (time_before(jiffies, myjif) && !ap->fw_running)
  1283. cpu_relax();
  1284. if (!ap->fw_running) {
  1285. printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
  1286. ace_dump_trace(ap);
  1287. writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
  1288. readl(&regs->CpuCtrl);
  1289. /* aman@sgi.com - account for badly behaving firmware/NIC:
  1290. * - have observed that the NIC may continue to generate
  1291. * interrupts for some reason; attempt to stop it - halt
  1292. * second CPU for Tigon II cards, and also clear Mb0
  1293. * - if we're a module, we'll fail to load if this was
  1294. * the only GbE card in the system => if the kernel does
  1295. * see an interrupt from the NIC, code to handle it is
  1296. * gone and OOps! - so free_irq also
  1297. */
  1298. if (ap->version >= 2)
  1299. writel(readl(&regs->CpuBCtrl) | CPU_HALT,
  1300. &regs->CpuBCtrl);
  1301. writel(0, &regs->Mb0Lo);
  1302. readl(&regs->Mb0Lo);
  1303. ecode = -EBUSY;
  1304. goto init_error;
  1305. }
  1306. /*
  1307. * We load the ring here as there seem to be no way to tell the
  1308. * firmware to wipe the ring without re-initializing it.
  1309. */
  1310. if (!test_and_set_bit(0, &ap->std_refill_busy))
  1311. ace_load_std_rx_ring(ap, RX_RING_SIZE);
  1312. else
  1313. printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
  1314. ap->name);
  1315. if (ap->version >= 2) {
  1316. if (!test_and_set_bit(0, &ap->mini_refill_busy))
  1317. ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
  1318. else
  1319. printk(KERN_ERR "%s: Someone is busy refilling "
  1320. "the RX mini ring\n", ap->name);
  1321. }
  1322. return 0;
  1323. init_error:
  1324. ace_init_cleanup(dev);
  1325. return ecode;
  1326. }
  1327. static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
  1328. {
  1329. struct ace_private *ap = netdev_priv(dev);
  1330. struct ace_regs __iomem *regs = ap->regs;
  1331. int board_idx = ap->board_idx;
  1332. if (board_idx >= 0) {
  1333. if (!jumbo) {
  1334. if (!tx_coal_tick[board_idx])
  1335. writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
  1336. if (!max_tx_desc[board_idx])
  1337. writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
  1338. if (!rx_coal_tick[board_idx])
  1339. writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
  1340. if (!max_rx_desc[board_idx])
  1341. writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
  1342. if (!tx_ratio[board_idx])
  1343. writel(DEF_TX_RATIO, &regs->TxBufRat);
  1344. } else {
  1345. if (!tx_coal_tick[board_idx])
  1346. writel(DEF_JUMBO_TX_COAL,
  1347. &regs->TuneTxCoalTicks);
  1348. if (!max_tx_desc[board_idx])
  1349. writel(DEF_JUMBO_TX_MAX_DESC,
  1350. &regs->TuneMaxTxDesc);
  1351. if (!rx_coal_tick[board_idx])
  1352. writel(DEF_JUMBO_RX_COAL,
  1353. &regs->TuneRxCoalTicks);
  1354. if (!max_rx_desc[board_idx])
  1355. writel(DEF_JUMBO_RX_MAX_DESC,
  1356. &regs->TuneMaxRxDesc);
  1357. if (!tx_ratio[board_idx])
  1358. writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
  1359. }
  1360. }
  1361. }
  1362. static void ace_watchdog(struct net_device *data)
  1363. {
  1364. struct net_device *dev = data;
  1365. struct ace_private *ap = netdev_priv(dev);
  1366. struct ace_regs __iomem *regs = ap->regs;
  1367. /*
  1368. * We haven't received a stats update event for more than 2.5
  1369. * seconds and there is data in the transmit queue, thus we
  1370. * asume the card is stuck.
  1371. */
  1372. if (*ap->tx_csm != ap->tx_ret_csm) {
  1373. printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
  1374. dev->name, (unsigned int)readl(&regs->HostCtrl));
  1375. /* This can happen due to ieee flow control. */
  1376. } else {
  1377. printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
  1378. dev->name);
  1379. #if 0
  1380. netif_wake_queue(dev);
  1381. #endif
  1382. }
  1383. }
  1384. static void ace_tasklet(unsigned long dev)
  1385. {
  1386. struct ace_private *ap = netdev_priv((struct net_device *)dev);
  1387. int cur_size;
  1388. cur_size = atomic_read(&ap->cur_rx_bufs);
  1389. if ((cur_size < RX_LOW_STD_THRES) &&
  1390. !test_and_set_bit(0, &ap->std_refill_busy)) {
  1391. #ifdef DEBUG
  1392. printk("refilling buffers (current %i)\n", cur_size);
  1393. #endif
  1394. ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
  1395. }
  1396. if (ap->version >= 2) {
  1397. cur_size = atomic_read(&ap->cur_mini_bufs);
  1398. if ((cur_size < RX_LOW_MINI_THRES) &&
  1399. !test_and_set_bit(0, &ap->mini_refill_busy)) {
  1400. #ifdef DEBUG
  1401. printk("refilling mini buffers (current %i)\n",
  1402. cur_size);
  1403. #endif
  1404. ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
  1405. }
  1406. }
  1407. cur_size = atomic_read(&ap->cur_jumbo_bufs);
  1408. if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
  1409. !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
  1410. #ifdef DEBUG
  1411. printk("refilling jumbo buffers (current %i)\n", cur_size);
  1412. #endif
  1413. ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
  1414. }
  1415. ap->tasklet_pending = 0;
  1416. }
  1417. /*
  1418. * Copy the contents of the NIC's trace buffer to kernel memory.
  1419. */
  1420. static void ace_dump_trace(struct ace_private *ap)
  1421. {
  1422. #if 0
  1423. if (!ap->trace_buf)
  1424. if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
  1425. return;
  1426. #endif
  1427. }
  1428. /*
  1429. * Load the standard rx ring.
  1430. *
  1431. * Loading rings is safe without holding the spin lock since this is
  1432. * done only before the device is enabled, thus no interrupts are
  1433. * generated and by the interrupt handler/tasklet handler.
  1434. */
  1435. static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
  1436. {
  1437. struct ace_regs __iomem *regs = ap->regs;
  1438. short i, idx;
  1439. prefetchw(&ap->cur_rx_bufs);
  1440. idx = ap->rx_std_skbprd;
  1441. for (i = 0; i < nr_bufs; i++) {
  1442. struct sk_buff *skb;
  1443. struct rx_desc *rd;
  1444. dma_addr_t mapping;
  1445. skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
  1446. if (!skb)
  1447. break;
  1448. skb_reserve(skb, NET_IP_ALIGN);
  1449. mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
  1450. offset_in_page(skb->data),
  1451. ACE_STD_BUFSIZE,
  1452. PCI_DMA_FROMDEVICE);
  1453. ap->skb->rx_std_skbuff[idx].skb = skb;
  1454. pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
  1455. mapping, mapping);
  1456. rd = &ap->rx_std_ring[idx];
  1457. set_aceaddr(&rd->addr, mapping);
  1458. rd->size = ACE_STD_BUFSIZE;
  1459. rd->idx = idx;
  1460. idx = (idx + 1) % RX_STD_RING_ENTRIES;
  1461. }
  1462. if (!i)
  1463. goto error_out;
  1464. atomic_add(i, &ap->cur_rx_bufs);
  1465. ap->rx_std_skbprd = idx;
  1466. if (ACE_IS_TIGON_I(ap)) {
  1467. struct cmd cmd;
  1468. cmd.evt = C_SET_RX_PRD_IDX;
  1469. cmd.code = 0;
  1470. cmd.idx = ap->rx_std_skbprd;
  1471. ace_issue_cmd(regs, &cmd);
  1472. } else {
  1473. writel(idx, &regs->RxStdPrd);
  1474. wmb();
  1475. }
  1476. out:
  1477. clear_bit(0, &ap->std_refill_busy);
  1478. return;
  1479. error_out:
  1480. printk(KERN_INFO "Out of memory when allocating "
  1481. "standard receive buffers\n");
  1482. goto out;
  1483. }
  1484. static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
  1485. {
  1486. struct ace_regs __iomem *regs = ap->regs;
  1487. short i, idx;
  1488. prefetchw(&ap->cur_mini_bufs);
  1489. idx = ap->rx_mini_skbprd;
  1490. for (i = 0; i < nr_bufs; i++) {
  1491. struct sk_buff *skb;
  1492. struct rx_desc *rd;
  1493. dma_addr_t mapping;
  1494. skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
  1495. if (!skb)
  1496. break;
  1497. skb_reserve(skb, NET_IP_ALIGN);
  1498. mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
  1499. offset_in_page(skb->data),
  1500. ACE_MINI_BUFSIZE,
  1501. PCI_DMA_FROMDEVICE);
  1502. ap->skb->rx_mini_skbuff[idx].skb = skb;
  1503. pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
  1504. mapping, mapping);
  1505. rd = &ap->rx_mini_ring[idx];
  1506. set_aceaddr(&rd->addr, mapping);
  1507. rd->size = ACE_MINI_BUFSIZE;
  1508. rd->idx = idx;
  1509. idx = (idx + 1) % RX_MINI_RING_ENTRIES;
  1510. }
  1511. if (!i)
  1512. goto error_out;
  1513. atomic_add(i, &ap->cur_mini_bufs);
  1514. ap->rx_mini_skbprd = idx;
  1515. writel(idx, &regs->RxMiniPrd);
  1516. wmb();
  1517. out:
  1518. clear_bit(0, &ap->mini_refill_busy);
  1519. return;
  1520. error_out:
  1521. printk(KERN_INFO "Out of memory when allocating "
  1522. "mini receive buffers\n");
  1523. goto out;
  1524. }
  1525. /*
  1526. * Load the jumbo rx ring, this may happen at any time if the MTU
  1527. * is changed to a value > 1500.
  1528. */
  1529. static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
  1530. {
  1531. struct ace_regs __iomem *regs = ap->regs;
  1532. short i, idx;
  1533. idx = ap->rx_jumbo_skbprd;
  1534. for (i = 0; i < nr_bufs; i++) {
  1535. struct sk_buff *skb;
  1536. struct rx_desc *rd;
  1537. dma_addr_t mapping;
  1538. skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
  1539. if (!skb)
  1540. break;
  1541. skb_reserve(skb, NET_IP_ALIGN);
  1542. mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
  1543. offset_in_page(skb->data),
  1544. ACE_JUMBO_BUFSIZE,
  1545. PCI_DMA_FROMDEVICE);
  1546. ap->skb->rx_jumbo_skbuff[idx].skb = skb;
  1547. pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
  1548. mapping, mapping);
  1549. rd = &ap->rx_jumbo_ring[idx];
  1550. set_aceaddr(&rd->addr, mapping);
  1551. rd->size = ACE_JUMBO_BUFSIZE;
  1552. rd->idx = idx;
  1553. idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
  1554. }
  1555. if (!i)
  1556. goto error_out;
  1557. atomic_add(i, &ap->cur_jumbo_bufs);
  1558. ap->rx_jumbo_skbprd = idx;
  1559. if (ACE_IS_TIGON_I(ap)) {
  1560. struct cmd cmd;
  1561. cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
  1562. cmd.code = 0;
  1563. cmd.idx = ap->rx_jumbo_skbprd;
  1564. ace_issue_cmd(regs, &cmd);
  1565. } else {
  1566. writel(idx, &regs->RxJumboPrd);
  1567. wmb();
  1568. }
  1569. out:
  1570. clear_bit(0, &ap->jumbo_refill_busy);
  1571. return;
  1572. error_out:
  1573. if (net_ratelimit())
  1574. printk(KERN_INFO "Out of memory when allocating "
  1575. "jumbo receive buffers\n");
  1576. goto out;
  1577. }
  1578. /*
  1579. * All events are considered to be slow (RX/TX ints do not generate
  1580. * events) and are handled here, outside the main interrupt handler,
  1581. * to reduce the size of the handler.
  1582. */
  1583. static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
  1584. {
  1585. struct ace_private *ap;
  1586. ap = netdev_priv(dev);
  1587. while (evtcsm != evtprd) {
  1588. switch (ap->evt_ring[evtcsm].evt) {
  1589. case E_FW_RUNNING:
  1590. printk(KERN_INFO "%s: Firmware up and running\n",
  1591. ap->name);
  1592. ap->fw_running = 1;
  1593. wmb();
  1594. break;
  1595. case E_STATS_UPDATED:
  1596. break;
  1597. case E_LNK_STATE:
  1598. {
  1599. u16 code = ap->evt_ring[evtcsm].code;
  1600. switch (code) {
  1601. case E_C_LINK_UP:
  1602. {
  1603. u32 state = readl(&ap->regs->GigLnkState);
  1604. printk(KERN_WARNING "%s: Optical link UP "
  1605. "(%s Duplex, Flow Control: %s%s)\n",
  1606. ap->name,
  1607. state & LNK_FULL_DUPLEX ? "Full":"Half",
  1608. state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
  1609. state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
  1610. break;
  1611. }
  1612. case E_C_LINK_DOWN:
  1613. printk(KERN_WARNING "%s: Optical link DOWN\n",
  1614. ap->name);
  1615. break;
  1616. case E_C_LINK_10_100:
  1617. printk(KERN_WARNING "%s: 10/100BaseT link "
  1618. "UP\n", ap->name);
  1619. break;
  1620. default:
  1621. printk(KERN_ERR "%s: Unknown optical link "
  1622. "state %02x\n", ap->name, code);
  1623. }
  1624. break;
  1625. }
  1626. case E_ERROR:
  1627. switch(ap->evt_ring[evtcsm].code) {
  1628. case E_C_ERR_INVAL_CMD:
  1629. printk(KERN_ERR "%s: invalid command error\n",
  1630. ap->name);
  1631. break;
  1632. case E_C_ERR_UNIMP_CMD:
  1633. printk(KERN_ERR "%s: unimplemented command "
  1634. "error\n", ap->name);
  1635. break;
  1636. case E_C_ERR_BAD_CFG:
  1637. printk(KERN_ERR "%s: bad config error\n",
  1638. ap->name);
  1639. break;
  1640. default:
  1641. printk(KERN_ERR "%s: unknown error %02x\n",
  1642. ap->name, ap->evt_ring[evtcsm].code);
  1643. }
  1644. break;
  1645. case E_RESET_JUMBO_RNG:
  1646. {
  1647. int i;
  1648. for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
  1649. if (ap->skb->rx_jumbo_skbuff[i].skb) {
  1650. ap->rx_jumbo_ring[i].size = 0;
  1651. set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
  1652. dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
  1653. ap->skb->rx_jumbo_skbuff[i].skb = NULL;
  1654. }
  1655. }
  1656. if (ACE_IS_TIGON_I(ap)) {
  1657. struct cmd cmd;
  1658. cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
  1659. cmd.code = 0;
  1660. cmd.idx = 0;
  1661. ace_issue_cmd(ap->regs, &cmd);
  1662. } else {
  1663. writel(0, &((ap->regs)->RxJumboPrd));
  1664. wmb();
  1665. }
  1666. ap->jumbo = 0;
  1667. ap->rx_jumbo_skbprd = 0;
  1668. printk(KERN_INFO "%s: Jumbo ring flushed\n",
  1669. ap->name);
  1670. clear_bit(0, &ap->jumbo_refill_busy);
  1671. break;
  1672. }
  1673. default:
  1674. printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
  1675. ap->name, ap->evt_ring[evtcsm].evt);
  1676. }
  1677. evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
  1678. }
  1679. return evtcsm;
  1680. }
  1681. static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
  1682. {
  1683. struct ace_private *ap = netdev_priv(dev);
  1684. u32 idx;
  1685. int mini_count = 0, std_count = 0;
  1686. idx = rxretcsm;
  1687. prefetchw(&ap->cur_rx_bufs);
  1688. prefetchw(&ap->cur_mini_bufs);
  1689. while (idx != rxretprd) {
  1690. struct ring_info *rip;
  1691. struct sk_buff *skb;
  1692. struct rx_desc *rxdesc, *retdesc;
  1693. u32 skbidx;
  1694. int bd_flags, desc_type, mapsize;
  1695. u16 csum;
  1696. /* make sure the rx descriptor isn't read before rxretprd */
  1697. if (idx == rxretcsm)
  1698. rmb();
  1699. retdesc = &ap->rx_return_ring[idx];
  1700. skbidx = retdesc->idx;
  1701. bd_flags = retdesc->flags;
  1702. desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
  1703. switch(desc_type) {
  1704. /*
  1705. * Normal frames do not have any flags set
  1706. *
  1707. * Mini and normal frames arrive frequently,
  1708. * so use a local counter to avoid doing
  1709. * atomic operations for each packet arriving.
  1710. */
  1711. case 0:
  1712. rip = &ap->skb->rx_std_skbuff[skbidx];
  1713. mapsize = ACE_STD_BUFSIZE;
  1714. rxdesc = &ap->rx_std_ring[skbidx];
  1715. std_count++;
  1716. break;
  1717. case BD_FLG_JUMBO:
  1718. rip = &ap->skb->rx_jumbo_skbuff[skbidx];
  1719. mapsize = ACE_JUMBO_BUFSIZE;
  1720. rxdesc = &ap->rx_jumbo_ring[skbidx];
  1721. atomic_dec(&ap->cur_jumbo_bufs);
  1722. break;
  1723. case BD_FLG_MINI:
  1724. rip = &ap->skb->rx_mini_skbuff[skbidx];
  1725. mapsize = ACE_MINI_BUFSIZE;
  1726. rxdesc = &ap->rx_mini_ring[skbidx];
  1727. mini_count++;
  1728. break;
  1729. default:
  1730. printk(KERN_INFO "%s: unknown frame type (0x%02x) "
  1731. "returned by NIC\n", dev->name,
  1732. retdesc->flags);
  1733. goto error;
  1734. }
  1735. skb = rip->skb;
  1736. rip->skb = NULL;
  1737. pci_unmap_page(ap->pdev,
  1738. pci_unmap_addr(rip, mapping),
  1739. mapsize,
  1740. PCI_DMA_FROMDEVICE);
  1741. skb_put(skb, retdesc->size);
  1742. /*
  1743. * Fly baby, fly!
  1744. */
  1745. csum = retdesc->tcp_udp_csum;
  1746. skb->protocol = eth_type_trans(skb, dev);
  1747. /*
  1748. * Instead of forcing the poor tigon mips cpu to calculate
  1749. * pseudo hdr checksum, we do this ourselves.
  1750. */
  1751. if (bd_flags & BD_FLG_TCP_UDP_SUM) {
  1752. skb->csum = htons(csum);
  1753. skb->ip_summed = CHECKSUM_COMPLETE;
  1754. } else {
  1755. skb->ip_summed = CHECKSUM_NONE;
  1756. }
  1757. /* send it up */
  1758. #if ACENIC_DO_VLAN
  1759. if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
  1760. vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
  1761. } else
  1762. #endif
  1763. netif_rx(skb);
  1764. dev->last_rx = jiffies;
  1765. dev->stats.rx_packets++;
  1766. dev->stats.rx_bytes += retdesc->size;
  1767. idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
  1768. }
  1769. atomic_sub(std_count, &ap->cur_rx_bufs);
  1770. if (!ACE_IS_TIGON_I(ap))
  1771. atomic_sub(mini_count, &ap->cur_mini_bufs);
  1772. out:
  1773. /*
  1774. * According to the documentation RxRetCsm is obsolete with
  1775. * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
  1776. */
  1777. if (ACE_IS_TIGON_I(ap)) {
  1778. writel(idx, &ap->regs->RxRetCsm);
  1779. }
  1780. ap->cur_rx = idx;
  1781. return;
  1782. error:
  1783. idx = rxretprd;
  1784. goto out;
  1785. }
  1786. static inline void ace_tx_int(struct net_device *dev,
  1787. u32 txcsm, u32 idx)
  1788. {
  1789. struct ace_private *ap = netdev_priv(dev);
  1790. do {
  1791. struct sk_buff *skb;
  1792. dma_addr_t mapping;
  1793. struct tx_ring_info *info;
  1794. info = ap->skb->tx_skbuff + idx;
  1795. skb = info->skb;
  1796. mapping = pci_unmap_addr(info, mapping);
  1797. if (mapping) {
  1798. pci_unmap_page(ap->pdev, mapping,
  1799. pci_unmap_len(info, maplen),
  1800. PCI_DMA_TODEVICE);
  1801. pci_unmap_addr_set(info, mapping, 0);
  1802. }
  1803. if (skb) {
  1804. dev->stats.tx_packets++;
  1805. dev->stats.tx_bytes += skb->len;
  1806. dev_kfree_skb_irq(skb);
  1807. info->skb = NULL;
  1808. }
  1809. idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
  1810. } while (idx != txcsm);
  1811. if (netif_queue_stopped(dev))
  1812. netif_wake_queue(dev);
  1813. wmb();
  1814. ap->tx_ret_csm = txcsm;
  1815. /* So... tx_ret_csm is advanced _after_ check for device wakeup.
  1816. *
  1817. * We could try to make it before. In this case we would get
  1818. * the following race condition: hard_start_xmit on other cpu
  1819. * enters after we advanced tx_ret_csm and fills space,
  1820. * which we have just freed, so that we make illegal device wakeup.
  1821. * There is no good way to workaround this (at entry
  1822. * to ace_start_xmit detects this condition and prevents
  1823. * ring corruption, but it is not a good workaround.)
  1824. *
  1825. * When tx_ret_csm is advanced after, we wake up device _only_
  1826. * if we really have some space in ring (though the core doing
  1827. * hard_start_xmit can see full ring for some period and has to
  1828. * synchronize.) Superb.
  1829. * BUT! We get another subtle race condition. hard_start_xmit
  1830. * may think that ring is full between wakeup and advancing
  1831. * tx_ret_csm and will stop device instantly! It is not so bad.
  1832. * We are guaranteed that there is something in ring, so that
  1833. * the next irq will resume transmission. To speedup this we could
  1834. * mark descriptor, which closes ring with BD_FLG_COAL_NOW
  1835. * (see ace_start_xmit).
  1836. *
  1837. * Well, this dilemma exists in all lock-free devices.
  1838. * We, following scheme used in drivers by Donald Becker,
  1839. * select the least dangerous.
  1840. * --ANK
  1841. */
  1842. }
  1843. static irqreturn_t ace_interrupt(int irq, void *dev_id)
  1844. {
  1845. struct net_device *dev = (struct net_device *)dev_id;
  1846. struct ace_private *ap = netdev_priv(dev);
  1847. struct ace_regs __iomem *regs = ap->regs;
  1848. u32 idx;
  1849. u32 txcsm, rxretcsm, rxretprd;
  1850. u32 evtcsm, evtprd;
  1851. /*
  1852. * In case of PCI shared interrupts or spurious interrupts,
  1853. * we want to make sure it is actually our interrupt before
  1854. * spending any time in here.
  1855. */
  1856. if (!(readl(&regs->HostCtrl) & IN_INT))
  1857. return IRQ_NONE;
  1858. /*
  1859. * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
  1860. * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
  1861. * writel(0, &regs->Mb0Lo).
  1862. *
  1863. * "IRQ avoidance" recommended in docs applies to IRQs served
  1864. * threads and it is wrong even for that case.
  1865. */
  1866. writel(0, &regs->Mb0Lo);
  1867. readl(&regs->Mb0Lo);
  1868. /*
  1869. * There is no conflict between transmit handling in
  1870. * start_xmit and receive processing, thus there is no reason
  1871. * to take a spin lock for RX handling. Wait until we start
  1872. * working on the other stuff - hey we don't need a spin lock
  1873. * anymore.
  1874. */
  1875. rxretprd = *ap->rx_ret_prd;
  1876. rxretcsm = ap->cur_rx;
  1877. if (rxretprd != rxretcsm)
  1878. ace_rx_int(dev, rxretprd, rxretcsm);
  1879. txcsm = *ap->tx_csm;
  1880. idx = ap->tx_ret_csm;
  1881. if (txcsm != idx) {
  1882. /*
  1883. * If each skb takes only one descriptor this check degenerates
  1884. * to identity, because new space has just been opened.
  1885. * But if skbs are fragmented we must check that this index
  1886. * update releases enough of space, otherwise we just
  1887. * wait for device to make more work.
  1888. */
  1889. if (!tx_ring_full(ap, txcsm, ap->tx_prd))
  1890. ace_tx_int(dev, txcsm, idx);
  1891. }
  1892. evtcsm = readl(&regs->EvtCsm);
  1893. evtprd = *ap->evt_prd;
  1894. if (evtcsm != evtprd) {
  1895. evtcsm = ace_handle_event(dev, evtcsm, evtprd);
  1896. writel(evtcsm, &regs->EvtCsm);
  1897. }
  1898. /*
  1899. * This has to go last in the interrupt handler and run with
  1900. * the spin lock released ... what lock?
  1901. */
  1902. if (netif_running(dev)) {
  1903. int cur_size;
  1904. int run_tasklet = 0;
  1905. cur_size = atomic_read(&ap->cur_rx_bufs);
  1906. if (cur_size < RX_LOW_STD_THRES) {
  1907. if ((cur_size < RX_PANIC_STD_THRES) &&
  1908. !test_and_set_bit(0, &ap->std_refill_busy)) {
  1909. #ifdef DEBUG
  1910. printk("low on std buffers %i\n", cur_size);
  1911. #endif
  1912. ace_load_std_rx_ring(ap,
  1913. RX_RING_SIZE - cur_size);
  1914. } else
  1915. run_tasklet = 1;
  1916. }
  1917. if (!ACE_IS_TIGON_I(ap)) {
  1918. cur_size = atomic_read(&ap->cur_mini_bufs);
  1919. if (cur_size < RX_LOW_MINI_THRES) {
  1920. if ((cur_size < RX_PANIC_MINI_THRES) &&
  1921. !test_and_set_bit(0,
  1922. &ap->mini_refill_busy)) {
  1923. #ifdef DEBUG
  1924. printk("low on mini buffers %i\n",
  1925. cur_size);
  1926. #endif
  1927. ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
  1928. } else
  1929. run_tasklet = 1;
  1930. }
  1931. }
  1932. if (ap->jumbo) {
  1933. cur_size = atomic_read(&ap->cur_jumbo_bufs);
  1934. if (cur_size < RX_LOW_JUMBO_THRES) {
  1935. if ((cur_size < RX_PANIC_JUMBO_THRES) &&
  1936. !test_and_set_bit(0,
  1937. &ap->jumbo_refill_busy)){
  1938. #ifdef DEBUG
  1939. printk("low on jumbo buffers %i\n",
  1940. cur_size);
  1941. #endif
  1942. ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
  1943. } else
  1944. run_tasklet = 1;
  1945. }
  1946. }
  1947. if (run_tasklet && !ap->tasklet_pending) {
  1948. ap->tasklet_pending = 1;
  1949. tasklet_schedule(&ap->ace_tasklet);
  1950. }
  1951. }
  1952. return IRQ_HANDLED;
  1953. }
  1954. #if ACENIC_DO_VLAN
  1955. static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  1956. {
  1957. struct ace_private *ap = netdev_priv(dev);
  1958. unsigned long flags;
  1959. local_irq_save(flags);
  1960. ace_mask_irq(dev);
  1961. ap->vlgrp = grp;
  1962. ace_unmask_irq(dev);
  1963. local_irq_restore(flags);
  1964. }
  1965. #endif /* ACENIC_DO_VLAN */
  1966. static int ace_open(struct net_device *dev)
  1967. {
  1968. struct ace_private *ap = netdev_priv(dev);
  1969. struct ace_regs __iomem *regs = ap->regs;
  1970. struct cmd cmd;
  1971. if (!(ap->fw_running)) {
  1972. printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
  1973. return -EBUSY;
  1974. }
  1975. writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
  1976. cmd.evt = C_CLEAR_STATS;
  1977. cmd.code = 0;
  1978. cmd.idx = 0;
  1979. ace_issue_cmd(regs, &cmd);
  1980. cmd.evt = C_HOST_STATE;
  1981. cmd.code = C_C_STACK_UP;
  1982. cmd.idx = 0;
  1983. ace_issue_cmd(regs, &cmd);
  1984. if (ap->jumbo &&
  1985. !test_and_set_bit(0, &ap->jumbo_refill_busy))
  1986. ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
  1987. if (dev->flags & IFF_PROMISC) {
  1988. cmd.evt = C_SET_PROMISC_MODE;
  1989. cmd.code = C_C_PROMISC_ENABLE;
  1990. cmd.idx = 0;
  1991. ace_issue_cmd(regs, &cmd);
  1992. ap->promisc = 1;
  1993. }else
  1994. ap->promisc = 0;
  1995. ap->mcast_all = 0;
  1996. #if 0
  1997. cmd.evt = C_LNK_NEGOTIATION;
  1998. cmd.code = 0;
  1999. cmd.idx = 0;
  2000. ace_issue_cmd(regs, &cmd);
  2001. #endif
  2002. netif_start_queue(dev);
  2003. /*
  2004. * Setup the bottom half rx ring refill handler
  2005. */
  2006. tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
  2007. return 0;
  2008. }
  2009. static int ace_close(struct net_device *dev)
  2010. {
  2011. struct ace_private *ap = netdev_priv(dev);
  2012. struct ace_regs __iomem *regs = ap->regs;
  2013. struct cmd cmd;
  2014. unsigned long flags;
  2015. short i;
  2016. /*
  2017. * Without (or before) releasing irq and stopping hardware, this
  2018. * is an absolute non-sense, by the way. It will be reset instantly
  2019. * by the first irq.
  2020. */
  2021. netif_stop_queue(dev);
  2022. if (ap->promisc) {
  2023. cmd.evt = C_SET_PROMISC_MODE;
  2024. cmd.code = C_C_PROMISC_DISABLE;
  2025. cmd.idx = 0;
  2026. ace_issue_cmd(regs, &cmd);
  2027. ap->promisc = 0;
  2028. }
  2029. cmd.evt = C_HOST_STATE;
  2030. cmd.code = C_C_STACK_DOWN;
  2031. cmd.idx = 0;
  2032. ace_issue_cmd(regs, &cmd);
  2033. tasklet_kill(&ap->ace_tasklet);
  2034. /*
  2035. * Make sure one CPU is not processing packets while
  2036. * buffers are being released by another.
  2037. */
  2038. local_irq_save(flags);
  2039. ace_mask_irq(dev);
  2040. for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
  2041. struct sk_buff *skb;
  2042. dma_addr_t mapping;
  2043. struct tx_ring_info *info;
  2044. info = ap->skb->tx_skbuff + i;
  2045. skb = info->skb;
  2046. mapping = pci_unmap_addr(info, mapping);
  2047. if (mapping) {
  2048. if (ACE_IS_TIGON_I(ap)) {
  2049. /* NB: TIGON_1 is special, tx_ring is in io space */
  2050. struct tx_desc __iomem *tx;
  2051. tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
  2052. writel(0, &tx->addr.addrhi);
  2053. writel(0, &tx->addr.addrlo);
  2054. writel(0, &tx->flagsize);
  2055. } else
  2056. memset(ap->tx_ring + i, 0,
  2057. sizeof(struct tx_desc));
  2058. pci_unmap_page(ap->pdev, mapping,
  2059. pci_unmap_len(info, maplen),
  2060. PCI_DMA_TODEVICE);
  2061. pci_unmap_addr_set(info, mapping, 0);
  2062. }
  2063. if (skb) {
  2064. dev_kfree_skb(skb);
  2065. info->skb = NULL;
  2066. }
  2067. }
  2068. if (ap->jumbo) {
  2069. cmd.evt = C_RESET_JUMBO_RNG;
  2070. cmd.code = 0;
  2071. cmd.idx = 0;
  2072. ace_issue_cmd(regs, &cmd);
  2073. }
  2074. ace_unmask_irq(dev);
  2075. local_irq_restore(flags);
  2076. return 0;
  2077. }
  2078. static inline dma_addr_t
  2079. ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
  2080. struct sk_buff *tail, u32 idx)
  2081. {
  2082. dma_addr_t mapping;
  2083. struct tx_ring_info *info;
  2084. mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
  2085. offset_in_page(skb->data),
  2086. skb->len, PCI_DMA_TODEVICE);
  2087. info = ap->skb->tx_skbuff + idx;
  2088. info->skb = tail;
  2089. pci_unmap_addr_set(info, mapping, mapping);
  2090. pci_unmap_len_set(info, maplen, skb->len);
  2091. return mapping;
  2092. }
  2093. static inline void
  2094. ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
  2095. u32 flagsize, u32 vlan_tag)
  2096. {
  2097. #if !USE_TX_COAL_NOW
  2098. flagsize &= ~BD_FLG_COAL_NOW;
  2099. #endif
  2100. if (ACE_IS_TIGON_I(ap)) {
  2101. struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
  2102. writel(addr >> 32, &io->addr.addrhi);
  2103. writel(addr & 0xffffffff, &io->addr.addrlo);
  2104. writel(flagsize, &io->flagsize);
  2105. #if ACENIC_DO_VLAN
  2106. writel(vlan_tag, &io->vlanres);
  2107. #endif
  2108. } else {
  2109. desc->addr.addrhi = addr >> 32;
  2110. desc->addr.addrlo = addr;
  2111. desc->flagsize = flagsize;
  2112. #if ACENIC_DO_VLAN
  2113. desc->vlanres = vlan_tag;
  2114. #endif
  2115. }
  2116. }
  2117. static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
  2118. {
  2119. struct ace_private *ap = netdev_priv(dev);
  2120. struct ace_regs __iomem *regs = ap->regs;
  2121. struct tx_desc *desc;
  2122. u32 idx, flagsize;
  2123. unsigned long maxjiff = jiffies + 3*HZ;
  2124. restart:
  2125. idx = ap->tx_prd;
  2126. if (tx_ring_full(ap, ap->tx_ret_csm, idx))
  2127. goto overflow;
  2128. if (!skb_shinfo(skb)->nr_frags) {
  2129. dma_addr_t mapping;
  2130. u32 vlan_tag = 0;
  2131. mapping = ace_map_tx_skb(ap, skb, skb, idx);
  2132. flagsize = (skb->len << 16) | (BD_FLG_END);
  2133. if (skb->ip_summed == CHECKSUM_PARTIAL)
  2134. flagsize |= BD_FLG_TCP_UDP_SUM;
  2135. #if ACENIC_DO_VLAN
  2136. if (vlan_tx_tag_present(skb)) {
  2137. flagsize |= BD_FLG_VLAN_TAG;
  2138. vlan_tag = vlan_tx_tag_get(skb);
  2139. }
  2140. #endif
  2141. desc = ap->tx_ring + idx;
  2142. idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
  2143. /* Look at ace_tx_int for explanations. */
  2144. if (tx_ring_full(ap, ap->tx_ret_csm, idx))
  2145. flagsize |= BD_FLG_COAL_NOW;
  2146. ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
  2147. } else {
  2148. dma_addr_t mapping;
  2149. u32 vlan_tag = 0;
  2150. int i, len = 0;
  2151. mapping = ace_map_tx_skb(ap, skb, NULL, idx);
  2152. flagsize = (skb_headlen(skb) << 16);
  2153. if (skb->ip_summed == CHECKSUM_PARTIAL)
  2154. flagsize |= BD_FLG_TCP_UDP_SUM;
  2155. #if ACENIC_DO_VLAN
  2156. if (vlan_tx_tag_present(skb)) {
  2157. flagsize |= BD_FLG_VLAN_TAG;
  2158. vlan_tag = vlan_tx_tag_get(skb);
  2159. }
  2160. #endif
  2161. ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
  2162. idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
  2163. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2164. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2165. struct tx_ring_info *info;
  2166. len += frag->size;
  2167. info = ap->skb->tx_skbuff + idx;
  2168. desc = ap->tx_ring + idx;
  2169. mapping = pci_map_page(ap->pdev, frag->page,
  2170. frag->page_offset, frag->size,
  2171. PCI_DMA_TODEVICE);
  2172. flagsize = (frag->size << 16);
  2173. if (skb->ip_summed == CHECKSUM_PARTIAL)
  2174. flagsize |= BD_FLG_TCP_UDP_SUM;
  2175. idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
  2176. if (i == skb_shinfo(skb)->nr_frags - 1) {
  2177. flagsize |= BD_FLG_END;
  2178. if (tx_ring_full(ap, ap->tx_ret_csm, idx))
  2179. flagsize |= BD_FLG_COAL_NOW;
  2180. /*
  2181. * Only the last fragment frees
  2182. * the skb!
  2183. */
  2184. info->skb = skb;
  2185. } else {
  2186. info->skb = NULL;
  2187. }
  2188. pci_unmap_addr_set(info, mapping, mapping);
  2189. pci_unmap_len_set(info, maplen, frag->size);
  2190. ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
  2191. }
  2192. }
  2193. wmb();
  2194. ap->tx_prd = idx;
  2195. ace_set_txprd(regs, ap, idx);
  2196. if (flagsize & BD_FLG_COAL_NOW) {
  2197. netif_stop_queue(dev);
  2198. /*
  2199. * A TX-descriptor producer (an IRQ) might have gotten
  2200. * inbetween, making the ring free again. Since xmit is
  2201. * serialized, this is the only situation we have to
  2202. * re-test.
  2203. */
  2204. if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
  2205. netif_wake_queue(dev);
  2206. }
  2207. dev->trans_start = jiffies;
  2208. return NETDEV_TX_OK;
  2209. overflow:
  2210. /*
  2211. * This race condition is unavoidable with lock-free drivers.
  2212. * We wake up the queue _before_ tx_prd is advanced, so that we can
  2213. * enter hard_start_xmit too early, while tx ring still looks closed.
  2214. * This happens ~1-4 times per 100000 packets, so that we can allow
  2215. * to loop syncing to other CPU. Probably, we need an additional
  2216. * wmb() in ace_tx_intr as well.
  2217. *
  2218. * Note that this race is relieved by reserving one more entry
  2219. * in tx ring than it is necessary (see original non-SG driver).
  2220. * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
  2221. * is already overkill.
  2222. *
  2223. * Alternative is to return with 1 not throttling queue. In this
  2224. * case loop becomes longer, no more useful effects.
  2225. */
  2226. if (time_before(jiffies, maxjiff)) {
  2227. barrier();
  2228. cpu_relax();
  2229. goto restart;
  2230. }
  2231. /* The ring is stuck full. */
  2232. printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
  2233. return NETDEV_TX_BUSY;
  2234. }
  2235. static int ace_change_mtu(struct net_device *dev, int new_mtu)
  2236. {
  2237. struct ace_private *ap = netdev_priv(dev);
  2238. struct ace_regs __iomem *regs = ap->regs;
  2239. if (new_mtu > ACE_JUMBO_MTU)
  2240. return -EINVAL;
  2241. writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
  2242. dev->mtu = new_mtu;
  2243. if (new_mtu > ACE_STD_MTU) {
  2244. if (!(ap->jumbo)) {
  2245. printk(KERN_INFO "%s: Enabling Jumbo frame "
  2246. "support\n", dev->name);
  2247. ap->jumbo = 1;
  2248. if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
  2249. ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
  2250. ace_set_rxtx_parms(dev, 1);
  2251. }
  2252. } else {
  2253. while (test_and_set_bit(0, &ap->jumbo_refill_busy));
  2254. ace_sync_irq(dev->irq);
  2255. ace_set_rxtx_parms(dev, 0);
  2256. if (ap->jumbo) {
  2257. struct cmd cmd;
  2258. cmd.evt = C_RESET_JUMBO_RNG;
  2259. cmd.code = 0;
  2260. cmd.idx = 0;
  2261. ace_issue_cmd(regs, &cmd);
  2262. }
  2263. }
  2264. return 0;
  2265. }
  2266. static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  2267. {
  2268. struct ace_private *ap = netdev_priv(dev);
  2269. struct ace_regs __iomem *regs = ap->regs;
  2270. u32 link;
  2271. memset(ecmd, 0, sizeof(struct ethtool_cmd));
  2272. ecmd->supported =
  2273. (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
  2274. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
  2275. SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
  2276. SUPPORTED_Autoneg | SUPPORTED_FIBRE);
  2277. ecmd->port = PORT_FIBRE;
  2278. ecmd->transceiver = XCVR_INTERNAL;
  2279. link = readl(&regs->GigLnkState);
  2280. if (link & LNK_1000MB)
  2281. ecmd->speed = SPEED_1000;
  2282. else {
  2283. link = readl(&regs->FastLnkState);
  2284. if (link & LNK_100MB)
  2285. ecmd->speed = SPEED_100;
  2286. else if (link & LNK_10MB)
  2287. ecmd->speed = SPEED_10;
  2288. else
  2289. ecmd->speed = 0;
  2290. }
  2291. if (link & LNK_FULL_DUPLEX)
  2292. ecmd->duplex = DUPLEX_FULL;
  2293. else
  2294. ecmd->duplex = DUPLEX_HALF;
  2295. if (link & LNK_NEGOTIATE)
  2296. ecmd->autoneg = AUTONEG_ENABLE;
  2297. else
  2298. ecmd->autoneg = AUTONEG_DISABLE;
  2299. #if 0
  2300. /*
  2301. * Current struct ethtool_cmd is insufficient
  2302. */
  2303. ecmd->trace = readl(&regs->TuneTrace);
  2304. ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
  2305. ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
  2306. #endif
  2307. ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
  2308. ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
  2309. return 0;
  2310. }
  2311. static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  2312. {
  2313. struct ace_private *ap = netdev_priv(dev);
  2314. struct ace_regs __iomem *regs = ap->regs;
  2315. u32 link, speed;
  2316. link = readl(&regs->GigLnkState);
  2317. if (link & LNK_1000MB)
  2318. speed = SPEED_1000;
  2319. else {
  2320. link = readl(&regs->FastLnkState);
  2321. if (link & LNK_100MB)
  2322. speed = SPEED_100;
  2323. else if (link & LNK_10MB)
  2324. speed = SPEED_10;
  2325. else
  2326. speed = SPEED_100;
  2327. }
  2328. link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
  2329. LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
  2330. if (!ACE_IS_TIGON_I(ap))
  2331. link |= LNK_TX_FLOW_CTL_Y;
  2332. if (ecmd->autoneg == AUTONEG_ENABLE)
  2333. link |= LNK_NEGOTIATE;
  2334. if (ecmd->speed != speed) {
  2335. link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
  2336. switch (speed) {
  2337. case SPEED_1000:
  2338. link |= LNK_1000MB;
  2339. break;
  2340. case SPEED_100:
  2341. link |= LNK_100MB;
  2342. break;
  2343. case SPEED_10:
  2344. link |= LNK_10MB;
  2345. break;
  2346. }
  2347. }
  2348. if (ecmd->duplex == DUPLEX_FULL)
  2349. link |= LNK_FULL_DUPLEX;
  2350. if (link != ap->link) {
  2351. struct cmd cmd;
  2352. printk(KERN_INFO "%s: Renegotiating link state\n",
  2353. dev->name);
  2354. ap->link = link;
  2355. writel(link, &regs->TuneLink);
  2356. if (!ACE_IS_TIGON_I(ap))
  2357. writel(link, &regs->TuneFastLink);
  2358. wmb();
  2359. cmd.evt = C_LNK_NEGOTIATION;
  2360. cmd.code = 0;
  2361. cmd.idx = 0;
  2362. ace_issue_cmd(regs, &cmd);
  2363. }
  2364. return 0;
  2365. }
  2366. static void ace_get_drvinfo(struct net_device *dev,
  2367. struct ethtool_drvinfo *info)
  2368. {
  2369. struct ace_private *ap = netdev_priv(dev);
  2370. strlcpy(info->driver, "acenic", sizeof(info->driver));
  2371. snprintf(info->version, sizeof(info->version), "%i.%i.%i",
  2372. tigonFwReleaseMajor, tigonFwReleaseMinor,
  2373. tigonFwReleaseFix);
  2374. if (ap->pdev)
  2375. strlcpy(info->bus_info, pci_name(ap->pdev),
  2376. sizeof(info->bus_info));
  2377. }
  2378. /*
  2379. * Set the hardware MAC address.
  2380. */
  2381. static int ace_set_mac_addr(struct net_device *dev, void *p)
  2382. {
  2383. struct ace_private *ap = netdev_priv(dev);
  2384. struct ace_regs __iomem *regs = ap->regs;
  2385. struct sockaddr *addr=p;
  2386. u8 *da;
  2387. struct cmd cmd;
  2388. if(netif_running(dev))
  2389. return -EBUSY;
  2390. memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
  2391. da = (u8 *)dev->dev_addr;
  2392. writel(da[0] << 8 | da[1], &regs->MacAddrHi);
  2393. writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
  2394. &regs->MacAddrLo);
  2395. cmd.evt = C_SET_MAC_ADDR;
  2396. cmd.code = 0;
  2397. cmd.idx = 0;
  2398. ace_issue_cmd(regs, &cmd);
  2399. return 0;
  2400. }
  2401. static void ace_set_multicast_list(struct net_device *dev)
  2402. {
  2403. struct ace_private *ap = netdev_priv(dev);
  2404. struct ace_regs __iomem *regs = ap->regs;
  2405. struct cmd cmd;
  2406. if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
  2407. cmd.evt = C_SET_MULTICAST_MODE;
  2408. cmd.code = C_C_MCAST_ENABLE;
  2409. cmd.idx = 0;
  2410. ace_issue_cmd(regs, &cmd);
  2411. ap->mcast_all = 1;
  2412. } else if (ap->mcast_all) {
  2413. cmd.evt = C_SET_MULTICAST_MODE;
  2414. cmd.code = C_C_MCAST_DISABLE;
  2415. cmd.idx = 0;
  2416. ace_issue_cmd(regs, &cmd);
  2417. ap->mcast_all = 0;
  2418. }
  2419. if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
  2420. cmd.evt = C_SET_PROMISC_MODE;
  2421. cmd.code = C_C_PROMISC_ENABLE;
  2422. cmd.idx = 0;
  2423. ace_issue_cmd(regs, &cmd);
  2424. ap->promisc = 1;
  2425. }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
  2426. cmd.evt = C_SET_PROMISC_MODE;
  2427. cmd.code = C_C_PROMISC_DISABLE;
  2428. cmd.idx = 0;
  2429. ace_issue_cmd(regs, &cmd);
  2430. ap->promisc = 0;
  2431. }
  2432. /*
  2433. * For the time being multicast relies on the upper layers
  2434. * filtering it properly. The Firmware does not allow one to
  2435. * set the entire multicast list at a time and keeping track of
  2436. * it here is going to be messy.
  2437. */
  2438. if ((dev->mc_count) && !(ap->mcast_all)) {
  2439. cmd.evt = C_SET_MULTICAST_MODE;
  2440. cmd.code = C_C_MCAST_ENABLE;
  2441. cmd.idx = 0;
  2442. ace_issue_cmd(regs, &cmd);
  2443. }else if (!ap->mcast_all) {
  2444. cmd.evt = C_SET_MULTICAST_MODE;
  2445. cmd.code = C_C_MCAST_DISABLE;
  2446. cmd.idx = 0;
  2447. ace_issue_cmd(regs, &cmd);
  2448. }
  2449. }
  2450. static struct net_device_stats *ace_get_stats(struct net_device *dev)
  2451. {
  2452. struct ace_private *ap = netdev_priv(dev);
  2453. struct ace_mac_stats __iomem *mac_stats =
  2454. (struct ace_mac_stats __iomem *)ap->regs->Stats;
  2455. dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
  2456. dev->stats.multicast = readl(&mac_stats->kept_mc);
  2457. dev->stats.collisions = readl(&mac_stats->coll);
  2458. return &dev->stats;
  2459. }
  2460. static void __devinit ace_copy(struct ace_regs __iomem *regs, void *src,
  2461. u32 dest, int size)
  2462. {
  2463. void __iomem *tdest;
  2464. u32 *wsrc;
  2465. short tsize, i;
  2466. if (size <= 0)
  2467. return;
  2468. while (size > 0) {
  2469. tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
  2470. min_t(u32, size, ACE_WINDOW_SIZE));
  2471. tdest = (void __iomem *) &regs->Window +
  2472. (dest & (ACE_WINDOW_SIZE - 1));
  2473. writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
  2474. /*
  2475. * This requires byte swapping on big endian, however
  2476. * writel does that for us
  2477. */
  2478. wsrc = src;
  2479. for (i = 0; i < (tsize / 4); i++) {
  2480. writel(wsrc[i], tdest + i*4);
  2481. }
  2482. dest += tsize;
  2483. src += tsize;
  2484. size -= tsize;
  2485. }
  2486. return;
  2487. }
  2488. static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
  2489. {
  2490. void __iomem *tdest;
  2491. short tsize = 0, i;
  2492. if (size <= 0)
  2493. return;
  2494. while (size > 0) {
  2495. tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
  2496. min_t(u32, size, ACE_WINDOW_SIZE));
  2497. tdest = (void __iomem *) &regs->Window +
  2498. (dest & (ACE_WINDOW_SIZE - 1));
  2499. writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
  2500. for (i = 0; i < (tsize / 4); i++) {
  2501. writel(0, tdest + i*4);
  2502. }
  2503. dest += tsize;
  2504. size -= tsize;
  2505. }
  2506. return;
  2507. }
  2508. /*
  2509. * Download the firmware into the SRAM on the NIC
  2510. *
  2511. * This operation requires the NIC to be halted and is performed with
  2512. * interrupts disabled and with the spinlock hold.
  2513. */
  2514. static int __devinit ace_load_firmware(struct net_device *dev)
  2515. {
  2516. struct ace_private *ap = netdev_priv(dev);
  2517. struct ace_regs __iomem *regs = ap->regs;
  2518. if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
  2519. printk(KERN_ERR "%s: trying to download firmware while the "
  2520. "CPU is running!\n", ap->name);
  2521. return -EFAULT;
  2522. }
  2523. /*
  2524. * Do not try to clear more than 512KB or we end up seeing
  2525. * funny things on NICs with only 512KB SRAM
  2526. */
  2527. ace_clear(regs, 0x2000, 0x80000-0x2000);
  2528. if (ACE_IS_TIGON_I(ap)) {
  2529. ace_copy(regs, tigonFwText, tigonFwTextAddr, tigonFwTextLen);
  2530. ace_copy(regs, tigonFwData, tigonFwDataAddr, tigonFwDataLen);
  2531. ace_copy(regs, tigonFwRodata, tigonFwRodataAddr,
  2532. tigonFwRodataLen);
  2533. ace_clear(regs, tigonFwBssAddr, tigonFwBssLen);
  2534. ace_clear(regs, tigonFwSbssAddr, tigonFwSbssLen);
  2535. }else if (ap->version == 2) {
  2536. ace_clear(regs, tigon2FwBssAddr, tigon2FwBssLen);
  2537. ace_clear(regs, tigon2FwSbssAddr, tigon2FwSbssLen);
  2538. ace_copy(regs, tigon2FwText, tigon2FwTextAddr,tigon2FwTextLen);
  2539. ace_copy(regs, tigon2FwRodata, tigon2FwRodataAddr,
  2540. tigon2FwRodataLen);
  2541. ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen);
  2542. }
  2543. return 0;
  2544. }
  2545. /*
  2546. * The eeprom on the AceNIC is an Atmel i2c EEPROM.
  2547. *
  2548. * Accessing the EEPROM is `interesting' to say the least - don't read
  2549. * this code right after dinner.
  2550. *
  2551. * This is all about black magic and bit-banging the device .... I
  2552. * wonder in what hospital they have put the guy who designed the i2c
  2553. * specs.
  2554. *
  2555. * Oh yes, this is only the beginning!
  2556. *
  2557. * Thanks to Stevarino Webinski for helping tracking down the bugs in the
  2558. * code i2c readout code by beta testing all my hacks.
  2559. */
  2560. static void __devinit eeprom_start(struct ace_regs __iomem *regs)
  2561. {
  2562. u32 local;
  2563. readl(&regs->LocalCtrl);
  2564. udelay(ACE_SHORT_DELAY);
  2565. local = readl(&regs->LocalCtrl);
  2566. local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
  2567. writel(local, &regs->LocalCtrl);
  2568. readl(&regs->LocalCtrl);
  2569. mb();
  2570. udelay(ACE_SHORT_DELAY);
  2571. local |= EEPROM_CLK_OUT;
  2572. writel(local, &regs->LocalCtrl);
  2573. readl(&regs->LocalCtrl);
  2574. mb();
  2575. udelay(ACE_SHORT_DELAY);
  2576. local &= ~EEPROM_DATA_OUT;
  2577. writel(local, &regs->LocalCtrl);
  2578. readl(&regs->LocalCtrl);
  2579. mb();
  2580. udelay(ACE_SHORT_DELAY);
  2581. local &= ~EEPROM_CLK_OUT;
  2582. writel(local, &regs->LocalCtrl);
  2583. readl(&regs->LocalCtrl);
  2584. mb();
  2585. }
  2586. static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
  2587. {
  2588. short i;
  2589. u32 local;
  2590. udelay(ACE_SHORT_DELAY);
  2591. local = readl(&regs->LocalCtrl);
  2592. local &= ~EEPROM_DATA_OUT;
  2593. local |= EEPROM_WRITE_ENABLE;
  2594. writel(local, &regs->LocalCtrl);
  2595. readl(&regs->LocalCtrl);
  2596. mb();
  2597. for (i = 0; i < 8; i++, magic <<= 1) {
  2598. udelay(ACE_SHORT_DELAY);
  2599. if (magic & 0x80)
  2600. local |= EEPROM_DATA_OUT;
  2601. else
  2602. local &= ~EEPROM_DATA_OUT;
  2603. writel(local, &regs->LocalCtrl);
  2604. readl(&regs->LocalCtrl);
  2605. mb();
  2606. udelay(ACE_SHORT_DELAY);
  2607. local |= EEPROM_CLK_OUT;
  2608. writel(local, &regs->LocalCtrl);
  2609. readl(&regs->LocalCtrl);
  2610. mb();
  2611. udelay(ACE_SHORT_DELAY);
  2612. local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
  2613. writel(local, &regs->LocalCtrl);
  2614. readl(&regs->LocalCtrl);
  2615. mb();
  2616. }
  2617. }
  2618. static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
  2619. {
  2620. int state;
  2621. u32 local;
  2622. local = readl(&regs->LocalCtrl);
  2623. local &= ~EEPROM_WRITE_ENABLE;
  2624. writel(local, &regs->LocalCtrl);
  2625. readl(&regs->LocalCtrl);
  2626. mb();
  2627. udelay(ACE_LONG_DELAY);
  2628. local |= EEPROM_CLK_OUT;
  2629. writel(local, &regs->LocalCtrl);
  2630. readl(&regs->LocalCtrl);
  2631. mb();
  2632. udelay(ACE_SHORT_DELAY);
  2633. /* sample data in middle of high clk */
  2634. state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
  2635. udelay(ACE_SHORT_DELAY);
  2636. mb();
  2637. writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
  2638. readl(&regs->LocalCtrl);
  2639. mb();
  2640. return state;
  2641. }
  2642. static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
  2643. {
  2644. u32 local;
  2645. udelay(ACE_SHORT_DELAY);
  2646. local = readl(&regs->LocalCtrl);
  2647. local |= EEPROM_WRITE_ENABLE;
  2648. writel(local, &regs->LocalCtrl);
  2649. readl(&regs->LocalCtrl);
  2650. mb();
  2651. udelay(ACE_SHORT_DELAY);
  2652. local &= ~EEPROM_DATA_OUT;
  2653. writel(local, &regs->LocalCtrl);
  2654. readl(&regs->LocalCtrl);
  2655. mb();
  2656. udelay(ACE_SHORT_DELAY);
  2657. local |= EEPROM_CLK_OUT;
  2658. writel(local, &regs->LocalCtrl);
  2659. readl(&regs->LocalCtrl);
  2660. mb();
  2661. udelay(ACE_SHORT_DELAY);
  2662. local |= EEPROM_DATA_OUT;
  2663. writel(local, &regs->LocalCtrl);
  2664. readl(&regs->LocalCtrl);
  2665. mb();
  2666. udelay(ACE_LONG_DELAY);
  2667. local &= ~EEPROM_CLK_OUT;
  2668. writel(local, &regs->LocalCtrl);
  2669. mb();
  2670. }
  2671. /*
  2672. * Read a whole byte from the EEPROM.
  2673. */
  2674. static int __devinit read_eeprom_byte(struct net_device *dev,
  2675. unsigned long offset)
  2676. {
  2677. struct ace_private *ap = netdev_priv(dev);
  2678. struct ace_regs __iomem *regs = ap->regs;
  2679. unsigned long flags;
  2680. u32 local;
  2681. int result = 0;
  2682. short i;
  2683. /*
  2684. * Don't take interrupts on this CPU will bit banging
  2685. * the %#%#@$ I2C device
  2686. */
  2687. local_irq_save(flags);
  2688. eeprom_start(regs);
  2689. eeprom_prep(regs, EEPROM_WRITE_SELECT);
  2690. if (eeprom_check_ack(regs)) {
  2691. local_irq_restore(flags);
  2692. printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
  2693. result = -EIO;
  2694. goto eeprom_read_error;
  2695. }
  2696. eeprom_prep(regs, (offset >> 8) & 0xff);
  2697. if (eeprom_check_ack(regs)) {
  2698. local_irq_restore(flags);
  2699. printk(KERN_ERR "%s: Unable to set address byte 0\n",
  2700. ap->name);
  2701. result = -EIO;
  2702. goto eeprom_read_error;
  2703. }
  2704. eeprom_prep(regs, offset & 0xff);
  2705. if (eeprom_check_ack(regs)) {
  2706. local_irq_restore(flags);
  2707. printk(KERN_ERR "%s: Unable to set address byte 1\n",
  2708. ap->name);
  2709. result = -EIO;
  2710. goto eeprom_read_error;
  2711. }
  2712. eeprom_start(regs);
  2713. eeprom_prep(regs, EEPROM_READ_SELECT);
  2714. if (eeprom_check_ack(regs)) {
  2715. local_irq_restore(flags);
  2716. printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
  2717. ap->name);
  2718. result = -EIO;
  2719. goto eeprom_read_error;
  2720. }
  2721. for (i = 0; i < 8; i++) {
  2722. local = readl(&regs->LocalCtrl);
  2723. local &= ~EEPROM_WRITE_ENABLE;
  2724. writel(local, &regs->LocalCtrl);
  2725. readl(&regs->LocalCtrl);
  2726. udelay(ACE_LONG_DELAY);
  2727. mb();
  2728. local |= EEPROM_CLK_OUT;
  2729. writel(local, &regs->LocalCtrl);
  2730. readl(&regs->LocalCtrl);
  2731. mb();
  2732. udelay(ACE_SHORT_DELAY);
  2733. /* sample data mid high clk */
  2734. result = (result << 1) |
  2735. ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
  2736. udelay(ACE_SHORT_DELAY);
  2737. mb();
  2738. local = readl(&regs->LocalCtrl);
  2739. local &= ~EEPROM_CLK_OUT;
  2740. writel(local, &regs->LocalCtrl);
  2741. readl(&regs->LocalCtrl);
  2742. udelay(ACE_SHORT_DELAY);
  2743. mb();
  2744. if (i == 7) {
  2745. local |= EEPROM_WRITE_ENABLE;
  2746. writel(local, &regs->LocalCtrl);
  2747. readl(&regs->LocalCtrl);
  2748. mb();
  2749. udelay(ACE_SHORT_DELAY);
  2750. }
  2751. }
  2752. local |= EEPROM_DATA_OUT;
  2753. writel(local, &regs->LocalCtrl);
  2754. readl(&regs->LocalCtrl);
  2755. mb();
  2756. udelay(ACE_SHORT_DELAY);
  2757. writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
  2758. readl(&regs->LocalCtrl);
  2759. udelay(ACE_LONG_DELAY);
  2760. writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
  2761. readl(&regs->LocalCtrl);
  2762. mb();
  2763. udelay(ACE_SHORT_DELAY);
  2764. eeprom_stop(regs);
  2765. local_irq_restore(flags);
  2766. out:
  2767. return result;
  2768. eeprom_read_error:
  2769. printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
  2770. ap->name, offset);
  2771. goto out;
  2772. }
  2773. /*
  2774. * Local variables:
  2775. * compile-command: "gcc -D__SMP__ -D__KERNEL__ -DMODULE -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -DMODVERSIONS -include ../../include/linux/modversions.h -c -o acenic.o acenic.c"
  2776. * End:
  2777. */