setup.c 27 KB

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  1. /*
  2. * Architecture-specific setup.
  3. *
  4. * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
  5. * David Mosberger-Tang <davidm@hpl.hp.com>
  6. * Stephane Eranian <eranian@hpl.hp.com>
  7. * Copyright (C) 2000, 2004 Intel Corp
  8. * Rohit Seth <rohit.seth@intel.com>
  9. * Suresh Siddha <suresh.b.siddha@intel.com>
  10. * Gordon Jin <gordon.jin@intel.com>
  11. * Copyright (C) 1999 VA Linux Systems
  12. * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
  13. *
  14. * 12/26/04 S.Siddha, G.Jin, R.Seth
  15. * Add multi-threading and multi-core detection
  16. * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
  17. * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
  18. * 03/31/00 R.Seth cpu_initialized and current->processor fixes
  19. * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
  20. * 02/01/00 R.Seth fixed get_cpuinfo for SMP
  21. * 01/07/99 S.Eranian added the support for command line argument
  22. * 06/24/99 W.Drummond added boot_cpu_data.
  23. * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
  24. */
  25. #include <linux/module.h>
  26. #include <linux/init.h>
  27. #include <linux/acpi.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/console.h>
  30. #include <linux/delay.h>
  31. #include <linux/kernel.h>
  32. #include <linux/reboot.h>
  33. #include <linux/sched.h>
  34. #include <linux/seq_file.h>
  35. #include <linux/string.h>
  36. #include <linux/threads.h>
  37. #include <linux/screen_info.h>
  38. #include <linux/dmi.h>
  39. #include <linux/serial.h>
  40. #include <linux/serial_core.h>
  41. #include <linux/efi.h>
  42. #include <linux/initrd.h>
  43. #include <linux/pm.h>
  44. #include <linux/cpufreq.h>
  45. #include <linux/kexec.h>
  46. #include <linux/crash_dump.h>
  47. #include <asm/ia32.h>
  48. #include <asm/machvec.h>
  49. #include <asm/mca.h>
  50. #include <asm/meminit.h>
  51. #include <asm/page.h>
  52. #include <asm/patch.h>
  53. #include <asm/pgtable.h>
  54. #include <asm/processor.h>
  55. #include <asm/sal.h>
  56. #include <asm/sections.h>
  57. #include <asm/setup.h>
  58. #include <asm/smp.h>
  59. #include <asm/system.h>
  60. #include <asm/tlbflush.h>
  61. #include <asm/unistd.h>
  62. #include <asm/hpsim.h>
  63. #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
  64. # error "struct cpuinfo_ia64 too big!"
  65. #endif
  66. #ifdef CONFIG_SMP
  67. unsigned long __per_cpu_offset[NR_CPUS];
  68. EXPORT_SYMBOL(__per_cpu_offset);
  69. #endif
  70. DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
  71. DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
  72. unsigned long ia64_cycles_per_usec;
  73. struct ia64_boot_param *ia64_boot_param;
  74. struct screen_info screen_info;
  75. unsigned long vga_console_iobase;
  76. unsigned long vga_console_membase;
  77. static struct resource data_resource = {
  78. .name = "Kernel data",
  79. .flags = IORESOURCE_BUSY | IORESOURCE_MEM
  80. };
  81. static struct resource code_resource = {
  82. .name = "Kernel code",
  83. .flags = IORESOURCE_BUSY | IORESOURCE_MEM
  84. };
  85. static struct resource bss_resource = {
  86. .name = "Kernel bss",
  87. .flags = IORESOURCE_BUSY | IORESOURCE_MEM
  88. };
  89. unsigned long ia64_max_cacheline_size;
  90. int dma_get_cache_alignment(void)
  91. {
  92. return ia64_max_cacheline_size;
  93. }
  94. EXPORT_SYMBOL(dma_get_cache_alignment);
  95. unsigned long ia64_iobase; /* virtual address for I/O accesses */
  96. EXPORT_SYMBOL(ia64_iobase);
  97. struct io_space io_space[MAX_IO_SPACES];
  98. EXPORT_SYMBOL(io_space);
  99. unsigned int num_io_spaces;
  100. /*
  101. * "flush_icache_range()" needs to know what processor dependent stride size to use
  102. * when it makes i-cache(s) coherent with d-caches.
  103. */
  104. #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
  105. unsigned long ia64_i_cache_stride_shift = ~0;
  106. /*
  107. * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
  108. * mask specifies a mask of address bits that must be 0 in order for two buffers to be
  109. * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
  110. * address of the second buffer must be aligned to (merge_mask+1) in order to be
  111. * mergeable). By default, we assume there is no I/O MMU which can merge physically
  112. * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
  113. * page-size of 2^64.
  114. */
  115. unsigned long ia64_max_iommu_merge_mask = ~0UL;
  116. EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
  117. /*
  118. * We use a special marker for the end of memory and it uses the extra (+1) slot
  119. */
  120. struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
  121. int num_rsvd_regions __initdata;
  122. /*
  123. * Filter incoming memory segments based on the primitive map created from the boot
  124. * parameters. Segments contained in the map are removed from the memory ranges. A
  125. * caller-specified function is called with the memory ranges that remain after filtering.
  126. * This routine does not assume the incoming segments are sorted.
  127. */
  128. int __init
  129. filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
  130. {
  131. unsigned long range_start, range_end, prev_start;
  132. void (*func)(unsigned long, unsigned long, int);
  133. int i;
  134. #if IGNORE_PFN0
  135. if (start == PAGE_OFFSET) {
  136. printk(KERN_WARNING "warning: skipping physical page 0\n");
  137. start += PAGE_SIZE;
  138. if (start >= end) return 0;
  139. }
  140. #endif
  141. /*
  142. * lowest possible address(walker uses virtual)
  143. */
  144. prev_start = PAGE_OFFSET;
  145. func = arg;
  146. for (i = 0; i < num_rsvd_regions; ++i) {
  147. range_start = max(start, prev_start);
  148. range_end = min(end, rsvd_region[i].start);
  149. if (range_start < range_end)
  150. call_pernode_memory(__pa(range_start), range_end - range_start, func);
  151. /* nothing more available in this segment */
  152. if (range_end == end) return 0;
  153. prev_start = rsvd_region[i].end;
  154. }
  155. /* end of memory marker allows full processing inside loop body */
  156. return 0;
  157. }
  158. /*
  159. * Similar to "filter_rsvd_memory()", but the reserved memory ranges
  160. * are not filtered out.
  161. */
  162. int __init
  163. filter_memory(unsigned long start, unsigned long end, void *arg)
  164. {
  165. void (*func)(unsigned long, unsigned long, int);
  166. #if IGNORE_PFN0
  167. if (start == PAGE_OFFSET) {
  168. printk(KERN_WARNING "warning: skipping physical page 0\n");
  169. start += PAGE_SIZE;
  170. if (start >= end)
  171. return 0;
  172. }
  173. #endif
  174. func = arg;
  175. if (start < end)
  176. call_pernode_memory(__pa(start), end - start, func);
  177. return 0;
  178. }
  179. static void __init
  180. sort_regions (struct rsvd_region *rsvd_region, int max)
  181. {
  182. int j;
  183. /* simple bubble sorting */
  184. while (max--) {
  185. for (j = 0; j < max; ++j) {
  186. if (rsvd_region[j].start > rsvd_region[j+1].start) {
  187. struct rsvd_region tmp;
  188. tmp = rsvd_region[j];
  189. rsvd_region[j] = rsvd_region[j + 1];
  190. rsvd_region[j + 1] = tmp;
  191. }
  192. }
  193. }
  194. }
  195. /*
  196. * Request address space for all standard resources
  197. */
  198. static int __init register_memory(void)
  199. {
  200. code_resource.start = ia64_tpa(_text);
  201. code_resource.end = ia64_tpa(_etext) - 1;
  202. data_resource.start = ia64_tpa(_etext);
  203. data_resource.end = ia64_tpa(_edata) - 1;
  204. bss_resource.start = ia64_tpa(__bss_start);
  205. bss_resource.end = ia64_tpa(_end) - 1;
  206. efi_initialize_iomem_resources(&code_resource, &data_resource,
  207. &bss_resource);
  208. return 0;
  209. }
  210. __initcall(register_memory);
  211. #ifdef CONFIG_KEXEC
  212. static void __init setup_crashkernel(unsigned long total, int *n)
  213. {
  214. unsigned long long base = 0, size = 0;
  215. int ret;
  216. ret = parse_crashkernel(boot_command_line, total,
  217. &size, &base);
  218. if (ret == 0 && size > 0) {
  219. if (!base) {
  220. sort_regions(rsvd_region, *n);
  221. base = kdump_find_rsvd_region(size,
  222. rsvd_region, *n);
  223. }
  224. if (base != ~0UL) {
  225. printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
  226. "for crashkernel (System RAM: %ldMB)\n",
  227. (unsigned long)(size >> 20),
  228. (unsigned long)(base >> 20),
  229. (unsigned long)(total >> 20));
  230. rsvd_region[*n].start =
  231. (unsigned long)__va(base);
  232. rsvd_region[*n].end =
  233. (unsigned long)__va(base + size);
  234. (*n)++;
  235. crashk_res.start = base;
  236. crashk_res.end = base + size - 1;
  237. }
  238. }
  239. efi_memmap_res.start = ia64_boot_param->efi_memmap;
  240. efi_memmap_res.end = efi_memmap_res.start +
  241. ia64_boot_param->efi_memmap_size;
  242. boot_param_res.start = __pa(ia64_boot_param);
  243. boot_param_res.end = boot_param_res.start +
  244. sizeof(*ia64_boot_param);
  245. }
  246. #else
  247. static inline void __init setup_crashkernel(unsigned long total, int *n)
  248. {}
  249. #endif
  250. /**
  251. * reserve_memory - setup reserved memory areas
  252. *
  253. * Setup the reserved memory areas set aside for the boot parameters,
  254. * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
  255. * see include/asm-ia64/meminit.h if you need to define more.
  256. */
  257. void __init
  258. reserve_memory (void)
  259. {
  260. int n = 0;
  261. unsigned long total_memory;
  262. /*
  263. * none of the entries in this table overlap
  264. */
  265. rsvd_region[n].start = (unsigned long) ia64_boot_param;
  266. rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
  267. n++;
  268. rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
  269. rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
  270. n++;
  271. rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
  272. rsvd_region[n].end = (rsvd_region[n].start
  273. + strlen(__va(ia64_boot_param->command_line)) + 1);
  274. n++;
  275. rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
  276. rsvd_region[n].end = (unsigned long) ia64_imva(_end);
  277. n++;
  278. #ifdef CONFIG_BLK_DEV_INITRD
  279. if (ia64_boot_param->initrd_start) {
  280. rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
  281. rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
  282. n++;
  283. }
  284. #endif
  285. #ifdef CONFIG_PROC_VMCORE
  286. if (reserve_elfcorehdr(&rsvd_region[n].start,
  287. &rsvd_region[n].end) == 0)
  288. n++;
  289. #endif
  290. total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
  291. n++;
  292. setup_crashkernel(total_memory, &n);
  293. /* end of memory marker */
  294. rsvd_region[n].start = ~0UL;
  295. rsvd_region[n].end = ~0UL;
  296. n++;
  297. num_rsvd_regions = n;
  298. BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
  299. sort_regions(rsvd_region, num_rsvd_regions);
  300. }
  301. /**
  302. * find_initrd - get initrd parameters from the boot parameter structure
  303. *
  304. * Grab the initrd start and end from the boot parameter struct given us by
  305. * the boot loader.
  306. */
  307. void __init
  308. find_initrd (void)
  309. {
  310. #ifdef CONFIG_BLK_DEV_INITRD
  311. if (ia64_boot_param->initrd_start) {
  312. initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
  313. initrd_end = initrd_start+ia64_boot_param->initrd_size;
  314. printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
  315. initrd_start, ia64_boot_param->initrd_size);
  316. }
  317. #endif
  318. }
  319. static void __init
  320. io_port_init (void)
  321. {
  322. unsigned long phys_iobase;
  323. /*
  324. * Set `iobase' based on the EFI memory map or, failing that, the
  325. * value firmware left in ar.k0.
  326. *
  327. * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
  328. * the port's virtual address, so ia32_load_state() loads it with a
  329. * user virtual address. But in ia64 mode, glibc uses the
  330. * *physical* address in ar.k0 to mmap the appropriate area from
  331. * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
  332. * cases, user-mode can only use the legacy 0-64K I/O port space.
  333. *
  334. * ar.k0 is not involved in kernel I/O port accesses, which can use
  335. * any of the I/O port spaces and are done via MMIO using the
  336. * virtual mmio_base from the appropriate io_space[].
  337. */
  338. phys_iobase = efi_get_iobase();
  339. if (!phys_iobase) {
  340. phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
  341. printk(KERN_INFO "No I/O port range found in EFI memory map, "
  342. "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
  343. }
  344. ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
  345. ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
  346. /* setup legacy IO port space */
  347. io_space[0].mmio_base = ia64_iobase;
  348. io_space[0].sparse = 1;
  349. num_io_spaces = 1;
  350. }
  351. /**
  352. * early_console_setup - setup debugging console
  353. *
  354. * Consoles started here require little enough setup that we can start using
  355. * them very early in the boot process, either right after the machine
  356. * vector initialization, or even before if the drivers can detect their hw.
  357. *
  358. * Returns non-zero if a console couldn't be setup.
  359. */
  360. static inline int __init
  361. early_console_setup (char *cmdline)
  362. {
  363. int earlycons = 0;
  364. #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
  365. {
  366. extern int sn_serial_console_early_setup(void);
  367. if (!sn_serial_console_early_setup())
  368. earlycons++;
  369. }
  370. #endif
  371. #ifdef CONFIG_EFI_PCDP
  372. if (!efi_setup_pcdp_console(cmdline))
  373. earlycons++;
  374. #endif
  375. if (!simcons_register())
  376. earlycons++;
  377. return (earlycons) ? 0 : -1;
  378. }
  379. static inline void
  380. mark_bsp_online (void)
  381. {
  382. #ifdef CONFIG_SMP
  383. /* If we register an early console, allow CPU 0 to printk */
  384. cpu_set(smp_processor_id(), cpu_online_map);
  385. #endif
  386. }
  387. static __initdata int nomca;
  388. static __init int setup_nomca(char *s)
  389. {
  390. nomca = 1;
  391. return 0;
  392. }
  393. early_param("nomca", setup_nomca);
  394. #ifdef CONFIG_PROC_VMCORE
  395. /* elfcorehdr= specifies the location of elf core header
  396. * stored by the crashed kernel.
  397. */
  398. static int __init parse_elfcorehdr(char *arg)
  399. {
  400. if (!arg)
  401. return -EINVAL;
  402. elfcorehdr_addr = memparse(arg, &arg);
  403. return 0;
  404. }
  405. early_param("elfcorehdr", parse_elfcorehdr);
  406. int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end)
  407. {
  408. unsigned long length;
  409. /* We get the address using the kernel command line,
  410. * but the size is extracted from the EFI tables.
  411. * Both address and size are required for reservation
  412. * to work properly.
  413. */
  414. if (elfcorehdr_addr >= ELFCORE_ADDR_MAX)
  415. return -EINVAL;
  416. if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) {
  417. elfcorehdr_addr = ELFCORE_ADDR_MAX;
  418. return -EINVAL;
  419. }
  420. *start = (unsigned long)__va(elfcorehdr_addr);
  421. *end = *start + length;
  422. return 0;
  423. }
  424. #endif /* CONFIG_PROC_VMCORE */
  425. void __init
  426. setup_arch (char **cmdline_p)
  427. {
  428. unw_init();
  429. ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
  430. *cmdline_p = __va(ia64_boot_param->command_line);
  431. strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
  432. efi_init();
  433. io_port_init();
  434. #ifdef CONFIG_IA64_GENERIC
  435. /* machvec needs to be parsed from the command line
  436. * before parse_early_param() is called to ensure
  437. * that ia64_mv is initialised before any command line
  438. * settings may cause console setup to occur
  439. */
  440. machvec_init_from_cmdline(*cmdline_p);
  441. #endif
  442. parse_early_param();
  443. if (early_console_setup(*cmdline_p) == 0)
  444. mark_bsp_online();
  445. #ifdef CONFIG_ACPI
  446. /* Initialize the ACPI boot-time table parser */
  447. acpi_table_init();
  448. # ifdef CONFIG_ACPI_NUMA
  449. acpi_numa_init();
  450. per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ?
  451. 32 : cpus_weight(early_cpu_possible_map)), additional_cpus);
  452. # endif
  453. #else
  454. # ifdef CONFIG_SMP
  455. smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
  456. # endif
  457. #endif /* CONFIG_APCI_BOOT */
  458. find_memory();
  459. /* process SAL system table: */
  460. ia64_sal_init(__va(efi.sal_systab));
  461. #ifdef CONFIG_SMP
  462. cpu_physical_id(0) = hard_smp_processor_id();
  463. #endif
  464. cpu_init(); /* initialize the bootstrap CPU */
  465. mmu_context_init(); /* initialize context_id bitmap */
  466. check_sal_cache_flush();
  467. #ifdef CONFIG_ACPI
  468. acpi_boot_init();
  469. #endif
  470. #ifdef CONFIG_VT
  471. if (!conswitchp) {
  472. # if defined(CONFIG_DUMMY_CONSOLE)
  473. conswitchp = &dummy_con;
  474. # endif
  475. # if defined(CONFIG_VGA_CONSOLE)
  476. /*
  477. * Non-legacy systems may route legacy VGA MMIO range to system
  478. * memory. vga_con probes the MMIO hole, so memory looks like
  479. * a VGA device to it. The EFI memory map can tell us if it's
  480. * memory so we can avoid this problem.
  481. */
  482. if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
  483. conswitchp = &vga_con;
  484. # endif
  485. }
  486. #endif
  487. /* enable IA-64 Machine Check Abort Handling unless disabled */
  488. if (!nomca)
  489. ia64_mca_init();
  490. platform_setup(cmdline_p);
  491. paging_init();
  492. }
  493. /*
  494. * Display cpu info for all CPUs.
  495. */
  496. static int
  497. show_cpuinfo (struct seq_file *m, void *v)
  498. {
  499. #ifdef CONFIG_SMP
  500. # define lpj c->loops_per_jiffy
  501. # define cpunum c->cpu
  502. #else
  503. # define lpj loops_per_jiffy
  504. # define cpunum 0
  505. #endif
  506. static struct {
  507. unsigned long mask;
  508. const char *feature_name;
  509. } feature_bits[] = {
  510. { 1UL << 0, "branchlong" },
  511. { 1UL << 1, "spontaneous deferral"},
  512. { 1UL << 2, "16-byte atomic ops" }
  513. };
  514. char features[128], *cp, *sep;
  515. struct cpuinfo_ia64 *c = v;
  516. unsigned long mask;
  517. unsigned long proc_freq;
  518. int i, size;
  519. mask = c->features;
  520. /* build the feature string: */
  521. memcpy(features, "standard", 9);
  522. cp = features;
  523. size = sizeof(features);
  524. sep = "";
  525. for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) {
  526. if (mask & feature_bits[i].mask) {
  527. cp += snprintf(cp, size, "%s%s", sep,
  528. feature_bits[i].feature_name),
  529. sep = ", ";
  530. mask &= ~feature_bits[i].mask;
  531. size = sizeof(features) - (cp - features);
  532. }
  533. }
  534. if (mask && size > 1) {
  535. /* print unknown features as a hex value */
  536. snprintf(cp, size, "%s0x%lx", sep, mask);
  537. }
  538. proc_freq = cpufreq_quick_get(cpunum);
  539. if (!proc_freq)
  540. proc_freq = c->proc_freq / 1000;
  541. seq_printf(m,
  542. "processor : %d\n"
  543. "vendor : %s\n"
  544. "arch : IA-64\n"
  545. "family : %u\n"
  546. "model : %u\n"
  547. "model name : %s\n"
  548. "revision : %u\n"
  549. "archrev : %u\n"
  550. "features : %s\n"
  551. "cpu number : %lu\n"
  552. "cpu regs : %u\n"
  553. "cpu MHz : %lu.%03lu\n"
  554. "itc MHz : %lu.%06lu\n"
  555. "BogoMIPS : %lu.%02lu\n",
  556. cpunum, c->vendor, c->family, c->model,
  557. c->model_name, c->revision, c->archrev,
  558. features, c->ppn, c->number,
  559. proc_freq / 1000, proc_freq % 1000,
  560. c->itc_freq / 1000000, c->itc_freq % 1000000,
  561. lpj*HZ/500000, (lpj*HZ/5000) % 100);
  562. #ifdef CONFIG_SMP
  563. seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
  564. if (c->socket_id != -1)
  565. seq_printf(m, "physical id: %u\n", c->socket_id);
  566. if (c->threads_per_core > 1 || c->cores_per_socket > 1)
  567. seq_printf(m,
  568. "core id : %u\n"
  569. "thread id : %u\n",
  570. c->core_id, c->thread_id);
  571. #endif
  572. seq_printf(m,"\n");
  573. return 0;
  574. }
  575. static void *
  576. c_start (struct seq_file *m, loff_t *pos)
  577. {
  578. #ifdef CONFIG_SMP
  579. while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
  580. ++*pos;
  581. #endif
  582. return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
  583. }
  584. static void *
  585. c_next (struct seq_file *m, void *v, loff_t *pos)
  586. {
  587. ++*pos;
  588. return c_start(m, pos);
  589. }
  590. static void
  591. c_stop (struct seq_file *m, void *v)
  592. {
  593. }
  594. const struct seq_operations cpuinfo_op = {
  595. .start = c_start,
  596. .next = c_next,
  597. .stop = c_stop,
  598. .show = show_cpuinfo
  599. };
  600. #define MAX_BRANDS 8
  601. static char brandname[MAX_BRANDS][128];
  602. static char * __cpuinit
  603. get_model_name(__u8 family, __u8 model)
  604. {
  605. static int overflow;
  606. char brand[128];
  607. int i;
  608. memcpy(brand, "Unknown", 8);
  609. if (ia64_pal_get_brand_info(brand)) {
  610. if (family == 0x7)
  611. memcpy(brand, "Merced", 7);
  612. else if (family == 0x1f) switch (model) {
  613. case 0: memcpy(brand, "McKinley", 9); break;
  614. case 1: memcpy(brand, "Madison", 8); break;
  615. case 2: memcpy(brand, "Madison up to 9M cache", 23); break;
  616. }
  617. }
  618. for (i = 0; i < MAX_BRANDS; i++)
  619. if (strcmp(brandname[i], brand) == 0)
  620. return brandname[i];
  621. for (i = 0; i < MAX_BRANDS; i++)
  622. if (brandname[i][0] == '\0')
  623. return strcpy(brandname[i], brand);
  624. if (overflow++ == 0)
  625. printk(KERN_ERR
  626. "%s: Table overflow. Some processor model information will be missing\n",
  627. __func__);
  628. return "Unknown";
  629. }
  630. static void __cpuinit
  631. identify_cpu (struct cpuinfo_ia64 *c)
  632. {
  633. union {
  634. unsigned long bits[5];
  635. struct {
  636. /* id 0 & 1: */
  637. char vendor[16];
  638. /* id 2 */
  639. u64 ppn; /* processor serial number */
  640. /* id 3: */
  641. unsigned number : 8;
  642. unsigned revision : 8;
  643. unsigned model : 8;
  644. unsigned family : 8;
  645. unsigned archrev : 8;
  646. unsigned reserved : 24;
  647. /* id 4: */
  648. u64 features;
  649. } field;
  650. } cpuid;
  651. pal_vm_info_1_u_t vm1;
  652. pal_vm_info_2_u_t vm2;
  653. pal_status_t status;
  654. unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
  655. int i;
  656. for (i = 0; i < 5; ++i)
  657. cpuid.bits[i] = ia64_get_cpuid(i);
  658. memcpy(c->vendor, cpuid.field.vendor, 16);
  659. #ifdef CONFIG_SMP
  660. c->cpu = smp_processor_id();
  661. /* below default values will be overwritten by identify_siblings()
  662. * for Multi-Threading/Multi-Core capable CPUs
  663. */
  664. c->threads_per_core = c->cores_per_socket = c->num_log = 1;
  665. c->socket_id = -1;
  666. identify_siblings(c);
  667. if (c->threads_per_core > smp_num_siblings)
  668. smp_num_siblings = c->threads_per_core;
  669. #endif
  670. c->ppn = cpuid.field.ppn;
  671. c->number = cpuid.field.number;
  672. c->revision = cpuid.field.revision;
  673. c->model = cpuid.field.model;
  674. c->family = cpuid.field.family;
  675. c->archrev = cpuid.field.archrev;
  676. c->features = cpuid.field.features;
  677. c->model_name = get_model_name(c->family, c->model);
  678. status = ia64_pal_vm_summary(&vm1, &vm2);
  679. if (status == PAL_STATUS_SUCCESS) {
  680. impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
  681. phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
  682. }
  683. c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
  684. c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
  685. }
  686. void __init
  687. setup_per_cpu_areas (void)
  688. {
  689. /* start_kernel() requires this... */
  690. #ifdef CONFIG_ACPI_HOTPLUG_CPU
  691. prefill_possible_map();
  692. #endif
  693. }
  694. /*
  695. * Calculate the max. cache line size.
  696. *
  697. * In addition, the minimum of the i-cache stride sizes is calculated for
  698. * "flush_icache_range()".
  699. */
  700. static void __cpuinit
  701. get_max_cacheline_size (void)
  702. {
  703. unsigned long line_size, max = 1;
  704. u64 l, levels, unique_caches;
  705. pal_cache_config_info_t cci;
  706. s64 status;
  707. status = ia64_pal_cache_summary(&levels, &unique_caches);
  708. if (status != 0) {
  709. printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
  710. __func__, status);
  711. max = SMP_CACHE_BYTES;
  712. /* Safest setup for "flush_icache_range()" */
  713. ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
  714. goto out;
  715. }
  716. for (l = 0; l < levels; ++l) {
  717. status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
  718. &cci);
  719. if (status != 0) {
  720. printk(KERN_ERR
  721. "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
  722. __func__, l, status);
  723. max = SMP_CACHE_BYTES;
  724. /* The safest setup for "flush_icache_range()" */
  725. cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
  726. cci.pcci_unified = 1;
  727. }
  728. line_size = 1 << cci.pcci_line_size;
  729. if (line_size > max)
  730. max = line_size;
  731. if (!cci.pcci_unified) {
  732. status = ia64_pal_cache_config_info(l,
  733. /* cache_type (instruction)= */ 1,
  734. &cci);
  735. if (status != 0) {
  736. printk(KERN_ERR
  737. "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
  738. __func__, l, status);
  739. /* The safest setup for "flush_icache_range()" */
  740. cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
  741. }
  742. }
  743. if (cci.pcci_stride < ia64_i_cache_stride_shift)
  744. ia64_i_cache_stride_shift = cci.pcci_stride;
  745. }
  746. out:
  747. if (max > ia64_max_cacheline_size)
  748. ia64_max_cacheline_size = max;
  749. }
  750. /*
  751. * cpu_init() initializes state that is per-CPU. This function acts
  752. * as a 'CPU state barrier', nothing should get across.
  753. */
  754. void __cpuinit
  755. cpu_init (void)
  756. {
  757. extern void __cpuinit ia64_mmu_init (void *);
  758. static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG;
  759. unsigned long num_phys_stacked;
  760. pal_vm_info_2_u_t vmi;
  761. unsigned int max_ctx;
  762. struct cpuinfo_ia64 *cpu_info;
  763. void *cpu_data;
  764. cpu_data = per_cpu_init();
  765. #ifdef CONFIG_SMP
  766. /*
  767. * insert boot cpu into sibling and core mapes
  768. * (must be done after per_cpu area is setup)
  769. */
  770. if (smp_processor_id() == 0) {
  771. cpu_set(0, per_cpu(cpu_sibling_map, 0));
  772. cpu_set(0, cpu_core_map[0]);
  773. }
  774. #endif
  775. /*
  776. * We set ar.k3 so that assembly code in MCA handler can compute
  777. * physical addresses of per cpu variables with a simple:
  778. * phys = ar.k3 + &per_cpu_var
  779. */
  780. ia64_set_kr(IA64_KR_PER_CPU_DATA,
  781. ia64_tpa(cpu_data) - (long) __per_cpu_start);
  782. get_max_cacheline_size();
  783. /*
  784. * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
  785. * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
  786. * depends on the data returned by identify_cpu(). We break the dependency by
  787. * accessing cpu_data() through the canonical per-CPU address.
  788. */
  789. cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
  790. identify_cpu(cpu_info);
  791. #ifdef CONFIG_MCKINLEY
  792. {
  793. # define FEATURE_SET 16
  794. struct ia64_pal_retval iprv;
  795. if (cpu_info->family == 0x1f) {
  796. PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
  797. if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
  798. PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
  799. (iprv.v1 | 0x80), FEATURE_SET, 0);
  800. }
  801. }
  802. #endif
  803. /* Clear the stack memory reserved for pt_regs: */
  804. memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
  805. ia64_set_kr(IA64_KR_FPU_OWNER, 0);
  806. /*
  807. * Initialize the page-table base register to a global
  808. * directory with all zeroes. This ensure that we can handle
  809. * TLB-misses to user address-space even before we created the
  810. * first user address-space. This may happen, e.g., due to
  811. * aggressive use of lfetch.fault.
  812. */
  813. ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
  814. /*
  815. * Initialize default control register to defer speculative faults except
  816. * for those arising from TLB misses, which are not deferred. The
  817. * kernel MUST NOT depend on a particular setting of these bits (in other words,
  818. * the kernel must have recovery code for all speculative accesses). Turn on
  819. * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
  820. * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
  821. * be fine).
  822. */
  823. ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
  824. | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
  825. atomic_inc(&init_mm.mm_count);
  826. current->active_mm = &init_mm;
  827. if (current->mm)
  828. BUG();
  829. ia64_mmu_init(ia64_imva(cpu_data));
  830. ia64_mca_cpu_init(ia64_imva(cpu_data));
  831. #ifdef CONFIG_IA32_SUPPORT
  832. ia32_cpu_init();
  833. #endif
  834. /* Clear ITC to eliminate sched_clock() overflows in human time. */
  835. ia64_set_itc(0);
  836. /* disable all local interrupt sources: */
  837. ia64_set_itv(1 << 16);
  838. ia64_set_lrr0(1 << 16);
  839. ia64_set_lrr1(1 << 16);
  840. ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
  841. ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
  842. /* clear TPR & XTP to enable all interrupt classes: */
  843. ia64_setreg(_IA64_REG_CR_TPR, 0);
  844. /* Clear any pending interrupts left by SAL/EFI */
  845. while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR)
  846. ia64_eoi();
  847. #ifdef CONFIG_SMP
  848. normal_xtp();
  849. #endif
  850. /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
  851. if (ia64_pal_vm_summary(NULL, &vmi) == 0) {
  852. max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
  853. setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL);
  854. } else {
  855. printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
  856. max_ctx = (1U << 15) - 1; /* use architected minimum */
  857. }
  858. while (max_ctx < ia64_ctx.max_ctx) {
  859. unsigned int old = ia64_ctx.max_ctx;
  860. if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
  861. break;
  862. }
  863. if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
  864. printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
  865. "stacked regs\n");
  866. num_phys_stacked = 96;
  867. }
  868. /* size of physical stacked register partition plus 8 bytes: */
  869. if (num_phys_stacked > max_num_phys_stacked) {
  870. ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8);
  871. max_num_phys_stacked = num_phys_stacked;
  872. }
  873. platform_cpu_init();
  874. pm_idle = default_idle;
  875. }
  876. void __init
  877. check_bugs (void)
  878. {
  879. ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
  880. (unsigned long) __end___mckinley_e9_bundles);
  881. }
  882. static int __init run_dmi_scan(void)
  883. {
  884. dmi_scan_machine();
  885. return 0;
  886. }
  887. core_initcall(run_dmi_scan);