minstate.h 7.2 KB

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  1. #include <asm/cache.h>
  2. #include "entry.h"
  3. #ifdef CONFIG_VIRT_CPU_ACCOUNTING
  4. /* read ar.itc in advance, and use it before leaving bank 0 */
  5. #define ACCOUNT_GET_STAMP \
  6. (pUStk) mov.m r20=ar.itc;
  7. #define ACCOUNT_SYS_ENTER \
  8. (pUStk) br.call.spnt rp=account_sys_enter \
  9. ;;
  10. #else
  11. #define ACCOUNT_GET_STAMP
  12. #define ACCOUNT_SYS_ENTER
  13. #endif
  14. /*
  15. * DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
  16. * the minimum state necessary that allows us to turn psr.ic back
  17. * on.
  18. *
  19. * Assumed state upon entry:
  20. * psr.ic: off
  21. * r31: contains saved predicates (pr)
  22. *
  23. * Upon exit, the state is as follows:
  24. * psr.ic: off
  25. * r2 = points to &pt_regs.r16
  26. * r8 = contents of ar.ccv
  27. * r9 = contents of ar.csd
  28. * r10 = contents of ar.ssd
  29. * r11 = FPSR_DEFAULT
  30. * r12 = kernel sp (kernel virtual address)
  31. * r13 = points to current task_struct (kernel virtual address)
  32. * p15 = TRUE if psr.i is set in cr.ipsr
  33. * predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
  34. * preserved
  35. *
  36. * Note that psr.ic is NOT turned on by this macro. This is so that
  37. * we can pass interruption state as arguments to a handler.
  38. */
  39. #define DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \
  40. mov r16=IA64_KR(CURRENT); /* M */ \
  41. mov r27=ar.rsc; /* M */ \
  42. mov r20=r1; /* A */ \
  43. mov r25=ar.unat; /* M */ \
  44. mov r29=cr.ipsr; /* M */ \
  45. mov r26=ar.pfs; /* I */ \
  46. mov r28=cr.iip; /* M */ \
  47. mov r21=ar.fpsr; /* M */ \
  48. COVER; /* B;; (or nothing) */ \
  49. ;; \
  50. adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16; \
  51. ;; \
  52. ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \
  53. st1 [r16]=r0; /* clear current->thread.on_ustack flag */ \
  54. adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 \
  55. /* switch from user to kernel RBS: */ \
  56. ;; \
  57. invala; /* M */ \
  58. SAVE_IFS; \
  59. cmp.eq pKStk,pUStk=r0,r17; /* are we in kernel mode already? */ \
  60. ;; \
  61. (pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
  62. ;; \
  63. (pUStk) mov.m r24=ar.rnat; \
  64. (pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \
  65. (pKStk) mov r1=sp; /* get sp */ \
  66. ;; \
  67. (pUStk) lfetch.fault.excl.nt1 [r22]; \
  68. (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
  69. (pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \
  70. ;; \
  71. (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
  72. (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \
  73. ;; \
  74. (pUStk) mov r18=ar.bsp; \
  75. (pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \
  76. adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \
  77. adds r16=PT(CR_IPSR),r1; \
  78. ;; \
  79. lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
  80. st8 [r16]=r29; /* save cr.ipsr */ \
  81. ;; \
  82. lfetch.fault.excl.nt1 [r17]; \
  83. tbit.nz p15,p0=r29,IA64_PSR_I_BIT; \
  84. mov r29=b0 \
  85. ;; \
  86. adds r16=PT(R8),r1; /* initialize first base pointer */ \
  87. adds r17=PT(R9),r1; /* initialize second base pointer */ \
  88. (pKStk) mov r18=r0; /* make sure r18 isn't NaT */ \
  89. ;; \
  90. .mem.offset 0,0; st8.spill [r16]=r8,16; \
  91. .mem.offset 8,0; st8.spill [r17]=r9,16; \
  92. ;; \
  93. .mem.offset 0,0; st8.spill [r16]=r10,24; \
  94. .mem.offset 8,0; st8.spill [r17]=r11,24; \
  95. ;; \
  96. st8 [r16]=r28,16; /* save cr.iip */ \
  97. st8 [r17]=r30,16; /* save cr.ifs */ \
  98. (pUStk) sub r18=r18,r22; /* r18=RSE.ndirty*8 */ \
  99. mov r8=ar.ccv; \
  100. mov r9=ar.csd; \
  101. mov r10=ar.ssd; \
  102. movl r11=FPSR_DEFAULT; /* L-unit */ \
  103. ;; \
  104. st8 [r16]=r25,16; /* save ar.unat */ \
  105. st8 [r17]=r26,16; /* save ar.pfs */ \
  106. shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \
  107. ;; \
  108. st8 [r16]=r27,16; /* save ar.rsc */ \
  109. (pUStk) st8 [r17]=r24,16; /* save ar.rnat */ \
  110. (pKStk) adds r17=16,r17; /* skip over ar_rnat field */ \
  111. ;; /* avoid RAW on r16 & r17 */ \
  112. (pUStk) st8 [r16]=r23,16; /* save ar.bspstore */ \
  113. st8 [r17]=r31,16; /* save predicates */ \
  114. (pKStk) adds r16=16,r16; /* skip over ar_bspstore field */ \
  115. ;; \
  116. st8 [r16]=r29,16; /* save b0 */ \
  117. st8 [r17]=r18,16; /* save ar.rsc value for "loadrs" */ \
  118. cmp.eq pNonSys,pSys=r0,r0 /* initialize pSys=0, pNonSys=1 */ \
  119. ;; \
  120. .mem.offset 0,0; st8.spill [r16]=r20,16; /* save original r1 */ \
  121. .mem.offset 8,0; st8.spill [r17]=r12,16; \
  122. adds r12=-16,r1; /* switch to kernel memory stack (with 16 bytes of scratch) */ \
  123. ;; \
  124. .mem.offset 0,0; st8.spill [r16]=r13,16; \
  125. .mem.offset 8,0; st8.spill [r17]=r21,16; /* save ar.fpsr */ \
  126. mov r13=IA64_KR(CURRENT); /* establish `current' */ \
  127. ;; \
  128. .mem.offset 0,0; st8.spill [r16]=r15,16; \
  129. .mem.offset 8,0; st8.spill [r17]=r14,16; \
  130. ;; \
  131. .mem.offset 0,0; st8.spill [r16]=r2,16; \
  132. .mem.offset 8,0; st8.spill [r17]=r3,16; \
  133. ACCOUNT_GET_STAMP \
  134. adds r2=IA64_PT_REGS_R16_OFFSET,r1; \
  135. ;; \
  136. EXTRA; \
  137. movl r1=__gp; /* establish kernel global pointer */ \
  138. ;; \
  139. ACCOUNT_SYS_ENTER \
  140. bsw.1; /* switch back to bank 1 (must be last in insn group) */ \
  141. ;;
  142. /*
  143. * SAVE_REST saves the remainder of pt_regs (with psr.ic on).
  144. *
  145. * Assumed state upon entry:
  146. * psr.ic: on
  147. * r2: points to &pt_regs.r16
  148. * r3: points to &pt_regs.r17
  149. * r8: contents of ar.ccv
  150. * r9: contents of ar.csd
  151. * r10: contents of ar.ssd
  152. * r11: FPSR_DEFAULT
  153. *
  154. * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
  155. */
  156. #define SAVE_REST \
  157. .mem.offset 0,0; st8.spill [r2]=r16,16; \
  158. .mem.offset 8,0; st8.spill [r3]=r17,16; \
  159. ;; \
  160. .mem.offset 0,0; st8.spill [r2]=r18,16; \
  161. .mem.offset 8,0; st8.spill [r3]=r19,16; \
  162. ;; \
  163. .mem.offset 0,0; st8.spill [r2]=r20,16; \
  164. .mem.offset 8,0; st8.spill [r3]=r21,16; \
  165. mov r18=b6; \
  166. ;; \
  167. .mem.offset 0,0; st8.spill [r2]=r22,16; \
  168. .mem.offset 8,0; st8.spill [r3]=r23,16; \
  169. mov r19=b7; \
  170. ;; \
  171. .mem.offset 0,0; st8.spill [r2]=r24,16; \
  172. .mem.offset 8,0; st8.spill [r3]=r25,16; \
  173. ;; \
  174. .mem.offset 0,0; st8.spill [r2]=r26,16; \
  175. .mem.offset 8,0; st8.spill [r3]=r27,16; \
  176. ;; \
  177. .mem.offset 0,0; st8.spill [r2]=r28,16; \
  178. .mem.offset 8,0; st8.spill [r3]=r29,16; \
  179. ;; \
  180. .mem.offset 0,0; st8.spill [r2]=r30,16; \
  181. .mem.offset 8,0; st8.spill [r3]=r31,32; \
  182. ;; \
  183. mov ar.fpsr=r11; /* M-unit */ \
  184. st8 [r2]=r8,8; /* ar.ccv */ \
  185. adds r24=PT(B6)-PT(F7),r3; \
  186. ;; \
  187. stf.spill [r2]=f6,32; \
  188. stf.spill [r3]=f7,32; \
  189. ;; \
  190. stf.spill [r2]=f8,32; \
  191. stf.spill [r3]=f9,32; \
  192. ;; \
  193. stf.spill [r2]=f10; \
  194. stf.spill [r3]=f11; \
  195. adds r25=PT(B7)-PT(F11),r3; \
  196. ;; \
  197. st8 [r24]=r18,16; /* b6 */ \
  198. st8 [r25]=r19,16; /* b7 */ \
  199. ;; \
  200. st8 [r24]=r9; /* ar.csd */ \
  201. st8 [r25]=r10; /* ar.ssd */ \
  202. ;;
  203. #define SAVE_MIN_WITH_COVER DO_SAVE_MIN(cover, mov r30=cr.ifs,)
  204. #define SAVE_MIN_WITH_COVER_R19 DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19)
  205. #define SAVE_MIN DO_SAVE_MIN( , mov r30=r0, )