proc-xscale.S 25 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-xscale.S
  3. *
  4. * Author: Nicolas Pitre
  5. * Created: November 2000
  6. * Copyright: (C) 2000, 2001 MontaVista Software Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * MMU functions for the Intel XScale CPUs
  13. *
  14. * 2001 Aug 21:
  15. * some contributions by Brett Gaines <brett.w.gaines@intel.com>
  16. * Copyright 2001 by Intel Corp.
  17. *
  18. * 2001 Sep 08:
  19. * Completely revisited, many important fixes
  20. * Nicolas Pitre <nico@cam.org>
  21. */
  22. #include <linux/linkage.h>
  23. #include <linux/init.h>
  24. #include <asm/assembler.h>
  25. #include <asm/elf.h>
  26. #include <asm/pgtable.h>
  27. #include <asm/pgtable-hwdef.h>
  28. #include <asm/page.h>
  29. #include <asm/ptrace.h>
  30. #include "proc-macros.S"
  31. /*
  32. * This is the maximum size of an area which will be flushed. If the area
  33. * is larger than this, then we flush the whole cache
  34. */
  35. #define MAX_AREA_SIZE 32768
  36. /*
  37. * the cache line size of the I and D cache
  38. */
  39. #define CACHELINESIZE 32
  40. /*
  41. * the size of the data cache
  42. */
  43. #define CACHESIZE 32768
  44. /*
  45. * Virtual address used to allocate the cache when flushed
  46. *
  47. * This must be an address range which is _never_ used. It should
  48. * apparently have a mapping in the corresponding page table for
  49. * compatibility with future CPUs that _could_ require it. For instance we
  50. * don't care.
  51. *
  52. * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
  53. * the 2 areas in alternance each time the clean_d_cache macro is used.
  54. * Without this the XScale core exhibits cache eviction problems and no one
  55. * knows why.
  56. *
  57. * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
  58. */
  59. #define CLEAN_ADDR 0xfffe0000
  60. /*
  61. * This macro is used to wait for a CP15 write and is needed
  62. * when we have to ensure that the last operation to the co-pro
  63. * was completed before continuing with operation.
  64. */
  65. .macro cpwait, rd
  66. mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
  67. mov \rd, \rd @ wait for completion
  68. sub pc, pc, #4 @ flush instruction pipeline
  69. .endm
  70. .macro cpwait_ret, lr, rd
  71. mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
  72. sub pc, \lr, \rd, LSR #32 @ wait for completion and
  73. @ flush instruction pipeline
  74. .endm
  75. /*
  76. * This macro cleans the entire dcache using line allocate.
  77. * The main loop has been unrolled to reduce loop overhead.
  78. * rd and rs are two scratch registers.
  79. */
  80. .macro clean_d_cache, rd, rs
  81. ldr \rs, =clean_addr
  82. ldr \rd, [\rs]
  83. eor \rd, \rd, #CACHESIZE
  84. str \rd, [\rs]
  85. add \rs, \rd, #CACHESIZE
  86. 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  87. add \rd, \rd, #CACHELINESIZE
  88. mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  89. add \rd, \rd, #CACHELINESIZE
  90. mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  91. add \rd, \rd, #CACHELINESIZE
  92. mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  93. add \rd, \rd, #CACHELINESIZE
  94. teq \rd, \rs
  95. bne 1b
  96. .endm
  97. .data
  98. clean_addr: .word CLEAN_ADDR
  99. .text
  100. /*
  101. * cpu_xscale_proc_init()
  102. *
  103. * Nothing too exciting at the moment
  104. */
  105. ENTRY(cpu_xscale_proc_init)
  106. @ enable write buffer coalescing. Some bootloader disable it
  107. mrc p15, 0, r1, c1, c0, 1
  108. bic r1, r1, #1
  109. mcr p15, 0, r1, c1, c0, 1
  110. mov pc, lr
  111. /*
  112. * cpu_xscale_proc_fin()
  113. */
  114. ENTRY(cpu_xscale_proc_fin)
  115. str lr, [sp, #-4]!
  116. mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
  117. msr cpsr_c, r0
  118. bl xscale_flush_kern_cache_all @ clean caches
  119. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  120. bic r0, r0, #0x1800 @ ...IZ...........
  121. bic r0, r0, #0x0006 @ .............CA.
  122. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  123. ldr pc, [sp], #4
  124. /*
  125. * cpu_xscale_reset(loc)
  126. *
  127. * Perform a soft reset of the system. Put the CPU into the
  128. * same state as it would be if it had been reset, and branch
  129. * to what would be the reset vector.
  130. *
  131. * loc: location to jump to for soft reset
  132. *
  133. * Beware PXA270 erratum E7.
  134. */
  135. .align 5
  136. ENTRY(cpu_xscale_reset)
  137. mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
  138. msr cpsr_c, r1 @ reset CPSR
  139. mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
  140. mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
  141. mrc p15, 0, r1, c1, c0, 0 @ ctrl register
  142. bic r1, r1, #0x0086 @ ........B....CA.
  143. bic r1, r1, #0x3900 @ ..VIZ..S........
  144. sub pc, pc, #4 @ flush pipeline
  145. @ *** cache line aligned ***
  146. mcr p15, 0, r1, c1, c0, 0 @ ctrl register
  147. bic r1, r1, #0x0001 @ ...............M
  148. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
  149. mcr p15, 0, r1, c1, c0, 0 @ ctrl register
  150. @ CAUTION: MMU turned off from this point. We count on the pipeline
  151. @ already containing those two last instructions to survive.
  152. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  153. mov pc, r0
  154. /*
  155. * cpu_xscale_do_idle()
  156. *
  157. * Cause the processor to idle
  158. *
  159. * For now we do nothing but go to idle mode for every case
  160. *
  161. * XScale supports clock switching, but using idle mode support
  162. * allows external hardware to react to system state changes.
  163. */
  164. .align 5
  165. ENTRY(cpu_xscale_do_idle)
  166. mov r0, #1
  167. mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
  168. mov pc, lr
  169. /* ================================= CACHE ================================ */
  170. /*
  171. * flush_user_cache_all()
  172. *
  173. * Invalidate all cache entries in a particular address
  174. * space.
  175. */
  176. ENTRY(xscale_flush_user_cache_all)
  177. /* FALLTHROUGH */
  178. /*
  179. * flush_kern_cache_all()
  180. *
  181. * Clean and invalidate the entire cache.
  182. */
  183. ENTRY(xscale_flush_kern_cache_all)
  184. mov r2, #VM_EXEC
  185. mov ip, #0
  186. __flush_whole_cache:
  187. clean_d_cache r0, r1
  188. tst r2, #VM_EXEC
  189. mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
  190. mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  191. mov pc, lr
  192. /*
  193. * flush_user_cache_range(start, end, vm_flags)
  194. *
  195. * Invalidate a range of cache entries in the specified
  196. * address space.
  197. *
  198. * - start - start address (may not be aligned)
  199. * - end - end address (exclusive, may not be aligned)
  200. * - vma - vma_area_struct describing address space
  201. */
  202. .align 5
  203. ENTRY(xscale_flush_user_cache_range)
  204. mov ip, #0
  205. sub r3, r1, r0 @ calculate total size
  206. cmp r3, #MAX_AREA_SIZE
  207. bhs __flush_whole_cache
  208. 1: tst r2, #VM_EXEC
  209. mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
  210. mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
  211. mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
  212. add r0, r0, #CACHELINESIZE
  213. cmp r0, r1
  214. blo 1b
  215. tst r2, #VM_EXEC
  216. mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
  217. mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  218. mov pc, lr
  219. /*
  220. * coherent_kern_range(start, end)
  221. *
  222. * Ensure coherency between the Icache and the Dcache in the
  223. * region described by start. If you have non-snooping
  224. * Harvard caches, you need to implement this function.
  225. *
  226. * - start - virtual start address
  227. * - end - virtual end address
  228. *
  229. * Note: single I-cache line invalidation isn't used here since
  230. * it also trashes the mini I-cache used by JTAG debuggers.
  231. */
  232. ENTRY(xscale_coherent_kern_range)
  233. bic r0, r0, #CACHELINESIZE - 1
  234. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  235. add r0, r0, #CACHELINESIZE
  236. cmp r0, r1
  237. blo 1b
  238. mov r0, #0
  239. mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
  240. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  241. mov pc, lr
  242. /*
  243. * coherent_user_range(start, end)
  244. *
  245. * Ensure coherency between the Icache and the Dcache in the
  246. * region described by start. If you have non-snooping
  247. * Harvard caches, you need to implement this function.
  248. *
  249. * - start - virtual start address
  250. * - end - virtual end address
  251. */
  252. ENTRY(xscale_coherent_user_range)
  253. bic r0, r0, #CACHELINESIZE - 1
  254. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  255. mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
  256. add r0, r0, #CACHELINESIZE
  257. cmp r0, r1
  258. blo 1b
  259. mov r0, #0
  260. mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
  261. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  262. mov pc, lr
  263. /*
  264. * flush_kern_dcache_page(void *page)
  265. *
  266. * Ensure no D cache aliasing occurs, either with itself or
  267. * the I cache
  268. *
  269. * - addr - page aligned address
  270. */
  271. ENTRY(xscale_flush_kern_dcache_page)
  272. add r1, r0, #PAGE_SZ
  273. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  274. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  275. add r0, r0, #CACHELINESIZE
  276. cmp r0, r1
  277. blo 1b
  278. mov r0, #0
  279. mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
  280. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  281. mov pc, lr
  282. /*
  283. * dma_inv_range(start, end)
  284. *
  285. * Invalidate (discard) the specified virtual address range.
  286. * May not write back any entries. If 'start' or 'end'
  287. * are not cache line aligned, those lines must be written
  288. * back.
  289. *
  290. * - start - virtual start address
  291. * - end - virtual end address
  292. */
  293. ENTRY(xscale_dma_inv_range)
  294. tst r0, #CACHELINESIZE - 1
  295. bic r0, r0, #CACHELINESIZE - 1
  296. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  297. tst r1, #CACHELINESIZE - 1
  298. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  299. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  300. add r0, r0, #CACHELINESIZE
  301. cmp r0, r1
  302. blo 1b
  303. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  304. mov pc, lr
  305. /*
  306. * dma_clean_range(start, end)
  307. *
  308. * Clean the specified virtual address range.
  309. *
  310. * - start - virtual start address
  311. * - end - virtual end address
  312. */
  313. ENTRY(xscale_dma_clean_range)
  314. bic r0, r0, #CACHELINESIZE - 1
  315. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  316. add r0, r0, #CACHELINESIZE
  317. cmp r0, r1
  318. blo 1b
  319. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  320. mov pc, lr
  321. /*
  322. * dma_flush_range(start, end)
  323. *
  324. * Clean and invalidate the specified virtual address range.
  325. *
  326. * - start - virtual start address
  327. * - end - virtual end address
  328. */
  329. ENTRY(xscale_dma_flush_range)
  330. bic r0, r0, #CACHELINESIZE - 1
  331. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  332. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  333. add r0, r0, #CACHELINESIZE
  334. cmp r0, r1
  335. blo 1b
  336. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  337. mov pc, lr
  338. ENTRY(xscale_cache_fns)
  339. .long xscale_flush_kern_cache_all
  340. .long xscale_flush_user_cache_all
  341. .long xscale_flush_user_cache_range
  342. .long xscale_coherent_kern_range
  343. .long xscale_coherent_user_range
  344. .long xscale_flush_kern_dcache_page
  345. .long xscale_dma_inv_range
  346. .long xscale_dma_clean_range
  347. .long xscale_dma_flush_range
  348. /*
  349. * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
  350. * clear the dirty bits, which means that if we invalidate a dirty line,
  351. * the dirty data can still be written back to external memory later on.
  352. *
  353. * The recommended workaround is to always do a clean D-cache line before
  354. * doing an invalidate D-cache line, so on the affected processors,
  355. * dma_inv_range() is implemented as dma_flush_range().
  356. *
  357. * See erratum #25 of "Intel 80200 Processor Specification Update",
  358. * revision January 22, 2003, available at:
  359. * http://www.intel.com/design/iio/specupdt/273415.htm
  360. */
  361. ENTRY(xscale_80200_A0_A1_cache_fns)
  362. .long xscale_flush_kern_cache_all
  363. .long xscale_flush_user_cache_all
  364. .long xscale_flush_user_cache_range
  365. .long xscale_coherent_kern_range
  366. .long xscale_coherent_user_range
  367. .long xscale_flush_kern_dcache_page
  368. .long xscale_dma_flush_range
  369. .long xscale_dma_clean_range
  370. .long xscale_dma_flush_range
  371. ENTRY(cpu_xscale_dcache_clean_area)
  372. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  373. add r0, r0, #CACHELINESIZE
  374. subs r1, r1, #CACHELINESIZE
  375. bhi 1b
  376. mov pc, lr
  377. /* =============================== PageTable ============================== */
  378. #define PTE_CACHE_WRITE_ALLOCATE 0
  379. /*
  380. * cpu_xscale_switch_mm(pgd)
  381. *
  382. * Set the translation base pointer to be as described by pgd.
  383. *
  384. * pgd: new page tables
  385. */
  386. .align 5
  387. ENTRY(cpu_xscale_switch_mm)
  388. clean_d_cache r1, r2
  389. mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
  390. mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  391. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  392. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  393. cpwait_ret lr, ip
  394. /*
  395. * cpu_xscale_set_pte_ext(ptep, pte, ext)
  396. *
  397. * Set a PTE and flush it out
  398. *
  399. * Errata 40: must set memory to write-through for user read-only pages.
  400. */
  401. .align 5
  402. ENTRY(cpu_xscale_set_pte_ext)
  403. str r1, [r0], #-2048 @ linux version
  404. bic r2, r1, #0xff0
  405. orr r2, r2, #PTE_TYPE_EXT @ extended page
  406. eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  407. tst r3, #L_PTE_USER @ User?
  408. orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
  409. tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  410. orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
  411. @ combined with user -> user r/w
  412. @
  413. @ Handle the X bit. We want to set this bit for the minicache
  414. @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
  415. @ and we have a writeable, cacheable region. If we ignore the
  416. @ U and E bits, we can allow user space to use the minicache as
  417. @ well.
  418. @
  419. @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
  420. @
  421. eor ip, r1, #L_PTE_CACHEABLE
  422. tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
  423. #if PTE_CACHE_WRITE_ALLOCATE
  424. eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
  425. tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
  426. #endif
  427. orreq r2, r2, #PTE_EXT_TEX(1)
  428. @
  429. @ Erratum 40: The B bit must be cleared for a user read-only
  430. @ cacheable page.
  431. @
  432. @ B = B & ~(U & C & ~W)
  433. @
  434. and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
  435. teq ip, #L_PTE_USER | L_PTE_CACHEABLE
  436. biceq r2, r2, #PTE_BUFFERABLE
  437. tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  438. movne r2, #0 @ no -> fault
  439. str r2, [r0] @ hardware version
  440. mov ip, #0
  441. mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
  442. mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  443. mov pc, lr
  444. .ltorg
  445. .align
  446. __INIT
  447. .type __xscale_setup, #function
  448. __xscale_setup:
  449. mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
  450. mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  451. mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
  452. mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
  453. orr r0, r0, #1 << 13 @ Its undefined whether this
  454. mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
  455. adr r5, xscale_crval
  456. ldmia r5, {r5, r6}
  457. mrc p15, 0, r0, c1, c0, 0 @ get control register
  458. bic r0, r0, r5
  459. orr r0, r0, r6
  460. mov pc, lr
  461. .size __xscale_setup, . - __xscale_setup
  462. /*
  463. * R
  464. * .RVI ZFRS BLDP WCAM
  465. * ..11 1.01 .... .101
  466. *
  467. */
  468. .type xscale_crval, #object
  469. xscale_crval:
  470. crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
  471. __INITDATA
  472. /*
  473. * Purpose : Function pointers used to access above functions - all calls
  474. * come through these
  475. */
  476. .type xscale_processor_functions, #object
  477. ENTRY(xscale_processor_functions)
  478. .word v5t_early_abort
  479. .word pabort_noifar
  480. .word cpu_xscale_proc_init
  481. .word cpu_xscale_proc_fin
  482. .word cpu_xscale_reset
  483. .word cpu_xscale_do_idle
  484. .word cpu_xscale_dcache_clean_area
  485. .word cpu_xscale_switch_mm
  486. .word cpu_xscale_set_pte_ext
  487. .size xscale_processor_functions, . - xscale_processor_functions
  488. .section ".rodata"
  489. .type cpu_arch_name, #object
  490. cpu_arch_name:
  491. .asciz "armv5te"
  492. .size cpu_arch_name, . - cpu_arch_name
  493. .type cpu_elf_name, #object
  494. cpu_elf_name:
  495. .asciz "v5"
  496. .size cpu_elf_name, . - cpu_elf_name
  497. .type cpu_80200_A0_A1_name, #object
  498. cpu_80200_A0_A1_name:
  499. .asciz "XScale-80200 A0/A1"
  500. .size cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
  501. .type cpu_80200_name, #object
  502. cpu_80200_name:
  503. .asciz "XScale-80200"
  504. .size cpu_80200_name, . - cpu_80200_name
  505. .type cpu_80219_name, #object
  506. cpu_80219_name:
  507. .asciz "XScale-80219"
  508. .size cpu_80219_name, . - cpu_80219_name
  509. .type cpu_8032x_name, #object
  510. cpu_8032x_name:
  511. .asciz "XScale-IOP8032x Family"
  512. .size cpu_8032x_name, . - cpu_8032x_name
  513. .type cpu_8033x_name, #object
  514. cpu_8033x_name:
  515. .asciz "XScale-IOP8033x Family"
  516. .size cpu_8033x_name, . - cpu_8033x_name
  517. .type cpu_pxa250_name, #object
  518. cpu_pxa250_name:
  519. .asciz "XScale-PXA250"
  520. .size cpu_pxa250_name, . - cpu_pxa250_name
  521. .type cpu_pxa210_name, #object
  522. cpu_pxa210_name:
  523. .asciz "XScale-PXA210"
  524. .size cpu_pxa210_name, . - cpu_pxa210_name
  525. .type cpu_ixp42x_name, #object
  526. cpu_ixp42x_name:
  527. .asciz "XScale-IXP42x Family"
  528. .size cpu_ixp42x_name, . - cpu_ixp42x_name
  529. .type cpu_ixp43x_name, #object
  530. cpu_ixp43x_name:
  531. .asciz "XScale-IXP43x Family"
  532. .size cpu_ixp43x_name, . - cpu_ixp43x_name
  533. .type cpu_ixp46x_name, #object
  534. cpu_ixp46x_name:
  535. .asciz "XScale-IXP46x Family"
  536. .size cpu_ixp46x_name, . - cpu_ixp46x_name
  537. .type cpu_ixp2400_name, #object
  538. cpu_ixp2400_name:
  539. .asciz "XScale-IXP2400"
  540. .size cpu_ixp2400_name, . - cpu_ixp2400_name
  541. .type cpu_ixp2800_name, #object
  542. cpu_ixp2800_name:
  543. .asciz "XScale-IXP2800"
  544. .size cpu_ixp2800_name, . - cpu_ixp2800_name
  545. .type cpu_pxa255_name, #object
  546. cpu_pxa255_name:
  547. .asciz "XScale-PXA255"
  548. .size cpu_pxa255_name, . - cpu_pxa255_name
  549. .type cpu_pxa270_name, #object
  550. cpu_pxa270_name:
  551. .asciz "XScale-PXA270"
  552. .size cpu_pxa270_name, . - cpu_pxa270_name
  553. .align
  554. .section ".proc.info.init", #alloc, #execinstr
  555. .type __80200_A0_A1_proc_info,#object
  556. __80200_A0_A1_proc_info:
  557. .long 0x69052000
  558. .long 0xfffffffe
  559. .long PMD_TYPE_SECT | \
  560. PMD_SECT_BUFFERABLE | \
  561. PMD_SECT_CACHEABLE | \
  562. PMD_SECT_AP_WRITE | \
  563. PMD_SECT_AP_READ
  564. .long PMD_TYPE_SECT | \
  565. PMD_SECT_AP_WRITE | \
  566. PMD_SECT_AP_READ
  567. b __xscale_setup
  568. .long cpu_arch_name
  569. .long cpu_elf_name
  570. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  571. .long cpu_80200_name
  572. .long xscale_processor_functions
  573. .long v4wbi_tlb_fns
  574. .long xscale_mc_user_fns
  575. .long xscale_80200_A0_A1_cache_fns
  576. .size __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
  577. .type __80200_proc_info,#object
  578. __80200_proc_info:
  579. .long 0x69052000
  580. .long 0xfffffff0
  581. .long PMD_TYPE_SECT | \
  582. PMD_SECT_BUFFERABLE | \
  583. PMD_SECT_CACHEABLE | \
  584. PMD_SECT_AP_WRITE | \
  585. PMD_SECT_AP_READ
  586. .long PMD_TYPE_SECT | \
  587. PMD_SECT_AP_WRITE | \
  588. PMD_SECT_AP_READ
  589. b __xscale_setup
  590. .long cpu_arch_name
  591. .long cpu_elf_name
  592. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  593. .long cpu_80200_name
  594. .long xscale_processor_functions
  595. .long v4wbi_tlb_fns
  596. .long xscale_mc_user_fns
  597. .long xscale_cache_fns
  598. .size __80200_proc_info, . - __80200_proc_info
  599. .type __80219_proc_info,#object
  600. __80219_proc_info:
  601. .long 0x69052e20
  602. .long 0xffffffe0
  603. .long PMD_TYPE_SECT | \
  604. PMD_SECT_BUFFERABLE | \
  605. PMD_SECT_CACHEABLE | \
  606. PMD_SECT_AP_WRITE | \
  607. PMD_SECT_AP_READ
  608. .long PMD_TYPE_SECT | \
  609. PMD_SECT_AP_WRITE | \
  610. PMD_SECT_AP_READ
  611. b __xscale_setup
  612. .long cpu_arch_name
  613. .long cpu_elf_name
  614. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  615. .long cpu_80219_name
  616. .long xscale_processor_functions
  617. .long v4wbi_tlb_fns
  618. .long xscale_mc_user_fns
  619. .long xscale_cache_fns
  620. .size __80219_proc_info, . - __80219_proc_info
  621. .type __8032x_proc_info,#object
  622. __8032x_proc_info:
  623. .long 0x69052420
  624. .long 0xfffff7e0
  625. .long PMD_TYPE_SECT | \
  626. PMD_SECT_BUFFERABLE | \
  627. PMD_SECT_CACHEABLE | \
  628. PMD_SECT_AP_WRITE | \
  629. PMD_SECT_AP_READ
  630. .long PMD_TYPE_SECT | \
  631. PMD_SECT_AP_WRITE | \
  632. PMD_SECT_AP_READ
  633. b __xscale_setup
  634. .long cpu_arch_name
  635. .long cpu_elf_name
  636. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  637. .long cpu_8032x_name
  638. .long xscale_processor_functions
  639. .long v4wbi_tlb_fns
  640. .long xscale_mc_user_fns
  641. .long xscale_cache_fns
  642. .size __8032x_proc_info, . - __8032x_proc_info
  643. .type __8033x_proc_info,#object
  644. __8033x_proc_info:
  645. .long 0x69054010
  646. .long 0xfffffd30
  647. .long PMD_TYPE_SECT | \
  648. PMD_SECT_BUFFERABLE | \
  649. PMD_SECT_CACHEABLE | \
  650. PMD_SECT_AP_WRITE | \
  651. PMD_SECT_AP_READ
  652. .long PMD_TYPE_SECT | \
  653. PMD_SECT_AP_WRITE | \
  654. PMD_SECT_AP_READ
  655. b __xscale_setup
  656. .long cpu_arch_name
  657. .long cpu_elf_name
  658. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  659. .long cpu_8033x_name
  660. .long xscale_processor_functions
  661. .long v4wbi_tlb_fns
  662. .long xscale_mc_user_fns
  663. .long xscale_cache_fns
  664. .size __8033x_proc_info, . - __8033x_proc_info
  665. .type __pxa250_proc_info,#object
  666. __pxa250_proc_info:
  667. .long 0x69052100
  668. .long 0xfffff7f0
  669. .long PMD_TYPE_SECT | \
  670. PMD_SECT_BUFFERABLE | \
  671. PMD_SECT_CACHEABLE | \
  672. PMD_SECT_AP_WRITE | \
  673. PMD_SECT_AP_READ
  674. .long PMD_TYPE_SECT | \
  675. PMD_SECT_AP_WRITE | \
  676. PMD_SECT_AP_READ
  677. b __xscale_setup
  678. .long cpu_arch_name
  679. .long cpu_elf_name
  680. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  681. .long cpu_pxa250_name
  682. .long xscale_processor_functions
  683. .long v4wbi_tlb_fns
  684. .long xscale_mc_user_fns
  685. .long xscale_cache_fns
  686. .size __pxa250_proc_info, . - __pxa250_proc_info
  687. .type __pxa210_proc_info,#object
  688. __pxa210_proc_info:
  689. .long 0x69052120
  690. .long 0xfffff3f0
  691. .long PMD_TYPE_SECT | \
  692. PMD_SECT_BUFFERABLE | \
  693. PMD_SECT_CACHEABLE | \
  694. PMD_SECT_AP_WRITE | \
  695. PMD_SECT_AP_READ
  696. .long PMD_TYPE_SECT | \
  697. PMD_SECT_AP_WRITE | \
  698. PMD_SECT_AP_READ
  699. b __xscale_setup
  700. .long cpu_arch_name
  701. .long cpu_elf_name
  702. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  703. .long cpu_pxa210_name
  704. .long xscale_processor_functions
  705. .long v4wbi_tlb_fns
  706. .long xscale_mc_user_fns
  707. .long xscale_cache_fns
  708. .size __pxa210_proc_info, . - __pxa210_proc_info
  709. .type __ixp2400_proc_info, #object
  710. __ixp2400_proc_info:
  711. .long 0x69054190
  712. .long 0xfffffff0
  713. .long PMD_TYPE_SECT | \
  714. PMD_SECT_BUFFERABLE | \
  715. PMD_SECT_CACHEABLE | \
  716. PMD_SECT_AP_WRITE | \
  717. PMD_SECT_AP_READ
  718. .long PMD_TYPE_SECT | \
  719. PMD_SECT_AP_WRITE | \
  720. PMD_SECT_AP_READ
  721. b __xscale_setup
  722. .long cpu_arch_name
  723. .long cpu_elf_name
  724. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  725. .long cpu_ixp2400_name
  726. .long xscale_processor_functions
  727. .long v4wbi_tlb_fns
  728. .long xscale_mc_user_fns
  729. .long xscale_cache_fns
  730. .size __ixp2400_proc_info, . - __ixp2400_proc_info
  731. .type __ixp2800_proc_info, #object
  732. __ixp2800_proc_info:
  733. .long 0x690541a0
  734. .long 0xfffffff0
  735. .long PMD_TYPE_SECT | \
  736. PMD_SECT_BUFFERABLE | \
  737. PMD_SECT_CACHEABLE | \
  738. PMD_SECT_AP_WRITE | \
  739. PMD_SECT_AP_READ
  740. .long PMD_TYPE_SECT | \
  741. PMD_SECT_AP_WRITE | \
  742. PMD_SECT_AP_READ
  743. b __xscale_setup
  744. .long cpu_arch_name
  745. .long cpu_elf_name
  746. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  747. .long cpu_ixp2800_name
  748. .long xscale_processor_functions
  749. .long v4wbi_tlb_fns
  750. .long xscale_mc_user_fns
  751. .long xscale_cache_fns
  752. .size __ixp2800_proc_info, . - __ixp2800_proc_info
  753. .type __ixp42x_proc_info, #object
  754. __ixp42x_proc_info:
  755. .long 0x690541c0
  756. .long 0xffffffc0
  757. .long PMD_TYPE_SECT | \
  758. PMD_SECT_BUFFERABLE | \
  759. PMD_SECT_CACHEABLE | \
  760. PMD_SECT_AP_WRITE | \
  761. PMD_SECT_AP_READ
  762. .long PMD_TYPE_SECT | \
  763. PMD_SECT_AP_WRITE | \
  764. PMD_SECT_AP_READ
  765. b __xscale_setup
  766. .long cpu_arch_name
  767. .long cpu_elf_name
  768. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  769. .long cpu_ixp42x_name
  770. .long xscale_processor_functions
  771. .long v4wbi_tlb_fns
  772. .long xscale_mc_user_fns
  773. .long xscale_cache_fns
  774. .size __ixp42x_proc_info, . - __ixp42x_proc_info
  775. .type __ixp43x_proc_info, #object
  776. __ixp43x_proc_info:
  777. .long 0x69054040
  778. .long 0xfffffff0
  779. .long PMD_TYPE_SECT | \
  780. PMD_SECT_BUFFERABLE | \
  781. PMD_SECT_CACHEABLE | \
  782. PMD_SECT_AP_WRITE | \
  783. PMD_SECT_AP_READ
  784. .long PMD_TYPE_SECT | \
  785. PMD_SECT_AP_WRITE | \
  786. PMD_SECT_AP_READ
  787. b __xscale_setup
  788. .long cpu_arch_name
  789. .long cpu_elf_name
  790. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  791. .long cpu_ixp43x_name
  792. .long xscale_processor_functions
  793. .long v4wbi_tlb_fns
  794. .long xscale_mc_user_fns
  795. .long xscale_cache_fns
  796. .size __ixp43x_proc_info, . - __ixp43x_proc_info
  797. .type __ixp46x_proc_info, #object
  798. __ixp46x_proc_info:
  799. .long 0x69054200
  800. .long 0xffffff00
  801. .long PMD_TYPE_SECT | \
  802. PMD_SECT_BUFFERABLE | \
  803. PMD_SECT_CACHEABLE | \
  804. PMD_SECT_AP_WRITE | \
  805. PMD_SECT_AP_READ
  806. .long PMD_TYPE_SECT | \
  807. PMD_SECT_AP_WRITE | \
  808. PMD_SECT_AP_READ
  809. b __xscale_setup
  810. .long cpu_arch_name
  811. .long cpu_elf_name
  812. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  813. .long cpu_ixp46x_name
  814. .long xscale_processor_functions
  815. .long v4wbi_tlb_fns
  816. .long xscale_mc_user_fns
  817. .long xscale_cache_fns
  818. .size __ixp46x_proc_info, . - __ixp46x_proc_info
  819. .type __pxa255_proc_info,#object
  820. __pxa255_proc_info:
  821. .long 0x69052d00
  822. .long 0xfffffff0
  823. .long PMD_TYPE_SECT | \
  824. PMD_SECT_BUFFERABLE | \
  825. PMD_SECT_CACHEABLE | \
  826. PMD_SECT_AP_WRITE | \
  827. PMD_SECT_AP_READ
  828. .long PMD_TYPE_SECT | \
  829. PMD_SECT_AP_WRITE | \
  830. PMD_SECT_AP_READ
  831. b __xscale_setup
  832. .long cpu_arch_name
  833. .long cpu_elf_name
  834. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  835. .long cpu_pxa255_name
  836. .long xscale_processor_functions
  837. .long v4wbi_tlb_fns
  838. .long xscale_mc_user_fns
  839. .long xscale_cache_fns
  840. .size __pxa255_proc_info, . - __pxa255_proc_info
  841. .type __pxa270_proc_info,#object
  842. __pxa270_proc_info:
  843. .long 0x69054110
  844. .long 0xfffffff0
  845. .long PMD_TYPE_SECT | \
  846. PMD_SECT_BUFFERABLE | \
  847. PMD_SECT_CACHEABLE | \
  848. PMD_SECT_AP_WRITE | \
  849. PMD_SECT_AP_READ
  850. .long PMD_TYPE_SECT | \
  851. PMD_SECT_AP_WRITE | \
  852. PMD_SECT_AP_READ
  853. b __xscale_setup
  854. .long cpu_arch_name
  855. .long cpu_elf_name
  856. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  857. .long cpu_pxa270_name
  858. .long xscale_processor_functions
  859. .long v4wbi_tlb_fns
  860. .long xscale_mc_user_fns
  861. .long xscale_cache_fns
  862. .size __pxa270_proc_info, . - __pxa270_proc_info