proc-feroceon.S 12 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
  3. *
  4. * Heavily based on proc-arm926.S
  5. * Maintainer: Assaf Hoffman <hoffman@marvell.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/linkage.h>
  22. #include <linux/init.h>
  23. #include <asm/assembler.h>
  24. #include <asm/elf.h>
  25. #include <asm/pgtable-hwdef.h>
  26. #include <asm/pgtable.h>
  27. #include <asm/page.h>
  28. #include <asm/ptrace.h>
  29. #include "proc-macros.S"
  30. /*
  31. * This is the maximum size of an area which will be invalidated
  32. * using the single invalidate entry instructions. Anything larger
  33. * than this, and we go for the whole cache.
  34. *
  35. * This value should be chosen such that we choose the cheapest
  36. * alternative.
  37. */
  38. #define CACHE_DLIMIT 16384
  39. /*
  40. * the cache line size of the I and D cache
  41. */
  42. #define CACHE_DLINESIZE 32
  43. .text
  44. /*
  45. * cpu_feroceon_proc_init()
  46. */
  47. ENTRY(cpu_feroceon_proc_init)
  48. mov pc, lr
  49. /*
  50. * cpu_feroceon_proc_fin()
  51. */
  52. ENTRY(cpu_feroceon_proc_fin)
  53. stmfd sp!, {lr}
  54. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  55. msr cpsr_c, ip
  56. bl feroceon_flush_kern_cache_all
  57. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  58. bic r0, r0, #0x1000 @ ...i............
  59. bic r0, r0, #0x000e @ ............wca.
  60. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  61. ldmfd sp!, {pc}
  62. /*
  63. * cpu_feroceon_reset(loc)
  64. *
  65. * Perform a soft reset of the system. Put the CPU into the
  66. * same state as it would be if it had been reset, and branch
  67. * to what would be the reset vector.
  68. *
  69. * loc: location to jump to for soft reset
  70. */
  71. .align 5
  72. ENTRY(cpu_feroceon_reset)
  73. mov ip, #0
  74. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  75. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  76. #ifdef CONFIG_MMU
  77. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  78. #endif
  79. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  80. bic ip, ip, #0x000f @ ............wcam
  81. bic ip, ip, #0x1100 @ ...i...s........
  82. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  83. mov pc, r0
  84. /*
  85. * cpu_feroceon_do_idle()
  86. *
  87. * Called with IRQs disabled
  88. */
  89. .align 5
  90. ENTRY(cpu_feroceon_do_idle)
  91. mov r0, #0
  92. mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
  93. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  94. mov pc, lr
  95. /*
  96. * flush_user_cache_all()
  97. *
  98. * Clean and invalidate all cache entries in a particular
  99. * address space.
  100. */
  101. .align 5
  102. ENTRY(feroceon_flush_user_cache_all)
  103. /* FALLTHROUGH */
  104. /*
  105. * flush_kern_cache_all()
  106. *
  107. * Clean and invalidate the entire cache.
  108. */
  109. ENTRY(feroceon_flush_kern_cache_all)
  110. mov r2, #VM_EXEC
  111. mov ip, #0
  112. __flush_whole_cache:
  113. 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
  114. bne 1b
  115. tst r2, #VM_EXEC
  116. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  117. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  118. mov pc, lr
  119. /*
  120. * flush_user_cache_range(start, end, flags)
  121. *
  122. * Clean and invalidate a range of cache entries in the
  123. * specified address range.
  124. *
  125. * - start - start address (inclusive)
  126. * - end - end address (exclusive)
  127. * - flags - vm_flags describing address space
  128. */
  129. .align 5
  130. ENTRY(feroceon_flush_user_cache_range)
  131. mov ip, #0
  132. sub r3, r1, r0 @ calculate total size
  133. cmp r3, #CACHE_DLIMIT
  134. bgt __flush_whole_cache
  135. 1: tst r2, #VM_EXEC
  136. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  137. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  138. add r0, r0, #CACHE_DLINESIZE
  139. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  140. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  141. add r0, r0, #CACHE_DLINESIZE
  142. cmp r0, r1
  143. blo 1b
  144. tst r2, #VM_EXEC
  145. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  146. mov pc, lr
  147. /*
  148. * coherent_kern_range(start, end)
  149. *
  150. * Ensure coherency between the Icache and the Dcache in the
  151. * region described by start, end. If you have non-snooping
  152. * Harvard caches, you need to implement this function.
  153. *
  154. * - start - virtual start address
  155. * - end - virtual end address
  156. */
  157. .align 5
  158. ENTRY(feroceon_coherent_kern_range)
  159. /* FALLTHROUGH */
  160. /*
  161. * coherent_user_range(start, end)
  162. *
  163. * Ensure coherency between the Icache and the Dcache in the
  164. * region described by start, end. If you have non-snooping
  165. * Harvard caches, you need to implement this function.
  166. *
  167. * - start - virtual start address
  168. * - end - virtual end address
  169. */
  170. ENTRY(feroceon_coherent_user_range)
  171. bic r0, r0, #CACHE_DLINESIZE - 1
  172. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  173. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  174. add r0, r0, #CACHE_DLINESIZE
  175. cmp r0, r1
  176. blo 1b
  177. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  178. mov pc, lr
  179. /*
  180. * flush_kern_dcache_page(void *page)
  181. *
  182. * Ensure no D cache aliasing occurs, either with itself or
  183. * the I cache
  184. *
  185. * - addr - page aligned address
  186. */
  187. .align 5
  188. ENTRY(feroceon_flush_kern_dcache_page)
  189. add r1, r0, #PAGE_SZ
  190. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  191. add r0, r0, #CACHE_DLINESIZE
  192. cmp r0, r1
  193. blo 1b
  194. mov r0, #0
  195. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  196. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  197. mov pc, lr
  198. /*
  199. * dma_inv_range(start, end)
  200. *
  201. * Invalidate (discard) the specified virtual address range.
  202. * May not write back any entries. If 'start' or 'end'
  203. * are not cache line aligned, those lines must be written
  204. * back.
  205. *
  206. * - start - virtual start address
  207. * - end - virtual end address
  208. *
  209. * (same as v4wb)
  210. */
  211. .align 5
  212. ENTRY(feroceon_dma_inv_range)
  213. tst r0, #CACHE_DLINESIZE - 1
  214. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  215. tst r1, #CACHE_DLINESIZE - 1
  216. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  217. bic r0, r0, #CACHE_DLINESIZE - 1
  218. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  219. add r0, r0, #CACHE_DLINESIZE
  220. cmp r0, r1
  221. blo 1b
  222. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  223. mov pc, lr
  224. /*
  225. * dma_clean_range(start, end)
  226. *
  227. * Clean the specified virtual address range.
  228. *
  229. * - start - virtual start address
  230. * - end - virtual end address
  231. *
  232. * (same as v4wb)
  233. */
  234. .align 5
  235. ENTRY(feroceon_dma_clean_range)
  236. bic r0, r0, #CACHE_DLINESIZE - 1
  237. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  238. add r0, r0, #CACHE_DLINESIZE
  239. cmp r0, r1
  240. blo 1b
  241. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  242. mov pc, lr
  243. /*
  244. * dma_flush_range(start, end)
  245. *
  246. * Clean and invalidate the specified virtual address range.
  247. *
  248. * - start - virtual start address
  249. * - end - virtual end address
  250. */
  251. .align 5
  252. ENTRY(feroceon_dma_flush_range)
  253. bic r0, r0, #CACHE_DLINESIZE - 1
  254. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  255. add r0, r0, #CACHE_DLINESIZE
  256. cmp r0, r1
  257. blo 1b
  258. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  259. mov pc, lr
  260. ENTRY(feroceon_cache_fns)
  261. .long feroceon_flush_kern_cache_all
  262. .long feroceon_flush_user_cache_all
  263. .long feroceon_flush_user_cache_range
  264. .long feroceon_coherent_kern_range
  265. .long feroceon_coherent_user_range
  266. .long feroceon_flush_kern_dcache_page
  267. .long feroceon_dma_inv_range
  268. .long feroceon_dma_clean_range
  269. .long feroceon_dma_flush_range
  270. .align 5
  271. ENTRY(cpu_feroceon_dcache_clean_area)
  272. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  273. add r0, r0, #CACHE_DLINESIZE
  274. subs r1, r1, #CACHE_DLINESIZE
  275. bhi 1b
  276. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  277. mov pc, lr
  278. /* =============================== PageTable ============================== */
  279. /*
  280. * cpu_feroceon_switch_mm(pgd)
  281. *
  282. * Set the translation base pointer to be as described by pgd.
  283. *
  284. * pgd: new page tables
  285. */
  286. .align 5
  287. ENTRY(cpu_feroceon_switch_mm)
  288. #ifdef CONFIG_MMU
  289. mov ip, #0
  290. @ && 'Clean & Invalidate whole DCache'
  291. 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
  292. bne 1b
  293. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  294. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  295. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  296. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  297. #endif
  298. mov pc, lr
  299. /*
  300. * cpu_feroceon_set_pte_ext(ptep, pte, ext)
  301. *
  302. * Set a PTE and flush it out
  303. */
  304. .align 5
  305. ENTRY(cpu_feroceon_set_pte_ext)
  306. #ifdef CONFIG_MMU
  307. str r1, [r0], #-2048 @ linux version
  308. eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  309. bic r2, r1, #PTE_SMALL_AP_MASK
  310. bic r2, r2, #PTE_TYPE_MASK
  311. orr r2, r2, #PTE_TYPE_SMALL
  312. tst r1, #L_PTE_USER @ User?
  313. orrne r2, r2, #PTE_SMALL_AP_URO_SRW
  314. tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  315. orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
  316. tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  317. movne r2, #0
  318. str r2, [r0] @ hardware version
  319. mov r0, r0
  320. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  321. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  322. #endif
  323. mov pc, lr
  324. __INIT
  325. .type __feroceon_setup, #function
  326. __feroceon_setup:
  327. mov r0, #0
  328. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  329. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  330. #ifdef CONFIG_MMU
  331. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  332. #endif
  333. adr r5, feroceon_crval
  334. ldmia r5, {r5, r6}
  335. mrc p15, 0, r0, c1, c0 @ get control register v4
  336. bic r0, r0, r5
  337. orr r0, r0, r6
  338. mov pc, lr
  339. .size __feroceon_setup, . - __feroceon_setup
  340. /*
  341. * R
  342. * .RVI ZFRS BLDP WCAM
  343. * .011 0001 ..11 0101
  344. *
  345. */
  346. .type feroceon_crval, #object
  347. feroceon_crval:
  348. crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
  349. __INITDATA
  350. /*
  351. * Purpose : Function pointers used to access above functions - all calls
  352. * come through these
  353. */
  354. .type feroceon_processor_functions, #object
  355. feroceon_processor_functions:
  356. .word v5t_early_abort
  357. .word pabort_noifar
  358. .word cpu_feroceon_proc_init
  359. .word cpu_feroceon_proc_fin
  360. .word cpu_feroceon_reset
  361. .word cpu_feroceon_do_idle
  362. .word cpu_feroceon_dcache_clean_area
  363. .word cpu_feroceon_switch_mm
  364. .word cpu_feroceon_set_pte_ext
  365. .size feroceon_processor_functions, . - feroceon_processor_functions
  366. .section ".rodata"
  367. .type cpu_arch_name, #object
  368. cpu_arch_name:
  369. .asciz "armv5te"
  370. .size cpu_arch_name, . - cpu_arch_name
  371. .type cpu_elf_name, #object
  372. cpu_elf_name:
  373. .asciz "v5"
  374. .size cpu_elf_name, . - cpu_elf_name
  375. .type cpu_feroceon_name, #object
  376. cpu_feroceon_name:
  377. .asciz "Feroceon"
  378. .size cpu_feroceon_name, . - cpu_feroceon_name
  379. .align
  380. .section ".proc.info.init", #alloc, #execinstr
  381. #ifdef CONFIG_CPU_FEROCEON_OLD_ID
  382. .type __feroceon_old_id_proc_info,#object
  383. __feroceon_old_id_proc_info:
  384. .long 0x41069260
  385. .long 0xfffffff0
  386. .long PMD_TYPE_SECT | \
  387. PMD_SECT_BUFFERABLE | \
  388. PMD_SECT_CACHEABLE | \
  389. PMD_BIT4 | \
  390. PMD_SECT_AP_WRITE | \
  391. PMD_SECT_AP_READ
  392. .long PMD_TYPE_SECT | \
  393. PMD_BIT4 | \
  394. PMD_SECT_AP_WRITE | \
  395. PMD_SECT_AP_READ
  396. b __feroceon_setup
  397. .long cpu_arch_name
  398. .long cpu_elf_name
  399. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  400. .long cpu_feroceon_name
  401. .long feroceon_processor_functions
  402. .long v4wbi_tlb_fns
  403. .long feroceon_user_fns
  404. .long feroceon_cache_fns
  405. .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
  406. #endif
  407. .type __feroceon_proc_info,#object
  408. __feroceon_proc_info:
  409. .long 0x56055310
  410. .long 0xfffffff0
  411. .long PMD_TYPE_SECT | \
  412. PMD_SECT_BUFFERABLE | \
  413. PMD_SECT_CACHEABLE | \
  414. PMD_BIT4 | \
  415. PMD_SECT_AP_WRITE | \
  416. PMD_SECT_AP_READ
  417. .long PMD_TYPE_SECT | \
  418. PMD_BIT4 | \
  419. PMD_SECT_AP_WRITE | \
  420. PMD_SECT_AP_READ
  421. b __feroceon_setup
  422. .long cpu_arch_name
  423. .long cpu_elf_name
  424. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  425. .long cpu_feroceon_name
  426. .long feroceon_processor_functions
  427. .long v4wbi_tlb_fns
  428. .long feroceon_user_fns
  429. .long feroceon_cache_fns
  430. .size __feroceon_proc_info, . - __feroceon_proc_info