pxa3xx.c 13 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/pxa3xx.c
  3. *
  4. * code specific to pxa3xx aka Monahans
  5. *
  6. * Copyright (C) 2006 Marvell International Ltd.
  7. *
  8. * 2007-09-02: eric miao <eric.miao@marvell.com>
  9. * initial version
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/pm.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/irq.h>
  21. #include <linux/io.h>
  22. #include <linux/sysdev.h>
  23. #include <asm/hardware.h>
  24. #include <asm/arch/pxa3xx-regs.h>
  25. #include <asm/arch/ohci.h>
  26. #include <asm/arch/pm.h>
  27. #include <asm/arch/dma.h>
  28. #include <asm/arch/ssp.h>
  29. #include "generic.h"
  30. #include "devices.h"
  31. #include "clock.h"
  32. /* Crystal clock: 13MHz */
  33. #define BASE_CLK 13000000
  34. /* Ring Oscillator Clock: 60MHz */
  35. #define RO_CLK 60000000
  36. #define ACCR_D0CS (1 << 26)
  37. #define ACCR_PCCE (1 << 11)
  38. /* crystal frequency to static memory controller multiplier (SMCFS) */
  39. static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
  40. /* crystal frequency to HSIO bus frequency multiplier (HSS) */
  41. static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
  42. /*
  43. * Get the clock frequency as reflected by CCSR and the turbo flag.
  44. * We assume these values have been applied via a fcs.
  45. * If info is not 0 we also display the current settings.
  46. */
  47. unsigned int pxa3xx_get_clk_frequency_khz(int info)
  48. {
  49. unsigned long acsr, xclkcfg;
  50. unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
  51. /* Read XCLKCFG register turbo bit */
  52. __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
  53. t = xclkcfg & 0x1;
  54. acsr = ACSR;
  55. xl = acsr & 0x1f;
  56. xn = (acsr >> 8) & 0x7;
  57. hss = (acsr >> 14) & 0x3;
  58. XL = xl * BASE_CLK;
  59. XN = xn * XL;
  60. ro = acsr & ACCR_D0CS;
  61. CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
  62. HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
  63. if (info) {
  64. pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
  65. RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
  66. (ro) ? "" : "in");
  67. pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
  68. XL / 1000000, (XL % 1000000) / 10000, xl);
  69. pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
  70. XN / 1000000, (XN % 1000000) / 10000, xn,
  71. (t) ? "" : "in");
  72. pr_info("HSIO bus clock: %d.%02dMHz\n",
  73. HSS / 1000000, (HSS % 1000000) / 10000);
  74. }
  75. return CLK / 1000;
  76. }
  77. /*
  78. * Return the current static memory controller clock frequency
  79. * in units of 10kHz
  80. */
  81. unsigned int pxa3xx_get_memclk_frequency_10khz(void)
  82. {
  83. unsigned long acsr;
  84. unsigned int smcfs, clk = 0;
  85. acsr = ACSR;
  86. smcfs = (acsr >> 23) & 0x7;
  87. clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
  88. return (clk / 10000);
  89. }
  90. /*
  91. * Return the current AC97 clock frequency.
  92. */
  93. static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
  94. {
  95. unsigned long rate = 312000000;
  96. unsigned long ac97_div;
  97. ac97_div = AC97_DIV;
  98. /* This may loose precision for some rates but won't for the
  99. * standard 24.576MHz.
  100. */
  101. rate /= (ac97_div >> 12) & 0x7fff;
  102. rate *= (ac97_div & 0xfff);
  103. return rate;
  104. }
  105. /*
  106. * Return the current HSIO bus clock frequency
  107. */
  108. static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
  109. {
  110. unsigned long acsr;
  111. unsigned int hss, hsio_clk;
  112. acsr = ACSR;
  113. hss = (acsr >> 14) & 0x3;
  114. hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
  115. return hsio_clk;
  116. }
  117. static void clk_pxa3xx_cken_enable(struct clk *clk)
  118. {
  119. unsigned long mask = 1ul << (clk->cken & 0x1f);
  120. if (clk->cken < 32)
  121. CKENA |= mask;
  122. else
  123. CKENB |= mask;
  124. }
  125. static void clk_pxa3xx_cken_disable(struct clk *clk)
  126. {
  127. unsigned long mask = 1ul << (clk->cken & 0x1f);
  128. if (clk->cken < 32)
  129. CKENA &= ~mask;
  130. else
  131. CKENB &= ~mask;
  132. }
  133. static const struct clkops clk_pxa3xx_cken_ops = {
  134. .enable = clk_pxa3xx_cken_enable,
  135. .disable = clk_pxa3xx_cken_disable,
  136. };
  137. static const struct clkops clk_pxa3xx_hsio_ops = {
  138. .enable = clk_pxa3xx_cken_enable,
  139. .disable = clk_pxa3xx_cken_disable,
  140. .getrate = clk_pxa3xx_hsio_getrate,
  141. };
  142. static const struct clkops clk_pxa3xx_ac97_ops = {
  143. .enable = clk_pxa3xx_cken_enable,
  144. .disable = clk_pxa3xx_cken_disable,
  145. .getrate = clk_pxa3xx_ac97_getrate,
  146. };
  147. static void clk_pout_enable(struct clk *clk)
  148. {
  149. OSCC |= OSCC_PEN;
  150. }
  151. static void clk_pout_disable(struct clk *clk)
  152. {
  153. OSCC &= ~OSCC_PEN;
  154. }
  155. static const struct clkops clk_pout_ops = {
  156. .enable = clk_pout_enable,
  157. .disable = clk_pout_disable,
  158. };
  159. #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \
  160. { \
  161. .name = _name, \
  162. .dev = _dev, \
  163. .ops = &clk_pxa3xx_cken_ops, \
  164. .rate = _rate, \
  165. .cken = CKEN_##_cken, \
  166. .delay = _delay, \
  167. }
  168. #define PXA3xx_CK(_name, _cken, _ops, _dev) \
  169. { \
  170. .name = _name, \
  171. .dev = _dev, \
  172. .ops = _ops, \
  173. .cken = CKEN_##_cken, \
  174. }
  175. static struct clk pxa3xx_clks[] = {
  176. {
  177. .name = "CLK_POUT",
  178. .ops = &clk_pout_ops,
  179. .rate = 13000000,
  180. .delay = 70,
  181. },
  182. PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
  183. PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
  184. PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL),
  185. PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
  186. PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
  187. PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
  188. PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
  189. PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
  190. PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
  191. PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev),
  192. PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
  193. PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
  194. PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
  195. PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
  196. PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
  197. PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
  198. PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
  199. };
  200. #ifdef CONFIG_PM
  201. #define ISRAM_START 0x5c000000
  202. #define ISRAM_SIZE SZ_256K
  203. static void __iomem *sram;
  204. static unsigned long wakeup_src;
  205. #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
  206. #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
  207. enum { SLEEP_SAVE_CKENA,
  208. SLEEP_SAVE_CKENB,
  209. SLEEP_SAVE_ACCR,
  210. SLEEP_SAVE_COUNT,
  211. };
  212. static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
  213. {
  214. SAVE(CKENA);
  215. SAVE(CKENB);
  216. SAVE(ACCR);
  217. }
  218. static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
  219. {
  220. RESTORE(ACCR);
  221. RESTORE(CKENA);
  222. RESTORE(CKENB);
  223. }
  224. /*
  225. * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
  226. * memory controller has to be reinitialised, so we place some code
  227. * in the SRAM to perform this function.
  228. *
  229. * We disable FIQs across the standby - otherwise, we might receive a
  230. * FIQ while the SDRAM is unavailable.
  231. */
  232. static void pxa3xx_cpu_standby(unsigned int pwrmode)
  233. {
  234. extern const char pm_enter_standby_start[], pm_enter_standby_end[];
  235. void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
  236. memcpy_toio(sram + 0x8000, pm_enter_standby_start,
  237. pm_enter_standby_end - pm_enter_standby_start);
  238. AD2D0SR = ~0;
  239. AD2D1SR = ~0;
  240. AD2D0ER = wakeup_src;
  241. AD2D1ER = 0;
  242. ASCR = ASCR;
  243. ARSR = ARSR;
  244. local_fiq_disable();
  245. fn(pwrmode);
  246. local_fiq_enable();
  247. AD2D0ER = 0;
  248. AD2D1ER = 0;
  249. }
  250. /*
  251. * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
  252. * PXA3xx development kits assumes that the resuming process continues
  253. * with the address stored within the first 4 bytes of SDRAM. The PSPR
  254. * register is used privately by BootROM and OBM, and _must_ be set to
  255. * 0x5c014000 for the moment.
  256. */
  257. static void pxa3xx_cpu_pm_suspend(void)
  258. {
  259. volatile unsigned long *p = (volatile void *)0xc0000000;
  260. unsigned long saved_data = *p;
  261. extern void pxa3xx_cpu_suspend(void);
  262. extern void pxa3xx_cpu_resume(void);
  263. /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
  264. CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
  265. CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
  266. /* clear and setup wakeup source */
  267. AD3SR = ~0;
  268. AD3ER = wakeup_src;
  269. ASCR = ASCR;
  270. ARSR = ARSR;
  271. PCFR |= (1u << 13); /* L1_DIS */
  272. PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
  273. PSPR = 0x5c014000;
  274. /* overwrite with the resume address */
  275. *p = virt_to_phys(pxa3xx_cpu_resume);
  276. pxa3xx_cpu_suspend();
  277. *p = saved_data;
  278. AD3ER = 0;
  279. }
  280. static void pxa3xx_cpu_pm_enter(suspend_state_t state)
  281. {
  282. /*
  283. * Don't sleep if no wakeup sources are defined
  284. */
  285. if (wakeup_src == 0) {
  286. printk(KERN_ERR "Not suspending: no wakeup sources\n");
  287. return;
  288. }
  289. switch (state) {
  290. case PM_SUSPEND_STANDBY:
  291. pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
  292. break;
  293. case PM_SUSPEND_MEM:
  294. pxa3xx_cpu_pm_suspend();
  295. break;
  296. }
  297. }
  298. static int pxa3xx_cpu_pm_valid(suspend_state_t state)
  299. {
  300. return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
  301. }
  302. static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
  303. .save_count = SLEEP_SAVE_COUNT,
  304. .save = pxa3xx_cpu_pm_save,
  305. .restore = pxa3xx_cpu_pm_restore,
  306. .valid = pxa3xx_cpu_pm_valid,
  307. .enter = pxa3xx_cpu_pm_enter,
  308. };
  309. static void __init pxa3xx_init_pm(void)
  310. {
  311. sram = ioremap(ISRAM_START, ISRAM_SIZE);
  312. if (!sram) {
  313. printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
  314. return;
  315. }
  316. /*
  317. * Since we copy wakeup code into the SRAM, we need to ensure
  318. * that it is preserved over the low power modes. Note: bit 8
  319. * is undocumented in the developer manual, but must be set.
  320. */
  321. AD1R |= ADXR_L2 | ADXR_R0;
  322. AD2R |= ADXR_L2 | ADXR_R0;
  323. AD3R |= ADXR_L2 | ADXR_R0;
  324. /*
  325. * Clear the resume enable registers.
  326. */
  327. AD1D0ER = 0;
  328. AD2D0ER = 0;
  329. AD2D1ER = 0;
  330. AD3ER = 0;
  331. pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
  332. }
  333. static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
  334. {
  335. unsigned long flags, mask = 0;
  336. switch (irq) {
  337. case IRQ_SSP3:
  338. mask = ADXER_MFP_WSSP3;
  339. break;
  340. case IRQ_MSL:
  341. mask = ADXER_WMSL0;
  342. break;
  343. case IRQ_USBH2:
  344. case IRQ_USBH1:
  345. mask = ADXER_WUSBH;
  346. break;
  347. case IRQ_KEYPAD:
  348. mask = ADXER_WKP;
  349. break;
  350. case IRQ_AC97:
  351. mask = ADXER_MFP_WAC97;
  352. break;
  353. case IRQ_USIM:
  354. mask = ADXER_WUSIM0;
  355. break;
  356. case IRQ_SSP2:
  357. mask = ADXER_MFP_WSSP2;
  358. break;
  359. case IRQ_I2C:
  360. mask = ADXER_MFP_WI2C;
  361. break;
  362. case IRQ_STUART:
  363. mask = ADXER_MFP_WUART3;
  364. break;
  365. case IRQ_BTUART:
  366. mask = ADXER_MFP_WUART2;
  367. break;
  368. case IRQ_FFUART:
  369. mask = ADXER_MFP_WUART1;
  370. break;
  371. case IRQ_MMC:
  372. mask = ADXER_MFP_WMMC1;
  373. break;
  374. case IRQ_SSP:
  375. mask = ADXER_MFP_WSSP1;
  376. break;
  377. case IRQ_RTCAlrm:
  378. mask = ADXER_WRTC;
  379. break;
  380. case IRQ_SSP4:
  381. mask = ADXER_MFP_WSSP4;
  382. break;
  383. case IRQ_TSI:
  384. mask = ADXER_WTSI;
  385. break;
  386. case IRQ_USIM2:
  387. mask = ADXER_WUSIM1;
  388. break;
  389. case IRQ_MMC2:
  390. mask = ADXER_MFP_WMMC2;
  391. break;
  392. case IRQ_NAND:
  393. mask = ADXER_MFP_WFLASH;
  394. break;
  395. case IRQ_USB2:
  396. mask = ADXER_WUSB2;
  397. break;
  398. case IRQ_WAKEUP0:
  399. mask = ADXER_WEXTWAKE0;
  400. break;
  401. case IRQ_WAKEUP1:
  402. mask = ADXER_WEXTWAKE1;
  403. break;
  404. case IRQ_MMC3:
  405. mask = ADXER_MFP_GEN12;
  406. break;
  407. default:
  408. return -EINVAL;
  409. }
  410. local_irq_save(flags);
  411. if (on)
  412. wakeup_src |= mask;
  413. else
  414. wakeup_src &= ~mask;
  415. local_irq_restore(flags);
  416. return 0;
  417. }
  418. #else
  419. static inline void pxa3xx_init_pm(void) {}
  420. #define pxa3xx_set_wake NULL
  421. #endif
  422. void __init pxa3xx_init_irq(void)
  423. {
  424. /* enable CP6 access */
  425. u32 value;
  426. __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
  427. value |= (1 << 6);
  428. __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
  429. pxa_init_irq(56, pxa3xx_set_wake);
  430. pxa_init_gpio(128, NULL);
  431. }
  432. /*
  433. * device registration specific to PXA3xx.
  434. */
  435. static struct platform_device *devices[] __initdata = {
  436. &pxa_device_udc,
  437. &pxa_device_ffuart,
  438. &pxa_device_btuart,
  439. &pxa_device_stuart,
  440. &pxa_device_i2s,
  441. &pxa_device_rtc,
  442. &pxa27x_device_ssp1,
  443. &pxa27x_device_ssp2,
  444. &pxa27x_device_ssp3,
  445. &pxa3xx_device_ssp4,
  446. };
  447. static struct sys_device pxa3xx_sysdev[] = {
  448. {
  449. .cls = &pxa_irq_sysclass,
  450. }, {
  451. .cls = &pxa3xx_mfp_sysclass,
  452. }, {
  453. .cls = &pxa_gpio_sysclass,
  454. },
  455. };
  456. static int __init pxa3xx_init(void)
  457. {
  458. int i, ret = 0;
  459. if (cpu_is_pxa3xx()) {
  460. /*
  461. * clear RDH bit every time after reset
  462. *
  463. * Note: the last 3 bits DxS are write-1-to-clear so carefully
  464. * preserve them here in case they will be referenced later
  465. */
  466. ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
  467. clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
  468. if ((ret = pxa_init_dma(32)))
  469. return ret;
  470. pxa3xx_init_pm();
  471. for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
  472. ret = sysdev_register(&pxa3xx_sysdev[i]);
  473. if (ret)
  474. pr_err("failed to register sysdev[%d]\n", i);
  475. }
  476. ret = platform_add_devices(devices, ARRAY_SIZE(devices));
  477. }
  478. return ret;
  479. }
  480. postcore_initcall(pxa3xx_init);