r8a66597-udc.c 40 KB

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  1. /*
  2. * R8A66597 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/clk.h>
  28. #include <linux/usb/ch9.h>
  29. #include <linux/usb/gadget.h>
  30. #include "r8a66597-udc.h"
  31. #define DRIVER_VERSION "2009-08-18"
  32. static const char udc_name[] = "r8a66597_udc";
  33. static const char *r8a66597_ep_name[] = {
  34. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
  35. "ep8", "ep9",
  36. };
  37. static void disable_controller(struct r8a66597 *r8a66597);
  38. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
  39. static void irq_packet_write(struct r8a66597_ep *ep,
  40. struct r8a66597_request *req);
  41. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  42. gfp_t gfp_flags);
  43. static void transfer_complete(struct r8a66597_ep *ep,
  44. struct r8a66597_request *req, int status);
  45. /*-------------------------------------------------------------------------*/
  46. static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
  47. {
  48. return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
  49. }
  50. static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  51. unsigned long reg)
  52. {
  53. u16 tmp;
  54. tmp = r8a66597_read(r8a66597, INTENB0);
  55. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  56. INTENB0);
  57. r8a66597_bset(r8a66597, (1 << pipenum), reg);
  58. r8a66597_write(r8a66597, tmp, INTENB0);
  59. }
  60. static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  61. unsigned long reg)
  62. {
  63. u16 tmp;
  64. tmp = r8a66597_read(r8a66597, INTENB0);
  65. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  66. INTENB0);
  67. r8a66597_bclr(r8a66597, (1 << pipenum), reg);
  68. r8a66597_write(r8a66597, tmp, INTENB0);
  69. }
  70. static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
  71. {
  72. r8a66597_bset(r8a66597, CTRE, INTENB0);
  73. r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
  74. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  75. }
  76. static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
  77. __releases(r8a66597->lock)
  78. __acquires(r8a66597->lock)
  79. {
  80. r8a66597_bclr(r8a66597, CTRE, INTENB0);
  81. r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
  82. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  83. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  84. spin_unlock(&r8a66597->lock);
  85. r8a66597->driver->disconnect(&r8a66597->gadget);
  86. spin_lock(&r8a66597->lock);
  87. disable_controller(r8a66597);
  88. INIT_LIST_HEAD(&r8a66597->ep[0].queue);
  89. }
  90. static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
  91. {
  92. u16 pid = 0;
  93. unsigned long offset;
  94. if (pipenum == 0)
  95. pid = r8a66597_read(r8a66597, DCPCTR) & PID;
  96. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  97. offset = get_pipectr_addr(pipenum);
  98. pid = r8a66597_read(r8a66597, offset) & PID;
  99. } else
  100. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  101. return pid;
  102. }
  103. static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
  104. u16 pid)
  105. {
  106. unsigned long offset;
  107. if (pipenum == 0)
  108. r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
  109. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  110. offset = get_pipectr_addr(pipenum);
  111. r8a66597_mdfy(r8a66597, pid, PID, offset);
  112. } else
  113. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  114. }
  115. static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
  116. {
  117. control_reg_set_pid(r8a66597, pipenum, PID_BUF);
  118. }
  119. static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
  120. {
  121. control_reg_set_pid(r8a66597, pipenum, PID_NAK);
  122. }
  123. static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
  124. {
  125. control_reg_set_pid(r8a66597, pipenum, PID_STALL);
  126. }
  127. static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
  128. {
  129. u16 ret = 0;
  130. unsigned long offset;
  131. if (pipenum == 0)
  132. ret = r8a66597_read(r8a66597, DCPCTR);
  133. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  134. offset = get_pipectr_addr(pipenum);
  135. ret = r8a66597_read(r8a66597, offset);
  136. } else
  137. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  138. return ret;
  139. }
  140. static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
  141. {
  142. unsigned long offset;
  143. pipe_stop(r8a66597, pipenum);
  144. if (pipenum == 0)
  145. r8a66597_bset(r8a66597, SQCLR, DCPCTR);
  146. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  147. offset = get_pipectr_addr(pipenum);
  148. r8a66597_bset(r8a66597, SQCLR, offset);
  149. } else
  150. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  151. }
  152. static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
  153. {
  154. u16 tmp;
  155. int size;
  156. if (pipenum == 0) {
  157. tmp = r8a66597_read(r8a66597, DCPCFG);
  158. if ((tmp & R8A66597_CNTMD) != 0)
  159. size = 256;
  160. else {
  161. tmp = r8a66597_read(r8a66597, DCPMAXP);
  162. size = tmp & MAXP;
  163. }
  164. } else {
  165. r8a66597_write(r8a66597, pipenum, PIPESEL);
  166. tmp = r8a66597_read(r8a66597, PIPECFG);
  167. if ((tmp & R8A66597_CNTMD) != 0) {
  168. tmp = r8a66597_read(r8a66597, PIPEBUF);
  169. size = ((tmp >> 10) + 1) * 64;
  170. } else {
  171. tmp = r8a66597_read(r8a66597, PIPEMAXP);
  172. size = tmp & MXPS;
  173. }
  174. }
  175. return size;
  176. }
  177. static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
  178. {
  179. if (r8a66597->pdata->on_chip)
  180. return MBW_32;
  181. else
  182. return MBW_16;
  183. }
  184. static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
  185. {
  186. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  187. if (ep->use_dma)
  188. return;
  189. r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
  190. ndelay(450);
  191. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  192. }
  193. static int pipe_buffer_setting(struct r8a66597 *r8a66597,
  194. struct r8a66597_pipe_info *info)
  195. {
  196. u16 bufnum = 0, buf_bsize = 0;
  197. u16 pipecfg = 0;
  198. if (info->pipe == 0)
  199. return -EINVAL;
  200. r8a66597_write(r8a66597, info->pipe, PIPESEL);
  201. if (info->dir_in)
  202. pipecfg |= R8A66597_DIR;
  203. pipecfg |= info->type;
  204. pipecfg |= info->epnum;
  205. switch (info->type) {
  206. case R8A66597_INT:
  207. bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
  208. buf_bsize = 0;
  209. break;
  210. case R8A66597_BULK:
  211. bufnum = r8a66597->bi_bufnum +
  212. (info->pipe - R8A66597_BASE_PIPENUM_BULK) * 16;
  213. r8a66597->bi_bufnum += 16;
  214. buf_bsize = 7;
  215. pipecfg |= R8A66597_DBLB;
  216. if (!info->dir_in)
  217. pipecfg |= R8A66597_SHTNAK;
  218. break;
  219. case R8A66597_ISO:
  220. bufnum = r8a66597->bi_bufnum +
  221. (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
  222. r8a66597->bi_bufnum += 16;
  223. buf_bsize = 7;
  224. break;
  225. }
  226. if (r8a66597->bi_bufnum > R8A66597_MAX_BUFNUM) {
  227. printk(KERN_ERR "r8a66597 pipe memory is insufficient(%d)\n",
  228. r8a66597->bi_bufnum);
  229. return -ENOMEM;
  230. }
  231. r8a66597_write(r8a66597, pipecfg, PIPECFG);
  232. r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
  233. r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
  234. if (info->interval)
  235. info->interval--;
  236. r8a66597_write(r8a66597, info->interval, PIPEPERI);
  237. return 0;
  238. }
  239. static void pipe_buffer_release(struct r8a66597 *r8a66597,
  240. struct r8a66597_pipe_info *info)
  241. {
  242. if (info->pipe == 0)
  243. return;
  244. switch (info->type) {
  245. case R8A66597_BULK:
  246. if (is_bulk_pipe(info->pipe))
  247. r8a66597->bi_bufnum -= 16;
  248. break;
  249. case R8A66597_ISO:
  250. if (is_isoc_pipe(info->pipe))
  251. r8a66597->bi_bufnum -= 16;
  252. break;
  253. }
  254. if (is_bulk_pipe(info->pipe))
  255. r8a66597->bulk--;
  256. else if (is_interrupt_pipe(info->pipe))
  257. r8a66597->interrupt--;
  258. else if (is_isoc_pipe(info->pipe)) {
  259. r8a66597->isochronous--;
  260. if (info->type == R8A66597_BULK)
  261. r8a66597->bulk--;
  262. } else
  263. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  264. info->pipe);
  265. }
  266. static void pipe_initialize(struct r8a66597_ep *ep)
  267. {
  268. struct r8a66597 *r8a66597 = ep->r8a66597;
  269. r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
  270. r8a66597_write(r8a66597, ACLRM, ep->pipectr);
  271. r8a66597_write(r8a66597, 0, ep->pipectr);
  272. r8a66597_write(r8a66597, SQCLR, ep->pipectr);
  273. if (ep->use_dma) {
  274. r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
  275. ndelay(450);
  276. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  277. }
  278. }
  279. static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
  280. struct r8a66597_ep *ep,
  281. const struct usb_endpoint_descriptor *desc,
  282. u16 pipenum, int dma)
  283. {
  284. ep->use_dma = 0;
  285. ep->fifoaddr = CFIFO;
  286. ep->fifosel = CFIFOSEL;
  287. ep->fifoctr = CFIFOCTR;
  288. ep->fifotrn = 0;
  289. ep->pipectr = get_pipectr_addr(pipenum);
  290. ep->pipenum = pipenum;
  291. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  292. r8a66597->pipenum2ep[pipenum] = ep;
  293. r8a66597->epaddr2ep[desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK]
  294. = ep;
  295. INIT_LIST_HEAD(&ep->queue);
  296. }
  297. static void r8a66597_ep_release(struct r8a66597_ep *ep)
  298. {
  299. struct r8a66597 *r8a66597 = ep->r8a66597;
  300. u16 pipenum = ep->pipenum;
  301. if (pipenum == 0)
  302. return;
  303. if (ep->use_dma)
  304. r8a66597->num_dma--;
  305. ep->pipenum = 0;
  306. ep->busy = 0;
  307. ep->use_dma = 0;
  308. }
  309. static int alloc_pipe_config(struct r8a66597_ep *ep,
  310. const struct usb_endpoint_descriptor *desc)
  311. {
  312. struct r8a66597 *r8a66597 = ep->r8a66597;
  313. struct r8a66597_pipe_info info;
  314. int dma = 0;
  315. unsigned char *counter;
  316. int ret;
  317. ep->desc = desc;
  318. if (ep->pipenum) /* already allocated pipe */
  319. return 0;
  320. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  321. case USB_ENDPOINT_XFER_BULK:
  322. if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
  323. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  324. printk(KERN_ERR "bulk pipe is insufficient\n");
  325. return -ENODEV;
  326. } else {
  327. info.pipe = R8A66597_BASE_PIPENUM_ISOC
  328. + r8a66597->isochronous;
  329. counter = &r8a66597->isochronous;
  330. }
  331. } else {
  332. info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
  333. counter = &r8a66597->bulk;
  334. }
  335. info.type = R8A66597_BULK;
  336. dma = 1;
  337. break;
  338. case USB_ENDPOINT_XFER_INT:
  339. if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
  340. printk(KERN_ERR "interrupt pipe is insufficient\n");
  341. return -ENODEV;
  342. }
  343. info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
  344. info.type = R8A66597_INT;
  345. counter = &r8a66597->interrupt;
  346. break;
  347. case USB_ENDPOINT_XFER_ISOC:
  348. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  349. printk(KERN_ERR "isochronous pipe is insufficient\n");
  350. return -ENODEV;
  351. }
  352. info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
  353. info.type = R8A66597_ISO;
  354. counter = &r8a66597->isochronous;
  355. break;
  356. default:
  357. printk(KERN_ERR "unexpect xfer type\n");
  358. return -EINVAL;
  359. }
  360. ep->type = info.type;
  361. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  362. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  363. info.interval = desc->bInterval;
  364. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  365. info.dir_in = 1;
  366. else
  367. info.dir_in = 0;
  368. ret = pipe_buffer_setting(r8a66597, &info);
  369. if (ret < 0) {
  370. printk(KERN_ERR "pipe_buffer_setting fail\n");
  371. return ret;
  372. }
  373. (*counter)++;
  374. if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
  375. r8a66597->bulk++;
  376. r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
  377. pipe_initialize(ep);
  378. return 0;
  379. }
  380. static int free_pipe_config(struct r8a66597_ep *ep)
  381. {
  382. struct r8a66597 *r8a66597 = ep->r8a66597;
  383. struct r8a66597_pipe_info info;
  384. info.pipe = ep->pipenum;
  385. info.type = ep->type;
  386. pipe_buffer_release(r8a66597, &info);
  387. r8a66597_ep_release(ep);
  388. return 0;
  389. }
  390. /*-------------------------------------------------------------------------*/
  391. static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
  392. {
  393. enable_irq_ready(r8a66597, pipenum);
  394. enable_irq_nrdy(r8a66597, pipenum);
  395. }
  396. static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
  397. {
  398. disable_irq_ready(r8a66597, pipenum);
  399. disable_irq_nrdy(r8a66597, pipenum);
  400. }
  401. /* if complete is true, gadget driver complete function is not call */
  402. static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
  403. {
  404. r8a66597->ep[0].internal_ccpl = ccpl;
  405. pipe_start(r8a66597, 0);
  406. r8a66597_bset(r8a66597, CCPL, DCPCTR);
  407. }
  408. static void start_ep0_write(struct r8a66597_ep *ep,
  409. struct r8a66597_request *req)
  410. {
  411. struct r8a66597 *r8a66597 = ep->r8a66597;
  412. pipe_change(r8a66597, ep->pipenum);
  413. r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
  414. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  415. if (req->req.length == 0) {
  416. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  417. pipe_start(r8a66597, 0);
  418. transfer_complete(ep, req, 0);
  419. } else {
  420. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  421. irq_ep0_write(ep, req);
  422. }
  423. }
  424. static void start_packet_write(struct r8a66597_ep *ep,
  425. struct r8a66597_request *req)
  426. {
  427. struct r8a66597 *r8a66597 = ep->r8a66597;
  428. u16 tmp;
  429. pipe_change(r8a66597, ep->pipenum);
  430. disable_irq_empty(r8a66597, ep->pipenum);
  431. pipe_start(r8a66597, ep->pipenum);
  432. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  433. if (unlikely((tmp & FRDY) == 0))
  434. pipe_irq_enable(r8a66597, ep->pipenum);
  435. else
  436. irq_packet_write(ep, req);
  437. }
  438. static void start_packet_read(struct r8a66597_ep *ep,
  439. struct r8a66597_request *req)
  440. {
  441. struct r8a66597 *r8a66597 = ep->r8a66597;
  442. u16 pipenum = ep->pipenum;
  443. if (ep->pipenum == 0) {
  444. r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
  445. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  446. pipe_start(r8a66597, pipenum);
  447. pipe_irq_enable(r8a66597, pipenum);
  448. } else {
  449. if (ep->use_dma) {
  450. r8a66597_bset(r8a66597, TRCLR, ep->fifosel);
  451. pipe_change(r8a66597, pipenum);
  452. r8a66597_bset(r8a66597, TRENB, ep->fifosel);
  453. r8a66597_write(r8a66597,
  454. (req->req.length + ep->ep.maxpacket - 1)
  455. / ep->ep.maxpacket,
  456. ep->fifotrn);
  457. }
  458. pipe_start(r8a66597, pipenum); /* trigger once */
  459. pipe_irq_enable(r8a66597, pipenum);
  460. }
  461. }
  462. static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
  463. {
  464. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  465. start_packet_write(ep, req);
  466. else
  467. start_packet_read(ep, req);
  468. }
  469. static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
  470. {
  471. u16 ctsq;
  472. ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
  473. switch (ctsq) {
  474. case CS_RDDS:
  475. start_ep0_write(ep, req);
  476. break;
  477. case CS_WRDS:
  478. start_packet_read(ep, req);
  479. break;
  480. case CS_WRND:
  481. control_end(ep->r8a66597, 0);
  482. break;
  483. default:
  484. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  485. break;
  486. }
  487. }
  488. static void init_controller(struct r8a66597 *r8a66597)
  489. {
  490. u16 vif = r8a66597->pdata->vif ? LDRV : 0;
  491. u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
  492. u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
  493. if (r8a66597->pdata->on_chip) {
  494. r8a66597_bset(r8a66597, 0x04, SYSCFG1);
  495. r8a66597_bset(r8a66597, HSE, SYSCFG0);
  496. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  497. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  498. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  499. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  500. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  501. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  502. DMA0CFG);
  503. } else {
  504. r8a66597_bset(r8a66597, vif | endian, PINCFG);
  505. r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
  506. r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
  507. XTAL, SYSCFG0);
  508. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  509. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  510. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  511. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  512. msleep(3);
  513. r8a66597_bset(r8a66597, PLLC, SYSCFG0);
  514. msleep(1);
  515. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  516. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  517. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  518. DMA0CFG);
  519. }
  520. }
  521. static void disable_controller(struct r8a66597 *r8a66597)
  522. {
  523. if (r8a66597->pdata->on_chip) {
  524. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  525. r8a66597_write(r8a66597, 0, INTENB0);
  526. r8a66597_write(r8a66597, 0, INTENB1);
  527. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  528. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  529. } else {
  530. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  531. udelay(1);
  532. r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
  533. udelay(1);
  534. udelay(1);
  535. r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
  536. }
  537. }
  538. static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
  539. {
  540. u16 tmp;
  541. if (!r8a66597->pdata->on_chip) {
  542. tmp = r8a66597_read(r8a66597, SYSCFG0);
  543. if (!(tmp & XCKE))
  544. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  545. }
  546. }
  547. static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
  548. {
  549. return list_entry(ep->queue.next, struct r8a66597_request, queue);
  550. }
  551. /*-------------------------------------------------------------------------*/
  552. static void transfer_complete(struct r8a66597_ep *ep,
  553. struct r8a66597_request *req, int status)
  554. __releases(r8a66597->lock)
  555. __acquires(r8a66597->lock)
  556. {
  557. int restart = 0;
  558. if (unlikely(ep->pipenum == 0)) {
  559. if (ep->internal_ccpl) {
  560. ep->internal_ccpl = 0;
  561. return;
  562. }
  563. }
  564. list_del_init(&req->queue);
  565. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  566. req->req.status = -ESHUTDOWN;
  567. else
  568. req->req.status = status;
  569. if (!list_empty(&ep->queue))
  570. restart = 1;
  571. spin_unlock(&ep->r8a66597->lock);
  572. req->req.complete(&ep->ep, &req->req);
  573. spin_lock(&ep->r8a66597->lock);
  574. if (restart) {
  575. req = get_request_from_ep(ep);
  576. if (ep->desc)
  577. start_packet(ep, req);
  578. }
  579. }
  580. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
  581. {
  582. int i;
  583. u16 tmp;
  584. unsigned bufsize;
  585. size_t size;
  586. void *buf;
  587. u16 pipenum = ep->pipenum;
  588. struct r8a66597 *r8a66597 = ep->r8a66597;
  589. pipe_change(r8a66597, pipenum);
  590. r8a66597_bset(r8a66597, ISEL, ep->fifosel);
  591. i = 0;
  592. do {
  593. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  594. if (i++ > 100000) {
  595. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
  596. "conflict. please power off this controller.");
  597. return;
  598. }
  599. ndelay(1);
  600. } while ((tmp & FRDY) == 0);
  601. /* prepare parameters */
  602. bufsize = get_buffer_size(r8a66597, pipenum);
  603. buf = req->req.buf + req->req.actual;
  604. size = min(bufsize, req->req.length - req->req.actual);
  605. /* write fifo */
  606. if (req->req.buf) {
  607. if (size > 0)
  608. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  609. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  610. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  611. }
  612. /* update parameters */
  613. req->req.actual += size;
  614. /* check transfer finish */
  615. if ((!req->req.zero && (req->req.actual == req->req.length))
  616. || (size % ep->ep.maxpacket)
  617. || (size == 0)) {
  618. disable_irq_ready(r8a66597, pipenum);
  619. disable_irq_empty(r8a66597, pipenum);
  620. } else {
  621. disable_irq_ready(r8a66597, pipenum);
  622. enable_irq_empty(r8a66597, pipenum);
  623. }
  624. pipe_start(r8a66597, pipenum);
  625. }
  626. static void irq_packet_write(struct r8a66597_ep *ep,
  627. struct r8a66597_request *req)
  628. {
  629. u16 tmp;
  630. unsigned bufsize;
  631. size_t size;
  632. void *buf;
  633. u16 pipenum = ep->pipenum;
  634. struct r8a66597 *r8a66597 = ep->r8a66597;
  635. pipe_change(r8a66597, pipenum);
  636. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  637. if (unlikely((tmp & FRDY) == 0)) {
  638. pipe_stop(r8a66597, pipenum);
  639. pipe_irq_disable(r8a66597, pipenum);
  640. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  641. return;
  642. }
  643. /* prepare parameters */
  644. bufsize = get_buffer_size(r8a66597, pipenum);
  645. buf = req->req.buf + req->req.actual;
  646. size = min(bufsize, req->req.length - req->req.actual);
  647. /* write fifo */
  648. if (req->req.buf) {
  649. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  650. if ((size == 0)
  651. || ((size % ep->ep.maxpacket) != 0)
  652. || ((bufsize != ep->ep.maxpacket)
  653. && (bufsize > size)))
  654. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  655. }
  656. /* update parameters */
  657. req->req.actual += size;
  658. /* check transfer finish */
  659. if ((!req->req.zero && (req->req.actual == req->req.length))
  660. || (size % ep->ep.maxpacket)
  661. || (size == 0)) {
  662. disable_irq_ready(r8a66597, pipenum);
  663. enable_irq_empty(r8a66597, pipenum);
  664. } else {
  665. disable_irq_empty(r8a66597, pipenum);
  666. pipe_irq_enable(r8a66597, pipenum);
  667. }
  668. }
  669. static void irq_packet_read(struct r8a66597_ep *ep,
  670. struct r8a66597_request *req)
  671. {
  672. u16 tmp;
  673. int rcv_len, bufsize, req_len;
  674. int size;
  675. void *buf;
  676. u16 pipenum = ep->pipenum;
  677. struct r8a66597 *r8a66597 = ep->r8a66597;
  678. int finish = 0;
  679. pipe_change(r8a66597, pipenum);
  680. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  681. if (unlikely((tmp & FRDY) == 0)) {
  682. req->req.status = -EPIPE;
  683. pipe_stop(r8a66597, pipenum);
  684. pipe_irq_disable(r8a66597, pipenum);
  685. printk(KERN_ERR "read fifo not ready");
  686. return;
  687. }
  688. /* prepare parameters */
  689. rcv_len = tmp & DTLN;
  690. bufsize = get_buffer_size(r8a66597, pipenum);
  691. buf = req->req.buf + req->req.actual;
  692. req_len = req->req.length - req->req.actual;
  693. if (rcv_len < bufsize)
  694. size = min(rcv_len, req_len);
  695. else
  696. size = min(bufsize, req_len);
  697. /* update parameters */
  698. req->req.actual += size;
  699. /* check transfer finish */
  700. if ((!req->req.zero && (req->req.actual == req->req.length))
  701. || (size % ep->ep.maxpacket)
  702. || (size == 0)) {
  703. pipe_stop(r8a66597, pipenum);
  704. pipe_irq_disable(r8a66597, pipenum);
  705. finish = 1;
  706. }
  707. /* read fifo */
  708. if (req->req.buf) {
  709. if (size == 0)
  710. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  711. else
  712. r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
  713. }
  714. if ((ep->pipenum != 0) && finish)
  715. transfer_complete(ep, req, 0);
  716. }
  717. static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
  718. {
  719. u16 check;
  720. u16 pipenum;
  721. struct r8a66597_ep *ep;
  722. struct r8a66597_request *req;
  723. if ((status & BRDY0) && (enb & BRDY0)) {
  724. r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
  725. r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
  726. ep = &r8a66597->ep[0];
  727. req = get_request_from_ep(ep);
  728. irq_packet_read(ep, req);
  729. } else {
  730. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  731. check = 1 << pipenum;
  732. if ((status & check) && (enb & check)) {
  733. r8a66597_write(r8a66597, ~check, BRDYSTS);
  734. ep = r8a66597->pipenum2ep[pipenum];
  735. req = get_request_from_ep(ep);
  736. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  737. irq_packet_write(ep, req);
  738. else
  739. irq_packet_read(ep, req);
  740. }
  741. }
  742. }
  743. }
  744. static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
  745. {
  746. u16 tmp;
  747. u16 check;
  748. u16 pipenum;
  749. struct r8a66597_ep *ep;
  750. struct r8a66597_request *req;
  751. if ((status & BEMP0) && (enb & BEMP0)) {
  752. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  753. ep = &r8a66597->ep[0];
  754. req = get_request_from_ep(ep);
  755. irq_ep0_write(ep, req);
  756. } else {
  757. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  758. check = 1 << pipenum;
  759. if ((status & check) && (enb & check)) {
  760. r8a66597_write(r8a66597, ~check, BEMPSTS);
  761. tmp = control_reg_get(r8a66597, pipenum);
  762. if ((tmp & INBUFM) == 0) {
  763. disable_irq_empty(r8a66597, pipenum);
  764. pipe_irq_disable(r8a66597, pipenum);
  765. pipe_stop(r8a66597, pipenum);
  766. ep = r8a66597->pipenum2ep[pipenum];
  767. req = get_request_from_ep(ep);
  768. if (!list_empty(&ep->queue))
  769. transfer_complete(ep, req, 0);
  770. }
  771. }
  772. }
  773. }
  774. }
  775. static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  776. __releases(r8a66597->lock)
  777. __acquires(r8a66597->lock)
  778. {
  779. struct r8a66597_ep *ep;
  780. u16 pid;
  781. u16 status = 0;
  782. u16 w_index = le16_to_cpu(ctrl->wIndex);
  783. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  784. case USB_RECIP_DEVICE:
  785. status = 1 << USB_DEVICE_SELF_POWERED;
  786. break;
  787. case USB_RECIP_INTERFACE:
  788. status = 0;
  789. break;
  790. case USB_RECIP_ENDPOINT:
  791. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  792. pid = control_reg_get_pid(r8a66597, ep->pipenum);
  793. if (pid == PID_STALL)
  794. status = 1 << USB_ENDPOINT_HALT;
  795. else
  796. status = 0;
  797. break;
  798. default:
  799. pipe_stall(r8a66597, 0);
  800. return; /* exit */
  801. }
  802. r8a66597->ep0_data = cpu_to_le16(status);
  803. r8a66597->ep0_req->buf = &r8a66597->ep0_data;
  804. r8a66597->ep0_req->length = 2;
  805. /* AV: what happens if we get called again before that gets through? */
  806. spin_unlock(&r8a66597->lock);
  807. r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_KERNEL);
  808. spin_lock(&r8a66597->lock);
  809. }
  810. static void clear_feature(struct r8a66597 *r8a66597,
  811. struct usb_ctrlrequest *ctrl)
  812. {
  813. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  814. case USB_RECIP_DEVICE:
  815. control_end(r8a66597, 1);
  816. break;
  817. case USB_RECIP_INTERFACE:
  818. control_end(r8a66597, 1);
  819. break;
  820. case USB_RECIP_ENDPOINT: {
  821. struct r8a66597_ep *ep;
  822. struct r8a66597_request *req;
  823. u16 w_index = le16_to_cpu(ctrl->wIndex);
  824. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  825. pipe_stop(r8a66597, ep->pipenum);
  826. control_reg_sqclr(r8a66597, ep->pipenum);
  827. control_end(r8a66597, 1);
  828. req = get_request_from_ep(ep);
  829. if (ep->busy) {
  830. ep->busy = 0;
  831. if (list_empty(&ep->queue))
  832. break;
  833. start_packet(ep, req);
  834. } else if (!list_empty(&ep->queue))
  835. pipe_start(r8a66597, ep->pipenum);
  836. }
  837. break;
  838. default:
  839. pipe_stall(r8a66597, 0);
  840. break;
  841. }
  842. }
  843. static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  844. {
  845. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  846. case USB_RECIP_DEVICE:
  847. control_end(r8a66597, 1);
  848. break;
  849. case USB_RECIP_INTERFACE:
  850. control_end(r8a66597, 1);
  851. break;
  852. case USB_RECIP_ENDPOINT: {
  853. struct r8a66597_ep *ep;
  854. u16 w_index = le16_to_cpu(ctrl->wIndex);
  855. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  856. pipe_stall(r8a66597, ep->pipenum);
  857. control_end(r8a66597, 1);
  858. }
  859. break;
  860. default:
  861. pipe_stall(r8a66597, 0);
  862. break;
  863. }
  864. }
  865. /* if return value is true, call class driver's setup() */
  866. static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  867. {
  868. u16 *p = (u16 *)ctrl;
  869. unsigned long offset = USBREQ;
  870. int i, ret = 0;
  871. /* read fifo */
  872. r8a66597_write(r8a66597, ~VALID, INTSTS0);
  873. for (i = 0; i < 4; i++)
  874. p[i] = r8a66597_read(r8a66597, offset + i*2);
  875. /* check request */
  876. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  877. switch (ctrl->bRequest) {
  878. case USB_REQ_GET_STATUS:
  879. get_status(r8a66597, ctrl);
  880. break;
  881. case USB_REQ_CLEAR_FEATURE:
  882. clear_feature(r8a66597, ctrl);
  883. break;
  884. case USB_REQ_SET_FEATURE:
  885. set_feature(r8a66597, ctrl);
  886. break;
  887. default:
  888. ret = 1;
  889. break;
  890. }
  891. } else
  892. ret = 1;
  893. return ret;
  894. }
  895. static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
  896. {
  897. u16 speed = get_usb_speed(r8a66597);
  898. switch (speed) {
  899. case HSMODE:
  900. r8a66597->gadget.speed = USB_SPEED_HIGH;
  901. break;
  902. case FSMODE:
  903. r8a66597->gadget.speed = USB_SPEED_FULL;
  904. break;
  905. default:
  906. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  907. printk(KERN_ERR "USB speed unknown\n");
  908. }
  909. }
  910. static void irq_device_state(struct r8a66597 *r8a66597)
  911. {
  912. u16 dvsq;
  913. dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
  914. r8a66597_write(r8a66597, ~DVST, INTSTS0);
  915. if (dvsq == DS_DFLT) {
  916. /* bus reset */
  917. r8a66597->driver->disconnect(&r8a66597->gadget);
  918. r8a66597_update_usb_speed(r8a66597);
  919. }
  920. if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
  921. r8a66597_update_usb_speed(r8a66597);
  922. if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
  923. && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  924. r8a66597_update_usb_speed(r8a66597);
  925. r8a66597->old_dvsq = dvsq;
  926. }
  927. static void irq_control_stage(struct r8a66597 *r8a66597)
  928. __releases(r8a66597->lock)
  929. __acquires(r8a66597->lock)
  930. {
  931. struct usb_ctrlrequest ctrl;
  932. u16 ctsq;
  933. ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  934. r8a66597_write(r8a66597, ~CTRT, INTSTS0);
  935. switch (ctsq) {
  936. case CS_IDST: {
  937. struct r8a66597_ep *ep;
  938. struct r8a66597_request *req;
  939. ep = &r8a66597->ep[0];
  940. req = get_request_from_ep(ep);
  941. transfer_complete(ep, req, 0);
  942. }
  943. break;
  944. case CS_RDDS:
  945. case CS_WRDS:
  946. case CS_WRND:
  947. if (setup_packet(r8a66597, &ctrl)) {
  948. spin_unlock(&r8a66597->lock);
  949. if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
  950. < 0)
  951. pipe_stall(r8a66597, 0);
  952. spin_lock(&r8a66597->lock);
  953. }
  954. break;
  955. case CS_RDSS:
  956. case CS_WRSS:
  957. control_end(r8a66597, 0);
  958. break;
  959. default:
  960. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  961. break;
  962. }
  963. }
  964. static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
  965. {
  966. struct r8a66597 *r8a66597 = _r8a66597;
  967. u16 intsts0;
  968. u16 intenb0;
  969. u16 brdysts, nrdysts, bempsts;
  970. u16 brdyenb, nrdyenb, bempenb;
  971. u16 savepipe;
  972. u16 mask0;
  973. spin_lock(&r8a66597->lock);
  974. intsts0 = r8a66597_read(r8a66597, INTSTS0);
  975. intenb0 = r8a66597_read(r8a66597, INTENB0);
  976. savepipe = r8a66597_read(r8a66597, CFIFOSEL);
  977. mask0 = intsts0 & intenb0;
  978. if (mask0) {
  979. brdysts = r8a66597_read(r8a66597, BRDYSTS);
  980. nrdysts = r8a66597_read(r8a66597, NRDYSTS);
  981. bempsts = r8a66597_read(r8a66597, BEMPSTS);
  982. brdyenb = r8a66597_read(r8a66597, BRDYENB);
  983. nrdyenb = r8a66597_read(r8a66597, NRDYENB);
  984. bempenb = r8a66597_read(r8a66597, BEMPENB);
  985. if (mask0 & VBINT) {
  986. r8a66597_write(r8a66597, 0xffff & ~VBINT,
  987. INTSTS0);
  988. r8a66597_start_xclock(r8a66597);
  989. /* start vbus sampling */
  990. r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
  991. & VBSTS;
  992. r8a66597->scount = R8A66597_MAX_SAMPLING;
  993. mod_timer(&r8a66597->timer,
  994. jiffies + msecs_to_jiffies(50));
  995. }
  996. if (intsts0 & DVSQ)
  997. irq_device_state(r8a66597);
  998. if ((intsts0 & BRDY) && (intenb0 & BRDYE)
  999. && (brdysts & brdyenb))
  1000. irq_pipe_ready(r8a66597, brdysts, brdyenb);
  1001. if ((intsts0 & BEMP) && (intenb0 & BEMPE)
  1002. && (bempsts & bempenb))
  1003. irq_pipe_empty(r8a66597, bempsts, bempenb);
  1004. if (intsts0 & CTRT)
  1005. irq_control_stage(r8a66597);
  1006. }
  1007. r8a66597_write(r8a66597, savepipe, CFIFOSEL);
  1008. spin_unlock(&r8a66597->lock);
  1009. return IRQ_HANDLED;
  1010. }
  1011. static void r8a66597_timer(unsigned long _r8a66597)
  1012. {
  1013. struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
  1014. unsigned long flags;
  1015. u16 tmp;
  1016. spin_lock_irqsave(&r8a66597->lock, flags);
  1017. tmp = r8a66597_read(r8a66597, SYSCFG0);
  1018. if (r8a66597->scount > 0) {
  1019. tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
  1020. if (tmp == r8a66597->old_vbus) {
  1021. r8a66597->scount--;
  1022. if (r8a66597->scount == 0) {
  1023. if (tmp == VBSTS)
  1024. r8a66597_usb_connect(r8a66597);
  1025. else
  1026. r8a66597_usb_disconnect(r8a66597);
  1027. } else {
  1028. mod_timer(&r8a66597->timer,
  1029. jiffies + msecs_to_jiffies(50));
  1030. }
  1031. } else {
  1032. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1033. r8a66597->old_vbus = tmp;
  1034. mod_timer(&r8a66597->timer,
  1035. jiffies + msecs_to_jiffies(50));
  1036. }
  1037. }
  1038. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1039. }
  1040. /*-------------------------------------------------------------------------*/
  1041. static int r8a66597_enable(struct usb_ep *_ep,
  1042. const struct usb_endpoint_descriptor *desc)
  1043. {
  1044. struct r8a66597_ep *ep;
  1045. ep = container_of(_ep, struct r8a66597_ep, ep);
  1046. return alloc_pipe_config(ep, desc);
  1047. }
  1048. static int r8a66597_disable(struct usb_ep *_ep)
  1049. {
  1050. struct r8a66597_ep *ep;
  1051. struct r8a66597_request *req;
  1052. unsigned long flags;
  1053. ep = container_of(_ep, struct r8a66597_ep, ep);
  1054. BUG_ON(!ep);
  1055. while (!list_empty(&ep->queue)) {
  1056. req = get_request_from_ep(ep);
  1057. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1058. transfer_complete(ep, req, -ECONNRESET);
  1059. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1060. }
  1061. pipe_irq_disable(ep->r8a66597, ep->pipenum);
  1062. return free_pipe_config(ep);
  1063. }
  1064. static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
  1065. gfp_t gfp_flags)
  1066. {
  1067. struct r8a66597_request *req;
  1068. req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
  1069. if (!req)
  1070. return NULL;
  1071. INIT_LIST_HEAD(&req->queue);
  1072. return &req->req;
  1073. }
  1074. static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1075. {
  1076. struct r8a66597_request *req;
  1077. req = container_of(_req, struct r8a66597_request, req);
  1078. kfree(req);
  1079. }
  1080. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  1081. gfp_t gfp_flags)
  1082. {
  1083. struct r8a66597_ep *ep;
  1084. struct r8a66597_request *req;
  1085. unsigned long flags;
  1086. int request = 0;
  1087. ep = container_of(_ep, struct r8a66597_ep, ep);
  1088. req = container_of(_req, struct r8a66597_request, req);
  1089. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1090. return -ESHUTDOWN;
  1091. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1092. if (list_empty(&ep->queue))
  1093. request = 1;
  1094. list_add_tail(&req->queue, &ep->queue);
  1095. req->req.actual = 0;
  1096. req->req.status = -EINPROGRESS;
  1097. if (ep->desc == NULL) /* control */
  1098. start_ep0(ep, req);
  1099. else {
  1100. if (request && !ep->busy)
  1101. start_packet(ep, req);
  1102. }
  1103. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1104. return 0;
  1105. }
  1106. static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1107. {
  1108. struct r8a66597_ep *ep;
  1109. struct r8a66597_request *req;
  1110. unsigned long flags;
  1111. ep = container_of(_ep, struct r8a66597_ep, ep);
  1112. req = container_of(_req, struct r8a66597_request, req);
  1113. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1114. if (!list_empty(&ep->queue))
  1115. transfer_complete(ep, req, -ECONNRESET);
  1116. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1117. return 0;
  1118. }
  1119. static int r8a66597_set_halt(struct usb_ep *_ep, int value)
  1120. {
  1121. struct r8a66597_ep *ep;
  1122. struct r8a66597_request *req;
  1123. unsigned long flags;
  1124. int ret = 0;
  1125. ep = container_of(_ep, struct r8a66597_ep, ep);
  1126. req = get_request_from_ep(ep);
  1127. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1128. if (!list_empty(&ep->queue)) {
  1129. ret = -EAGAIN;
  1130. goto out;
  1131. }
  1132. if (value) {
  1133. ep->busy = 1;
  1134. pipe_stall(ep->r8a66597, ep->pipenum);
  1135. } else {
  1136. ep->busy = 0;
  1137. pipe_stop(ep->r8a66597, ep->pipenum);
  1138. }
  1139. out:
  1140. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1141. return ret;
  1142. }
  1143. static void r8a66597_fifo_flush(struct usb_ep *_ep)
  1144. {
  1145. struct r8a66597_ep *ep;
  1146. unsigned long flags;
  1147. ep = container_of(_ep, struct r8a66597_ep, ep);
  1148. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1149. if (list_empty(&ep->queue) && !ep->busy) {
  1150. pipe_stop(ep->r8a66597, ep->pipenum);
  1151. r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
  1152. }
  1153. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1154. }
  1155. static struct usb_ep_ops r8a66597_ep_ops = {
  1156. .enable = r8a66597_enable,
  1157. .disable = r8a66597_disable,
  1158. .alloc_request = r8a66597_alloc_request,
  1159. .free_request = r8a66597_free_request,
  1160. .queue = r8a66597_queue,
  1161. .dequeue = r8a66597_dequeue,
  1162. .set_halt = r8a66597_set_halt,
  1163. .fifo_flush = r8a66597_fifo_flush,
  1164. };
  1165. /*-------------------------------------------------------------------------*/
  1166. static struct r8a66597 *the_controller;
  1167. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1168. {
  1169. struct r8a66597 *r8a66597 = the_controller;
  1170. int retval;
  1171. if (!driver
  1172. || driver->speed != USB_SPEED_HIGH
  1173. || !driver->bind
  1174. || !driver->setup)
  1175. return -EINVAL;
  1176. if (!r8a66597)
  1177. return -ENODEV;
  1178. if (r8a66597->driver)
  1179. return -EBUSY;
  1180. /* hook up the driver */
  1181. driver->driver.bus = NULL;
  1182. r8a66597->driver = driver;
  1183. r8a66597->gadget.dev.driver = &driver->driver;
  1184. retval = device_add(&r8a66597->gadget.dev);
  1185. if (retval) {
  1186. printk(KERN_ERR "device_add error (%d)\n", retval);
  1187. goto error;
  1188. }
  1189. retval = driver->bind(&r8a66597->gadget);
  1190. if (retval) {
  1191. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1192. device_del(&r8a66597->gadget.dev);
  1193. goto error;
  1194. }
  1195. r8a66597_bset(r8a66597, VBSE, INTENB0);
  1196. if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
  1197. r8a66597_start_xclock(r8a66597);
  1198. /* start vbus sampling */
  1199. r8a66597->old_vbus = r8a66597_read(r8a66597,
  1200. INTSTS0) & VBSTS;
  1201. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1202. mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
  1203. }
  1204. return 0;
  1205. error:
  1206. r8a66597->driver = NULL;
  1207. r8a66597->gadget.dev.driver = NULL;
  1208. return retval;
  1209. }
  1210. EXPORT_SYMBOL(usb_gadget_register_driver);
  1211. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1212. {
  1213. struct r8a66597 *r8a66597 = the_controller;
  1214. unsigned long flags;
  1215. if (driver != r8a66597->driver || !driver->unbind)
  1216. return -EINVAL;
  1217. spin_lock_irqsave(&r8a66597->lock, flags);
  1218. if (r8a66597->gadget.speed != USB_SPEED_UNKNOWN)
  1219. r8a66597_usb_disconnect(r8a66597);
  1220. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1221. r8a66597_bclr(r8a66597, VBSE, INTENB0);
  1222. driver->unbind(&r8a66597->gadget);
  1223. init_controller(r8a66597);
  1224. disable_controller(r8a66597);
  1225. device_del(&r8a66597->gadget.dev);
  1226. r8a66597->driver = NULL;
  1227. return 0;
  1228. }
  1229. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1230. /*-------------------------------------------------------------------------*/
  1231. static int r8a66597_get_frame(struct usb_gadget *_gadget)
  1232. {
  1233. struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
  1234. return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
  1235. }
  1236. static struct usb_gadget_ops r8a66597_gadget_ops = {
  1237. .get_frame = r8a66597_get_frame,
  1238. };
  1239. static int __exit r8a66597_remove(struct platform_device *pdev)
  1240. {
  1241. struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
  1242. del_timer_sync(&r8a66597->timer);
  1243. iounmap((void *)r8a66597->reg);
  1244. free_irq(platform_get_irq(pdev, 0), r8a66597);
  1245. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1246. #ifdef CONFIG_HAVE_CLK
  1247. if (r8a66597->pdata->on_chip) {
  1248. clk_disable(r8a66597->clk);
  1249. clk_put(r8a66597->clk);
  1250. }
  1251. #endif
  1252. kfree(r8a66597);
  1253. return 0;
  1254. }
  1255. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1256. {
  1257. }
  1258. static int __init r8a66597_probe(struct platform_device *pdev)
  1259. {
  1260. #ifdef CONFIG_HAVE_CLK
  1261. char clk_name[8];
  1262. #endif
  1263. struct resource *res, *ires;
  1264. int irq;
  1265. void __iomem *reg = NULL;
  1266. struct r8a66597 *r8a66597 = NULL;
  1267. int ret = 0;
  1268. int i;
  1269. unsigned long irq_trigger;
  1270. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1271. if (!res) {
  1272. ret = -ENODEV;
  1273. printk(KERN_ERR "platform_get_resource error.\n");
  1274. goto clean_up;
  1275. }
  1276. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1277. irq = ires->start;
  1278. irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1279. if (irq < 0) {
  1280. ret = -ENODEV;
  1281. printk(KERN_ERR "platform_get_irq error.\n");
  1282. goto clean_up;
  1283. }
  1284. reg = ioremap(res->start, resource_size(res));
  1285. if (reg == NULL) {
  1286. ret = -ENOMEM;
  1287. printk(KERN_ERR "ioremap error.\n");
  1288. goto clean_up;
  1289. }
  1290. /* initialize ucd */
  1291. r8a66597 = kzalloc(sizeof(struct r8a66597), GFP_KERNEL);
  1292. if (r8a66597 == NULL) {
  1293. printk(KERN_ERR "kzalloc error\n");
  1294. goto clean_up;
  1295. }
  1296. spin_lock_init(&r8a66597->lock);
  1297. dev_set_drvdata(&pdev->dev, r8a66597);
  1298. r8a66597->pdata = pdev->dev.platform_data;
  1299. r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
  1300. r8a66597->gadget.ops = &r8a66597_gadget_ops;
  1301. device_initialize(&r8a66597->gadget.dev);
  1302. dev_set_name(&r8a66597->gadget.dev, "gadget");
  1303. r8a66597->gadget.is_dualspeed = 1;
  1304. r8a66597->gadget.dev.parent = &pdev->dev;
  1305. r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1306. r8a66597->gadget.dev.release = pdev->dev.release;
  1307. r8a66597->gadget.name = udc_name;
  1308. init_timer(&r8a66597->timer);
  1309. r8a66597->timer.function = r8a66597_timer;
  1310. r8a66597->timer.data = (unsigned long)r8a66597;
  1311. r8a66597->reg = (unsigned long)reg;
  1312. r8a66597->bi_bufnum = R8A66597_BASE_BUFNUM;
  1313. #ifdef CONFIG_HAVE_CLK
  1314. if (r8a66597->pdata->on_chip) {
  1315. snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
  1316. r8a66597->clk = clk_get(&pdev->dev, clk_name);
  1317. if (IS_ERR(r8a66597->clk)) {
  1318. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1319. clk_name);
  1320. ret = PTR_ERR(r8a66597->clk);
  1321. goto clean_up;
  1322. }
  1323. clk_enable(r8a66597->clk);
  1324. }
  1325. #endif
  1326. disable_controller(r8a66597); /* make sure controller is disabled */
  1327. ret = request_irq(irq, r8a66597_irq, IRQF_DISABLED | IRQF_SHARED,
  1328. udc_name, r8a66597);
  1329. if (ret < 0) {
  1330. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1331. goto clean_up2;
  1332. }
  1333. INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
  1334. r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
  1335. INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
  1336. for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
  1337. struct r8a66597_ep *ep = &r8a66597->ep[i];
  1338. if (i != 0) {
  1339. INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
  1340. list_add_tail(&r8a66597->ep[i].ep.ep_list,
  1341. &r8a66597->gadget.ep_list);
  1342. }
  1343. ep->r8a66597 = r8a66597;
  1344. INIT_LIST_HEAD(&ep->queue);
  1345. ep->ep.name = r8a66597_ep_name[i];
  1346. ep->ep.ops = &r8a66597_ep_ops;
  1347. ep->ep.maxpacket = 512;
  1348. }
  1349. r8a66597->ep[0].ep.maxpacket = 64;
  1350. r8a66597->ep[0].pipenum = 0;
  1351. r8a66597->ep[0].fifoaddr = CFIFO;
  1352. r8a66597->ep[0].fifosel = CFIFOSEL;
  1353. r8a66597->ep[0].fifoctr = CFIFOCTR;
  1354. r8a66597->ep[0].fifotrn = 0;
  1355. r8a66597->ep[0].pipectr = get_pipectr_addr(0);
  1356. r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
  1357. r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
  1358. the_controller = r8a66597;
  1359. r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
  1360. GFP_KERNEL);
  1361. if (r8a66597->ep0_req == NULL)
  1362. goto clean_up3;
  1363. r8a66597->ep0_req->complete = nop_completion;
  1364. init_controller(r8a66597);
  1365. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1366. return 0;
  1367. clean_up3:
  1368. free_irq(irq, r8a66597);
  1369. clean_up2:
  1370. #ifdef CONFIG_HAVE_CLK
  1371. if (r8a66597->pdata->on_chip) {
  1372. clk_disable(r8a66597->clk);
  1373. clk_put(r8a66597->clk);
  1374. }
  1375. #endif
  1376. clean_up:
  1377. if (r8a66597) {
  1378. if (r8a66597->ep0_req)
  1379. r8a66597_free_request(&r8a66597->ep[0].ep,
  1380. r8a66597->ep0_req);
  1381. kfree(r8a66597);
  1382. }
  1383. if (reg)
  1384. iounmap(reg);
  1385. return ret;
  1386. }
  1387. /*-------------------------------------------------------------------------*/
  1388. static struct platform_driver r8a66597_driver = {
  1389. .remove = __exit_p(r8a66597_remove),
  1390. .driver = {
  1391. .name = (char *) udc_name,
  1392. },
  1393. };
  1394. static int __init r8a66597_udc_init(void)
  1395. {
  1396. return platform_driver_probe(&r8a66597_driver, r8a66597_probe);
  1397. }
  1398. module_init(r8a66597_udc_init);
  1399. static void __exit r8a66597_udc_cleanup(void)
  1400. {
  1401. platform_driver_unregister(&r8a66597_driver);
  1402. }
  1403. module_exit(r8a66597_udc_cleanup);
  1404. MODULE_DESCRIPTION("R8A66597 USB gadget driver");
  1405. MODULE_LICENSE("GPL");
  1406. MODULE_AUTHOR("Yoshihiro Shimoda");