r8152.c 50 KB

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  1. /*
  2. * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/init.h>
  10. #include <linux/signal.h>
  11. #include <linux/slab.h>
  12. #include <linux/module.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/mii.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/usb.h>
  18. #include <linux/crc32.h>
  19. #include <linux/if_vlan.h>
  20. #include <linux/uaccess.h>
  21. #include <linux/list.h>
  22. #include <linux/ip.h>
  23. #include <linux/ipv6.h>
  24. /* Version Information */
  25. #define DRIVER_VERSION "v1.02.0 (2013/10/28)"
  26. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  27. #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
  28. #define MODULENAME "r8152"
  29. #define R8152_PHY_ID 32
  30. #define PLA_IDR 0xc000
  31. #define PLA_RCR 0xc010
  32. #define PLA_RMS 0xc016
  33. #define PLA_RXFIFO_CTRL0 0xc0a0
  34. #define PLA_RXFIFO_CTRL1 0xc0a4
  35. #define PLA_RXFIFO_CTRL2 0xc0a8
  36. #define PLA_FMC 0xc0b4
  37. #define PLA_CFG_WOL 0xc0b6
  38. #define PLA_MAR 0xcd00
  39. #define PAL_BDC_CR 0xd1a0
  40. #define PLA_LEDSEL 0xdd90
  41. #define PLA_LED_FEATURE 0xdd92
  42. #define PLA_PHYAR 0xde00
  43. #define PLA_GPHY_INTR_IMR 0xe022
  44. #define PLA_EEE_CR 0xe040
  45. #define PLA_EEEP_CR 0xe080
  46. #define PLA_MAC_PWR_CTRL 0xe0c0
  47. #define PLA_TCR0 0xe610
  48. #define PLA_TCR1 0xe612
  49. #define PLA_TXFIFO_CTRL 0xe618
  50. #define PLA_RSTTELLY 0xe800
  51. #define PLA_CR 0xe813
  52. #define PLA_CRWECR 0xe81c
  53. #define PLA_CONFIG5 0xe822
  54. #define PLA_PHY_PWR 0xe84c
  55. #define PLA_OOB_CTRL 0xe84f
  56. #define PLA_CPCR 0xe854
  57. #define PLA_MISC_0 0xe858
  58. #define PLA_MISC_1 0xe85a
  59. #define PLA_OCP_GPHY_BASE 0xe86c
  60. #define PLA_TELLYCNT 0xe890
  61. #define PLA_SFF_STS_7 0xe8de
  62. #define PLA_PHYSTATUS 0xe908
  63. #define PLA_BP_BA 0xfc26
  64. #define PLA_BP_0 0xfc28
  65. #define PLA_BP_1 0xfc2a
  66. #define PLA_BP_2 0xfc2c
  67. #define PLA_BP_3 0xfc2e
  68. #define PLA_BP_4 0xfc30
  69. #define PLA_BP_5 0xfc32
  70. #define PLA_BP_6 0xfc34
  71. #define PLA_BP_7 0xfc36
  72. #define USB_DEV_STAT 0xb808
  73. #define USB_USB_CTRL 0xd406
  74. #define USB_PHY_CTRL 0xd408
  75. #define USB_TX_AGG 0xd40a
  76. #define USB_RX_BUF_TH 0xd40c
  77. #define USB_USB_TIMER 0xd428
  78. #define USB_PM_CTRL_STATUS 0xd432
  79. #define USB_TX_DMA 0xd434
  80. #define USB_UPS_CTRL 0xd800
  81. #define USB_BP_BA 0xfc26
  82. #define USB_BP_0 0xfc28
  83. #define USB_BP_1 0xfc2a
  84. #define USB_BP_2 0xfc2c
  85. #define USB_BP_3 0xfc2e
  86. #define USB_BP_4 0xfc30
  87. #define USB_BP_5 0xfc32
  88. #define USB_BP_6 0xfc34
  89. #define USB_BP_7 0xfc36
  90. /* OCP Registers */
  91. #define OCP_ALDPS_CONFIG 0x2010
  92. #define OCP_EEE_CONFIG1 0x2080
  93. #define OCP_EEE_CONFIG2 0x2092
  94. #define OCP_EEE_CONFIG3 0x2094
  95. #define OCP_EEE_AR 0xa41a
  96. #define OCP_EEE_DATA 0xa41c
  97. /* PLA_RCR */
  98. #define RCR_AAP 0x00000001
  99. #define RCR_APM 0x00000002
  100. #define RCR_AM 0x00000004
  101. #define RCR_AB 0x00000008
  102. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  103. /* PLA_RXFIFO_CTRL0 */
  104. #define RXFIFO_THR1_NORMAL 0x00080002
  105. #define RXFIFO_THR1_OOB 0x01800003
  106. /* PLA_RXFIFO_CTRL1 */
  107. #define RXFIFO_THR2_FULL 0x00000060
  108. #define RXFIFO_THR2_HIGH 0x00000038
  109. #define RXFIFO_THR2_OOB 0x0000004a
  110. /* PLA_RXFIFO_CTRL2 */
  111. #define RXFIFO_THR3_FULL 0x00000078
  112. #define RXFIFO_THR3_HIGH 0x00000048
  113. #define RXFIFO_THR3_OOB 0x0000005a
  114. /* PLA_TXFIFO_CTRL */
  115. #define TXFIFO_THR_NORMAL 0x00400008
  116. /* PLA_FMC */
  117. #define FMC_FCR_MCU_EN 0x0001
  118. /* PLA_EEEP_CR */
  119. #define EEEP_CR_EEEP_TX 0x0002
  120. /* PLA_TCR0 */
  121. #define TCR0_TX_EMPTY 0x0800
  122. #define TCR0_AUTO_FIFO 0x0080
  123. /* PLA_TCR1 */
  124. #define VERSION_MASK 0x7cf0
  125. /* PLA_CR */
  126. #define CR_RST 0x10
  127. #define CR_RE 0x08
  128. #define CR_TE 0x04
  129. /* PLA_CRWECR */
  130. #define CRWECR_NORAML 0x00
  131. #define CRWECR_CONFIG 0xc0
  132. /* PLA_OOB_CTRL */
  133. #define NOW_IS_OOB 0x80
  134. #define TXFIFO_EMPTY 0x20
  135. #define RXFIFO_EMPTY 0x10
  136. #define LINK_LIST_READY 0x02
  137. #define DIS_MCU_CLROOB 0x01
  138. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  139. /* PLA_MISC_1 */
  140. #define RXDY_GATED_EN 0x0008
  141. /* PLA_SFF_STS_7 */
  142. #define RE_INIT_LL 0x8000
  143. #define MCU_BORW_EN 0x4000
  144. /* PLA_CPCR */
  145. #define CPCR_RX_VLAN 0x0040
  146. /* PLA_CFG_WOL */
  147. #define MAGIC_EN 0x0001
  148. /* PAL_BDC_CR */
  149. #define ALDPS_PROXY_MODE 0x0001
  150. /* PLA_CONFIG5 */
  151. #define LAN_WAKE_EN 0x0002
  152. /* PLA_LED_FEATURE */
  153. #define LED_MODE_MASK 0x0700
  154. /* PLA_PHY_PWR */
  155. #define TX_10M_IDLE_EN 0x0080
  156. #define PFM_PWM_SWITCH 0x0040
  157. /* PLA_MAC_PWR_CTRL */
  158. #define D3_CLK_GATED_EN 0x00004000
  159. #define MCU_CLK_RATIO 0x07010f07
  160. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  161. /* PLA_GPHY_INTR_IMR */
  162. #define GPHY_STS_MSK 0x0001
  163. #define SPEED_DOWN_MSK 0x0002
  164. #define SPDWN_RXDV_MSK 0x0004
  165. #define SPDWN_LINKCHG_MSK 0x0008
  166. /* PLA_PHYAR */
  167. #define PHYAR_FLAG 0x80000000
  168. /* PLA_EEE_CR */
  169. #define EEE_RX_EN 0x0001
  170. #define EEE_TX_EN 0x0002
  171. /* USB_DEV_STAT */
  172. #define STAT_SPEED_MASK 0x0006
  173. #define STAT_SPEED_HIGH 0x0000
  174. #define STAT_SPEED_FULL 0x0001
  175. /* USB_TX_AGG */
  176. #define TX_AGG_MAX_THRESHOLD 0x03
  177. /* USB_RX_BUF_TH */
  178. #define RX_BUF_THR 0x7a120180
  179. /* USB_TX_DMA */
  180. #define TEST_MODE_DISABLE 0x00000001
  181. #define TX_SIZE_ADJUST1 0x00000100
  182. /* USB_UPS_CTRL */
  183. #define POWER_CUT 0x0100
  184. /* USB_PM_CTRL_STATUS */
  185. #define RWSUME_INDICATE 0x0001
  186. /* USB_USB_CTRL */
  187. #define RX_AGG_DISABLE 0x0010
  188. /* OCP_ALDPS_CONFIG */
  189. #define ENPWRSAVE 0x8000
  190. #define ENPDNPS 0x0200
  191. #define LINKENA 0x0100
  192. #define DIS_SDSAVE 0x0010
  193. /* OCP_EEE_CONFIG1 */
  194. #define RG_TXLPI_MSK_HFDUP 0x8000
  195. #define RG_MATCLR_EN 0x4000
  196. #define EEE_10_CAP 0x2000
  197. #define EEE_NWAY_EN 0x1000
  198. #define TX_QUIET_EN 0x0200
  199. #define RX_QUIET_EN 0x0100
  200. #define SDRISETIME 0x0010 /* bit 4 ~ 6 */
  201. #define RG_RXLPI_MSK_HFDUP 0x0008
  202. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  203. /* OCP_EEE_CONFIG2 */
  204. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  205. #define RG_DACQUIET_EN 0x0400
  206. #define RG_LDVQUIET_EN 0x0200
  207. #define RG_CKRSEL 0x0020
  208. #define RG_EEEPRG_EN 0x0010
  209. /* OCP_EEE_CONFIG3 */
  210. #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
  211. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  212. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  213. /* OCP_EEE_AR */
  214. /* bit[15:14] function */
  215. #define FUN_ADDR 0x0000
  216. #define FUN_DATA 0x4000
  217. /* bit[4:0] device addr */
  218. #define DEVICE_ADDR 0x0007
  219. /* OCP_EEE_DATA */
  220. #define EEE_ADDR 0x003C
  221. #define EEE_DATA 0x0002
  222. enum rtl_register_content {
  223. _100bps = 0x08,
  224. _10bps = 0x04,
  225. LINK_STATUS = 0x02,
  226. FULL_DUP = 0x01,
  227. };
  228. #define RTL8152_MAX_TX 10
  229. #define RTL8152_MAX_RX 10
  230. #define INTBUFSIZE 2
  231. #define INTR_LINK 0x0004
  232. #define RTL8152_REQT_READ 0xc0
  233. #define RTL8152_REQT_WRITE 0x40
  234. #define RTL8152_REQ_GET_REGS 0x05
  235. #define RTL8152_REQ_SET_REGS 0x05
  236. #define BYTE_EN_DWORD 0xff
  237. #define BYTE_EN_WORD 0x33
  238. #define BYTE_EN_BYTE 0x11
  239. #define BYTE_EN_SIX_BYTES 0x3f
  240. #define BYTE_EN_START_MASK 0x0f
  241. #define BYTE_EN_END_MASK 0xf0
  242. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  243. #define RTL8152_TX_TIMEOUT (HZ)
  244. /* rtl8152 flags */
  245. enum rtl8152_flags {
  246. RTL8152_UNPLUG = 0,
  247. RTL8152_SET_RX_MODE,
  248. WORK_ENABLE,
  249. RTL8152_LINK_CHG,
  250. };
  251. /* Define these values to match your device */
  252. #define VENDOR_ID_REALTEK 0x0bda
  253. #define PRODUCT_ID_RTL8152 0x8152
  254. #define MCU_TYPE_PLA 0x0100
  255. #define MCU_TYPE_USB 0x0000
  256. struct rx_desc {
  257. __le32 opts1;
  258. #define RX_LEN_MASK 0x7fff
  259. __le32 opts2;
  260. __le32 opts3;
  261. __le32 opts4;
  262. __le32 opts5;
  263. __le32 opts6;
  264. };
  265. struct tx_desc {
  266. __le32 opts1;
  267. #define TX_FS (1 << 31) /* First segment of a packet */
  268. #define TX_LS (1 << 30) /* Final segment of a packet */
  269. #define TX_LEN_MASK 0x3ffff
  270. __le32 opts2;
  271. #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
  272. #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
  273. #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
  274. #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
  275. };
  276. struct r8152;
  277. struct rx_agg {
  278. struct list_head list;
  279. struct urb *urb;
  280. struct r8152 *context;
  281. void *buffer;
  282. void *head;
  283. };
  284. struct tx_agg {
  285. struct list_head list;
  286. struct urb *urb;
  287. struct r8152 *context;
  288. void *buffer;
  289. void *head;
  290. u32 skb_num;
  291. u32 skb_len;
  292. };
  293. struct r8152 {
  294. unsigned long flags;
  295. struct usb_device *udev;
  296. struct tasklet_struct tl;
  297. struct usb_interface *intf;
  298. struct net_device *netdev;
  299. struct urb *intr_urb;
  300. struct tx_agg tx_info[RTL8152_MAX_TX];
  301. struct rx_agg rx_info[RTL8152_MAX_RX];
  302. struct list_head rx_done, tx_free;
  303. struct sk_buff_head tx_queue;
  304. spinlock_t rx_lock, tx_lock;
  305. struct delayed_work schedule;
  306. struct mii_if_info mii;
  307. int intr_interval;
  308. u32 msg_enable;
  309. u32 tx_qlen;
  310. u16 ocp_base;
  311. u8 *intr_buff;
  312. u8 version;
  313. u8 speed;
  314. };
  315. enum rtl_version {
  316. RTL_VER_UNKNOWN = 0,
  317. RTL_VER_01,
  318. RTL_VER_02
  319. };
  320. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  321. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  322. */
  323. static const int multicast_filter_limit = 32;
  324. static unsigned int rx_buf_sz = 16384;
  325. static
  326. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  327. {
  328. int ret;
  329. void *tmp;
  330. tmp = kmalloc(size, GFP_KERNEL);
  331. if (!tmp)
  332. return -ENOMEM;
  333. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  334. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  335. value, index, tmp, size, 500);
  336. memcpy(data, tmp, size);
  337. kfree(tmp);
  338. return ret;
  339. }
  340. static
  341. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  342. {
  343. int ret;
  344. void *tmp;
  345. tmp = kmalloc(size, GFP_KERNEL);
  346. if (!tmp)
  347. return -ENOMEM;
  348. memcpy(tmp, data, size);
  349. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  350. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  351. value, index, tmp, size, 500);
  352. kfree(tmp);
  353. return ret;
  354. }
  355. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  356. void *data, u16 type)
  357. {
  358. u16 limit = 64;
  359. int ret = 0;
  360. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  361. return -ENODEV;
  362. /* both size and indix must be 4 bytes align */
  363. if ((size & 3) || !size || (index & 3) || !data)
  364. return -EPERM;
  365. if ((u32)index + (u32)size > 0xffff)
  366. return -EPERM;
  367. while (size) {
  368. if (size > limit) {
  369. ret = get_registers(tp, index, type, limit, data);
  370. if (ret < 0)
  371. break;
  372. index += limit;
  373. data += limit;
  374. size -= limit;
  375. } else {
  376. ret = get_registers(tp, index, type, size, data);
  377. if (ret < 0)
  378. break;
  379. index += size;
  380. data += size;
  381. size = 0;
  382. break;
  383. }
  384. }
  385. return ret;
  386. }
  387. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  388. u16 size, void *data, u16 type)
  389. {
  390. int ret;
  391. u16 byteen_start, byteen_end, byen;
  392. u16 limit = 512;
  393. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  394. return -ENODEV;
  395. /* both size and indix must be 4 bytes align */
  396. if ((size & 3) || !size || (index & 3) || !data)
  397. return -EPERM;
  398. if ((u32)index + (u32)size > 0xffff)
  399. return -EPERM;
  400. byteen_start = byteen & BYTE_EN_START_MASK;
  401. byteen_end = byteen & BYTE_EN_END_MASK;
  402. byen = byteen_start | (byteen_start << 4);
  403. ret = set_registers(tp, index, type | byen, 4, data);
  404. if (ret < 0)
  405. goto error1;
  406. index += 4;
  407. data += 4;
  408. size -= 4;
  409. if (size) {
  410. size -= 4;
  411. while (size) {
  412. if (size > limit) {
  413. ret = set_registers(tp, index,
  414. type | BYTE_EN_DWORD,
  415. limit, data);
  416. if (ret < 0)
  417. goto error1;
  418. index += limit;
  419. data += limit;
  420. size -= limit;
  421. } else {
  422. ret = set_registers(tp, index,
  423. type | BYTE_EN_DWORD,
  424. size, data);
  425. if (ret < 0)
  426. goto error1;
  427. index += size;
  428. data += size;
  429. size = 0;
  430. break;
  431. }
  432. }
  433. byen = byteen_end | (byteen_end >> 4);
  434. ret = set_registers(tp, index, type | byen, 4, data);
  435. if (ret < 0)
  436. goto error1;
  437. }
  438. error1:
  439. return ret;
  440. }
  441. static inline
  442. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  443. {
  444. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  445. }
  446. static inline
  447. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  448. {
  449. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  450. }
  451. static inline
  452. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  453. {
  454. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  455. }
  456. static inline
  457. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  458. {
  459. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  460. }
  461. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  462. {
  463. __le32 data;
  464. generic_ocp_read(tp, index, sizeof(data), &data, type);
  465. return __le32_to_cpu(data);
  466. }
  467. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  468. {
  469. __le32 tmp = __cpu_to_le32(data);
  470. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  471. }
  472. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  473. {
  474. u32 data;
  475. __le32 tmp;
  476. u8 shift = index & 2;
  477. index &= ~3;
  478. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  479. data = __le32_to_cpu(tmp);
  480. data >>= (shift * 8);
  481. data &= 0xffff;
  482. return (u16)data;
  483. }
  484. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  485. {
  486. u32 mask = 0xffff;
  487. __le32 tmp;
  488. u16 byen = BYTE_EN_WORD;
  489. u8 shift = index & 2;
  490. data &= mask;
  491. if (index & 2) {
  492. byen <<= shift;
  493. mask <<= (shift * 8);
  494. data <<= (shift * 8);
  495. index &= ~3;
  496. }
  497. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  498. data |= __le32_to_cpu(tmp) & ~mask;
  499. tmp = __cpu_to_le32(data);
  500. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  501. }
  502. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  503. {
  504. u32 data;
  505. __le32 tmp;
  506. u8 shift = index & 3;
  507. index &= ~3;
  508. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  509. data = __le32_to_cpu(tmp);
  510. data >>= (shift * 8);
  511. data &= 0xff;
  512. return (u8)data;
  513. }
  514. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  515. {
  516. u32 mask = 0xff;
  517. __le32 tmp;
  518. u16 byen = BYTE_EN_BYTE;
  519. u8 shift = index & 3;
  520. data &= mask;
  521. if (index & 3) {
  522. byen <<= shift;
  523. mask <<= (shift * 8);
  524. data <<= (shift * 8);
  525. index &= ~3;
  526. }
  527. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  528. data |= __le32_to_cpu(tmp) & ~mask;
  529. tmp = __cpu_to_le32(data);
  530. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  531. }
  532. static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  533. {
  534. u32 ocp_data;
  535. int i;
  536. ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) |
  537. (value & 0xffff);
  538. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  539. for (i = 20; i > 0; i--) {
  540. udelay(25);
  541. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  542. if (!(ocp_data & PHYAR_FLAG))
  543. break;
  544. }
  545. udelay(20);
  546. }
  547. static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  548. {
  549. u32 ocp_data;
  550. int i;
  551. ocp_data = (reg_addr & 0x1f) << 16;
  552. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  553. for (i = 20; i > 0; i--) {
  554. udelay(25);
  555. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  556. if (ocp_data & PHYAR_FLAG)
  557. break;
  558. }
  559. udelay(20);
  560. if (!(ocp_data & PHYAR_FLAG))
  561. return -EAGAIN;
  562. return (u16)(ocp_data & 0xffff);
  563. }
  564. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  565. {
  566. struct r8152 *tp = netdev_priv(netdev);
  567. if (phy_id != R8152_PHY_ID)
  568. return -EINVAL;
  569. return r8152_mdio_read(tp, reg);
  570. }
  571. static
  572. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  573. {
  574. struct r8152 *tp = netdev_priv(netdev);
  575. if (phy_id != R8152_PHY_ID)
  576. return;
  577. r8152_mdio_write(tp, reg, val);
  578. }
  579. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  580. {
  581. u16 ocp_base, ocp_index;
  582. ocp_base = addr & 0xf000;
  583. if (ocp_base != tp->ocp_base) {
  584. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  585. tp->ocp_base = ocp_base;
  586. }
  587. ocp_index = (addr & 0x0fff) | 0xb000;
  588. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  589. }
  590. static
  591. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  592. static inline void set_ethernet_addr(struct r8152 *tp)
  593. {
  594. struct net_device *dev = tp->netdev;
  595. u8 node_id[8] = {0};
  596. if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
  597. netif_notice(tp, probe, dev, "inet addr fail\n");
  598. else {
  599. memcpy(dev->dev_addr, node_id, dev->addr_len);
  600. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  601. }
  602. }
  603. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  604. {
  605. struct r8152 *tp = netdev_priv(netdev);
  606. struct sockaddr *addr = p;
  607. if (!is_valid_ether_addr(addr->sa_data))
  608. return -EADDRNOTAVAIL;
  609. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  610. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  611. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  612. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  613. return 0;
  614. }
  615. static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
  616. {
  617. return &dev->stats;
  618. }
  619. static void read_bulk_callback(struct urb *urb)
  620. {
  621. struct net_device *netdev;
  622. unsigned long flags;
  623. int status = urb->status;
  624. struct rx_agg *agg;
  625. struct r8152 *tp;
  626. int result;
  627. agg = urb->context;
  628. if (!agg)
  629. return;
  630. tp = agg->context;
  631. if (!tp)
  632. return;
  633. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  634. return;
  635. if (!test_bit(WORK_ENABLE, &tp->flags))
  636. return;
  637. netdev = tp->netdev;
  638. /* When link down, the driver would cancel all bulks. */
  639. /* This avoid the re-submitting bulk */
  640. if (!netif_carrier_ok(netdev))
  641. return;
  642. switch (status) {
  643. case 0:
  644. if (urb->actual_length < ETH_ZLEN)
  645. break;
  646. spin_lock_irqsave(&tp->rx_lock, flags);
  647. list_add_tail(&agg->list, &tp->rx_done);
  648. spin_unlock_irqrestore(&tp->rx_lock, flags);
  649. tasklet_schedule(&tp->tl);
  650. return;
  651. case -ESHUTDOWN:
  652. set_bit(RTL8152_UNPLUG, &tp->flags);
  653. netif_device_detach(tp->netdev);
  654. return;
  655. case -ENOENT:
  656. return; /* the urb is in unlink state */
  657. case -ETIME:
  658. pr_warn_ratelimited("may be reset is needed?..\n");
  659. break;
  660. default:
  661. pr_warn_ratelimited("Rx status %d\n", status);
  662. break;
  663. }
  664. result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  665. if (result == -ENODEV) {
  666. netif_device_detach(tp->netdev);
  667. } else if (result) {
  668. spin_lock_irqsave(&tp->rx_lock, flags);
  669. list_add_tail(&agg->list, &tp->rx_done);
  670. spin_unlock_irqrestore(&tp->rx_lock, flags);
  671. tasklet_schedule(&tp->tl);
  672. }
  673. }
  674. static void write_bulk_callback(struct urb *urb)
  675. {
  676. struct net_device_stats *stats;
  677. unsigned long flags;
  678. struct tx_agg *agg;
  679. struct r8152 *tp;
  680. int status = urb->status;
  681. agg = urb->context;
  682. if (!agg)
  683. return;
  684. tp = agg->context;
  685. if (!tp)
  686. return;
  687. stats = rtl8152_get_stats(tp->netdev);
  688. if (status) {
  689. pr_warn_ratelimited("Tx status %d\n", status);
  690. stats->tx_errors += agg->skb_num;
  691. } else {
  692. stats->tx_packets += agg->skb_num;
  693. stats->tx_bytes += agg->skb_len;
  694. }
  695. spin_lock_irqsave(&tp->tx_lock, flags);
  696. list_add_tail(&agg->list, &tp->tx_free);
  697. spin_unlock_irqrestore(&tp->tx_lock, flags);
  698. if (!netif_carrier_ok(tp->netdev))
  699. return;
  700. if (!test_bit(WORK_ENABLE, &tp->flags))
  701. return;
  702. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  703. return;
  704. if (!skb_queue_empty(&tp->tx_queue))
  705. tasklet_schedule(&tp->tl);
  706. }
  707. static void intr_callback(struct urb *urb)
  708. {
  709. struct r8152 *tp;
  710. __le16 *d;
  711. int status = urb->status;
  712. int res;
  713. tp = urb->context;
  714. if (!tp)
  715. return;
  716. if (!test_bit(WORK_ENABLE, &tp->flags))
  717. return;
  718. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  719. return;
  720. switch (status) {
  721. case 0: /* success */
  722. break;
  723. case -ECONNRESET: /* unlink */
  724. case -ESHUTDOWN:
  725. netif_device_detach(tp->netdev);
  726. case -ENOENT:
  727. return;
  728. case -EOVERFLOW:
  729. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  730. goto resubmit;
  731. /* -EPIPE: should clear the halt */
  732. default:
  733. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  734. goto resubmit;
  735. }
  736. d = urb->transfer_buffer;
  737. if (INTR_LINK & __le16_to_cpu(d[0])) {
  738. if (!(tp->speed & LINK_STATUS)) {
  739. set_bit(RTL8152_LINK_CHG, &tp->flags);
  740. schedule_delayed_work(&tp->schedule, 0);
  741. }
  742. } else {
  743. if (tp->speed & LINK_STATUS) {
  744. set_bit(RTL8152_LINK_CHG, &tp->flags);
  745. schedule_delayed_work(&tp->schedule, 0);
  746. }
  747. }
  748. resubmit:
  749. res = usb_submit_urb(urb, GFP_ATOMIC);
  750. if (res == -ENODEV)
  751. netif_device_detach(tp->netdev);
  752. else if (res)
  753. netif_err(tp, intr, tp->netdev,
  754. "can't resubmit intr, status %d\n", res);
  755. }
  756. static inline void *rx_agg_align(void *data)
  757. {
  758. return (void *)ALIGN((uintptr_t)data, 8);
  759. }
  760. static inline void *tx_agg_align(void *data)
  761. {
  762. return (void *)ALIGN((uintptr_t)data, 4);
  763. }
  764. static void free_all_mem(struct r8152 *tp)
  765. {
  766. int i;
  767. for (i = 0; i < RTL8152_MAX_RX; i++) {
  768. if (tp->rx_info[i].urb) {
  769. usb_free_urb(tp->rx_info[i].urb);
  770. tp->rx_info[i].urb = NULL;
  771. }
  772. if (tp->rx_info[i].buffer) {
  773. kfree(tp->rx_info[i].buffer);
  774. tp->rx_info[i].buffer = NULL;
  775. tp->rx_info[i].head = NULL;
  776. }
  777. }
  778. for (i = 0; i < RTL8152_MAX_TX; i++) {
  779. if (tp->tx_info[i].urb) {
  780. usb_free_urb(tp->tx_info[i].urb);
  781. tp->tx_info[i].urb = NULL;
  782. }
  783. if (tp->tx_info[i].buffer) {
  784. kfree(tp->tx_info[i].buffer);
  785. tp->tx_info[i].buffer = NULL;
  786. tp->tx_info[i].head = NULL;
  787. }
  788. }
  789. if (tp->intr_urb) {
  790. usb_free_urb(tp->intr_urb);
  791. tp->intr_urb = NULL;
  792. }
  793. if (tp->intr_buff) {
  794. kfree(tp->intr_buff);
  795. tp->intr_buff = NULL;
  796. }
  797. }
  798. static int alloc_all_mem(struct r8152 *tp)
  799. {
  800. struct net_device *netdev = tp->netdev;
  801. struct usb_interface *intf = tp->intf;
  802. struct usb_host_interface *alt = intf->cur_altsetting;
  803. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  804. struct urb *urb;
  805. int node, i;
  806. u8 *buf;
  807. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  808. spin_lock_init(&tp->rx_lock);
  809. spin_lock_init(&tp->tx_lock);
  810. INIT_LIST_HEAD(&tp->rx_done);
  811. INIT_LIST_HEAD(&tp->tx_free);
  812. skb_queue_head_init(&tp->tx_queue);
  813. for (i = 0; i < RTL8152_MAX_RX; i++) {
  814. buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
  815. if (!buf)
  816. goto err1;
  817. if (buf != rx_agg_align(buf)) {
  818. kfree(buf);
  819. buf = kmalloc_node(rx_buf_sz + 8, GFP_KERNEL, node);
  820. if (!buf)
  821. goto err1;
  822. }
  823. urb = usb_alloc_urb(0, GFP_KERNEL);
  824. if (!urb) {
  825. kfree(buf);
  826. goto err1;
  827. }
  828. INIT_LIST_HEAD(&tp->rx_info[i].list);
  829. tp->rx_info[i].context = tp;
  830. tp->rx_info[i].urb = urb;
  831. tp->rx_info[i].buffer = buf;
  832. tp->rx_info[i].head = rx_agg_align(buf);
  833. }
  834. for (i = 0; i < RTL8152_MAX_TX; i++) {
  835. buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
  836. if (!buf)
  837. goto err1;
  838. if (buf != tx_agg_align(buf)) {
  839. kfree(buf);
  840. buf = kmalloc_node(rx_buf_sz + 4, GFP_KERNEL, node);
  841. if (!buf)
  842. goto err1;
  843. }
  844. urb = usb_alloc_urb(0, GFP_KERNEL);
  845. if (!urb) {
  846. kfree(buf);
  847. goto err1;
  848. }
  849. INIT_LIST_HEAD(&tp->tx_info[i].list);
  850. tp->tx_info[i].context = tp;
  851. tp->tx_info[i].urb = urb;
  852. tp->tx_info[i].buffer = buf;
  853. tp->tx_info[i].head = tx_agg_align(buf);
  854. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  855. }
  856. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  857. if (!tp->intr_urb)
  858. goto err1;
  859. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  860. if (!tp->intr_buff)
  861. goto err1;
  862. tp->intr_interval = (int)ep_intr->desc.bInterval;
  863. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  864. tp->intr_buff, INTBUFSIZE, intr_callback,
  865. tp, tp->intr_interval);
  866. return 0;
  867. err1:
  868. free_all_mem(tp);
  869. return -ENOMEM;
  870. }
  871. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  872. {
  873. struct tx_agg *agg = NULL;
  874. unsigned long flags;
  875. spin_lock_irqsave(&tp->tx_lock, flags);
  876. if (!list_empty(&tp->tx_free)) {
  877. struct list_head *cursor;
  878. cursor = tp->tx_free.next;
  879. list_del_init(cursor);
  880. agg = list_entry(cursor, struct tx_agg, list);
  881. }
  882. spin_unlock_irqrestore(&tp->tx_lock, flags);
  883. return agg;
  884. }
  885. static void
  886. r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
  887. {
  888. memset(desc, 0, sizeof(*desc));
  889. desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
  890. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  891. __be16 protocol;
  892. u8 ip_protocol;
  893. u32 opts2 = 0;
  894. if (skb->protocol == htons(ETH_P_8021Q))
  895. protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
  896. else
  897. protocol = skb->protocol;
  898. switch (protocol) {
  899. case htons(ETH_P_IP):
  900. opts2 |= IPV4_CS;
  901. ip_protocol = ip_hdr(skb)->protocol;
  902. break;
  903. case htons(ETH_P_IPV6):
  904. opts2 |= IPV6_CS;
  905. ip_protocol = ipv6_hdr(skb)->nexthdr;
  906. break;
  907. default:
  908. ip_protocol = IPPROTO_RAW;
  909. break;
  910. }
  911. if (ip_protocol == IPPROTO_TCP) {
  912. opts2 |= TCP_CS;
  913. opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
  914. } else if (ip_protocol == IPPROTO_UDP) {
  915. opts2 |= UDP_CS;
  916. } else {
  917. WARN_ON_ONCE(1);
  918. }
  919. desc->opts2 = cpu_to_le32(opts2);
  920. }
  921. }
  922. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  923. {
  924. int remain;
  925. u8 *tx_data;
  926. tx_data = agg->head;
  927. agg->skb_num = agg->skb_len = 0;
  928. remain = rx_buf_sz;
  929. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  930. struct tx_desc *tx_desc;
  931. struct sk_buff *skb;
  932. unsigned int len;
  933. skb = skb_dequeue(&tp->tx_queue);
  934. if (!skb)
  935. break;
  936. remain -= sizeof(*tx_desc);
  937. len = skb->len;
  938. if (remain < len) {
  939. skb_queue_head(&tp->tx_queue, skb);
  940. break;
  941. }
  942. tx_data = tx_agg_align(tx_data);
  943. tx_desc = (struct tx_desc *)tx_data;
  944. tx_data += sizeof(*tx_desc);
  945. r8152_tx_csum(tp, tx_desc, skb);
  946. memcpy(tx_data, skb->data, len);
  947. agg->skb_num++;
  948. agg->skb_len += len;
  949. dev_kfree_skb_any(skb);
  950. tx_data += len;
  951. remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  952. }
  953. netif_tx_lock(tp->netdev);
  954. if (netif_queue_stopped(tp->netdev) &&
  955. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  956. netif_wake_queue(tp->netdev);
  957. netif_tx_unlock(tp->netdev);
  958. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  959. agg->head, (int)(tx_data - (u8 *)agg->head),
  960. (usb_complete_t)write_bulk_callback, agg);
  961. return usb_submit_urb(agg->urb, GFP_ATOMIC);
  962. }
  963. static void rx_bottom(struct r8152 *tp)
  964. {
  965. unsigned long flags;
  966. struct list_head *cursor, *next;
  967. spin_lock_irqsave(&tp->rx_lock, flags);
  968. list_for_each_safe(cursor, next, &tp->rx_done) {
  969. struct rx_desc *rx_desc;
  970. struct rx_agg *agg;
  971. int len_used = 0;
  972. struct urb *urb;
  973. u8 *rx_data;
  974. int ret;
  975. list_del_init(cursor);
  976. spin_unlock_irqrestore(&tp->rx_lock, flags);
  977. agg = list_entry(cursor, struct rx_agg, list);
  978. urb = agg->urb;
  979. if (urb->actual_length < ETH_ZLEN)
  980. goto submit;
  981. rx_desc = agg->head;
  982. rx_data = agg->head;
  983. len_used += sizeof(struct rx_desc);
  984. while (urb->actual_length > len_used) {
  985. struct net_device *netdev = tp->netdev;
  986. struct net_device_stats *stats;
  987. unsigned int pkt_len;
  988. struct sk_buff *skb;
  989. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  990. if (pkt_len < ETH_ZLEN)
  991. break;
  992. len_used += pkt_len;
  993. if (urb->actual_length < len_used)
  994. break;
  995. stats = rtl8152_get_stats(netdev);
  996. pkt_len -= 4; /* CRC */
  997. rx_data += sizeof(struct rx_desc);
  998. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  999. if (!skb) {
  1000. stats->rx_dropped++;
  1001. break;
  1002. }
  1003. memcpy(skb->data, rx_data, pkt_len);
  1004. skb_put(skb, pkt_len);
  1005. skb->protocol = eth_type_trans(skb, netdev);
  1006. netif_rx(skb);
  1007. stats->rx_packets++;
  1008. stats->rx_bytes += pkt_len;
  1009. rx_data = rx_agg_align(rx_data + pkt_len + 4);
  1010. rx_desc = (struct rx_desc *)rx_data;
  1011. len_used = (int)(rx_data - (u8 *)agg->head);
  1012. len_used += sizeof(struct rx_desc);
  1013. }
  1014. submit:
  1015. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1016. spin_lock_irqsave(&tp->rx_lock, flags);
  1017. if (ret && ret != -ENODEV) {
  1018. list_add_tail(&agg->list, next);
  1019. tasklet_schedule(&tp->tl);
  1020. }
  1021. }
  1022. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1023. }
  1024. static void tx_bottom(struct r8152 *tp)
  1025. {
  1026. int res;
  1027. do {
  1028. struct tx_agg *agg;
  1029. if (skb_queue_empty(&tp->tx_queue))
  1030. break;
  1031. agg = r8152_get_tx_agg(tp);
  1032. if (!agg)
  1033. break;
  1034. res = r8152_tx_agg_fill(tp, agg);
  1035. if (res) {
  1036. struct net_device_stats *stats;
  1037. struct net_device *netdev;
  1038. unsigned long flags;
  1039. netdev = tp->netdev;
  1040. stats = rtl8152_get_stats(netdev);
  1041. if (res == -ENODEV) {
  1042. netif_device_detach(netdev);
  1043. } else {
  1044. netif_warn(tp, tx_err, netdev,
  1045. "failed tx_urb %d\n", res);
  1046. stats->tx_dropped += agg->skb_num;
  1047. spin_lock_irqsave(&tp->tx_lock, flags);
  1048. list_add_tail(&agg->list, &tp->tx_free);
  1049. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1050. }
  1051. }
  1052. } while (res == 0);
  1053. }
  1054. static void bottom_half(unsigned long data)
  1055. {
  1056. struct r8152 *tp;
  1057. tp = (struct r8152 *)data;
  1058. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1059. return;
  1060. if (!test_bit(WORK_ENABLE, &tp->flags))
  1061. return;
  1062. /* When link down, the driver would cancel all bulks. */
  1063. /* This avoid the re-submitting bulk */
  1064. if (!netif_carrier_ok(tp->netdev))
  1065. return;
  1066. rx_bottom(tp);
  1067. tx_bottom(tp);
  1068. }
  1069. static
  1070. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1071. {
  1072. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1073. agg->head, rx_buf_sz,
  1074. (usb_complete_t)read_bulk_callback, agg);
  1075. return usb_submit_urb(agg->urb, mem_flags);
  1076. }
  1077. static void rtl8152_tx_timeout(struct net_device *netdev)
  1078. {
  1079. struct r8152 *tp = netdev_priv(netdev);
  1080. int i;
  1081. netif_warn(tp, tx_err, netdev, "Tx timeout.\n");
  1082. for (i = 0; i < RTL8152_MAX_TX; i++)
  1083. usb_unlink_urb(tp->tx_info[i].urb);
  1084. }
  1085. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1086. {
  1087. struct r8152 *tp = netdev_priv(netdev);
  1088. if (tp->speed & LINK_STATUS) {
  1089. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1090. schedule_delayed_work(&tp->schedule, 0);
  1091. }
  1092. }
  1093. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1094. {
  1095. struct r8152 *tp = netdev_priv(netdev);
  1096. u32 mc_filter[2]; /* Multicast hash filter */
  1097. __le32 tmp[2];
  1098. u32 ocp_data;
  1099. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1100. netif_stop_queue(netdev);
  1101. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1102. ocp_data &= ~RCR_ACPT_ALL;
  1103. ocp_data |= RCR_AB | RCR_APM;
  1104. if (netdev->flags & IFF_PROMISC) {
  1105. /* Unconditionally log net taps. */
  1106. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1107. ocp_data |= RCR_AM | RCR_AAP;
  1108. mc_filter[1] = mc_filter[0] = 0xffffffff;
  1109. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1110. (netdev->flags & IFF_ALLMULTI)) {
  1111. /* Too many to filter perfectly -- accept all multicasts. */
  1112. ocp_data |= RCR_AM;
  1113. mc_filter[1] = mc_filter[0] = 0xffffffff;
  1114. } else {
  1115. struct netdev_hw_addr *ha;
  1116. mc_filter[1] = mc_filter[0] = 0;
  1117. netdev_for_each_mc_addr(ha, netdev) {
  1118. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1119. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1120. ocp_data |= RCR_AM;
  1121. }
  1122. }
  1123. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1124. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1125. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1126. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1127. netif_wake_queue(netdev);
  1128. }
  1129. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1130. struct net_device *netdev)
  1131. {
  1132. struct r8152 *tp = netdev_priv(netdev);
  1133. skb_tx_timestamp(skb);
  1134. skb_queue_tail(&tp->tx_queue, skb);
  1135. if (list_empty(&tp->tx_free) &&
  1136. skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
  1137. netif_stop_queue(netdev);
  1138. if (!list_empty(&tp->tx_free))
  1139. tasklet_schedule(&tp->tl);
  1140. return NETDEV_TX_OK;
  1141. }
  1142. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1143. {
  1144. u32 ocp_data;
  1145. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1146. ocp_data &= ~FMC_FCR_MCU_EN;
  1147. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1148. ocp_data |= FMC_FCR_MCU_EN;
  1149. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1150. }
  1151. static void rtl8152_nic_reset(struct r8152 *tp)
  1152. {
  1153. int i;
  1154. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1155. for (i = 0; i < 1000; i++) {
  1156. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1157. break;
  1158. udelay(100);
  1159. }
  1160. }
  1161. static void set_tx_qlen(struct r8152 *tp)
  1162. {
  1163. struct net_device *netdev = tp->netdev;
  1164. tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1165. sizeof(struct tx_desc));
  1166. }
  1167. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1168. {
  1169. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1170. }
  1171. static int rtl8152_enable(struct r8152 *tp)
  1172. {
  1173. u32 ocp_data;
  1174. int i, ret;
  1175. u8 speed;
  1176. set_tx_qlen(tp);
  1177. speed = rtl8152_get_speed(tp);
  1178. if (speed & _10bps) {
  1179. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1180. ocp_data |= EEEP_CR_EEEP_TX;
  1181. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1182. } else {
  1183. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1184. ocp_data &= ~EEEP_CR_EEEP_TX;
  1185. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1186. }
  1187. r8152b_reset_packet_filter(tp);
  1188. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1189. ocp_data |= CR_RE | CR_TE;
  1190. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1191. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1192. ocp_data &= ~RXDY_GATED_EN;
  1193. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1194. INIT_LIST_HEAD(&tp->rx_done);
  1195. ret = 0;
  1196. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1197. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1198. ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1199. }
  1200. return ret;
  1201. }
  1202. static void rtl8152_disable(struct r8152 *tp)
  1203. {
  1204. struct net_device_stats *stats = rtl8152_get_stats(tp->netdev);
  1205. struct sk_buff *skb;
  1206. u32 ocp_data;
  1207. int i;
  1208. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1209. ocp_data &= ~RCR_ACPT_ALL;
  1210. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1211. while ((skb = skb_dequeue(&tp->tx_queue))) {
  1212. dev_kfree_skb(skb);
  1213. stats->tx_dropped++;
  1214. }
  1215. for (i = 0; i < RTL8152_MAX_TX; i++)
  1216. usb_kill_urb(tp->tx_info[i].urb);
  1217. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1218. ocp_data |= RXDY_GATED_EN;
  1219. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1220. for (i = 0; i < 1000; i++) {
  1221. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1222. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1223. break;
  1224. mdelay(1);
  1225. }
  1226. for (i = 0; i < 1000; i++) {
  1227. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1228. break;
  1229. mdelay(1);
  1230. }
  1231. for (i = 0; i < RTL8152_MAX_RX; i++)
  1232. usb_kill_urb(tp->rx_info[i].urb);
  1233. rtl8152_nic_reset(tp);
  1234. }
  1235. static void r8152b_exit_oob(struct r8152 *tp)
  1236. {
  1237. u32 ocp_data;
  1238. int i;
  1239. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1240. ocp_data &= ~RCR_ACPT_ALL;
  1241. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1242. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1243. ocp_data |= RXDY_GATED_EN;
  1244. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1245. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1246. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  1247. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1248. ocp_data &= ~NOW_IS_OOB;
  1249. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1250. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1251. ocp_data &= ~MCU_BORW_EN;
  1252. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1253. for (i = 0; i < 1000; i++) {
  1254. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1255. if (ocp_data & LINK_LIST_READY)
  1256. break;
  1257. mdelay(1);
  1258. }
  1259. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1260. ocp_data |= RE_INIT_LL;
  1261. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1262. for (i = 0; i < 1000; i++) {
  1263. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1264. if (ocp_data & LINK_LIST_READY)
  1265. break;
  1266. mdelay(1);
  1267. }
  1268. rtl8152_nic_reset(tp);
  1269. /* rx share fifo credit full threshold */
  1270. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  1271. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
  1272. ocp_data &= STAT_SPEED_MASK;
  1273. if (ocp_data == STAT_SPEED_FULL) {
  1274. /* rx share fifo credit near full threshold */
  1275. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1276. RXFIFO_THR2_FULL);
  1277. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1278. RXFIFO_THR3_FULL);
  1279. } else {
  1280. /* rx share fifo credit near full threshold */
  1281. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1282. RXFIFO_THR2_HIGH);
  1283. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1284. RXFIFO_THR3_HIGH);
  1285. }
  1286. /* TX share fifo free credit full threshold */
  1287. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  1288. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  1289. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR);
  1290. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  1291. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  1292. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1293. ocp_data &= ~CPCR_RX_VLAN;
  1294. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1295. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  1296. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  1297. ocp_data |= TCR0_AUTO_FIFO;
  1298. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  1299. }
  1300. static void r8152b_enter_oob(struct r8152 *tp)
  1301. {
  1302. u32 ocp_data;
  1303. int i;
  1304. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1305. ocp_data &= ~NOW_IS_OOB;
  1306. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1307. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  1308. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  1309. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  1310. rtl8152_disable(tp);
  1311. for (i = 0; i < 1000; i++) {
  1312. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1313. if (ocp_data & LINK_LIST_READY)
  1314. break;
  1315. mdelay(1);
  1316. }
  1317. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1318. ocp_data |= RE_INIT_LL;
  1319. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1320. for (i = 0; i < 1000; i++) {
  1321. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1322. if (ocp_data & LINK_LIST_READY)
  1323. break;
  1324. mdelay(1);
  1325. }
  1326. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  1327. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1328. ocp_data |= MAGIC_EN;
  1329. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1330. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1331. ocp_data |= CPCR_RX_VLAN;
  1332. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1333. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  1334. ocp_data |= ALDPS_PROXY_MODE;
  1335. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  1336. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1337. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  1338. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1339. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
  1340. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1341. ocp_data &= ~RXDY_GATED_EN;
  1342. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1343. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1344. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  1345. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1346. }
  1347. static void r8152b_disable_aldps(struct r8152 *tp)
  1348. {
  1349. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1350. msleep(20);
  1351. }
  1352. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1353. {
  1354. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1355. LINKENA | DIS_SDSAVE);
  1356. }
  1357. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  1358. {
  1359. u16 bmcr, anar;
  1360. int ret = 0;
  1361. cancel_delayed_work_sync(&tp->schedule);
  1362. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1363. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  1364. ADVERTISE_100HALF | ADVERTISE_100FULL);
  1365. if (autoneg == AUTONEG_DISABLE) {
  1366. if (speed == SPEED_10) {
  1367. bmcr = 0;
  1368. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1369. } else if (speed == SPEED_100) {
  1370. bmcr = BMCR_SPEED100;
  1371. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1372. } else {
  1373. ret = -EINVAL;
  1374. goto out;
  1375. }
  1376. if (duplex == DUPLEX_FULL)
  1377. bmcr |= BMCR_FULLDPLX;
  1378. } else {
  1379. if (speed == SPEED_10) {
  1380. if (duplex == DUPLEX_FULL)
  1381. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1382. else
  1383. anar |= ADVERTISE_10HALF;
  1384. } else if (speed == SPEED_100) {
  1385. if (duplex == DUPLEX_FULL) {
  1386. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1387. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1388. } else {
  1389. anar |= ADVERTISE_10HALF;
  1390. anar |= ADVERTISE_100HALF;
  1391. }
  1392. } else {
  1393. ret = -EINVAL;
  1394. goto out;
  1395. }
  1396. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  1397. }
  1398. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1399. r8152_mdio_write(tp, MII_BMCR, bmcr);
  1400. out:
  1401. return ret;
  1402. }
  1403. static void rtl8152_down(struct r8152 *tp)
  1404. {
  1405. u32 ocp_data;
  1406. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1407. ocp_data &= ~POWER_CUT;
  1408. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1409. r8152b_disable_aldps(tp);
  1410. r8152b_enter_oob(tp);
  1411. r8152b_enable_aldps(tp);
  1412. }
  1413. static void set_carrier(struct r8152 *tp)
  1414. {
  1415. struct net_device *netdev = tp->netdev;
  1416. u8 speed;
  1417. clear_bit(RTL8152_LINK_CHG, &tp->flags);
  1418. speed = rtl8152_get_speed(tp);
  1419. if (speed & LINK_STATUS) {
  1420. if (!(tp->speed & LINK_STATUS)) {
  1421. rtl8152_enable(tp);
  1422. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1423. netif_carrier_on(netdev);
  1424. }
  1425. } else {
  1426. if (tp->speed & LINK_STATUS) {
  1427. netif_carrier_off(netdev);
  1428. tasklet_disable(&tp->tl);
  1429. rtl8152_disable(tp);
  1430. tasklet_enable(&tp->tl);
  1431. }
  1432. }
  1433. tp->speed = speed;
  1434. }
  1435. static void rtl_work_func_t(struct work_struct *work)
  1436. {
  1437. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  1438. if (!test_bit(WORK_ENABLE, &tp->flags))
  1439. goto out1;
  1440. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1441. goto out1;
  1442. if (test_bit(RTL8152_LINK_CHG, &tp->flags))
  1443. set_carrier(tp);
  1444. if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
  1445. _rtl8152_set_rx_mode(tp->netdev);
  1446. out1:
  1447. return;
  1448. }
  1449. static int rtl8152_open(struct net_device *netdev)
  1450. {
  1451. struct r8152 *tp = netdev_priv(netdev);
  1452. int res = 0;
  1453. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  1454. if (res) {
  1455. if (res == -ENODEV)
  1456. netif_device_detach(tp->netdev);
  1457. netif_warn(tp, ifup, netdev,
  1458. "intr_urb submit failed: %d\n", res);
  1459. return res;
  1460. }
  1461. rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
  1462. tp->speed = 0;
  1463. netif_carrier_off(netdev);
  1464. netif_start_queue(netdev);
  1465. set_bit(WORK_ENABLE, &tp->flags);
  1466. return res;
  1467. }
  1468. static int rtl8152_close(struct net_device *netdev)
  1469. {
  1470. struct r8152 *tp = netdev_priv(netdev);
  1471. int res = 0;
  1472. usb_kill_urb(tp->intr_urb);
  1473. clear_bit(WORK_ENABLE, &tp->flags);
  1474. cancel_delayed_work_sync(&tp->schedule);
  1475. netif_stop_queue(netdev);
  1476. tasklet_disable(&tp->tl);
  1477. rtl8152_disable(tp);
  1478. tasklet_enable(&tp->tl);
  1479. return res;
  1480. }
  1481. static void rtl_clear_bp(struct r8152 *tp)
  1482. {
  1483. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
  1484. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
  1485. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
  1486. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
  1487. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
  1488. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
  1489. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
  1490. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
  1491. mdelay(3);
  1492. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
  1493. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
  1494. }
  1495. static void r8152b_enable_eee(struct r8152 *tp)
  1496. {
  1497. u32 ocp_data;
  1498. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  1499. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  1500. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  1501. ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
  1502. EEE_10_CAP | EEE_NWAY_EN |
  1503. TX_QUIET_EN | RX_QUIET_EN |
  1504. SDRISETIME | RG_RXLPI_MSK_HFDUP |
  1505. SDFALLTIME);
  1506. ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
  1507. RG_LDVQUIET_EN | RG_CKRSEL |
  1508. RG_EEEPRG_EN);
  1509. ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
  1510. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
  1511. ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
  1512. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
  1513. ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
  1514. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  1515. }
  1516. static void r8152b_enable_fc(struct r8152 *tp)
  1517. {
  1518. u16 anar;
  1519. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1520. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1521. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1522. }
  1523. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1524. {
  1525. r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
  1526. r8152b_disable_aldps(tp);
  1527. }
  1528. static void r8152b_init(struct r8152 *tp)
  1529. {
  1530. u32 ocp_data;
  1531. int i;
  1532. rtl_clear_bp(tp);
  1533. if (tp->version == RTL_VER_01) {
  1534. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  1535. ocp_data &= ~LED_MODE_MASK;
  1536. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  1537. }
  1538. r8152b_hw_phy_cfg(tp);
  1539. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1540. ocp_data &= ~POWER_CUT;
  1541. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1542. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1543. ocp_data &= ~RWSUME_INDICATE;
  1544. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1545. r8152b_exit_oob(tp);
  1546. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  1547. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  1548. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  1549. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  1550. ocp_data &= ~MCU_CLK_RATIO_MASK;
  1551. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  1552. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  1553. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  1554. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  1555. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  1556. r8152b_enable_eee(tp);
  1557. r8152b_enable_aldps(tp);
  1558. r8152b_enable_fc(tp);
  1559. r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
  1560. BMCR_ANRESTART);
  1561. for (i = 0; i < 100; i++) {
  1562. udelay(100);
  1563. if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
  1564. break;
  1565. }
  1566. /* enable rx aggregation */
  1567. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  1568. ocp_data &= ~RX_AGG_DISABLE;
  1569. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  1570. }
  1571. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  1572. {
  1573. struct r8152 *tp = usb_get_intfdata(intf);
  1574. netif_device_detach(tp->netdev);
  1575. if (netif_running(tp->netdev)) {
  1576. clear_bit(WORK_ENABLE, &tp->flags);
  1577. usb_kill_urb(tp->intr_urb);
  1578. cancel_delayed_work_sync(&tp->schedule);
  1579. tasklet_disable(&tp->tl);
  1580. }
  1581. rtl8152_down(tp);
  1582. return 0;
  1583. }
  1584. static int rtl8152_resume(struct usb_interface *intf)
  1585. {
  1586. struct r8152 *tp = usb_get_intfdata(intf);
  1587. r8152b_init(tp);
  1588. netif_device_attach(tp->netdev);
  1589. if (netif_running(tp->netdev)) {
  1590. rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
  1591. tp->speed = 0;
  1592. netif_carrier_off(tp->netdev);
  1593. set_bit(WORK_ENABLE, &tp->flags);
  1594. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  1595. tasklet_enable(&tp->tl);
  1596. }
  1597. return 0;
  1598. }
  1599. static void rtl8152_get_drvinfo(struct net_device *netdev,
  1600. struct ethtool_drvinfo *info)
  1601. {
  1602. struct r8152 *tp = netdev_priv(netdev);
  1603. strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
  1604. strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
  1605. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  1606. }
  1607. static
  1608. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  1609. {
  1610. struct r8152 *tp = netdev_priv(netdev);
  1611. if (!tp->mii.mdio_read)
  1612. return -EOPNOTSUPP;
  1613. return mii_ethtool_gset(&tp->mii, cmd);
  1614. }
  1615. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1616. {
  1617. struct r8152 *tp = netdev_priv(dev);
  1618. return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  1619. }
  1620. static struct ethtool_ops ops = {
  1621. .get_drvinfo = rtl8152_get_drvinfo,
  1622. .get_settings = rtl8152_get_settings,
  1623. .set_settings = rtl8152_set_settings,
  1624. .get_link = ethtool_op_get_link,
  1625. };
  1626. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  1627. {
  1628. struct r8152 *tp = netdev_priv(netdev);
  1629. struct mii_ioctl_data *data = if_mii(rq);
  1630. int res = 0;
  1631. switch (cmd) {
  1632. case SIOCGMIIPHY:
  1633. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  1634. break;
  1635. case SIOCGMIIREG:
  1636. data->val_out = r8152_mdio_read(tp, data->reg_num);
  1637. break;
  1638. case SIOCSMIIREG:
  1639. if (!capable(CAP_NET_ADMIN)) {
  1640. res = -EPERM;
  1641. break;
  1642. }
  1643. r8152_mdio_write(tp, data->reg_num, data->val_in);
  1644. break;
  1645. default:
  1646. res = -EOPNOTSUPP;
  1647. }
  1648. return res;
  1649. }
  1650. static const struct net_device_ops rtl8152_netdev_ops = {
  1651. .ndo_open = rtl8152_open,
  1652. .ndo_stop = rtl8152_close,
  1653. .ndo_do_ioctl = rtl8152_ioctl,
  1654. .ndo_start_xmit = rtl8152_start_xmit,
  1655. .ndo_tx_timeout = rtl8152_tx_timeout,
  1656. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  1657. .ndo_set_mac_address = rtl8152_set_mac_address,
  1658. .ndo_change_mtu = eth_change_mtu,
  1659. .ndo_validate_addr = eth_validate_addr,
  1660. };
  1661. static void r8152b_get_version(struct r8152 *tp)
  1662. {
  1663. u32 ocp_data;
  1664. u16 version;
  1665. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  1666. version = (u16)(ocp_data & VERSION_MASK);
  1667. switch (version) {
  1668. case 0x4c00:
  1669. tp->version = RTL_VER_01;
  1670. break;
  1671. case 0x4c10:
  1672. tp->version = RTL_VER_02;
  1673. break;
  1674. default:
  1675. netif_info(tp, probe, tp->netdev,
  1676. "Unknown version 0x%04x\n", version);
  1677. break;
  1678. }
  1679. }
  1680. static int rtl8152_probe(struct usb_interface *intf,
  1681. const struct usb_device_id *id)
  1682. {
  1683. struct usb_device *udev = interface_to_usbdev(intf);
  1684. struct r8152 *tp;
  1685. struct net_device *netdev;
  1686. int ret;
  1687. if (udev->actconfig->desc.bConfigurationValue != 1) {
  1688. usb_driver_set_configuration(udev, 1);
  1689. return -ENODEV;
  1690. }
  1691. netdev = alloc_etherdev(sizeof(struct r8152));
  1692. if (!netdev) {
  1693. dev_err(&intf->dev, "Out of memory");
  1694. return -ENOMEM;
  1695. }
  1696. SET_NETDEV_DEV(netdev, &intf->dev);
  1697. tp = netdev_priv(netdev);
  1698. tp->msg_enable = 0x7FFF;
  1699. tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
  1700. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  1701. tp->udev = udev;
  1702. tp->netdev = netdev;
  1703. tp->intf = intf;
  1704. netdev->netdev_ops = &rtl8152_netdev_ops;
  1705. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  1706. netdev->features |= NETIF_F_IP_CSUM;
  1707. netdev->hw_features = NETIF_F_IP_CSUM;
  1708. SET_ETHTOOL_OPS(netdev, &ops);
  1709. tp->mii.dev = netdev;
  1710. tp->mii.mdio_read = read_mii_word;
  1711. tp->mii.mdio_write = write_mii_word;
  1712. tp->mii.phy_id_mask = 0x3f;
  1713. tp->mii.reg_num_mask = 0x1f;
  1714. tp->mii.phy_id = R8152_PHY_ID;
  1715. tp->mii.supports_gmii = 0;
  1716. r8152b_get_version(tp);
  1717. r8152b_init(tp);
  1718. set_ethernet_addr(tp);
  1719. ret = alloc_all_mem(tp);
  1720. if (ret)
  1721. goto out;
  1722. usb_set_intfdata(intf, tp);
  1723. ret = register_netdev(netdev);
  1724. if (ret != 0) {
  1725. netif_err(tp, probe, netdev, "couldn't register the device");
  1726. goto out1;
  1727. }
  1728. netif_info(tp, probe, netdev, "%s", DRIVER_VERSION);
  1729. return 0;
  1730. out1:
  1731. usb_set_intfdata(intf, NULL);
  1732. out:
  1733. free_netdev(netdev);
  1734. return ret;
  1735. }
  1736. static void rtl8152_unload(struct r8152 *tp)
  1737. {
  1738. u32 ocp_data;
  1739. if (tp->version != RTL_VER_01) {
  1740. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1741. ocp_data |= POWER_CUT;
  1742. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1743. }
  1744. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1745. ocp_data &= ~RWSUME_INDICATE;
  1746. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1747. }
  1748. static void rtl8152_disconnect(struct usb_interface *intf)
  1749. {
  1750. struct r8152 *tp = usb_get_intfdata(intf);
  1751. usb_set_intfdata(intf, NULL);
  1752. if (tp) {
  1753. set_bit(RTL8152_UNPLUG, &tp->flags);
  1754. tasklet_kill(&tp->tl);
  1755. unregister_netdev(tp->netdev);
  1756. rtl8152_unload(tp);
  1757. free_all_mem(tp);
  1758. free_netdev(tp->netdev);
  1759. }
  1760. }
  1761. /* table of devices that work with this driver */
  1762. static struct usb_device_id rtl8152_table[] = {
  1763. {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
  1764. {}
  1765. };
  1766. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  1767. static struct usb_driver rtl8152_driver = {
  1768. .name = MODULENAME,
  1769. .id_table = rtl8152_table,
  1770. .probe = rtl8152_probe,
  1771. .disconnect = rtl8152_disconnect,
  1772. .suspend = rtl8152_suspend,
  1773. .resume = rtl8152_resume,
  1774. .reset_resume = rtl8152_resume,
  1775. };
  1776. module_usb_driver(rtl8152_driver);
  1777. MODULE_AUTHOR(DRIVER_AUTHOR);
  1778. MODULE_DESCRIPTION(DRIVER_DESC);
  1779. MODULE_LICENSE("GPL");