core.h 12 KB

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  1. /*
  2. * include/linux/mfd/wm831x/core.h -- Core interface for WM831x
  3. *
  4. * Copyright 2009 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #ifndef __MFD_WM831X_CORE_H__
  15. #define __MFD_WM831X_CORE_H__
  16. /*
  17. * Register values.
  18. */
  19. #define WM831X_RESET_ID 0x00
  20. #define WM831X_REVISION 0x01
  21. #define WM831X_PARENT_ID 0x4000
  22. #define WM831X_SYSVDD_CONTROL 0x4001
  23. #define WM831X_THERMAL_MONITORING 0x4002
  24. #define WM831X_POWER_STATE 0x4003
  25. #define WM831X_WATCHDOG 0x4004
  26. #define WM831X_ON_PIN_CONTROL 0x4005
  27. #define WM831X_RESET_CONTROL 0x4006
  28. #define WM831X_CONTROL_INTERFACE 0x4007
  29. #define WM831X_SECURITY_KEY 0x4008
  30. #define WM831X_SOFTWARE_SCRATCH 0x4009
  31. #define WM831X_OTP_CONTROL 0x400A
  32. #define WM831X_GPIO_LEVEL 0x400C
  33. #define WM831X_SYSTEM_STATUS 0x400D
  34. #define WM831X_ON_SOURCE 0x400E
  35. #define WM831X_OFF_SOURCE 0x400F
  36. #define WM831X_SYSTEM_INTERRUPTS 0x4010
  37. #define WM831X_INTERRUPT_STATUS_1 0x4011
  38. #define WM831X_INTERRUPT_STATUS_2 0x4012
  39. #define WM831X_INTERRUPT_STATUS_3 0x4013
  40. #define WM831X_INTERRUPT_STATUS_4 0x4014
  41. #define WM831X_INTERRUPT_STATUS_5 0x4015
  42. #define WM831X_IRQ_CONFIG 0x4017
  43. #define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018
  44. #define WM831X_INTERRUPT_STATUS_1_MASK 0x4019
  45. #define WM831X_INTERRUPT_STATUS_2_MASK 0x401A
  46. #define WM831X_INTERRUPT_STATUS_3_MASK 0x401B
  47. #define WM831X_INTERRUPT_STATUS_4_MASK 0x401C
  48. #define WM831X_INTERRUPT_STATUS_5_MASK 0x401D
  49. #define WM831X_RTC_WRITE_COUNTER 0x4020
  50. #define WM831X_RTC_TIME_1 0x4021
  51. #define WM831X_RTC_TIME_2 0x4022
  52. #define WM831X_RTC_ALARM_1 0x4023
  53. #define WM831X_RTC_ALARM_2 0x4024
  54. #define WM831X_RTC_CONTROL 0x4025
  55. #define WM831X_RTC_TRIM 0x4026
  56. #define WM831X_TOUCH_CONTROL_1 0x4028
  57. #define WM831X_TOUCH_CONTROL_2 0x4029
  58. #define WM831X_TOUCH_DATA_X 0x402A
  59. #define WM831X_TOUCH_DATA_Y 0x402B
  60. #define WM831X_TOUCH_DATA_Z 0x402C
  61. #define WM831X_AUXADC_DATA 0x402D
  62. #define WM831X_AUXADC_CONTROL 0x402E
  63. #define WM831X_AUXADC_SOURCE 0x402F
  64. #define WM831X_COMPARATOR_CONTROL 0x4030
  65. #define WM831X_COMPARATOR_1 0x4031
  66. #define WM831X_COMPARATOR_2 0x4032
  67. #define WM831X_COMPARATOR_3 0x4033
  68. #define WM831X_COMPARATOR_4 0x4034
  69. #define WM831X_GPIO1_CONTROL 0x4038
  70. #define WM831X_GPIO2_CONTROL 0x4039
  71. #define WM831X_GPIO3_CONTROL 0x403A
  72. #define WM831X_GPIO4_CONTROL 0x403B
  73. #define WM831X_GPIO5_CONTROL 0x403C
  74. #define WM831X_GPIO6_CONTROL 0x403D
  75. #define WM831X_GPIO7_CONTROL 0x403E
  76. #define WM831X_GPIO8_CONTROL 0x403F
  77. #define WM831X_GPIO9_CONTROL 0x4040
  78. #define WM831X_GPIO10_CONTROL 0x4041
  79. #define WM831X_GPIO11_CONTROL 0x4042
  80. #define WM831X_GPIO12_CONTROL 0x4043
  81. #define WM831X_GPIO13_CONTROL 0x4044
  82. #define WM831X_GPIO14_CONTROL 0x4045
  83. #define WM831X_GPIO15_CONTROL 0x4046
  84. #define WM831X_GPIO16_CONTROL 0x4047
  85. #define WM831X_CHARGER_CONTROL_1 0x4048
  86. #define WM831X_CHARGER_CONTROL_2 0x4049
  87. #define WM831X_CHARGER_STATUS 0x404A
  88. #define WM831X_BACKUP_CHARGER_CONTROL 0x404B
  89. #define WM831X_STATUS_LED_1 0x404C
  90. #define WM831X_STATUS_LED_2 0x404D
  91. #define WM831X_CURRENT_SINK_1 0x404E
  92. #define WM831X_CURRENT_SINK_2 0x404F
  93. #define WM831X_DCDC_ENABLE 0x4050
  94. #define WM831X_LDO_ENABLE 0x4051
  95. #define WM831X_DCDC_STATUS 0x4052
  96. #define WM831X_LDO_STATUS 0x4053
  97. #define WM831X_DCDC_UV_STATUS 0x4054
  98. #define WM831X_LDO_UV_STATUS 0x4055
  99. #define WM831X_DC1_CONTROL_1 0x4056
  100. #define WM831X_DC1_CONTROL_2 0x4057
  101. #define WM831X_DC1_ON_CONFIG 0x4058
  102. #define WM831X_DC1_SLEEP_CONTROL 0x4059
  103. #define WM831X_DC1_DVS_CONTROL 0x405A
  104. #define WM831X_DC2_CONTROL_1 0x405B
  105. #define WM831X_DC2_CONTROL_2 0x405C
  106. #define WM831X_DC2_ON_CONFIG 0x405D
  107. #define WM831X_DC2_SLEEP_CONTROL 0x405E
  108. #define WM831X_DC2_DVS_CONTROL 0x405F
  109. #define WM831X_DC3_CONTROL_1 0x4060
  110. #define WM831X_DC3_CONTROL_2 0x4061
  111. #define WM831X_DC3_ON_CONFIG 0x4062
  112. #define WM831X_DC3_SLEEP_CONTROL 0x4063
  113. #define WM831X_DC4_CONTROL 0x4064
  114. #define WM831X_DC4_SLEEP_CONTROL 0x4065
  115. #define WM831X_EPE1_CONTROL 0x4066
  116. #define WM831X_EPE2_CONTROL 0x4067
  117. #define WM831X_LDO1_CONTROL 0x4068
  118. #define WM831X_LDO1_ON_CONTROL 0x4069
  119. #define WM831X_LDO1_SLEEP_CONTROL 0x406A
  120. #define WM831X_LDO2_CONTROL 0x406B
  121. #define WM831X_LDO2_ON_CONTROL 0x406C
  122. #define WM831X_LDO2_SLEEP_CONTROL 0x406D
  123. #define WM831X_LDO3_CONTROL 0x406E
  124. #define WM831X_LDO3_ON_CONTROL 0x406F
  125. #define WM831X_LDO3_SLEEP_CONTROL 0x4070
  126. #define WM831X_LDO4_CONTROL 0x4071
  127. #define WM831X_LDO4_ON_CONTROL 0x4072
  128. #define WM831X_LDO4_SLEEP_CONTROL 0x4073
  129. #define WM831X_LDO5_CONTROL 0x4074
  130. #define WM831X_LDO5_ON_CONTROL 0x4075
  131. #define WM831X_LDO5_SLEEP_CONTROL 0x4076
  132. #define WM831X_LDO6_CONTROL 0x4077
  133. #define WM831X_LDO6_ON_CONTROL 0x4078
  134. #define WM831X_LDO6_SLEEP_CONTROL 0x4079
  135. #define WM831X_LDO7_CONTROL 0x407A
  136. #define WM831X_LDO7_ON_CONTROL 0x407B
  137. #define WM831X_LDO7_SLEEP_CONTROL 0x407C
  138. #define WM831X_LDO8_CONTROL 0x407D
  139. #define WM831X_LDO8_ON_CONTROL 0x407E
  140. #define WM831X_LDO8_SLEEP_CONTROL 0x407F
  141. #define WM831X_LDO9_CONTROL 0x4080
  142. #define WM831X_LDO9_ON_CONTROL 0x4081
  143. #define WM831X_LDO9_SLEEP_CONTROL 0x4082
  144. #define WM831X_LDO10_CONTROL 0x4083
  145. #define WM831X_LDO10_ON_CONTROL 0x4084
  146. #define WM831X_LDO10_SLEEP_CONTROL 0x4085
  147. #define WM831X_LDO11_ON_CONTROL 0x4087
  148. #define WM831X_LDO11_SLEEP_CONTROL 0x4088
  149. #define WM831X_POWER_GOOD_SOURCE_1 0x408E
  150. #define WM831X_POWER_GOOD_SOURCE_2 0x408F
  151. #define WM831X_CLOCK_CONTROL_1 0x4090
  152. #define WM831X_CLOCK_CONTROL_2 0x4091
  153. #define WM831X_FLL_CONTROL_1 0x4092
  154. #define WM831X_FLL_CONTROL_2 0x4093
  155. #define WM831X_FLL_CONTROL_3 0x4094
  156. #define WM831X_FLL_CONTROL_4 0x4095
  157. #define WM831X_FLL_CONTROL_5 0x4096
  158. #define WM831X_UNIQUE_ID_1 0x7800
  159. #define WM831X_UNIQUE_ID_2 0x7801
  160. #define WM831X_UNIQUE_ID_3 0x7802
  161. #define WM831X_UNIQUE_ID_4 0x7803
  162. #define WM831X_UNIQUE_ID_5 0x7804
  163. #define WM831X_UNIQUE_ID_6 0x7805
  164. #define WM831X_UNIQUE_ID_7 0x7806
  165. #define WM831X_UNIQUE_ID_8 0x7807
  166. #define WM831X_FACTORY_OTP_ID 0x7808
  167. #define WM831X_FACTORY_OTP_1 0x7809
  168. #define WM831X_FACTORY_OTP_2 0x780A
  169. #define WM831X_FACTORY_OTP_3 0x780B
  170. #define WM831X_FACTORY_OTP_4 0x780C
  171. #define WM831X_FACTORY_OTP_5 0x780D
  172. #define WM831X_CUSTOMER_OTP_ID 0x7810
  173. #define WM831X_DC1_OTP_CONTROL 0x7811
  174. #define WM831X_DC2_OTP_CONTROL 0x7812
  175. #define WM831X_DC3_OTP_CONTROL 0x7813
  176. #define WM831X_LDO1_2_OTP_CONTROL 0x7814
  177. #define WM831X_LDO3_4_OTP_CONTROL 0x7815
  178. #define WM831X_LDO5_6_OTP_CONTROL 0x7816
  179. #define WM831X_LDO7_8_OTP_CONTROL 0x7817
  180. #define WM831X_LDO9_10_OTP_CONTROL 0x7818
  181. #define WM831X_LDO11_EPE_CONTROL 0x7819
  182. #define WM831X_GPIO1_OTP_CONTROL 0x781A
  183. #define WM831X_GPIO2_OTP_CONTROL 0x781B
  184. #define WM831X_GPIO3_OTP_CONTROL 0x781C
  185. #define WM831X_GPIO4_OTP_CONTROL 0x781D
  186. #define WM831X_GPIO5_OTP_CONTROL 0x781E
  187. #define WM831X_GPIO6_OTP_CONTROL 0x781F
  188. #define WM831X_DBE_CHECK_DATA 0x7827
  189. /*
  190. * R0 (0x00) - Reset ID
  191. */
  192. #define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
  193. #define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
  194. #define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
  195. /*
  196. * R1 (0x01) - Revision
  197. */
  198. #define WM831X_PARENT_REV_MASK 0xFF00 /* PARENT_REV - [15:8] */
  199. #define WM831X_PARENT_REV_SHIFT 8 /* PARENT_REV - [15:8] */
  200. #define WM831X_PARENT_REV_WIDTH 8 /* PARENT_REV - [15:8] */
  201. #define WM831X_CHILD_REV_MASK 0x00FF /* CHILD_REV - [7:0] */
  202. #define WM831X_CHILD_REV_SHIFT 0 /* CHILD_REV - [7:0] */
  203. #define WM831X_CHILD_REV_WIDTH 8 /* CHILD_REV - [7:0] */
  204. /*
  205. * R16384 (0x4000) - Parent ID
  206. */
  207. #define WM831X_PARENT_ID_MASK 0xFFFF /* PARENT_ID - [15:0] */
  208. #define WM831X_PARENT_ID_SHIFT 0 /* PARENT_ID - [15:0] */
  209. #define WM831X_PARENT_ID_WIDTH 16 /* PARENT_ID - [15:0] */
  210. struct wm831x {
  211. struct mutex io_lock;
  212. struct device *dev;
  213. int (*read_dev)(struct wm831x *wm831x, unsigned short reg,
  214. int bytes, void *dest);
  215. int (*write_dev)(struct wm831x *wm831x, unsigned short reg,
  216. int bytes, void *src);
  217. void *control_data;
  218. /* The WM831x has a security key blocking access to certain
  219. * registers. The mutex is taken by the accessors for locking
  220. * and unlocking the security key, locked is used to fail
  221. * writes if the lock is held.
  222. */
  223. struct mutex key_lock;
  224. unsigned int locked:1;
  225. };
  226. /* Device I/O API */
  227. int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg);
  228. int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
  229. unsigned short val);
  230. void wm831x_reg_lock(struct wm831x *wm831x);
  231. int wm831x_reg_unlock(struct wm831x *wm831x);
  232. int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
  233. unsigned short mask, unsigned short val);
  234. int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
  235. int count, u16 *buf);
  236. #endif