sgiwd93.c 8.4 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
  7. * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
  8. * Copyright (C) 2001 Florian Lohoff (flo@rfc822.org)
  9. * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
  10. *
  11. * (In all truth, Jed Schimmel wrote all this code.)
  12. */
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/types.h>
  16. #include <linux/mm.h>
  17. #include <linux/blkdev.h>
  18. #include <linux/version.h>
  19. #include <linux/delay.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/spinlock.h>
  22. #include <asm/page.h>
  23. #include <asm/pgtable.h>
  24. #include <asm/sgialib.h>
  25. #include <asm/sgi/sgi.h>
  26. #include <asm/sgi/mc.h>
  27. #include <asm/sgi/hpc3.h>
  28. #include <asm/sgi/ip22.h>
  29. #include <asm/irq.h>
  30. #include <asm/io.h>
  31. #include "scsi.h"
  32. #include <scsi/scsi_host.h>
  33. #include "wd33c93.h"
  34. #include <linux/stat.h>
  35. #if 0
  36. #define DPRINTK(args...) printk(args)
  37. #else
  38. #define DPRINTK(args...)
  39. #endif
  40. #define HDATA(ptr) ((struct ip22_hostdata *)((ptr)->hostdata))
  41. struct ip22_hostdata {
  42. struct WD33C93_hostdata wh;
  43. struct hpc_data {
  44. dma_addr_t dma;
  45. void * cpu;
  46. } hd;
  47. };
  48. struct hpc_chunk {
  49. struct hpc_dma_desc desc;
  50. u32 _padding; /* align to quadword boundary */
  51. };
  52. struct Scsi_Host *sgiwd93_host;
  53. struct Scsi_Host *sgiwd93_host1;
  54. /* Wuff wuff, wuff, wd33c93.c, wuff wuff, object oriented, bow wow. */
  55. static inline void write_wd33c93_count(const wd33c93_regs regs,
  56. unsigned long value)
  57. {
  58. *regs.SASR = WD_TRANSFER_COUNT_MSB;
  59. mb();
  60. *regs.SCMD = ((value >> 16) & 0xff);
  61. *regs.SCMD = ((value >> 8) & 0xff);
  62. *regs.SCMD = ((value >> 0) & 0xff);
  63. mb();
  64. }
  65. static inline unsigned long read_wd33c93_count(const wd33c93_regs regs)
  66. {
  67. unsigned long value;
  68. *regs.SASR = WD_TRANSFER_COUNT_MSB;
  69. mb();
  70. value = ((*regs.SCMD & 0xff) << 16);
  71. value |= ((*regs.SCMD & 0xff) << 8);
  72. value |= ((*regs.SCMD & 0xff) << 0);
  73. mb();
  74. return value;
  75. }
  76. static irqreturn_t sgiwd93_intr(int irq, void *dev_id, struct pt_regs *regs)
  77. {
  78. struct Scsi_Host * host = (struct Scsi_Host *) dev_id;
  79. unsigned long flags;
  80. spin_lock_irqsave(host->host_lock, flags);
  81. wd33c93_intr(host);
  82. spin_unlock_irqrestore(host->host_lock, flags);
  83. return IRQ_HANDLED;
  84. }
  85. static inline
  86. void fill_hpc_entries(struct hpc_chunk *hcp, Scsi_Cmnd *cmd, int datainp)
  87. {
  88. unsigned long len = cmd->SCp.this_residual;
  89. void *addr = cmd->SCp.ptr;
  90. dma_addr_t physaddr;
  91. unsigned long count;
  92. physaddr = dma_map_single(NULL, addr, len, cmd->sc_data_direction);
  93. cmd->SCp.dma_handle = physaddr;
  94. while (len) {
  95. /*
  96. * even cntinfo could be up to 16383, without
  97. * magic only 8192 works correctly
  98. */
  99. count = len > 8192 ? 8192 : len;
  100. hcp->desc.pbuf = physaddr;
  101. hcp->desc.cntinfo = count;
  102. hcp++;
  103. len -= count;
  104. physaddr += count;
  105. }
  106. /*
  107. * To make sure, if we trip an HPC bug, that we transfer every single
  108. * byte, we tag on an extra zero length dma descriptor at the end of
  109. * the chain.
  110. */
  111. hcp->desc.pbuf = 0;
  112. hcp->desc.cntinfo = HPCDMA_EOX;
  113. }
  114. static int dma_setup(Scsi_Cmnd *cmd, int datainp)
  115. {
  116. struct ip22_hostdata *hdata = HDATA(cmd->device->host);
  117. struct hpc3_scsiregs *hregs =
  118. (struct hpc3_scsiregs *) cmd->device->host->base;
  119. struct hpc_chunk *hcp = (struct hpc_chunk *) hdata->hd.cpu;
  120. DPRINTK("dma_setup: datainp<%d> hcp<%p> ", datainp, hcp);
  121. hdata->wh.dma_dir = datainp;
  122. /*
  123. * wd33c93 shouldn't pass us bogus dma_setups, but it does:-( The
  124. * other wd33c93 drivers deal with it the same way (which isn't that
  125. * obvious). IMHO a better fix would be, not to do these dma setups
  126. * in the first place.
  127. */
  128. if (cmd->SCp.ptr == NULL || cmd->SCp.this_residual == 0)
  129. return 1;
  130. fill_hpc_entries(hcp, cmd, datainp);
  131. DPRINTK(" HPCGO\n");
  132. /* Start up the HPC. */
  133. hregs->ndptr = hdata->hd.dma;
  134. if (datainp)
  135. hregs->ctrl = HPC3_SCTRL_ACTIVE;
  136. else
  137. hregs->ctrl = HPC3_SCTRL_ACTIVE | HPC3_SCTRL_DIR;
  138. return 0;
  139. }
  140. static void dma_stop(struct Scsi_Host *instance, Scsi_Cmnd *SCpnt,
  141. int status)
  142. {
  143. struct ip22_hostdata *hdata = HDATA(instance);
  144. struct hpc3_scsiregs *hregs;
  145. if (!SCpnt)
  146. return;
  147. hregs = (struct hpc3_scsiregs *) SCpnt->device->host->base;
  148. DPRINTK("dma_stop: status<%d> ", status);
  149. /* First stop the HPC and flush it's FIFO. */
  150. if (hdata->wh.dma_dir) {
  151. hregs->ctrl |= HPC3_SCTRL_FLUSH;
  152. while (hregs->ctrl & HPC3_SCTRL_ACTIVE)
  153. barrier();
  154. }
  155. hregs->ctrl = 0;
  156. dma_unmap_single(NULL, SCpnt->SCp.dma_handle, SCpnt->SCp.this_residual,
  157. SCpnt->sc_data_direction);
  158. DPRINTK("\n");
  159. }
  160. void sgiwd93_reset(unsigned long base)
  161. {
  162. struct hpc3_scsiregs *hregs = (struct hpc3_scsiregs *) base;
  163. hregs->ctrl = HPC3_SCTRL_CRESET;
  164. udelay(50);
  165. hregs->ctrl = 0;
  166. }
  167. static inline void init_hpc_chain(struct hpc_data *hd)
  168. {
  169. struct hpc_chunk *hcp = (struct hpc_chunk *) hd->cpu;
  170. struct hpc_chunk *dma = (struct hpc_chunk *) hd->dma;
  171. unsigned long start, end;
  172. start = (unsigned long) hcp;
  173. end = start + PAGE_SIZE;
  174. while (start < end) {
  175. hcp->desc.pnext = (u32) (dma + 1);
  176. hcp->desc.cntinfo = HPCDMA_EOX;
  177. hcp++; dma++;
  178. start += sizeof(struct hpc_chunk);
  179. };
  180. hcp--;
  181. hcp->desc.pnext = hd->dma;
  182. }
  183. static struct Scsi_Host * __init sgiwd93_setup_scsi(
  184. Scsi_Host_Template *SGIblows, int unit, int irq,
  185. struct hpc3_scsiregs *hregs, unsigned char *wdregs)
  186. {
  187. struct ip22_hostdata *hdata;
  188. struct Scsi_Host *host;
  189. wd33c93_regs regs;
  190. host = scsi_register(SGIblows, sizeof(struct ip22_hostdata));
  191. if (!host)
  192. return NULL;
  193. host->base = (unsigned long) hregs;
  194. host->irq = irq;
  195. hdata = HDATA(host);
  196. hdata->hd.cpu = dma_alloc_coherent(NULL, PAGE_SIZE, &hdata->hd.dma,
  197. GFP_KERNEL);
  198. if (!hdata->hd.cpu) {
  199. printk(KERN_WARNING "sgiwd93: Could not allocate memory for "
  200. "host %d buffer.\n", unit);
  201. goto out_unregister;
  202. }
  203. init_hpc_chain(&hdata->hd);
  204. regs.SASR = wdregs + 3;
  205. regs.SCMD = wdregs + 7;
  206. wd33c93_init(host, regs, dma_setup, dma_stop, WD33C93_FS_16_20);
  207. hdata->wh.no_sync = 0;
  208. if (request_irq(irq, sgiwd93_intr, 0, "SGI WD93", (void *) host)) {
  209. printk(KERN_WARNING "sgiwd93: Could not register irq %d "
  210. "for host %d.\n", irq, unit);
  211. goto out_free;
  212. }
  213. return host;
  214. out_free:
  215. dma_free_coherent(NULL, PAGE_SIZE, hdata->hd.cpu, hdata->hd.dma);
  216. wd33c93_release();
  217. out_unregister:
  218. scsi_unregister(host);
  219. return NULL;
  220. }
  221. int __init sgiwd93_detect(Scsi_Host_Template *SGIblows)
  222. {
  223. int found = 0;
  224. SGIblows->proc_name = "SGIWD93";
  225. sgiwd93_host = sgiwd93_setup_scsi(SGIblows, 0, SGI_WD93_0_IRQ,
  226. &hpc3c0->scsi_chan0,
  227. (unsigned char *)hpc3c0->scsi0_ext);
  228. if (sgiwd93_host)
  229. found++;
  230. /* Set up second controller on the Indigo2 */
  231. if (ip22_is_fullhouse()) {
  232. sgiwd93_host1 = sgiwd93_setup_scsi(SGIblows, 1, SGI_WD93_1_IRQ,
  233. &hpc3c0->scsi_chan1,
  234. (unsigned char *)hpc3c0->scsi1_ext);
  235. if (sgiwd93_host1)
  236. found++;
  237. }
  238. return found;
  239. }
  240. int sgiwd93_release(struct Scsi_Host *instance)
  241. {
  242. struct ip22_hostdata *hdata = HDATA(instance);
  243. int irq = 0;
  244. if (sgiwd93_host && sgiwd93_host == instance)
  245. irq = SGI_WD93_0_IRQ;
  246. else if (sgiwd93_host1 && sgiwd93_host1 == instance)
  247. irq = SGI_WD93_1_IRQ;
  248. free_irq(irq, sgiwd93_intr);
  249. dma_free_coherent(NULL, PAGE_SIZE, hdata->hd.cpu, hdata->hd.dma);
  250. wd33c93_release();
  251. return 1;
  252. }
  253. static int sgiwd93_bus_reset(Scsi_Cmnd *cmd)
  254. {
  255. /* FIXME perform bus-specific reset */
  256. /* FIXME 2: kill this function, and let midlayer fallback
  257. to the same result, calling wd33c93_host_reset() */
  258. spin_lock_irq(cmd->device->host->host_lock);
  259. wd33c93_host_reset(cmd);
  260. spin_unlock_irq(cmd->device->host->host_lock);
  261. return SUCCESS;
  262. }
  263. /*
  264. * Kludge alert - the SCSI code calls the abort and reset method with int
  265. * arguments not with pointers. So this is going to blow up beautyfully
  266. * on 64-bit systems with memory outside the compat address spaces.
  267. */
  268. static Scsi_Host_Template driver_template = {
  269. .proc_name = "SGIWD93",
  270. .name = "SGI WD93",
  271. .detect = sgiwd93_detect,
  272. .release = sgiwd93_release,
  273. .queuecommand = wd33c93_queuecommand,
  274. .eh_abort_handler = wd33c93_abort,
  275. .eh_bus_reset_handler = sgiwd93_bus_reset,
  276. .eh_host_reset_handler = wd33c93_host_reset,
  277. .can_queue = 16,
  278. .this_id = 7,
  279. .sg_tablesize = SG_ALL,
  280. .cmd_per_lun = 8,
  281. .use_clustering = DISABLE_CLUSTERING,
  282. };
  283. #include "scsi_module.c"