dma.c 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227
  1. /*
  2. * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corporation
  3. *
  4. * Provide default implementations of the DMA mapping callbacks for
  5. * directly mapped busses.
  6. */
  7. #include <linux/device.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/dma-debug.h>
  10. #include <linux/gfp.h>
  11. #include <linux/memblock.h>
  12. #include <asm/bug.h>
  13. #include <asm/abs_addr.h>
  14. #include <asm/machdep.h>
  15. /*
  16. * Generic direct DMA implementation
  17. *
  18. * This implementation supports a per-device offset that can be applied if
  19. * the address at which memory is visible to devices is not 0. Platform code
  20. * can set archdata.dma_data to an unsigned long holding the offset. By
  21. * default the offset is PCI_DRAM_OFFSET.
  22. */
  23. void *dma_direct_alloc_coherent(struct device *dev, size_t size,
  24. dma_addr_t *dma_handle, gfp_t flag)
  25. {
  26. void *ret;
  27. #ifdef CONFIG_NOT_COHERENT_CACHE
  28. ret = __dma_alloc_coherent(dev, size, dma_handle, flag);
  29. if (ret == NULL)
  30. return NULL;
  31. *dma_handle += get_dma_offset(dev);
  32. return ret;
  33. #else
  34. struct page *page;
  35. int node = dev_to_node(dev);
  36. /* ignore region specifiers */
  37. flag &= ~(__GFP_HIGHMEM);
  38. page = alloc_pages_node(node, flag, get_order(size));
  39. if (page == NULL)
  40. return NULL;
  41. ret = page_address(page);
  42. memset(ret, 0, size);
  43. *dma_handle = virt_to_abs(ret) + get_dma_offset(dev);
  44. return ret;
  45. #endif
  46. }
  47. void dma_direct_free_coherent(struct device *dev, size_t size,
  48. void *vaddr, dma_addr_t dma_handle)
  49. {
  50. #ifdef CONFIG_NOT_COHERENT_CACHE
  51. __dma_free_coherent(size, vaddr);
  52. #else
  53. free_pages((unsigned long)vaddr, get_order(size));
  54. #endif
  55. }
  56. static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
  57. int nents, enum dma_data_direction direction,
  58. struct dma_attrs *attrs)
  59. {
  60. struct scatterlist *sg;
  61. int i;
  62. for_each_sg(sgl, sg, nents, i) {
  63. sg->dma_address = sg_phys(sg) + get_dma_offset(dev);
  64. sg->dma_length = sg->length;
  65. __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
  66. }
  67. return nents;
  68. }
  69. static void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sg,
  70. int nents, enum dma_data_direction direction,
  71. struct dma_attrs *attrs)
  72. {
  73. }
  74. static int dma_direct_dma_supported(struct device *dev, u64 mask)
  75. {
  76. #ifdef CONFIG_PPC64
  77. /* Could be improved so platforms can set the limit in case
  78. * they have limited DMA windows
  79. */
  80. return mask >= get_dma_offset(dev) + (memblock_end_of_DRAM() - 1);
  81. #else
  82. return 1;
  83. #endif
  84. }
  85. static u64 dma_direct_get_required_mask(struct device *dev)
  86. {
  87. u64 end, mask;
  88. end = memblock_end_of_DRAM() + get_dma_offset(dev);
  89. mask = 1ULL << (fls64(end) - 1);
  90. mask += mask - 1;
  91. return mask;
  92. }
  93. static inline dma_addr_t dma_direct_map_page(struct device *dev,
  94. struct page *page,
  95. unsigned long offset,
  96. size_t size,
  97. enum dma_data_direction dir,
  98. struct dma_attrs *attrs)
  99. {
  100. BUG_ON(dir == DMA_NONE);
  101. __dma_sync_page(page, offset, size, dir);
  102. return page_to_phys(page) + offset + get_dma_offset(dev);
  103. }
  104. static inline void dma_direct_unmap_page(struct device *dev,
  105. dma_addr_t dma_address,
  106. size_t size,
  107. enum dma_data_direction direction,
  108. struct dma_attrs *attrs)
  109. {
  110. }
  111. #ifdef CONFIG_NOT_COHERENT_CACHE
  112. static inline void dma_direct_sync_sg(struct device *dev,
  113. struct scatterlist *sgl, int nents,
  114. enum dma_data_direction direction)
  115. {
  116. struct scatterlist *sg;
  117. int i;
  118. for_each_sg(sgl, sg, nents, i)
  119. __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
  120. }
  121. static inline void dma_direct_sync_single(struct device *dev,
  122. dma_addr_t dma_handle, size_t size,
  123. enum dma_data_direction direction)
  124. {
  125. __dma_sync(bus_to_virt(dma_handle), size, direction);
  126. }
  127. #endif
  128. struct dma_map_ops dma_direct_ops = {
  129. .alloc_coherent = dma_direct_alloc_coherent,
  130. .free_coherent = dma_direct_free_coherent,
  131. .map_sg = dma_direct_map_sg,
  132. .unmap_sg = dma_direct_unmap_sg,
  133. .dma_supported = dma_direct_dma_supported,
  134. .map_page = dma_direct_map_page,
  135. .unmap_page = dma_direct_unmap_page,
  136. .get_required_mask = dma_direct_get_required_mask,
  137. #ifdef CONFIG_NOT_COHERENT_CACHE
  138. .sync_single_for_cpu = dma_direct_sync_single,
  139. .sync_single_for_device = dma_direct_sync_single,
  140. .sync_sg_for_cpu = dma_direct_sync_sg,
  141. .sync_sg_for_device = dma_direct_sync_sg,
  142. #endif
  143. };
  144. EXPORT_SYMBOL(dma_direct_ops);
  145. #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
  146. int dma_set_mask(struct device *dev, u64 dma_mask)
  147. {
  148. struct dma_map_ops *dma_ops = get_dma_ops(dev);
  149. if (ppc_md.dma_set_mask)
  150. return ppc_md.dma_set_mask(dev, dma_mask);
  151. if ((dma_ops != NULL) && (dma_ops->set_dma_mask != NULL))
  152. return dma_ops->set_dma_mask(dev, dma_mask);
  153. if (!dev->dma_mask || !dma_supported(dev, dma_mask))
  154. return -EIO;
  155. *dev->dma_mask = dma_mask;
  156. return 0;
  157. }
  158. EXPORT_SYMBOL(dma_set_mask);
  159. u64 dma_get_required_mask(struct device *dev)
  160. {
  161. struct dma_map_ops *dma_ops = get_dma_ops(dev);
  162. if (ppc_md.dma_get_required_mask)
  163. return ppc_md.dma_get_required_mask(dev);
  164. if (unlikely(dma_ops == NULL))
  165. return 0;
  166. if (dma_ops->get_required_mask)
  167. return dma_ops->get_required_mask(dev);
  168. return DMA_BIT_MASK(8 * sizeof(dma_addr_t));
  169. }
  170. EXPORT_SYMBOL_GPL(dma_get_required_mask);
  171. static int __init dma_init(void)
  172. {
  173. dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
  174. return 0;
  175. }
  176. fs_initcall(dma_init);
  177. int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
  178. void *cpu_addr, dma_addr_t handle, size_t size)
  179. {
  180. unsigned long pfn;
  181. #ifdef CONFIG_NOT_COHERENT_CACHE
  182. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  183. pfn = __dma_get_coherent_pfn((unsigned long)cpu_addr);
  184. #else
  185. pfn = page_to_pfn(virt_to_page(cpu_addr));
  186. #endif
  187. return remap_pfn_range(vma, vma->vm_start,
  188. pfn + vma->vm_pgoff,
  189. vma->vm_end - vma->vm_start,
  190. vma->vm_page_prot);
  191. }
  192. EXPORT_SYMBOL_GPL(dma_mmap_coherent);