ymfpci_main.c 66 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Routines for control of YMF724/740/744/754 chips
  4. *
  5. * BUGS:
  6. * --
  7. *
  8. * TODO:
  9. * --
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <sound/driver.h>
  27. #include <linux/delay.h>
  28. #include <linux/init.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/pci.h>
  31. #include <linux/sched.h>
  32. #include <linux/slab.h>
  33. #include <linux/vmalloc.h>
  34. #include <sound/core.h>
  35. #include <sound/control.h>
  36. #include <sound/info.h>
  37. #include <sound/ymfpci.h>
  38. #include <sound/asoundef.h>
  39. #include <sound/mpu401.h>
  40. #include <asm/io.h>
  41. /*
  42. * constants
  43. */
  44. /*
  45. * common I/O routines
  46. */
  47. static void snd_ymfpci_irq_wait(ymfpci_t *chip);
  48. static inline u8 snd_ymfpci_readb(ymfpci_t *chip, u32 offset)
  49. {
  50. return readb(chip->reg_area_virt + offset);
  51. }
  52. static inline void snd_ymfpci_writeb(ymfpci_t *chip, u32 offset, u8 val)
  53. {
  54. writeb(val, chip->reg_area_virt + offset);
  55. }
  56. static inline u16 snd_ymfpci_readw(ymfpci_t *chip, u32 offset)
  57. {
  58. return readw(chip->reg_area_virt + offset);
  59. }
  60. static inline void snd_ymfpci_writew(ymfpci_t *chip, u32 offset, u16 val)
  61. {
  62. writew(val, chip->reg_area_virt + offset);
  63. }
  64. static inline u32 snd_ymfpci_readl(ymfpci_t *chip, u32 offset)
  65. {
  66. return readl(chip->reg_area_virt + offset);
  67. }
  68. static inline void snd_ymfpci_writel(ymfpci_t *chip, u32 offset, u32 val)
  69. {
  70. writel(val, chip->reg_area_virt + offset);
  71. }
  72. static int snd_ymfpci_codec_ready(ymfpci_t *chip, int secondary)
  73. {
  74. unsigned long end_time;
  75. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  76. end_time = jiffies + msecs_to_jiffies(750);
  77. do {
  78. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  79. return 0;
  80. set_current_state(TASK_UNINTERRUPTIBLE);
  81. schedule_timeout_uninterruptible(1);
  82. } while (time_before(jiffies, end_time));
  83. snd_printk(KERN_ERR "codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
  84. return -EBUSY;
  85. }
  86. static void snd_ymfpci_codec_write(ac97_t *ac97, u16 reg, u16 val)
  87. {
  88. ymfpci_t *chip = ac97->private_data;
  89. u32 cmd;
  90. snd_ymfpci_codec_ready(chip, 0);
  91. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  92. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  93. }
  94. static u16 snd_ymfpci_codec_read(ac97_t *ac97, u16 reg)
  95. {
  96. ymfpci_t *chip = ac97->private_data;
  97. if (snd_ymfpci_codec_ready(chip, 0))
  98. return ~0;
  99. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  100. if (snd_ymfpci_codec_ready(chip, 0))
  101. return ~0;
  102. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  103. int i;
  104. for (i = 0; i < 600; i++)
  105. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  106. }
  107. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  108. }
  109. /*
  110. * Misc routines
  111. */
  112. static u32 snd_ymfpci_calc_delta(u32 rate)
  113. {
  114. switch (rate) {
  115. case 8000: return 0x02aaab00;
  116. case 11025: return 0x03accd00;
  117. case 16000: return 0x05555500;
  118. case 22050: return 0x07599a00;
  119. case 32000: return 0x0aaaab00;
  120. case 44100: return 0x0eb33300;
  121. default: return ((rate << 16) / 375) << 5;
  122. }
  123. }
  124. static u32 def_rate[8] = {
  125. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  126. };
  127. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  128. {
  129. u32 i;
  130. static u32 val[8] = {
  131. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  132. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  133. };
  134. if (rate == 44100)
  135. return 0x40000000; /* FIXME: What's the right value? */
  136. for (i = 0; i < 8; i++)
  137. if (rate <= def_rate[i])
  138. return val[i];
  139. return val[0];
  140. }
  141. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  142. {
  143. u32 i;
  144. static u32 val[8] = {
  145. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  146. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  147. };
  148. if (rate == 44100)
  149. return 0x370A0000;
  150. for (i = 0; i < 8; i++)
  151. if (rate <= def_rate[i])
  152. return val[i];
  153. return val[0];
  154. }
  155. /*
  156. * Hardware start management
  157. */
  158. static void snd_ymfpci_hw_start(ymfpci_t *chip)
  159. {
  160. unsigned long flags;
  161. spin_lock_irqsave(&chip->reg_lock, flags);
  162. if (chip->start_count++ > 0)
  163. goto __end;
  164. snd_ymfpci_writel(chip, YDSXGR_MODE,
  165. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  166. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  167. __end:
  168. spin_unlock_irqrestore(&chip->reg_lock, flags);
  169. }
  170. static void snd_ymfpci_hw_stop(ymfpci_t *chip)
  171. {
  172. unsigned long flags;
  173. long timeout = 1000;
  174. spin_lock_irqsave(&chip->reg_lock, flags);
  175. if (--chip->start_count > 0)
  176. goto __end;
  177. snd_ymfpci_writel(chip, YDSXGR_MODE,
  178. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  179. while (timeout-- > 0) {
  180. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  181. break;
  182. }
  183. if (atomic_read(&chip->interrupt_sleep_count)) {
  184. atomic_set(&chip->interrupt_sleep_count, 0);
  185. wake_up(&chip->interrupt_sleep);
  186. }
  187. __end:
  188. spin_unlock_irqrestore(&chip->reg_lock, flags);
  189. }
  190. /*
  191. * Playback voice management
  192. */
  193. static int voice_alloc(ymfpci_t *chip, ymfpci_voice_type_t type, int pair, ymfpci_voice_t **rvoice)
  194. {
  195. ymfpci_voice_t *voice, *voice2;
  196. int idx;
  197. *rvoice = NULL;
  198. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  199. voice = &chip->voices[idx];
  200. voice2 = pair ? &chip->voices[idx+1] : NULL;
  201. if (voice->use || (voice2 && voice2->use))
  202. continue;
  203. voice->use = 1;
  204. if (voice2)
  205. voice2->use = 1;
  206. switch (type) {
  207. case YMFPCI_PCM:
  208. voice->pcm = 1;
  209. if (voice2)
  210. voice2->pcm = 1;
  211. break;
  212. case YMFPCI_SYNTH:
  213. voice->synth = 1;
  214. break;
  215. case YMFPCI_MIDI:
  216. voice->midi = 1;
  217. break;
  218. }
  219. snd_ymfpci_hw_start(chip);
  220. if (voice2)
  221. snd_ymfpci_hw_start(chip);
  222. *rvoice = voice;
  223. return 0;
  224. }
  225. return -ENOMEM;
  226. }
  227. static int snd_ymfpci_voice_alloc(ymfpci_t *chip, ymfpci_voice_type_t type, int pair, ymfpci_voice_t **rvoice)
  228. {
  229. unsigned long flags;
  230. int result;
  231. snd_assert(rvoice != NULL, return -EINVAL);
  232. snd_assert(!pair || type == YMFPCI_PCM, return -EINVAL);
  233. spin_lock_irqsave(&chip->voice_lock, flags);
  234. for (;;) {
  235. result = voice_alloc(chip, type, pair, rvoice);
  236. if (result == 0 || type != YMFPCI_PCM)
  237. break;
  238. /* TODO: synth/midi voice deallocation */
  239. break;
  240. }
  241. spin_unlock_irqrestore(&chip->voice_lock, flags);
  242. return result;
  243. }
  244. static int snd_ymfpci_voice_free(ymfpci_t *chip, ymfpci_voice_t *pvoice)
  245. {
  246. unsigned long flags;
  247. snd_assert(pvoice != NULL, return -EINVAL);
  248. snd_ymfpci_hw_stop(chip);
  249. spin_lock_irqsave(&chip->voice_lock, flags);
  250. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  251. pvoice->ypcm = NULL;
  252. pvoice->interrupt = NULL;
  253. spin_unlock_irqrestore(&chip->voice_lock, flags);
  254. return 0;
  255. }
  256. /*
  257. * PCM part
  258. */
  259. static void snd_ymfpci_pcm_interrupt(ymfpci_t *chip, ymfpci_voice_t *voice)
  260. {
  261. ymfpci_pcm_t *ypcm;
  262. u32 pos, delta;
  263. if ((ypcm = voice->ypcm) == NULL)
  264. return;
  265. if (ypcm->substream == NULL)
  266. return;
  267. spin_lock(&chip->reg_lock);
  268. if (ypcm->running) {
  269. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  270. if (pos < ypcm->last_pos)
  271. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  272. else
  273. delta = pos - ypcm->last_pos;
  274. ypcm->period_pos += delta;
  275. ypcm->last_pos = pos;
  276. if (ypcm->period_pos >= ypcm->period_size) {
  277. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  278. ypcm->period_pos %= ypcm->period_size;
  279. spin_unlock(&chip->reg_lock);
  280. snd_pcm_period_elapsed(ypcm->substream);
  281. spin_lock(&chip->reg_lock);
  282. }
  283. if (unlikely(ypcm->update_pcm_vol)) {
  284. unsigned int subs = ypcm->substream->number;
  285. unsigned int next_bank = 1 - chip->active_bank;
  286. snd_ymfpci_playback_bank_t *bank;
  287. u32 volume;
  288. bank = &voice->bank[next_bank];
  289. volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
  290. bank->left_gain_end = volume;
  291. if (ypcm->output_rear)
  292. bank->eff2_gain_end = volume;
  293. if (ypcm->voices[1])
  294. bank = &ypcm->voices[1]->bank[next_bank];
  295. volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
  296. bank->right_gain_end = volume;
  297. if (ypcm->output_rear)
  298. bank->eff3_gain_end = volume;
  299. ypcm->update_pcm_vol--;
  300. }
  301. }
  302. spin_unlock(&chip->reg_lock);
  303. }
  304. static void snd_ymfpci_pcm_capture_interrupt(snd_pcm_substream_t *substream)
  305. {
  306. snd_pcm_runtime_t *runtime = substream->runtime;
  307. ymfpci_pcm_t *ypcm = runtime->private_data;
  308. ymfpci_t *chip = ypcm->chip;
  309. u32 pos, delta;
  310. spin_lock(&chip->reg_lock);
  311. if (ypcm->running) {
  312. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  313. if (pos < ypcm->last_pos)
  314. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  315. else
  316. delta = pos - ypcm->last_pos;
  317. ypcm->period_pos += delta;
  318. ypcm->last_pos = pos;
  319. if (ypcm->period_pos >= ypcm->period_size) {
  320. ypcm->period_pos %= ypcm->period_size;
  321. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  322. spin_unlock(&chip->reg_lock);
  323. snd_pcm_period_elapsed(substream);
  324. spin_lock(&chip->reg_lock);
  325. }
  326. }
  327. spin_unlock(&chip->reg_lock);
  328. }
  329. static int snd_ymfpci_playback_trigger(snd_pcm_substream_t * substream,
  330. int cmd)
  331. {
  332. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  333. ymfpci_pcm_t *ypcm = substream->runtime->private_data;
  334. int result = 0;
  335. spin_lock(&chip->reg_lock);
  336. if (ypcm->voices[0] == NULL) {
  337. result = -EINVAL;
  338. goto __unlock;
  339. }
  340. switch (cmd) {
  341. case SNDRV_PCM_TRIGGER_START:
  342. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  343. case SNDRV_PCM_TRIGGER_RESUME:
  344. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  345. if (ypcm->voices[1] != NULL)
  346. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  347. ypcm->running = 1;
  348. break;
  349. case SNDRV_PCM_TRIGGER_STOP:
  350. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  351. case SNDRV_PCM_TRIGGER_SUSPEND:
  352. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  353. if (ypcm->voices[1] != NULL)
  354. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  355. ypcm->running = 0;
  356. break;
  357. default:
  358. result = -EINVAL;
  359. break;
  360. }
  361. __unlock:
  362. spin_unlock(&chip->reg_lock);
  363. return result;
  364. }
  365. static int snd_ymfpci_capture_trigger(snd_pcm_substream_t * substream,
  366. int cmd)
  367. {
  368. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  369. ymfpci_pcm_t *ypcm = substream->runtime->private_data;
  370. int result = 0;
  371. u32 tmp;
  372. spin_lock(&chip->reg_lock);
  373. switch (cmd) {
  374. case SNDRV_PCM_TRIGGER_START:
  375. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  376. case SNDRV_PCM_TRIGGER_RESUME:
  377. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  378. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  379. ypcm->running = 1;
  380. break;
  381. case SNDRV_PCM_TRIGGER_STOP:
  382. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  383. case SNDRV_PCM_TRIGGER_SUSPEND:
  384. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  385. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  386. ypcm->running = 0;
  387. break;
  388. default:
  389. result = -EINVAL;
  390. break;
  391. }
  392. spin_unlock(&chip->reg_lock);
  393. return result;
  394. }
  395. static int snd_ymfpci_pcm_voice_alloc(ymfpci_pcm_t *ypcm, int voices)
  396. {
  397. int err;
  398. if (ypcm->voices[1] != NULL && voices < 2) {
  399. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  400. ypcm->voices[1] = NULL;
  401. }
  402. if (voices == 1 && ypcm->voices[0] != NULL)
  403. return 0; /* already allocated */
  404. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  405. return 0; /* already allocated */
  406. if (voices > 1) {
  407. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  408. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  409. ypcm->voices[0] = NULL;
  410. }
  411. }
  412. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  413. if (err < 0)
  414. return err;
  415. ypcm->voices[0]->ypcm = ypcm;
  416. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  417. if (voices > 1) {
  418. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  419. ypcm->voices[1]->ypcm = ypcm;
  420. }
  421. return 0;
  422. }
  423. static void snd_ymfpci_pcm_init_voice(ymfpci_pcm_t *ypcm, unsigned int voiceidx,
  424. snd_pcm_runtime_t *runtime,
  425. int has_pcm_volume)
  426. {
  427. ymfpci_voice_t *voice = ypcm->voices[voiceidx];
  428. u32 format;
  429. u32 delta = snd_ymfpci_calc_delta(runtime->rate);
  430. u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
  431. u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
  432. snd_ymfpci_playback_bank_t *bank;
  433. unsigned int nbank;
  434. u32 vol_left, vol_right;
  435. u8 use_left, use_right;
  436. snd_assert(voice != NULL, return);
  437. if (runtime->channels == 1) {
  438. use_left = 1;
  439. use_right = 1;
  440. } else {
  441. use_left = (voiceidx & 1) == 0;
  442. use_right = !use_left;
  443. }
  444. if (has_pcm_volume) {
  445. vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
  446. [ypcm->substream->number].left << 15);
  447. vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
  448. [ypcm->substream->number].right << 15);
  449. } else {
  450. vol_left = cpu_to_le32(0x40000000);
  451. vol_right = cpu_to_le32(0x40000000);
  452. }
  453. format = runtime->channels == 2 ? 0x00010000 : 0;
  454. if (snd_pcm_format_width(runtime->format) == 8)
  455. format |= 0x80000000;
  456. if (runtime->channels == 2 && (voiceidx & 1) != 0)
  457. format |= 1;
  458. for (nbank = 0; nbank < 2; nbank++) {
  459. bank = &voice->bank[nbank];
  460. memset(bank, 0, sizeof(*bank));
  461. bank->format = cpu_to_le32(format);
  462. bank->base = cpu_to_le32(runtime->dma_addr);
  463. bank->loop_end = cpu_to_le32(ypcm->buffer_size);
  464. bank->lpfQ = cpu_to_le32(lpfQ);
  465. bank->delta =
  466. bank->delta_end = cpu_to_le32(delta);
  467. bank->lpfK =
  468. bank->lpfK_end = cpu_to_le32(lpfK);
  469. bank->eg_gain =
  470. bank->eg_gain_end = cpu_to_le32(0x40000000);
  471. if (ypcm->output_front) {
  472. if (use_left) {
  473. bank->left_gain =
  474. bank->left_gain_end = vol_left;
  475. }
  476. if (use_right) {
  477. bank->right_gain =
  478. bank->right_gain_end = vol_right;
  479. }
  480. }
  481. if (ypcm->output_rear) {
  482. if (use_left) {
  483. bank->eff2_gain =
  484. bank->eff2_gain_end = vol_left;
  485. }
  486. if (use_right) {
  487. bank->eff3_gain =
  488. bank->eff3_gain_end = vol_right;
  489. }
  490. }
  491. }
  492. }
  493. static int __devinit snd_ymfpci_ac3_init(ymfpci_t *chip)
  494. {
  495. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  496. 4096, &chip->ac3_tmp_base) < 0)
  497. return -ENOMEM;
  498. chip->bank_effect[3][0]->base =
  499. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  500. chip->bank_effect[3][0]->loop_end =
  501. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  502. chip->bank_effect[4][0]->base =
  503. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  504. chip->bank_effect[4][0]->loop_end =
  505. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  506. spin_lock_irq(&chip->reg_lock);
  507. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  508. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  509. spin_unlock_irq(&chip->reg_lock);
  510. return 0;
  511. }
  512. static int snd_ymfpci_ac3_done(ymfpci_t *chip)
  513. {
  514. spin_lock_irq(&chip->reg_lock);
  515. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  516. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  517. spin_unlock_irq(&chip->reg_lock);
  518. // snd_ymfpci_irq_wait(chip);
  519. if (chip->ac3_tmp_base.area) {
  520. snd_dma_free_pages(&chip->ac3_tmp_base);
  521. chip->ac3_tmp_base.area = NULL;
  522. }
  523. return 0;
  524. }
  525. static int snd_ymfpci_playback_hw_params(snd_pcm_substream_t * substream,
  526. snd_pcm_hw_params_t * hw_params)
  527. {
  528. snd_pcm_runtime_t *runtime = substream->runtime;
  529. ymfpci_pcm_t *ypcm = runtime->private_data;
  530. int err;
  531. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  532. return err;
  533. if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
  534. return err;
  535. return 0;
  536. }
  537. static int snd_ymfpci_playback_hw_free(snd_pcm_substream_t * substream)
  538. {
  539. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  540. snd_pcm_runtime_t *runtime = substream->runtime;
  541. ymfpci_pcm_t *ypcm;
  542. if (runtime->private_data == NULL)
  543. return 0;
  544. ypcm = runtime->private_data;
  545. /* wait, until the PCI operations are not finished */
  546. snd_ymfpci_irq_wait(chip);
  547. snd_pcm_lib_free_pages(substream);
  548. if (ypcm->voices[1]) {
  549. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  550. ypcm->voices[1] = NULL;
  551. }
  552. if (ypcm->voices[0]) {
  553. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  554. ypcm->voices[0] = NULL;
  555. }
  556. return 0;
  557. }
  558. static int snd_ymfpci_playback_prepare(snd_pcm_substream_t * substream)
  559. {
  560. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  561. snd_pcm_runtime_t *runtime = substream->runtime;
  562. ymfpci_pcm_t *ypcm = runtime->private_data;
  563. unsigned int nvoice;
  564. ypcm->period_size = runtime->period_size;
  565. ypcm->buffer_size = runtime->buffer_size;
  566. ypcm->period_pos = 0;
  567. ypcm->last_pos = 0;
  568. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  569. snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
  570. substream->pcm == chip->pcm);
  571. return 0;
  572. }
  573. static int snd_ymfpci_capture_hw_params(snd_pcm_substream_t * substream,
  574. snd_pcm_hw_params_t * hw_params)
  575. {
  576. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  577. }
  578. static int snd_ymfpci_capture_hw_free(snd_pcm_substream_t * substream)
  579. {
  580. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  581. /* wait, until the PCI operations are not finished */
  582. snd_ymfpci_irq_wait(chip);
  583. return snd_pcm_lib_free_pages(substream);
  584. }
  585. static int snd_ymfpci_capture_prepare(snd_pcm_substream_t * substream)
  586. {
  587. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  588. snd_pcm_runtime_t *runtime = substream->runtime;
  589. ymfpci_pcm_t *ypcm = runtime->private_data;
  590. snd_ymfpci_capture_bank_t * bank;
  591. int nbank;
  592. u32 rate, format;
  593. ypcm->period_size = runtime->period_size;
  594. ypcm->buffer_size = runtime->buffer_size;
  595. ypcm->period_pos = 0;
  596. ypcm->last_pos = 0;
  597. ypcm->shift = 0;
  598. rate = ((48000 * 4096) / runtime->rate) - 1;
  599. format = 0;
  600. if (runtime->channels == 2) {
  601. format |= 2;
  602. ypcm->shift++;
  603. }
  604. if (snd_pcm_format_width(runtime->format) == 8)
  605. format |= 1;
  606. else
  607. ypcm->shift++;
  608. switch (ypcm->capture_bank_number) {
  609. case 0:
  610. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  611. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  612. break;
  613. case 1:
  614. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  615. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  616. break;
  617. }
  618. for (nbank = 0; nbank < 2; nbank++) {
  619. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  620. bank->base = cpu_to_le32(runtime->dma_addr);
  621. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  622. bank->start = 0;
  623. bank->num_of_loops = 0;
  624. }
  625. return 0;
  626. }
  627. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(snd_pcm_substream_t * substream)
  628. {
  629. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  630. snd_pcm_runtime_t *runtime = substream->runtime;
  631. ymfpci_pcm_t *ypcm = runtime->private_data;
  632. ymfpci_voice_t *voice = ypcm->voices[0];
  633. if (!(ypcm->running && voice))
  634. return 0;
  635. return le32_to_cpu(voice->bank[chip->active_bank].start);
  636. }
  637. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(snd_pcm_substream_t * substream)
  638. {
  639. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  640. snd_pcm_runtime_t *runtime = substream->runtime;
  641. ymfpci_pcm_t *ypcm = runtime->private_data;
  642. if (!ypcm->running)
  643. return 0;
  644. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  645. }
  646. static void snd_ymfpci_irq_wait(ymfpci_t *chip)
  647. {
  648. wait_queue_t wait;
  649. int loops = 4;
  650. while (loops-- > 0) {
  651. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  652. continue;
  653. init_waitqueue_entry(&wait, current);
  654. add_wait_queue(&chip->interrupt_sleep, &wait);
  655. atomic_inc(&chip->interrupt_sleep_count);
  656. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  657. remove_wait_queue(&chip->interrupt_sleep, &wait);
  658. }
  659. }
  660. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  661. {
  662. ymfpci_t *chip = dev_id;
  663. u32 status, nvoice, mode;
  664. ymfpci_voice_t *voice;
  665. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  666. if (status & 0x80000000) {
  667. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  668. spin_lock(&chip->voice_lock);
  669. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  670. voice = &chip->voices[nvoice];
  671. if (voice->interrupt)
  672. voice->interrupt(chip, voice);
  673. }
  674. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  675. if (chip->capture_substream[nvoice])
  676. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  677. }
  678. #if 0
  679. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  680. if (chip->effect_substream[nvoice])
  681. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  682. }
  683. #endif
  684. spin_unlock(&chip->voice_lock);
  685. spin_lock(&chip->reg_lock);
  686. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  687. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  688. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  689. spin_unlock(&chip->reg_lock);
  690. if (atomic_read(&chip->interrupt_sleep_count)) {
  691. atomic_set(&chip->interrupt_sleep_count, 0);
  692. wake_up(&chip->interrupt_sleep);
  693. }
  694. }
  695. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  696. if (status & 1) {
  697. if (chip->timer)
  698. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  699. }
  700. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  701. if (chip->rawmidi)
  702. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data, regs);
  703. return IRQ_HANDLED;
  704. }
  705. static snd_pcm_hardware_t snd_ymfpci_playback =
  706. {
  707. .info = (SNDRV_PCM_INFO_MMAP |
  708. SNDRV_PCM_INFO_MMAP_VALID |
  709. SNDRV_PCM_INFO_INTERLEAVED |
  710. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  711. SNDRV_PCM_INFO_PAUSE |
  712. SNDRV_PCM_INFO_RESUME),
  713. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  714. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  715. .rate_min = 8000,
  716. .rate_max = 48000,
  717. .channels_min = 1,
  718. .channels_max = 2,
  719. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  720. .period_bytes_min = 64,
  721. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  722. .periods_min = 3,
  723. .periods_max = 1024,
  724. .fifo_size = 0,
  725. };
  726. static snd_pcm_hardware_t snd_ymfpci_capture =
  727. {
  728. .info = (SNDRV_PCM_INFO_MMAP |
  729. SNDRV_PCM_INFO_MMAP_VALID |
  730. SNDRV_PCM_INFO_INTERLEAVED |
  731. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  732. SNDRV_PCM_INFO_PAUSE |
  733. SNDRV_PCM_INFO_RESUME),
  734. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  735. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  736. .rate_min = 8000,
  737. .rate_max = 48000,
  738. .channels_min = 1,
  739. .channels_max = 2,
  740. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  741. .period_bytes_min = 64,
  742. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  743. .periods_min = 3,
  744. .periods_max = 1024,
  745. .fifo_size = 0,
  746. };
  747. static void snd_ymfpci_pcm_free_substream(snd_pcm_runtime_t *runtime)
  748. {
  749. kfree(runtime->private_data);
  750. }
  751. static int snd_ymfpci_playback_open_1(snd_pcm_substream_t * substream)
  752. {
  753. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  754. snd_pcm_runtime_t *runtime = substream->runtime;
  755. ymfpci_pcm_t *ypcm;
  756. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  757. if (ypcm == NULL)
  758. return -ENOMEM;
  759. ypcm->chip = chip;
  760. ypcm->type = PLAYBACK_VOICE;
  761. ypcm->substream = substream;
  762. runtime->hw = snd_ymfpci_playback;
  763. runtime->private_data = ypcm;
  764. runtime->private_free = snd_ymfpci_pcm_free_substream;
  765. /* FIXME? True value is 256/48 = 5.33333 ms */
  766. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  767. return 0;
  768. }
  769. /* call with spinlock held */
  770. static void ymfpci_open_extension(ymfpci_t *chip)
  771. {
  772. if (! chip->rear_opened) {
  773. if (! chip->spdif_opened) /* set AC3 */
  774. snd_ymfpci_writel(chip, YDSXGR_MODE,
  775. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  776. /* enable second codec (4CHEN) */
  777. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  778. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  779. }
  780. }
  781. /* call with spinlock held */
  782. static void ymfpci_close_extension(ymfpci_t *chip)
  783. {
  784. if (! chip->rear_opened) {
  785. if (! chip->spdif_opened)
  786. snd_ymfpci_writel(chip, YDSXGR_MODE,
  787. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  788. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  789. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  790. }
  791. }
  792. static int snd_ymfpci_playback_open(snd_pcm_substream_t * substream)
  793. {
  794. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  795. snd_pcm_runtime_t *runtime = substream->runtime;
  796. ymfpci_pcm_t *ypcm;
  797. snd_kcontrol_t *kctl;
  798. int err;
  799. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  800. return err;
  801. ypcm = runtime->private_data;
  802. ypcm->output_front = 1;
  803. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  804. spin_lock_irq(&chip->reg_lock);
  805. if (ypcm->output_rear) {
  806. ymfpci_open_extension(chip);
  807. chip->rear_opened++;
  808. }
  809. spin_unlock_irq(&chip->reg_lock);
  810. kctl = chip->pcm_mixer[substream->number].ctl;
  811. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  812. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  813. return 0;
  814. }
  815. static int snd_ymfpci_playback_spdif_open(snd_pcm_substream_t * substream)
  816. {
  817. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  818. snd_pcm_runtime_t *runtime = substream->runtime;
  819. ymfpci_pcm_t *ypcm;
  820. int err;
  821. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  822. return err;
  823. ypcm = runtime->private_data;
  824. ypcm->output_front = 0;
  825. ypcm->output_rear = 1;
  826. spin_lock_irq(&chip->reg_lock);
  827. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  828. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  829. ymfpci_open_extension(chip);
  830. chip->spdif_pcm_bits = chip->spdif_bits;
  831. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  832. chip->spdif_opened++;
  833. spin_unlock_irq(&chip->reg_lock);
  834. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  835. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  836. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  837. return 0;
  838. }
  839. static int snd_ymfpci_playback_4ch_open(snd_pcm_substream_t * substream)
  840. {
  841. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  842. snd_pcm_runtime_t *runtime = substream->runtime;
  843. ymfpci_pcm_t *ypcm;
  844. int err;
  845. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  846. return err;
  847. ypcm = runtime->private_data;
  848. ypcm->output_front = 0;
  849. ypcm->output_rear = 1;
  850. spin_lock_irq(&chip->reg_lock);
  851. ymfpci_open_extension(chip);
  852. chip->rear_opened++;
  853. spin_unlock_irq(&chip->reg_lock);
  854. return 0;
  855. }
  856. static int snd_ymfpci_capture_open(snd_pcm_substream_t * substream,
  857. u32 capture_bank_number)
  858. {
  859. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  860. snd_pcm_runtime_t *runtime = substream->runtime;
  861. ymfpci_pcm_t *ypcm;
  862. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  863. if (ypcm == NULL)
  864. return -ENOMEM;
  865. ypcm->chip = chip;
  866. ypcm->type = capture_bank_number + CAPTURE_REC;
  867. ypcm->substream = substream;
  868. ypcm->capture_bank_number = capture_bank_number;
  869. chip->capture_substream[capture_bank_number] = substream;
  870. runtime->hw = snd_ymfpci_capture;
  871. /* FIXME? True value is 256/48 = 5.33333 ms */
  872. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  873. runtime->private_data = ypcm;
  874. runtime->private_free = snd_ymfpci_pcm_free_substream;
  875. snd_ymfpci_hw_start(chip);
  876. return 0;
  877. }
  878. static int snd_ymfpci_capture_rec_open(snd_pcm_substream_t * substream)
  879. {
  880. return snd_ymfpci_capture_open(substream, 0);
  881. }
  882. static int snd_ymfpci_capture_ac97_open(snd_pcm_substream_t * substream)
  883. {
  884. return snd_ymfpci_capture_open(substream, 1);
  885. }
  886. static int snd_ymfpci_playback_close_1(snd_pcm_substream_t * substream)
  887. {
  888. return 0;
  889. }
  890. static int snd_ymfpci_playback_close(snd_pcm_substream_t * substream)
  891. {
  892. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  893. ymfpci_pcm_t *ypcm = substream->runtime->private_data;
  894. snd_kcontrol_t *kctl;
  895. spin_lock_irq(&chip->reg_lock);
  896. if (ypcm->output_rear && chip->rear_opened > 0) {
  897. chip->rear_opened--;
  898. ymfpci_close_extension(chip);
  899. }
  900. spin_unlock_irq(&chip->reg_lock);
  901. kctl = chip->pcm_mixer[substream->number].ctl;
  902. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  903. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  904. return snd_ymfpci_playback_close_1(substream);
  905. }
  906. static int snd_ymfpci_playback_spdif_close(snd_pcm_substream_t * substream)
  907. {
  908. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  909. spin_lock_irq(&chip->reg_lock);
  910. chip->spdif_opened = 0;
  911. ymfpci_close_extension(chip);
  912. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  913. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  914. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  915. spin_unlock_irq(&chip->reg_lock);
  916. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  917. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  918. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  919. return snd_ymfpci_playback_close_1(substream);
  920. }
  921. static int snd_ymfpci_playback_4ch_close(snd_pcm_substream_t * substream)
  922. {
  923. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  924. spin_lock_irq(&chip->reg_lock);
  925. if (chip->rear_opened > 0) {
  926. chip->rear_opened--;
  927. ymfpci_close_extension(chip);
  928. }
  929. spin_unlock_irq(&chip->reg_lock);
  930. return snd_ymfpci_playback_close_1(substream);
  931. }
  932. static int snd_ymfpci_capture_close(snd_pcm_substream_t * substream)
  933. {
  934. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  935. snd_pcm_runtime_t *runtime = substream->runtime;
  936. ymfpci_pcm_t *ypcm = runtime->private_data;
  937. if (ypcm != NULL) {
  938. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  939. snd_ymfpci_hw_stop(chip);
  940. }
  941. return 0;
  942. }
  943. static snd_pcm_ops_t snd_ymfpci_playback_ops = {
  944. .open = snd_ymfpci_playback_open,
  945. .close = snd_ymfpci_playback_close,
  946. .ioctl = snd_pcm_lib_ioctl,
  947. .hw_params = snd_ymfpci_playback_hw_params,
  948. .hw_free = snd_ymfpci_playback_hw_free,
  949. .prepare = snd_ymfpci_playback_prepare,
  950. .trigger = snd_ymfpci_playback_trigger,
  951. .pointer = snd_ymfpci_playback_pointer,
  952. };
  953. static snd_pcm_ops_t snd_ymfpci_capture_rec_ops = {
  954. .open = snd_ymfpci_capture_rec_open,
  955. .close = snd_ymfpci_capture_close,
  956. .ioctl = snd_pcm_lib_ioctl,
  957. .hw_params = snd_ymfpci_capture_hw_params,
  958. .hw_free = snd_ymfpci_capture_hw_free,
  959. .prepare = snd_ymfpci_capture_prepare,
  960. .trigger = snd_ymfpci_capture_trigger,
  961. .pointer = snd_ymfpci_capture_pointer,
  962. };
  963. static void snd_ymfpci_pcm_free(snd_pcm_t *pcm)
  964. {
  965. ymfpci_t *chip = pcm->private_data;
  966. chip->pcm = NULL;
  967. snd_pcm_lib_preallocate_free_for_all(pcm);
  968. }
  969. int __devinit snd_ymfpci_pcm(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  970. {
  971. snd_pcm_t *pcm;
  972. int err;
  973. if (rpcm)
  974. *rpcm = NULL;
  975. if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
  976. return err;
  977. pcm->private_data = chip;
  978. pcm->private_free = snd_ymfpci_pcm_free;
  979. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  980. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  981. /* global setup */
  982. pcm->info_flags = 0;
  983. strcpy(pcm->name, "YMFPCI");
  984. chip->pcm = pcm;
  985. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  986. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  987. if (rpcm)
  988. *rpcm = pcm;
  989. return 0;
  990. }
  991. static snd_pcm_ops_t snd_ymfpci_capture_ac97_ops = {
  992. .open = snd_ymfpci_capture_ac97_open,
  993. .close = snd_ymfpci_capture_close,
  994. .ioctl = snd_pcm_lib_ioctl,
  995. .hw_params = snd_ymfpci_capture_hw_params,
  996. .hw_free = snd_ymfpci_capture_hw_free,
  997. .prepare = snd_ymfpci_capture_prepare,
  998. .trigger = snd_ymfpci_capture_trigger,
  999. .pointer = snd_ymfpci_capture_pointer,
  1000. };
  1001. static void snd_ymfpci_pcm2_free(snd_pcm_t *pcm)
  1002. {
  1003. ymfpci_t *chip = pcm->private_data;
  1004. chip->pcm2 = NULL;
  1005. snd_pcm_lib_preallocate_free_for_all(pcm);
  1006. }
  1007. int __devinit snd_ymfpci_pcm2(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  1008. {
  1009. snd_pcm_t *pcm;
  1010. int err;
  1011. if (rpcm)
  1012. *rpcm = NULL;
  1013. if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
  1014. return err;
  1015. pcm->private_data = chip;
  1016. pcm->private_free = snd_ymfpci_pcm2_free;
  1017. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1018. /* global setup */
  1019. pcm->info_flags = 0;
  1020. sprintf(pcm->name, "YMFPCI - %s",
  1021. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1022. chip->pcm2 = pcm;
  1023. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1024. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1025. if (rpcm)
  1026. *rpcm = pcm;
  1027. return 0;
  1028. }
  1029. static snd_pcm_ops_t snd_ymfpci_playback_spdif_ops = {
  1030. .open = snd_ymfpci_playback_spdif_open,
  1031. .close = snd_ymfpci_playback_spdif_close,
  1032. .ioctl = snd_pcm_lib_ioctl,
  1033. .hw_params = snd_ymfpci_playback_hw_params,
  1034. .hw_free = snd_ymfpci_playback_hw_free,
  1035. .prepare = snd_ymfpci_playback_prepare,
  1036. .trigger = snd_ymfpci_playback_trigger,
  1037. .pointer = snd_ymfpci_playback_pointer,
  1038. };
  1039. static void snd_ymfpci_pcm_spdif_free(snd_pcm_t *pcm)
  1040. {
  1041. ymfpci_t *chip = pcm->private_data;
  1042. chip->pcm_spdif = NULL;
  1043. snd_pcm_lib_preallocate_free_for_all(pcm);
  1044. }
  1045. int __devinit snd_ymfpci_pcm_spdif(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  1046. {
  1047. snd_pcm_t *pcm;
  1048. int err;
  1049. if (rpcm)
  1050. *rpcm = NULL;
  1051. if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
  1052. return err;
  1053. pcm->private_data = chip;
  1054. pcm->private_free = snd_ymfpci_pcm_spdif_free;
  1055. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1056. /* global setup */
  1057. pcm->info_flags = 0;
  1058. strcpy(pcm->name, "YMFPCI - IEC958");
  1059. chip->pcm_spdif = pcm;
  1060. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1061. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1062. if (rpcm)
  1063. *rpcm = pcm;
  1064. return 0;
  1065. }
  1066. static snd_pcm_ops_t snd_ymfpci_playback_4ch_ops = {
  1067. .open = snd_ymfpci_playback_4ch_open,
  1068. .close = snd_ymfpci_playback_4ch_close,
  1069. .ioctl = snd_pcm_lib_ioctl,
  1070. .hw_params = snd_ymfpci_playback_hw_params,
  1071. .hw_free = snd_ymfpci_playback_hw_free,
  1072. .prepare = snd_ymfpci_playback_prepare,
  1073. .trigger = snd_ymfpci_playback_trigger,
  1074. .pointer = snd_ymfpci_playback_pointer,
  1075. };
  1076. static void snd_ymfpci_pcm_4ch_free(snd_pcm_t *pcm)
  1077. {
  1078. ymfpci_t *chip = pcm->private_data;
  1079. chip->pcm_4ch = NULL;
  1080. snd_pcm_lib_preallocate_free_for_all(pcm);
  1081. }
  1082. int __devinit snd_ymfpci_pcm_4ch(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  1083. {
  1084. snd_pcm_t *pcm;
  1085. int err;
  1086. if (rpcm)
  1087. *rpcm = NULL;
  1088. if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
  1089. return err;
  1090. pcm->private_data = chip;
  1091. pcm->private_free = snd_ymfpci_pcm_4ch_free;
  1092. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1093. /* global setup */
  1094. pcm->info_flags = 0;
  1095. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1096. chip->pcm_4ch = pcm;
  1097. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1098. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1099. if (rpcm)
  1100. *rpcm = pcm;
  1101. return 0;
  1102. }
  1103. static int snd_ymfpci_spdif_default_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1104. {
  1105. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1106. uinfo->count = 1;
  1107. return 0;
  1108. }
  1109. static int snd_ymfpci_spdif_default_get(snd_kcontrol_t * kcontrol,
  1110. snd_ctl_elem_value_t * ucontrol)
  1111. {
  1112. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1113. spin_lock_irq(&chip->reg_lock);
  1114. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1115. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1116. spin_unlock_irq(&chip->reg_lock);
  1117. return 0;
  1118. }
  1119. static int snd_ymfpci_spdif_default_put(snd_kcontrol_t * kcontrol,
  1120. snd_ctl_elem_value_t * ucontrol)
  1121. {
  1122. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1123. unsigned int val;
  1124. int change;
  1125. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1126. (ucontrol->value.iec958.status[1] << 8);
  1127. spin_lock_irq(&chip->reg_lock);
  1128. change = chip->spdif_bits != val;
  1129. chip->spdif_bits = val;
  1130. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1131. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1132. spin_unlock_irq(&chip->reg_lock);
  1133. return change;
  1134. }
  1135. static snd_kcontrol_new_t snd_ymfpci_spdif_default __devinitdata =
  1136. {
  1137. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1138. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1139. .info = snd_ymfpci_spdif_default_info,
  1140. .get = snd_ymfpci_spdif_default_get,
  1141. .put = snd_ymfpci_spdif_default_put
  1142. };
  1143. static int snd_ymfpci_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1144. {
  1145. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1146. uinfo->count = 1;
  1147. return 0;
  1148. }
  1149. static int snd_ymfpci_spdif_mask_get(snd_kcontrol_t * kcontrol,
  1150. snd_ctl_elem_value_t * ucontrol)
  1151. {
  1152. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1153. spin_lock_irq(&chip->reg_lock);
  1154. ucontrol->value.iec958.status[0] = 0x3e;
  1155. ucontrol->value.iec958.status[1] = 0xff;
  1156. spin_unlock_irq(&chip->reg_lock);
  1157. return 0;
  1158. }
  1159. static snd_kcontrol_new_t snd_ymfpci_spdif_mask __devinitdata =
  1160. {
  1161. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1162. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1163. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1164. .info = snd_ymfpci_spdif_mask_info,
  1165. .get = snd_ymfpci_spdif_mask_get,
  1166. };
  1167. static int snd_ymfpci_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1168. {
  1169. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1170. uinfo->count = 1;
  1171. return 0;
  1172. }
  1173. static int snd_ymfpci_spdif_stream_get(snd_kcontrol_t * kcontrol,
  1174. snd_ctl_elem_value_t * ucontrol)
  1175. {
  1176. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1177. spin_lock_irq(&chip->reg_lock);
  1178. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1179. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1180. spin_unlock_irq(&chip->reg_lock);
  1181. return 0;
  1182. }
  1183. static int snd_ymfpci_spdif_stream_put(snd_kcontrol_t * kcontrol,
  1184. snd_ctl_elem_value_t * ucontrol)
  1185. {
  1186. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1187. unsigned int val;
  1188. int change;
  1189. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1190. (ucontrol->value.iec958.status[1] << 8);
  1191. spin_lock_irq(&chip->reg_lock);
  1192. change = chip->spdif_pcm_bits != val;
  1193. chip->spdif_pcm_bits = val;
  1194. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1195. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1196. spin_unlock_irq(&chip->reg_lock);
  1197. return change;
  1198. }
  1199. static snd_kcontrol_new_t snd_ymfpci_spdif_stream __devinitdata =
  1200. {
  1201. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1202. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1203. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1204. .info = snd_ymfpci_spdif_stream_info,
  1205. .get = snd_ymfpci_spdif_stream_get,
  1206. .put = snd_ymfpci_spdif_stream_put
  1207. };
  1208. static int snd_ymfpci_drec_source_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *info)
  1209. {
  1210. static char *texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1211. info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1212. info->count = 1;
  1213. info->value.enumerated.items = 3;
  1214. if (info->value.enumerated.item > 2)
  1215. info->value.enumerated.item = 2;
  1216. strcpy(info->value.enumerated.name, texts[info->value.enumerated.item]);
  1217. return 0;
  1218. }
  1219. static int snd_ymfpci_drec_source_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  1220. {
  1221. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1222. u16 reg;
  1223. spin_lock_irq(&chip->reg_lock);
  1224. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1225. spin_unlock_irq(&chip->reg_lock);
  1226. if (!(reg & 0x100))
  1227. value->value.enumerated.item[0] = 0;
  1228. else
  1229. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1230. return 0;
  1231. }
  1232. static int snd_ymfpci_drec_source_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  1233. {
  1234. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1235. u16 reg, old_reg;
  1236. spin_lock_irq(&chip->reg_lock);
  1237. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1238. if (value->value.enumerated.item[0] == 0)
  1239. reg = old_reg & ~0x100;
  1240. else
  1241. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1242. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1243. spin_unlock_irq(&chip->reg_lock);
  1244. return reg != old_reg;
  1245. }
  1246. static snd_kcontrol_new_t snd_ymfpci_drec_source __devinitdata = {
  1247. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1248. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1249. .name = "Direct Recording Source",
  1250. .info = snd_ymfpci_drec_source_info,
  1251. .get = snd_ymfpci_drec_source_get,
  1252. .put = snd_ymfpci_drec_source_put
  1253. };
  1254. /*
  1255. * Mixer controls
  1256. */
  1257. #define YMFPCI_SINGLE(xname, xindex, reg, shift) \
  1258. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1259. .info = snd_ymfpci_info_single, \
  1260. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1261. .private_value = ((reg) | ((shift) << 16)) }
  1262. static int snd_ymfpci_info_single(snd_kcontrol_t *kcontrol,
  1263. snd_ctl_elem_info_t *uinfo)
  1264. {
  1265. int reg = kcontrol->private_value & 0xffff;
  1266. switch (reg) {
  1267. case YDSXGR_SPDIFOUTCTRL: break;
  1268. case YDSXGR_SPDIFINCTRL: break;
  1269. default: return -EINVAL;
  1270. }
  1271. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1272. uinfo->count = 1;
  1273. uinfo->value.integer.min = 0;
  1274. uinfo->value.integer.max = 1;
  1275. return 0;
  1276. }
  1277. static int snd_ymfpci_get_single(snd_kcontrol_t *kcontrol,
  1278. snd_ctl_elem_value_t *ucontrol)
  1279. {
  1280. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1281. int reg = kcontrol->private_value & 0xffff;
  1282. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1283. unsigned int mask = 1;
  1284. switch (reg) {
  1285. case YDSXGR_SPDIFOUTCTRL: break;
  1286. case YDSXGR_SPDIFINCTRL: break;
  1287. default: return -EINVAL;
  1288. }
  1289. ucontrol->value.integer.value[0] =
  1290. (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1291. return 0;
  1292. }
  1293. static int snd_ymfpci_put_single(snd_kcontrol_t *kcontrol,
  1294. snd_ctl_elem_value_t *ucontrol)
  1295. {
  1296. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1297. int reg = kcontrol->private_value & 0xffff;
  1298. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1299. unsigned int mask = 1;
  1300. int change;
  1301. unsigned int val, oval;
  1302. switch (reg) {
  1303. case YDSXGR_SPDIFOUTCTRL: break;
  1304. case YDSXGR_SPDIFINCTRL: break;
  1305. default: return -EINVAL;
  1306. }
  1307. val = (ucontrol->value.integer.value[0] & mask);
  1308. val <<= shift;
  1309. spin_lock_irq(&chip->reg_lock);
  1310. oval = snd_ymfpci_readl(chip, reg);
  1311. val = (oval & ~(mask << shift)) | val;
  1312. change = val != oval;
  1313. snd_ymfpci_writel(chip, reg, val);
  1314. spin_unlock_irq(&chip->reg_lock);
  1315. return change;
  1316. }
  1317. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1318. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1319. .info = snd_ymfpci_info_double, \
  1320. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1321. .private_value = reg }
  1322. static int snd_ymfpci_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1323. {
  1324. unsigned int reg = kcontrol->private_value;
  1325. if (reg < 0x80 || reg >= 0xc0)
  1326. return -EINVAL;
  1327. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1328. uinfo->count = 2;
  1329. uinfo->value.integer.min = 0;
  1330. uinfo->value.integer.max = 16383;
  1331. return 0;
  1332. }
  1333. static int snd_ymfpci_get_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1334. {
  1335. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1336. unsigned int reg = kcontrol->private_value;
  1337. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1338. unsigned int val;
  1339. if (reg < 0x80 || reg >= 0xc0)
  1340. return -EINVAL;
  1341. spin_lock_irq(&chip->reg_lock);
  1342. val = snd_ymfpci_readl(chip, reg);
  1343. spin_unlock_irq(&chip->reg_lock);
  1344. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1345. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1346. return 0;
  1347. }
  1348. static int snd_ymfpci_put_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1349. {
  1350. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1351. unsigned int reg = kcontrol->private_value;
  1352. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1353. int change;
  1354. unsigned int val1, val2, oval;
  1355. if (reg < 0x80 || reg >= 0xc0)
  1356. return -EINVAL;
  1357. val1 = ucontrol->value.integer.value[0] & mask;
  1358. val2 = ucontrol->value.integer.value[1] & mask;
  1359. val1 <<= shift_left;
  1360. val2 <<= shift_right;
  1361. spin_lock_irq(&chip->reg_lock);
  1362. oval = snd_ymfpci_readl(chip, reg);
  1363. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1364. change = val1 != oval;
  1365. snd_ymfpci_writel(chip, reg, val1);
  1366. spin_unlock_irq(&chip->reg_lock);
  1367. return change;
  1368. }
  1369. /*
  1370. * 4ch duplication
  1371. */
  1372. static int snd_ymfpci_info_dup4ch(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1373. {
  1374. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1375. uinfo->count = 1;
  1376. uinfo->value.integer.min = 0;
  1377. uinfo->value.integer.max = 1;
  1378. return 0;
  1379. }
  1380. static int snd_ymfpci_get_dup4ch(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1381. {
  1382. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1383. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1384. return 0;
  1385. }
  1386. static int snd_ymfpci_put_dup4ch(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1387. {
  1388. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1389. int change;
  1390. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1391. if (change)
  1392. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1393. return change;
  1394. }
  1395. static snd_kcontrol_new_t snd_ymfpci_controls[] __devinitdata = {
  1396. YMFPCI_DOUBLE("Wave Playback Volume", 0, YDSXGR_NATIVEDACOUTVOL),
  1397. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1398. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1399. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1400. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1401. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1402. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1403. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1404. YMFPCI_DOUBLE("FM Legacy Volume", 0, YDSXGR_LEGACYOUTVOL),
  1405. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1406. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1407. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1408. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1409. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL, 0),
  1410. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL, 0),
  1411. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("Loop",NONE,NONE), 0, YDSXGR_SPDIFINCTRL, 4),
  1412. {
  1413. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1414. .name = "4ch Duplication",
  1415. .info = snd_ymfpci_info_dup4ch,
  1416. .get = snd_ymfpci_get_dup4ch,
  1417. .put = snd_ymfpci_put_dup4ch,
  1418. },
  1419. };
  1420. /*
  1421. * GPIO
  1422. */
  1423. static int snd_ymfpci_get_gpio_out(ymfpci_t *chip, int pin)
  1424. {
  1425. u16 reg, mode;
  1426. unsigned long flags;
  1427. spin_lock_irqsave(&chip->reg_lock, flags);
  1428. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1429. reg &= ~(1 << (pin + 8));
  1430. reg |= (1 << pin);
  1431. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1432. /* set the level mode for input line */
  1433. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1434. mode &= ~(3 << (pin * 2));
  1435. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1436. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1437. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1438. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1439. return (mode >> pin) & 1;
  1440. }
  1441. static int snd_ymfpci_set_gpio_out(ymfpci_t *chip, int pin, int enable)
  1442. {
  1443. u16 reg;
  1444. unsigned long flags;
  1445. spin_lock_irqsave(&chip->reg_lock, flags);
  1446. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1447. reg &= ~(1 << pin);
  1448. reg &= ~(1 << (pin + 8));
  1449. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1450. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1451. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1452. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1453. return 0;
  1454. }
  1455. static int snd_ymfpci_gpio_sw_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
  1456. {
  1457. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1458. uinfo->count = 1;
  1459. uinfo->value.integer.min = 0;
  1460. uinfo->value.integer.max = 1;
  1461. return 0;
  1462. }
  1463. static int snd_ymfpci_gpio_sw_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1464. {
  1465. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1466. int pin = (int)kcontrol->private_value;
  1467. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1468. return 0;
  1469. }
  1470. static int snd_ymfpci_gpio_sw_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1471. {
  1472. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1473. int pin = (int)kcontrol->private_value;
  1474. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1475. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1476. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1477. return 1;
  1478. }
  1479. return 0;
  1480. }
  1481. static snd_kcontrol_new_t snd_ymfpci_rear_shared __devinitdata = {
  1482. .name = "Shared Rear/Line-In Switch",
  1483. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1484. .info = snd_ymfpci_gpio_sw_info,
  1485. .get = snd_ymfpci_gpio_sw_get,
  1486. .put = snd_ymfpci_gpio_sw_put,
  1487. .private_value = 2,
  1488. };
  1489. /*
  1490. * PCM voice volume
  1491. */
  1492. static int snd_ymfpci_pcm_vol_info(snd_kcontrol_t *kcontrol,
  1493. snd_ctl_elem_info_t *uinfo)
  1494. {
  1495. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1496. uinfo->count = 2;
  1497. uinfo->value.integer.min = 0;
  1498. uinfo->value.integer.max = 0x8000;
  1499. return 0;
  1500. }
  1501. static int snd_ymfpci_pcm_vol_get(snd_kcontrol_t *kcontrol,
  1502. snd_ctl_elem_value_t *ucontrol)
  1503. {
  1504. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1505. unsigned int subs = kcontrol->id.subdevice;
  1506. ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
  1507. ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
  1508. return 0;
  1509. }
  1510. static int snd_ymfpci_pcm_vol_put(snd_kcontrol_t *kcontrol,
  1511. snd_ctl_elem_value_t *ucontrol)
  1512. {
  1513. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1514. unsigned int subs = kcontrol->id.subdevice;
  1515. snd_pcm_substream_t *substream;
  1516. unsigned long flags;
  1517. if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
  1518. ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
  1519. chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
  1520. chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
  1521. substream = (snd_pcm_substream_t *)kcontrol->private_value;
  1522. spin_lock_irqsave(&chip->voice_lock, flags);
  1523. if (substream->runtime && substream->runtime->private_data) {
  1524. ymfpci_pcm_t *ypcm = substream->runtime->private_data;
  1525. ypcm->update_pcm_vol = 2;
  1526. }
  1527. spin_unlock_irqrestore(&chip->voice_lock, flags);
  1528. return 1;
  1529. }
  1530. return 0;
  1531. }
  1532. static snd_kcontrol_new_t snd_ymfpci_pcm_volume __devinitdata = {
  1533. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1534. .name = "PCM Playback Volume",
  1535. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1536. SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1537. .info = snd_ymfpci_pcm_vol_info,
  1538. .get = snd_ymfpci_pcm_vol_get,
  1539. .put = snd_ymfpci_pcm_vol_put,
  1540. };
  1541. /*
  1542. * Mixer routines
  1543. */
  1544. static void snd_ymfpci_mixer_free_ac97_bus(ac97_bus_t *bus)
  1545. {
  1546. ymfpci_t *chip = bus->private_data;
  1547. chip->ac97_bus = NULL;
  1548. }
  1549. static void snd_ymfpci_mixer_free_ac97(ac97_t *ac97)
  1550. {
  1551. ymfpci_t *chip = ac97->private_data;
  1552. chip->ac97 = NULL;
  1553. }
  1554. int __devinit snd_ymfpci_mixer(ymfpci_t *chip, int rear_switch)
  1555. {
  1556. ac97_template_t ac97;
  1557. snd_kcontrol_t *kctl;
  1558. snd_pcm_substream_t *substream;
  1559. unsigned int idx;
  1560. int err;
  1561. static ac97_bus_ops_t ops = {
  1562. .write = snd_ymfpci_codec_write,
  1563. .read = snd_ymfpci_codec_read,
  1564. };
  1565. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1566. return err;
  1567. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1568. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1569. memset(&ac97, 0, sizeof(ac97));
  1570. ac97.private_data = chip;
  1571. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1572. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1573. return err;
  1574. /* to be sure */
  1575. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1576. AC97_EA_VRA|AC97_EA_VRM, 0);
  1577. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1578. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
  1579. return err;
  1580. }
  1581. /* add S/PDIF control */
  1582. snd_assert(chip->pcm_spdif != NULL, return -EIO);
  1583. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
  1584. return err;
  1585. kctl->id.device = chip->pcm_spdif->device;
  1586. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
  1587. return err;
  1588. kctl->id.device = chip->pcm_spdif->device;
  1589. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
  1590. return err;
  1591. kctl->id.device = chip->pcm_spdif->device;
  1592. chip->spdif_pcm_ctl = kctl;
  1593. /* direct recording source */
  1594. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  1595. (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
  1596. return err;
  1597. /*
  1598. * shared rear/line-in
  1599. */
  1600. if (rear_switch) {
  1601. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
  1602. return err;
  1603. }
  1604. /* per-voice volume */
  1605. substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1606. for (idx = 0; idx < 32; ++idx) {
  1607. kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
  1608. if (!kctl)
  1609. return -ENOMEM;
  1610. kctl->id.device = chip->pcm->device;
  1611. kctl->id.subdevice = idx;
  1612. kctl->private_value = (unsigned long)substream;
  1613. if ((err = snd_ctl_add(chip->card, kctl)) < 0)
  1614. return err;
  1615. chip->pcm_mixer[idx].left = 0x8000;
  1616. chip->pcm_mixer[idx].right = 0x8000;
  1617. chip->pcm_mixer[idx].ctl = kctl;
  1618. substream = substream->next;
  1619. }
  1620. return 0;
  1621. }
  1622. /*
  1623. * timer
  1624. */
  1625. static int snd_ymfpci_timer_start(snd_timer_t *timer)
  1626. {
  1627. ymfpci_t *chip;
  1628. unsigned long flags;
  1629. unsigned int count;
  1630. chip = snd_timer_chip(timer);
  1631. count = (timer->sticks << 1) - 1;
  1632. spin_lock_irqsave(&chip->reg_lock, flags);
  1633. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1634. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1635. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1636. return 0;
  1637. }
  1638. static int snd_ymfpci_timer_stop(snd_timer_t *timer)
  1639. {
  1640. ymfpci_t *chip;
  1641. unsigned long flags;
  1642. chip = snd_timer_chip(timer);
  1643. spin_lock_irqsave(&chip->reg_lock, flags);
  1644. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1645. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1646. return 0;
  1647. }
  1648. static int snd_ymfpci_timer_precise_resolution(snd_timer_t *timer,
  1649. unsigned long *num, unsigned long *den)
  1650. {
  1651. *num = 1;
  1652. *den = 48000;
  1653. return 0;
  1654. }
  1655. static struct _snd_timer_hardware snd_ymfpci_timer_hw = {
  1656. .flags = SNDRV_TIMER_HW_AUTO,
  1657. .resolution = 20833, /* 1/fs = 20.8333...us */
  1658. .ticks = 0x8000,
  1659. .start = snd_ymfpci_timer_start,
  1660. .stop = snd_ymfpci_timer_stop,
  1661. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1662. };
  1663. int __devinit snd_ymfpci_timer(ymfpci_t *chip, int device)
  1664. {
  1665. snd_timer_t *timer = NULL;
  1666. snd_timer_id_t tid;
  1667. int err;
  1668. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1669. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1670. tid.card = chip->card->number;
  1671. tid.device = device;
  1672. tid.subdevice = 0;
  1673. if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
  1674. strcpy(timer->name, "YMFPCI timer");
  1675. timer->private_data = chip;
  1676. timer->hw = snd_ymfpci_timer_hw;
  1677. }
  1678. chip->timer = timer;
  1679. return err;
  1680. }
  1681. /*
  1682. * proc interface
  1683. */
  1684. static void snd_ymfpci_proc_read(snd_info_entry_t *entry,
  1685. snd_info_buffer_t * buffer)
  1686. {
  1687. ymfpci_t *chip = entry->private_data;
  1688. int i;
  1689. snd_iprintf(buffer, "YMFPCI\n\n");
  1690. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1691. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1692. }
  1693. static int __devinit snd_ymfpci_proc_init(snd_card_t * card, ymfpci_t *chip)
  1694. {
  1695. snd_info_entry_t *entry;
  1696. if (! snd_card_proc_new(card, "ymfpci", &entry))
  1697. snd_info_set_text_ops(entry, chip, 1024, snd_ymfpci_proc_read);
  1698. return 0;
  1699. }
  1700. /*
  1701. * initialization routines
  1702. */
  1703. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1704. {
  1705. u8 cmd;
  1706. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1707. #if 0 // force to reset
  1708. if (cmd & 0x03) {
  1709. #endif
  1710. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1711. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1712. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1713. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1714. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1715. #if 0
  1716. }
  1717. #endif
  1718. }
  1719. static void snd_ymfpci_enable_dsp(ymfpci_t *chip)
  1720. {
  1721. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1722. }
  1723. static void snd_ymfpci_disable_dsp(ymfpci_t *chip)
  1724. {
  1725. u32 val;
  1726. int timeout = 1000;
  1727. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1728. if (val)
  1729. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1730. while (timeout-- > 0) {
  1731. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1732. if ((val & 0x00000002) == 0)
  1733. break;
  1734. }
  1735. }
  1736. #include "ymfpci_image.h"
  1737. static void snd_ymfpci_download_image(ymfpci_t *chip)
  1738. {
  1739. int i;
  1740. u16 ctrl;
  1741. unsigned long *inst;
  1742. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1743. snd_ymfpci_disable_dsp(chip);
  1744. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1745. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1746. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1747. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1748. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1749. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1750. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1751. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1752. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1753. /* setup DSP instruction code */
  1754. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1755. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2), DspInst[i]);
  1756. /* setup control instruction code */
  1757. switch (chip->device_id) {
  1758. case PCI_DEVICE_ID_YAMAHA_724F:
  1759. case PCI_DEVICE_ID_YAMAHA_740C:
  1760. case PCI_DEVICE_ID_YAMAHA_744:
  1761. case PCI_DEVICE_ID_YAMAHA_754:
  1762. inst = CntrlInst1E;
  1763. break;
  1764. default:
  1765. inst = CntrlInst;
  1766. break;
  1767. }
  1768. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1769. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2), inst[i]);
  1770. snd_ymfpci_enable_dsp(chip);
  1771. }
  1772. static int __devinit snd_ymfpci_memalloc(ymfpci_t *chip)
  1773. {
  1774. long size, playback_ctrl_size;
  1775. int voice, bank, reg;
  1776. u8 *ptr;
  1777. dma_addr_t ptr_addr;
  1778. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1779. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1780. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1781. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1782. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1783. size = ((playback_ctrl_size + 0x00ff) & ~0x00ff) +
  1784. ((chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES + 0x00ff) & ~0x00ff) +
  1785. ((chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES + 0x00ff) & ~0x00ff) +
  1786. ((chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES + 0x00ff) & ~0x00ff) +
  1787. chip->work_size;
  1788. /* work_ptr must be aligned to 256 bytes, but it's already
  1789. covered with the kernel page allocation mechanism */
  1790. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1791. size, &chip->work_ptr) < 0)
  1792. return -ENOMEM;
  1793. ptr = chip->work_ptr.area;
  1794. ptr_addr = chip->work_ptr.addr;
  1795. memset(ptr, 0, size); /* for sure */
  1796. chip->bank_base_playback = ptr;
  1797. chip->bank_base_playback_addr = ptr_addr;
  1798. chip->ctrl_playback = (u32 *)ptr;
  1799. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1800. ptr += (playback_ctrl_size + 0x00ff) & ~0x00ff;
  1801. ptr_addr += (playback_ctrl_size + 0x00ff) & ~0x00ff;
  1802. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1803. chip->voices[voice].number = voice;
  1804. chip->voices[voice].bank = (snd_ymfpci_playback_bank_t *)ptr;
  1805. chip->voices[voice].bank_addr = ptr_addr;
  1806. for (bank = 0; bank < 2; bank++) {
  1807. chip->bank_playback[voice][bank] = (snd_ymfpci_playback_bank_t *)ptr;
  1808. ptr += chip->bank_size_playback;
  1809. ptr_addr += chip->bank_size_playback;
  1810. }
  1811. }
  1812. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1813. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1814. chip->bank_base_capture = ptr;
  1815. chip->bank_base_capture_addr = ptr_addr;
  1816. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1817. for (bank = 0; bank < 2; bank++) {
  1818. chip->bank_capture[voice][bank] = (snd_ymfpci_capture_bank_t *)ptr;
  1819. ptr += chip->bank_size_capture;
  1820. ptr_addr += chip->bank_size_capture;
  1821. }
  1822. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1823. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1824. chip->bank_base_effect = ptr;
  1825. chip->bank_base_effect_addr = ptr_addr;
  1826. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1827. for (bank = 0; bank < 2; bank++) {
  1828. chip->bank_effect[voice][bank] = (snd_ymfpci_effect_bank_t *)ptr;
  1829. ptr += chip->bank_size_effect;
  1830. ptr_addr += chip->bank_size_effect;
  1831. }
  1832. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1833. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1834. chip->work_base = ptr;
  1835. chip->work_base_addr = ptr_addr;
  1836. snd_assert(ptr + chip->work_size == chip->work_ptr.area + chip->work_ptr.bytes, );
  1837. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1838. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1839. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1840. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1841. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1842. /* S/PDIF output initialization */
  1843. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1844. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1845. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1846. /* S/PDIF input initialization */
  1847. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1848. /* digital mixer setup */
  1849. for (reg = 0x80; reg < 0xc0; reg += 4)
  1850. snd_ymfpci_writel(chip, reg, 0);
  1851. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1852. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1853. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1854. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1855. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1856. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1857. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1858. return 0;
  1859. }
  1860. static int snd_ymfpci_free(ymfpci_t *chip)
  1861. {
  1862. u16 ctrl;
  1863. snd_assert(chip != NULL, return -EINVAL);
  1864. if (chip->res_reg_area) { /* don't touch busy hardware */
  1865. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1866. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1867. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1868. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1869. snd_ymfpci_disable_dsp(chip);
  1870. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1871. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1872. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1873. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1874. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1875. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1876. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1877. }
  1878. snd_ymfpci_ac3_done(chip);
  1879. /* Set PCI device to D3 state */
  1880. #if 0
  1881. /* FIXME: temporarily disabled, otherwise we cannot fire up
  1882. * the chip again unless reboot. ACPI bug?
  1883. */
  1884. pci_set_power_state(chip->pci, 3);
  1885. #endif
  1886. #ifdef CONFIG_PM
  1887. vfree(chip->saved_regs);
  1888. #endif
  1889. release_and_free_resource(chip->mpu_res);
  1890. release_and_free_resource(chip->fm_res);
  1891. snd_ymfpci_free_gameport(chip);
  1892. if (chip->reg_area_virt)
  1893. iounmap(chip->reg_area_virt);
  1894. if (chip->work_ptr.area)
  1895. snd_dma_free_pages(&chip->work_ptr);
  1896. if (chip->irq >= 0)
  1897. free_irq(chip->irq, (void *)chip);
  1898. release_and_free_resource(chip->res_reg_area);
  1899. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  1900. pci_disable_device(chip->pci);
  1901. kfree(chip);
  1902. return 0;
  1903. }
  1904. static int snd_ymfpci_dev_free(snd_device_t *device)
  1905. {
  1906. ymfpci_t *chip = device->device_data;
  1907. return snd_ymfpci_free(chip);
  1908. }
  1909. #ifdef CONFIG_PM
  1910. static int saved_regs_index[] = {
  1911. /* spdif */
  1912. YDSXGR_SPDIFOUTCTRL,
  1913. YDSXGR_SPDIFOUTSTATUS,
  1914. YDSXGR_SPDIFINCTRL,
  1915. /* volumes */
  1916. YDSXGR_PRIADCLOOPVOL,
  1917. YDSXGR_NATIVEDACINVOL,
  1918. YDSXGR_NATIVEDACOUTVOL,
  1919. // YDSXGR_BUF441OUTVOL,
  1920. YDSXGR_NATIVEADCINVOL,
  1921. YDSXGR_SPDIFLOOPVOL,
  1922. YDSXGR_SPDIFOUTVOL,
  1923. YDSXGR_ZVOUTVOL,
  1924. YDSXGR_LEGACYOUTVOL,
  1925. /* address bases */
  1926. YDSXGR_PLAYCTRLBASE,
  1927. YDSXGR_RECCTRLBASE,
  1928. YDSXGR_EFFCTRLBASE,
  1929. YDSXGR_WORKBASE,
  1930. /* capture set up */
  1931. YDSXGR_MAPOFREC,
  1932. YDSXGR_RECFORMAT,
  1933. YDSXGR_RECSLOTSR,
  1934. YDSXGR_ADCFORMAT,
  1935. YDSXGR_ADCSLOTSR,
  1936. };
  1937. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  1938. static int snd_ymfpci_suspend(snd_card_t *card, pm_message_t state)
  1939. {
  1940. ymfpci_t *chip = card->pm_private_data;
  1941. unsigned int i;
  1942. snd_pcm_suspend_all(chip->pcm);
  1943. snd_pcm_suspend_all(chip->pcm2);
  1944. snd_pcm_suspend_all(chip->pcm_spdif);
  1945. snd_pcm_suspend_all(chip->pcm_4ch);
  1946. snd_ac97_suspend(chip->ac97);
  1947. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  1948. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  1949. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  1950. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1951. snd_ymfpci_disable_dsp(chip);
  1952. pci_disable_device(chip->pci);
  1953. return 0;
  1954. }
  1955. static int snd_ymfpci_resume(snd_card_t *card)
  1956. {
  1957. ymfpci_t *chip = card->pm_private_data;
  1958. unsigned int i;
  1959. pci_enable_device(chip->pci);
  1960. pci_set_master(chip->pci);
  1961. snd_ymfpci_aclink_reset(chip->pci);
  1962. snd_ymfpci_codec_ready(chip, 0);
  1963. snd_ymfpci_download_image(chip);
  1964. udelay(100);
  1965. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  1966. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  1967. snd_ac97_resume(chip->ac97);
  1968. /* start hw again */
  1969. if (chip->start_count > 0) {
  1970. spin_lock_irq(&chip->reg_lock);
  1971. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  1972. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  1973. spin_unlock_irq(&chip->reg_lock);
  1974. }
  1975. return 0;
  1976. }
  1977. #endif /* CONFIG_PM */
  1978. int __devinit snd_ymfpci_create(snd_card_t * card,
  1979. struct pci_dev * pci,
  1980. unsigned short old_legacy_ctrl,
  1981. ymfpci_t ** rchip)
  1982. {
  1983. ymfpci_t *chip;
  1984. int err;
  1985. static snd_device_ops_t ops = {
  1986. .dev_free = snd_ymfpci_dev_free,
  1987. };
  1988. *rchip = NULL;
  1989. /* enable PCI device */
  1990. if ((err = pci_enable_device(pci)) < 0)
  1991. return err;
  1992. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1993. if (chip == NULL) {
  1994. pci_disable_device(pci);
  1995. return -ENOMEM;
  1996. }
  1997. chip->old_legacy_ctrl = old_legacy_ctrl;
  1998. spin_lock_init(&chip->reg_lock);
  1999. spin_lock_init(&chip->voice_lock);
  2000. init_waitqueue_head(&chip->interrupt_sleep);
  2001. atomic_set(&chip->interrupt_sleep_count, 0);
  2002. chip->card = card;
  2003. chip->pci = pci;
  2004. chip->irq = -1;
  2005. chip->device_id = pci->device;
  2006. pci_read_config_byte(pci, PCI_REVISION_ID, (u8 *)&chip->rev);
  2007. chip->reg_area_phys = pci_resource_start(pci, 0);
  2008. chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
  2009. pci_set_master(pci);
  2010. if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
  2011. snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  2012. snd_ymfpci_free(chip);
  2013. return -EBUSY;
  2014. }
  2015. if (request_irq(pci->irq, snd_ymfpci_interrupt, SA_INTERRUPT|SA_SHIRQ, "YMFPCI", (void *) chip)) {
  2016. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2017. snd_ymfpci_free(chip);
  2018. return -EBUSY;
  2019. }
  2020. chip->irq = pci->irq;
  2021. snd_ymfpci_aclink_reset(pci);
  2022. if (snd_ymfpci_codec_ready(chip, 0) < 0) {
  2023. snd_ymfpci_free(chip);
  2024. return -EIO;
  2025. }
  2026. snd_ymfpci_download_image(chip);
  2027. udelay(100); /* seems we need a delay after downloading image.. */
  2028. if (snd_ymfpci_memalloc(chip) < 0) {
  2029. snd_ymfpci_free(chip);
  2030. return -EIO;
  2031. }
  2032. if ((err = snd_ymfpci_ac3_init(chip)) < 0) {
  2033. snd_ymfpci_free(chip);
  2034. return err;
  2035. }
  2036. #ifdef CONFIG_PM
  2037. chip->saved_regs = vmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32));
  2038. if (chip->saved_regs == NULL) {
  2039. snd_ymfpci_free(chip);
  2040. return -ENOMEM;
  2041. }
  2042. snd_card_set_pm_callback(card, snd_ymfpci_suspend, snd_ymfpci_resume, chip);
  2043. #endif
  2044. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2045. snd_ymfpci_free(chip);
  2046. return err;
  2047. }
  2048. snd_ymfpci_proc_init(card, chip);
  2049. snd_card_set_dev(card, &pci->dev);
  2050. *rchip = chip;
  2051. return 0;
  2052. }