cs4281.c 65 KB

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  1. /*
  2. * Driver for Cirrus Logic CS4281 based PCI soundcard
  3. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #include <sound/driver.h>
  22. #include <asm/io.h>
  23. #include <linux/delay.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/init.h>
  26. #include <linux/pci.h>
  27. #include <linux/slab.h>
  28. #include <linux/gameport.h>
  29. #include <linux/moduleparam.h>
  30. #include <sound/core.h>
  31. #include <sound/control.h>
  32. #include <sound/pcm.h>
  33. #include <sound/rawmidi.h>
  34. #include <sound/ac97_codec.h>
  35. #include <sound/opl3.h>
  36. #include <sound/initval.h>
  37. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  38. MODULE_DESCRIPTION("Cirrus Logic CS4281");
  39. MODULE_LICENSE("GPL");
  40. MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
  41. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  42. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  43. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
  44. static int dual_codec[SNDRV_CARDS]; /* dual codec */
  45. module_param_array(index, int, NULL, 0444);
  46. MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
  47. module_param_array(id, charp, NULL, 0444);
  48. MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
  49. module_param_array(enable, bool, NULL, 0444);
  50. MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
  51. module_param_array(dual_codec, bool, NULL, 0444);
  52. MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
  53. /*
  54. * Direct registers
  55. */
  56. #define CS4281_BA0_SIZE 0x1000
  57. #define CS4281_BA1_SIZE 0x10000
  58. /*
  59. * BA0 registers
  60. */
  61. #define BA0_HISR 0x0000 /* Host Interrupt Status Register */
  62. #define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
  63. #define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
  64. #define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
  65. #define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
  66. #define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
  67. #define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
  68. #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
  69. #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
  70. #define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
  71. #define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
  72. #define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
  73. #define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
  74. #define BA0_HICR 0x0008 /* Host Interrupt Control Register */
  75. #define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
  76. #define BA0_HICR_IEV (1<<0) /* INTENA Value */
  77. #define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
  78. #define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
  79. /* Use same contants as for BA0_HISR */
  80. #define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
  81. #define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
  82. #define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
  83. #define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
  84. #define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
  85. #define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
  86. #define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
  87. #define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
  88. #define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
  89. #define BA0_HDSR_DRUN (1<<15) /* DMA Running */
  90. #define BA0_HDSR_RQ (1<<7) /* Pending Request */
  91. #define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
  92. #define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
  93. #define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
  94. #define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
  95. #define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
  96. #define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
  97. #define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
  98. #define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
  99. #define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
  100. #define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
  101. #define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
  102. #define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
  103. #define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
  104. #define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
  105. #define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
  106. #define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
  107. #define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
  108. #define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
  109. #define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
  110. #define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
  111. #define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
  112. #define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
  113. #define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
  114. #define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
  115. #define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
  116. #define BA0_DMR_POLL (1<<28) /* Enable poll mode */
  117. #define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
  118. #define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
  119. #define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
  120. #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
  121. #define BA0_DMR_USIGN (1<<19) /* Unsigned */
  122. #define BA0_DMR_BEND (1<<18) /* Big Endian */
  123. #define BA0_DMR_MONO (1<<17) /* Mono */
  124. #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
  125. #define BA0_DMR_TYPE_DEMAND (0<<6)
  126. #define BA0_DMR_TYPE_SINGLE (1<<6)
  127. #define BA0_DMR_TYPE_BLOCK (2<<6)
  128. #define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
  129. #define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
  130. #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
  131. #define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
  132. #define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
  133. #define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
  134. #define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
  135. #define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
  136. #define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
  137. #define BA0_FCR0 0x0180 /* FIFO Control 0 */
  138. #define BA0_FCR1 0x0184 /* FIFO Control 1 */
  139. #define BA0_FCR2 0x0188 /* FIFO Control 2 */
  140. #define BA0_FCR3 0x018c /* FIFO Control 3 */
  141. #define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
  142. #define BA0_FCR_DACZ (1<<30) /* DAC Zero */
  143. #define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
  144. #define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
  145. #define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
  146. #define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
  147. #define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
  148. #define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
  149. #define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
  150. #define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
  151. #define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
  152. #define BA0_FCHS 0x020c /* FIFO Channel Status */
  153. #define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
  154. #define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
  155. #define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
  156. #define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
  157. #define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
  158. #define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
  159. #define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
  160. #define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
  161. #define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
  162. #define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
  163. #define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
  164. #define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
  165. #define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
  166. #define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
  167. #define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
  168. #define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
  169. #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
  170. #define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
  171. #define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
  172. #define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
  173. #define BA0_PMCS 0x0344 /* Power Management Control/Status */
  174. #define BA0_CWPR 0x03e0 /* Configuration Write Protect */
  175. #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
  176. #define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
  177. #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
  178. #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
  179. #define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
  180. #define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
  181. #define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
  182. #define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
  183. #define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
  184. #define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
  185. #define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
  186. #define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
  187. #define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
  188. #define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
  189. #define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
  190. #define BA0_IISR 0x03f4 /* ISA Interrupt Select */
  191. #define BA0_TMS 0x03f8 /* Test Register */
  192. #define BA0_SSVID 0x03fc /* Subsystem ID register */
  193. #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
  194. #define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
  195. #define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
  196. #define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
  197. #define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
  198. #define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
  199. #define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
  200. #define BA0_FRR 0x0410 /* Feature Reporting Register */
  201. #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
  202. #define BA0_SERMC 0x0420 /* Serial Port Master Control */
  203. #define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
  204. #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
  205. #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
  206. #define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
  207. #define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
  208. #define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
  209. #define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
  210. #define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
  211. #define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
  212. #define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
  213. #define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
  214. #define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
  215. #define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
  216. #define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
  217. #define BA0_SERC1_AC97 (1<<1)
  218. #define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
  219. #define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
  220. #define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
  221. #define BA0_SERC2_AC97 (1<<1)
  222. #define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
  223. #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
  224. #define BA0_ACCTL 0x0460 /* AC'97 Control */
  225. #define BA0_ACCTL_TC (1<<6) /* Target Codec */
  226. #define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
  227. #define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
  228. #define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
  229. #define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
  230. #define BA0_ACSTS 0x0464 /* AC'97 Status */
  231. #define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
  232. #define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
  233. #define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
  234. #define BA0_ACOSV_SLV(x) (1<<((x)-3))
  235. #define BA0_ACCAD 0x046c /* AC'97 Command Address */
  236. #define BA0_ACCDA 0x0470 /* AC'97 Command Data */
  237. #define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
  238. #define BA0_ACISV_SLV(x) (1<<((x)-3))
  239. #define BA0_ACSAD 0x0478 /* AC'97 Status Address */
  240. #define BA0_ACSDA 0x047c /* AC'97 Status Data */
  241. #define BA0_JSPT 0x0480 /* Joystick poll/trigger */
  242. #define BA0_JSCTL 0x0484 /* Joystick control */
  243. #define BA0_JSC1 0x0488 /* Joystick control */
  244. #define BA0_JSC2 0x048c /* Joystick control */
  245. #define BA0_JSIO 0x04a0
  246. #define BA0_MIDCR 0x0490 /* MIDI Control */
  247. #define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
  248. #define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
  249. #define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
  250. #define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
  251. #define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
  252. #define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
  253. #define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
  254. #define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
  255. #define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
  256. #define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
  257. #define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
  258. #define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
  259. #define BA0_MIDWP 0x0498 /* MIDI Write */
  260. #define BA0_MIDRP 0x049c /* MIDI Read (ro) */
  261. #define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
  262. #define BA0_AODSD1_NDS(x) (1<<((x)-3))
  263. #define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
  264. #define BA0_AODSD2_NDS(x) (1<<((x)-3))
  265. #define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
  266. #define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
  267. #define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
  268. #define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
  269. #define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
  270. #define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
  271. #define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
  272. #define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
  273. #define BA0_FMDP 0x0734 /* FM Data Port */
  274. #define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
  275. #define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
  276. #define BA0_SSPM 0x0740 /* Sound System Power Management */
  277. #define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
  278. #define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
  279. #define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
  280. #define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
  281. #define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
  282. #define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
  283. #define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
  284. #define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
  285. #define BA0_SSCR 0x074c /* Sound System Control Register */
  286. #define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
  287. #define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
  288. #define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
  289. #define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
  290. #define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
  291. #define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
  292. #define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
  293. #define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
  294. #define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
  295. #define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
  296. #define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
  297. #define BA0_SRCSA 0x075c /* SRC Slot Assignments */
  298. #define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
  299. #define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
  300. #define BA0_PASR 0x0768 /* playback sample rate */
  301. #define BA0_CASR 0x076C /* capture sample rate */
  302. /* Source Slot Numbers - Playback */
  303. #define SRCSLOT_LEFT_PCM_PLAYBACK 0
  304. #define SRCSLOT_RIGHT_PCM_PLAYBACK 1
  305. #define SRCSLOT_PHONE_LINE_1_DAC 2
  306. #define SRCSLOT_CENTER_PCM_PLAYBACK 3
  307. #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
  308. #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
  309. #define SRCSLOT_LFE_PCM_PLAYBACK 6
  310. #define SRCSLOT_PHONE_LINE_2_DAC 7
  311. #define SRCSLOT_HEADSET_DAC 8
  312. #define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
  313. #define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
  314. /* Source Slot Numbers - Capture */
  315. #define SRCSLOT_LEFT_PCM_RECORD 10
  316. #define SRCSLOT_RIGHT_PCM_RECORD 11
  317. #define SRCSLOT_PHONE_LINE_1_ADC 12
  318. #define SRCSLOT_MIC_ADC 13
  319. #define SRCSLOT_PHONE_LINE_2_ADC 17
  320. #define SRCSLOT_HEADSET_ADC 18
  321. #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
  322. #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
  323. #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
  324. #define SRCSLOT_SECONDARY_MIC_ADC 23
  325. #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
  326. #define SRCSLOT_SECONDARY_HEADSET_ADC 28
  327. /* Source Slot Numbers - Others */
  328. #define SRCSLOT_POWER_DOWN 31
  329. /* MIDI modes */
  330. #define CS4281_MODE_OUTPUT (1<<0)
  331. #define CS4281_MODE_INPUT (1<<1)
  332. /* joystick bits */
  333. /* Bits for JSPT */
  334. #define JSPT_CAX 0x00000001
  335. #define JSPT_CAY 0x00000002
  336. #define JSPT_CBX 0x00000004
  337. #define JSPT_CBY 0x00000008
  338. #define JSPT_BA1 0x00000010
  339. #define JSPT_BA2 0x00000020
  340. #define JSPT_BB1 0x00000040
  341. #define JSPT_BB2 0x00000080
  342. /* Bits for JSCTL */
  343. #define JSCTL_SP_MASK 0x00000003
  344. #define JSCTL_SP_SLOW 0x00000000
  345. #define JSCTL_SP_MEDIUM_SLOW 0x00000001
  346. #define JSCTL_SP_MEDIUM_FAST 0x00000002
  347. #define JSCTL_SP_FAST 0x00000003
  348. #define JSCTL_ARE 0x00000004
  349. /* Data register pairs masks */
  350. #define JSC1_Y1V_MASK 0x0000FFFF
  351. #define JSC1_X1V_MASK 0xFFFF0000
  352. #define JSC1_Y1V_SHIFT 0
  353. #define JSC1_X1V_SHIFT 16
  354. #define JSC2_Y2V_MASK 0x0000FFFF
  355. #define JSC2_X2V_MASK 0xFFFF0000
  356. #define JSC2_Y2V_SHIFT 0
  357. #define JSC2_X2V_SHIFT 16
  358. /* JS GPIO */
  359. #define JSIO_DAX 0x00000001
  360. #define JSIO_DAY 0x00000002
  361. #define JSIO_DBX 0x00000004
  362. #define JSIO_DBY 0x00000008
  363. #define JSIO_AXOE 0x00000010
  364. #define JSIO_AYOE 0x00000020
  365. #define JSIO_BXOE 0x00000040
  366. #define JSIO_BYOE 0x00000080
  367. /*
  368. *
  369. */
  370. typedef struct snd_cs4281 cs4281_t;
  371. typedef struct snd_cs4281_dma cs4281_dma_t;
  372. struct snd_cs4281_dma {
  373. snd_pcm_substream_t *substream;
  374. unsigned int regDBA; /* offset to DBA register */
  375. unsigned int regDCA; /* offset to DCA register */
  376. unsigned int regDBC; /* offset to DBC register */
  377. unsigned int regDCC; /* offset to DCC register */
  378. unsigned int regDMR; /* offset to DMR register */
  379. unsigned int regDCR; /* offset to DCR register */
  380. unsigned int regHDSR; /* offset to HDSR register */
  381. unsigned int regFCR; /* offset to FCR register */
  382. unsigned int regFSIC; /* offset to FSIC register */
  383. unsigned int valDMR; /* DMA mode */
  384. unsigned int valDCR; /* DMA command */
  385. unsigned int valFCR; /* FIFO control */
  386. unsigned int fifo_offset; /* FIFO offset within BA1 */
  387. unsigned char left_slot; /* FIFO left slot */
  388. unsigned char right_slot; /* FIFO right slot */
  389. int frag; /* period number */
  390. };
  391. #define SUSPEND_REGISTERS 20
  392. struct snd_cs4281 {
  393. int irq;
  394. void __iomem *ba0; /* virtual (accessible) address */
  395. void __iomem *ba1; /* virtual (accessible) address */
  396. unsigned long ba0_addr;
  397. unsigned long ba1_addr;
  398. int dual_codec;
  399. ac97_bus_t *ac97_bus;
  400. ac97_t *ac97;
  401. ac97_t *ac97_secondary;
  402. struct pci_dev *pci;
  403. snd_card_t *card;
  404. snd_pcm_t *pcm;
  405. snd_rawmidi_t *rmidi;
  406. snd_rawmidi_substream_t *midi_input;
  407. snd_rawmidi_substream_t *midi_output;
  408. cs4281_dma_t dma[4];
  409. unsigned char src_left_play_slot;
  410. unsigned char src_right_play_slot;
  411. unsigned char src_left_rec_slot;
  412. unsigned char src_right_rec_slot;
  413. unsigned int spurious_dhtc_irq;
  414. unsigned int spurious_dtc_irq;
  415. spinlock_t reg_lock;
  416. unsigned int midcr;
  417. unsigned int uartm;
  418. struct gameport *gameport;
  419. #ifdef CONFIG_PM
  420. u32 suspend_regs[SUSPEND_REGISTERS];
  421. #endif
  422. };
  423. static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  424. static struct pci_device_id snd_cs4281_ids[] = {
  425. { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */
  426. { 0, }
  427. };
  428. MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
  429. /*
  430. * constants
  431. */
  432. #define CS4281_FIFO_SIZE 32
  433. /*
  434. * common I/O routines
  435. */
  436. static void snd_cs4281_delay(unsigned int delay)
  437. {
  438. if (delay > 999) {
  439. unsigned long end_time;
  440. delay = (delay * HZ) / 1000000;
  441. if (delay < 1)
  442. delay = 1;
  443. end_time = jiffies + delay;
  444. do {
  445. schedule_timeout_uninterruptible(1);
  446. } while (time_after_eq(end_time, jiffies));
  447. } else {
  448. udelay(delay);
  449. }
  450. }
  451. static inline void snd_cs4281_delay_long(void)
  452. {
  453. schedule_timeout_uninterruptible(1);
  454. }
  455. static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
  456. {
  457. writel(val, chip->ba0 + offset);
  458. }
  459. static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset)
  460. {
  461. return readl(chip->ba0 + offset);
  462. }
  463. static void snd_cs4281_ac97_write(ac97_t *ac97,
  464. unsigned short reg, unsigned short val)
  465. {
  466. /*
  467. * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
  468. * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
  469. * 3. Write ACCTL = Control Register = 460h for initiating the write
  470. * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
  471. * 5. if DCV not cleared, break and return error
  472. */
  473. cs4281_t *chip = ac97->private_data;
  474. int count;
  475. /*
  476. * Setup the AC97 control registers on the CS461x to send the
  477. * appropriate command to the AC97 to perform the read.
  478. * ACCAD = Command Address Register = 46Ch
  479. * ACCDA = Command Data Register = 470h
  480. * ACCTL = Control Register = 460h
  481. * set DCV - will clear when process completed
  482. * reset CRW - Write command
  483. * set VFRM - valid frame enabled
  484. * set ESYN - ASYNC generation enabled
  485. * set RSTN - ARST# inactive, AC97 codec not reset
  486. */
  487. snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
  488. snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
  489. snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
  490. BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
  491. for (count = 0; count < 2000; count++) {
  492. /*
  493. * First, we want to wait for a short time.
  494. */
  495. udelay(10);
  496. /*
  497. * Now, check to see if the write has completed.
  498. * ACCTL = 460h, DCV should be reset by now and 460h = 07h
  499. */
  500. if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
  501. return;
  502. }
  503. }
  504. snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
  505. }
  506. static unsigned short snd_cs4281_ac97_read(ac97_t *ac97,
  507. unsigned short reg)
  508. {
  509. cs4281_t *chip = ac97->private_data;
  510. int count;
  511. unsigned short result;
  512. // FIXME: volatile is necessary in the following due to a bug of
  513. // some gcc versions
  514. volatile int ac97_num = ((volatile ac97_t *)ac97)->num;
  515. /*
  516. * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
  517. * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
  518. * 3. Write ACCTL = Control Register = 460h for initiating the write
  519. * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
  520. * 5. if DCV not cleared, break and return error
  521. * 6. Read ACSTS = Status Register = 464h, check VSTS bit
  522. */
  523. snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
  524. /*
  525. * Setup the AC97 control registers on the CS461x to send the
  526. * appropriate command to the AC97 to perform the read.
  527. * ACCAD = Command Address Register = 46Ch
  528. * ACCDA = Command Data Register = 470h
  529. * ACCTL = Control Register = 460h
  530. * set DCV - will clear when process completed
  531. * set CRW - Read command
  532. * set VFRM - valid frame enabled
  533. * set ESYN - ASYNC generation enabled
  534. * set RSTN - ARST# inactive, AC97 codec not reset
  535. */
  536. snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
  537. snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
  538. snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
  539. BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
  540. (ac97_num ? BA0_ACCTL_TC : 0));
  541. /*
  542. * Wait for the read to occur.
  543. */
  544. for (count = 0; count < 500; count++) {
  545. /*
  546. * First, we want to wait for a short time.
  547. */
  548. udelay(10);
  549. /*
  550. * Now, check to see if the read has completed.
  551. * ACCTL = 460h, DCV should be reset by now and 460h = 17h
  552. */
  553. if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
  554. goto __ok1;
  555. }
  556. snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
  557. result = 0xffff;
  558. goto __end;
  559. __ok1:
  560. /*
  561. * Wait for the valid status bit to go active.
  562. */
  563. for (count = 0; count < 100; count++) {
  564. /*
  565. * Read the AC97 status register.
  566. * ACSTS = Status Register = 464h
  567. * VSTS - Valid Status
  568. */
  569. if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
  570. goto __ok2;
  571. udelay(10);
  572. }
  573. snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
  574. result = 0xffff;
  575. goto __end;
  576. __ok2:
  577. /*
  578. * Read the data returned from the AC97 register.
  579. * ACSDA = Status Data Register = 474h
  580. */
  581. result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
  582. __end:
  583. return result;
  584. }
  585. /*
  586. * PCM part
  587. */
  588. static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd)
  589. {
  590. cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
  591. cs4281_t *chip = snd_pcm_substream_chip(substream);
  592. spin_lock(&chip->reg_lock);
  593. switch (cmd) {
  594. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  595. dma->valDCR |= BA0_DCR_MSK;
  596. dma->valFCR |= BA0_FCR_FEN;
  597. break;
  598. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  599. dma->valDCR &= ~BA0_DCR_MSK;
  600. dma->valFCR &= ~BA0_FCR_FEN;
  601. break;
  602. case SNDRV_PCM_TRIGGER_START:
  603. case SNDRV_PCM_TRIGGER_RESUME:
  604. snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
  605. dma->valDMR |= BA0_DMR_DMA;
  606. dma->valDCR &= ~BA0_DCR_MSK;
  607. dma->valFCR |= BA0_FCR_FEN;
  608. break;
  609. case SNDRV_PCM_TRIGGER_STOP:
  610. case SNDRV_PCM_TRIGGER_SUSPEND:
  611. dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
  612. dma->valDCR |= BA0_DCR_MSK;
  613. dma->valFCR &= ~BA0_FCR_FEN;
  614. /* Leave wave playback FIFO enabled for FM */
  615. if (dma->regFCR != BA0_FCR0)
  616. dma->valFCR &= ~BA0_FCR_FEN;
  617. break;
  618. default:
  619. spin_unlock(&chip->reg_lock);
  620. return -EINVAL;
  621. }
  622. snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
  623. snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
  624. snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
  625. spin_unlock(&chip->reg_lock);
  626. return 0;
  627. }
  628. static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
  629. {
  630. unsigned int val = ~0;
  631. if (real_rate)
  632. *real_rate = rate;
  633. /* special "hardcoded" rates */
  634. switch (rate) {
  635. case 8000: return 5;
  636. case 11025: return 4;
  637. case 16000: return 3;
  638. case 22050: return 2;
  639. case 44100: return 1;
  640. case 48000: return 0;
  641. default:
  642. goto __variable;
  643. }
  644. __variable:
  645. val = 1536000 / rate;
  646. if (real_rate)
  647. *real_rate = 1536000 / val;
  648. return val;
  649. }
  650. static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src)
  651. {
  652. int rec_mono;
  653. dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
  654. (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
  655. if (runtime->channels == 1)
  656. dma->valDMR |= BA0_DMR_MONO;
  657. if (snd_pcm_format_unsigned(runtime->format) > 0)
  658. dma->valDMR |= BA0_DMR_USIGN;
  659. if (snd_pcm_format_big_endian(runtime->format) > 0)
  660. dma->valDMR |= BA0_DMR_BEND;
  661. switch (snd_pcm_format_width(runtime->format)) {
  662. case 8: dma->valDMR |= BA0_DMR_SIZE8;
  663. if (runtime->channels == 1)
  664. dma->valDMR |= BA0_DMR_SWAPC;
  665. break;
  666. case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
  667. }
  668. dma->frag = 0; /* for workaround */
  669. dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
  670. if (runtime->buffer_size != runtime->period_size)
  671. dma->valDCR |= BA0_DCR_HTCIE;
  672. /* Initialize DMA */
  673. snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
  674. snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
  675. rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
  676. snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
  677. (chip->src_right_play_slot << 8) |
  678. (chip->src_left_rec_slot << 16) |
  679. ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
  680. if (!src)
  681. goto __skip_src;
  682. if (!capture) {
  683. if (dma->left_slot == chip->src_left_play_slot) {
  684. unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
  685. snd_assert(dma->right_slot == chip->src_right_play_slot, );
  686. snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
  687. }
  688. } else {
  689. if (dma->left_slot == chip->src_left_rec_slot) {
  690. unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
  691. snd_assert(dma->right_slot == chip->src_right_rec_slot, );
  692. snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
  693. }
  694. }
  695. __skip_src:
  696. /* Deactivate wave playback FIFO before changing slot assignments */
  697. if (dma->regFCR == BA0_FCR0)
  698. snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
  699. /* Initialize FIFO */
  700. dma->valFCR = BA0_FCR_LS(dma->left_slot) |
  701. BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
  702. BA0_FCR_SZ(CS4281_FIFO_SIZE) |
  703. BA0_FCR_OF(dma->fifo_offset);
  704. snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
  705. /* Activate FIFO again for FM playback */
  706. if (dma->regFCR == BA0_FCR0)
  707. snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
  708. /* Clear FIFO Status and Interrupt Control Register */
  709. snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
  710. }
  711. static int snd_cs4281_hw_params(snd_pcm_substream_t * substream,
  712. snd_pcm_hw_params_t * hw_params)
  713. {
  714. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  715. }
  716. static int snd_cs4281_hw_free(snd_pcm_substream_t * substream)
  717. {
  718. return snd_pcm_lib_free_pages(substream);
  719. }
  720. static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream)
  721. {
  722. snd_pcm_runtime_t *runtime = substream->runtime;
  723. cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
  724. cs4281_t *chip = snd_pcm_substream_chip(substream);
  725. spin_lock_irq(&chip->reg_lock);
  726. snd_cs4281_mode(chip, dma, runtime, 0, 1);
  727. spin_unlock_irq(&chip->reg_lock);
  728. return 0;
  729. }
  730. static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream)
  731. {
  732. snd_pcm_runtime_t *runtime = substream->runtime;
  733. cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
  734. cs4281_t *chip = snd_pcm_substream_chip(substream);
  735. spin_lock_irq(&chip->reg_lock);
  736. snd_cs4281_mode(chip, dma, runtime, 1, 1);
  737. spin_unlock_irq(&chip->reg_lock);
  738. return 0;
  739. }
  740. static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream)
  741. {
  742. snd_pcm_runtime_t *runtime = substream->runtime;
  743. cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
  744. cs4281_t *chip = snd_pcm_substream_chip(substream);
  745. // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
  746. return runtime->buffer_size -
  747. snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
  748. }
  749. static snd_pcm_hardware_t snd_cs4281_playback =
  750. {
  751. .info = (SNDRV_PCM_INFO_MMAP |
  752. SNDRV_PCM_INFO_INTERLEAVED |
  753. SNDRV_PCM_INFO_MMAP_VALID |
  754. SNDRV_PCM_INFO_PAUSE |
  755. SNDRV_PCM_INFO_RESUME |
  756. SNDRV_PCM_INFO_SYNC_START),
  757. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
  758. SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
  759. SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
  760. SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
  761. SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
  762. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  763. .rate_min = 4000,
  764. .rate_max = 48000,
  765. .channels_min = 1,
  766. .channels_max = 2,
  767. .buffer_bytes_max = (512*1024),
  768. .period_bytes_min = 64,
  769. .period_bytes_max = (512*1024),
  770. .periods_min = 1,
  771. .periods_max = 2,
  772. .fifo_size = CS4281_FIFO_SIZE,
  773. };
  774. static snd_pcm_hardware_t snd_cs4281_capture =
  775. {
  776. .info = (SNDRV_PCM_INFO_MMAP |
  777. SNDRV_PCM_INFO_INTERLEAVED |
  778. SNDRV_PCM_INFO_MMAP_VALID |
  779. SNDRV_PCM_INFO_PAUSE |
  780. SNDRV_PCM_INFO_RESUME |
  781. SNDRV_PCM_INFO_SYNC_START),
  782. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
  783. SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
  784. SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
  785. SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
  786. SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
  787. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  788. .rate_min = 4000,
  789. .rate_max = 48000,
  790. .channels_min = 1,
  791. .channels_max = 2,
  792. .buffer_bytes_max = (512*1024),
  793. .period_bytes_min = 64,
  794. .period_bytes_max = (512*1024),
  795. .periods_min = 1,
  796. .periods_max = 2,
  797. .fifo_size = CS4281_FIFO_SIZE,
  798. };
  799. static int snd_cs4281_playback_open(snd_pcm_substream_t * substream)
  800. {
  801. cs4281_t *chip = snd_pcm_substream_chip(substream);
  802. snd_pcm_runtime_t *runtime = substream->runtime;
  803. cs4281_dma_t *dma;
  804. dma = &chip->dma[0];
  805. dma->substream = substream;
  806. dma->left_slot = 0;
  807. dma->right_slot = 1;
  808. runtime->private_data = dma;
  809. runtime->hw = snd_cs4281_playback;
  810. snd_pcm_set_sync(substream);
  811. /* should be detected from the AC'97 layer, but it seems
  812. that although CS4297A rev B reports 18-bit ADC resolution,
  813. samples are 20-bit */
  814. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
  815. return 0;
  816. }
  817. static int snd_cs4281_capture_open(snd_pcm_substream_t * substream)
  818. {
  819. cs4281_t *chip = snd_pcm_substream_chip(substream);
  820. snd_pcm_runtime_t *runtime = substream->runtime;
  821. cs4281_dma_t *dma;
  822. dma = &chip->dma[1];
  823. dma->substream = substream;
  824. dma->left_slot = 10;
  825. dma->right_slot = 11;
  826. runtime->private_data = dma;
  827. runtime->hw = snd_cs4281_capture;
  828. snd_pcm_set_sync(substream);
  829. /* should be detected from the AC'97 layer, but it seems
  830. that although CS4297A rev B reports 18-bit ADC resolution,
  831. samples are 20-bit */
  832. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
  833. return 0;
  834. }
  835. static int snd_cs4281_playback_close(snd_pcm_substream_t * substream)
  836. {
  837. cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
  838. dma->substream = NULL;
  839. return 0;
  840. }
  841. static int snd_cs4281_capture_close(snd_pcm_substream_t * substream)
  842. {
  843. cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
  844. dma->substream = NULL;
  845. return 0;
  846. }
  847. static snd_pcm_ops_t snd_cs4281_playback_ops = {
  848. .open = snd_cs4281_playback_open,
  849. .close = snd_cs4281_playback_close,
  850. .ioctl = snd_pcm_lib_ioctl,
  851. .hw_params = snd_cs4281_hw_params,
  852. .hw_free = snd_cs4281_hw_free,
  853. .prepare = snd_cs4281_playback_prepare,
  854. .trigger = snd_cs4281_trigger,
  855. .pointer = snd_cs4281_pointer,
  856. };
  857. static snd_pcm_ops_t snd_cs4281_capture_ops = {
  858. .open = snd_cs4281_capture_open,
  859. .close = snd_cs4281_capture_close,
  860. .ioctl = snd_pcm_lib_ioctl,
  861. .hw_params = snd_cs4281_hw_params,
  862. .hw_free = snd_cs4281_hw_free,
  863. .prepare = snd_cs4281_capture_prepare,
  864. .trigger = snd_cs4281_trigger,
  865. .pointer = snd_cs4281_pointer,
  866. };
  867. static void snd_cs4281_pcm_free(snd_pcm_t *pcm)
  868. {
  869. cs4281_t *chip = pcm->private_data;
  870. chip->pcm = NULL;
  871. snd_pcm_lib_preallocate_free_for_all(pcm);
  872. }
  873. static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm)
  874. {
  875. snd_pcm_t *pcm;
  876. int err;
  877. if (rpcm)
  878. *rpcm = NULL;
  879. err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
  880. if (err < 0)
  881. return err;
  882. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
  883. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
  884. pcm->private_data = chip;
  885. pcm->private_free = snd_cs4281_pcm_free;
  886. pcm->info_flags = 0;
  887. strcpy(pcm->name, "CS4281");
  888. chip->pcm = pcm;
  889. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  890. snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
  891. if (rpcm)
  892. *rpcm = pcm;
  893. return 0;
  894. }
  895. /*
  896. * Mixer section
  897. */
  898. #define CS_VOL_MASK 0x1f
  899. static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
  900. {
  901. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  902. uinfo->count = 2;
  903. uinfo->value.integer.min = 0;
  904. uinfo->value.integer.max = CS_VOL_MASK;
  905. return 0;
  906. }
  907. static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  908. {
  909. cs4281_t *chip = snd_kcontrol_chip(kcontrol);
  910. int regL = (kcontrol->private_value >> 16) & 0xffff;
  911. int regR = kcontrol->private_value & 0xffff;
  912. int volL, volR;
  913. volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
  914. volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
  915. ucontrol->value.integer.value[0] = volL;
  916. ucontrol->value.integer.value[1] = volR;
  917. return 0;
  918. }
  919. static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  920. {
  921. cs4281_t *chip = snd_kcontrol_chip(kcontrol);
  922. int change = 0;
  923. int regL = (kcontrol->private_value >> 16) & 0xffff;
  924. int regR = kcontrol->private_value & 0xffff;
  925. int volL, volR;
  926. volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
  927. volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
  928. if (ucontrol->value.integer.value[0] != volL) {
  929. volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
  930. snd_cs4281_pokeBA0(chip, regL, volL);
  931. change = 1;
  932. }
  933. if (ucontrol->value.integer.value[0] != volL) {
  934. volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
  935. snd_cs4281_pokeBA0(chip, regR, volR);
  936. change = 1;
  937. }
  938. return change;
  939. }
  940. static snd_kcontrol_new_t snd_cs4281_fm_vol =
  941. {
  942. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  943. .name = "Synth Playback Volume",
  944. .info = snd_cs4281_info_volume,
  945. .get = snd_cs4281_get_volume,
  946. .put = snd_cs4281_put_volume,
  947. .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
  948. };
  949. static snd_kcontrol_new_t snd_cs4281_pcm_vol =
  950. {
  951. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  952. .name = "PCM Stream Playback Volume",
  953. .info = snd_cs4281_info_volume,
  954. .get = snd_cs4281_get_volume,
  955. .put = snd_cs4281_put_volume,
  956. .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
  957. };
  958. static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus)
  959. {
  960. cs4281_t *chip = bus->private_data;
  961. chip->ac97_bus = NULL;
  962. }
  963. static void snd_cs4281_mixer_free_ac97(ac97_t *ac97)
  964. {
  965. cs4281_t *chip = ac97->private_data;
  966. if (ac97->num)
  967. chip->ac97_secondary = NULL;
  968. else
  969. chip->ac97 = NULL;
  970. }
  971. static int __devinit snd_cs4281_mixer(cs4281_t * chip)
  972. {
  973. snd_card_t *card = chip->card;
  974. ac97_template_t ac97;
  975. int err;
  976. static ac97_bus_ops_t ops = {
  977. .write = snd_cs4281_ac97_write,
  978. .read = snd_cs4281_ac97_read,
  979. };
  980. if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  981. return err;
  982. chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
  983. memset(&ac97, 0, sizeof(ac97));
  984. ac97.private_data = chip;
  985. ac97.private_free = snd_cs4281_mixer_free_ac97;
  986. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  987. return err;
  988. if (chip->dual_codec) {
  989. ac97.num = 1;
  990. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
  991. return err;
  992. }
  993. if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
  994. return err;
  995. if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
  996. return err;
  997. return 0;
  998. }
  999. /*
  1000. * proc interface
  1001. */
  1002. static void snd_cs4281_proc_read(snd_info_entry_t *entry,
  1003. snd_info_buffer_t * buffer)
  1004. {
  1005. cs4281_t *chip = entry->private_data;
  1006. snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
  1007. snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
  1008. snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
  1009. }
  1010. static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data,
  1011. struct file *file, char __user *buf,
  1012. unsigned long count, unsigned long pos)
  1013. {
  1014. long size;
  1015. cs4281_t *chip = entry->private_data;
  1016. size = count;
  1017. if (pos + size > CS4281_BA0_SIZE)
  1018. size = (long)CS4281_BA0_SIZE - pos;
  1019. if (size > 0) {
  1020. if (copy_to_user_fromio(buf, chip->ba0 + pos, size))
  1021. return -EFAULT;
  1022. }
  1023. return size;
  1024. }
  1025. static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data,
  1026. struct file *file, char __user *buf,
  1027. unsigned long count, unsigned long pos)
  1028. {
  1029. long size;
  1030. cs4281_t *chip = entry->private_data;
  1031. size = count;
  1032. if (pos + size > CS4281_BA1_SIZE)
  1033. size = (long)CS4281_BA1_SIZE - pos;
  1034. if (size > 0) {
  1035. if (copy_to_user_fromio(buf, chip->ba1 + pos, size))
  1036. return -EFAULT;
  1037. }
  1038. return size;
  1039. }
  1040. static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
  1041. .read = snd_cs4281_BA0_read,
  1042. };
  1043. static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
  1044. .read = snd_cs4281_BA1_read,
  1045. };
  1046. static void __devinit snd_cs4281_proc_init(cs4281_t * chip)
  1047. {
  1048. snd_info_entry_t *entry;
  1049. if (! snd_card_proc_new(chip->card, "cs4281", &entry))
  1050. snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read);
  1051. if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
  1052. entry->content = SNDRV_INFO_CONTENT_DATA;
  1053. entry->private_data = chip;
  1054. entry->c.ops = &snd_cs4281_proc_ops_BA0;
  1055. entry->size = CS4281_BA0_SIZE;
  1056. }
  1057. if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
  1058. entry->content = SNDRV_INFO_CONTENT_DATA;
  1059. entry->private_data = chip;
  1060. entry->c.ops = &snd_cs4281_proc_ops_BA1;
  1061. entry->size = CS4281_BA1_SIZE;
  1062. }
  1063. }
  1064. /*
  1065. * joystick support
  1066. */
  1067. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  1068. static void snd_cs4281_gameport_trigger(struct gameport *gameport)
  1069. {
  1070. cs4281_t *chip = gameport_get_port_data(gameport);
  1071. snd_assert(chip, return);
  1072. snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
  1073. }
  1074. static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
  1075. {
  1076. cs4281_t *chip = gameport_get_port_data(gameport);
  1077. snd_assert(chip, return 0);
  1078. return snd_cs4281_peekBA0(chip, BA0_JSPT);
  1079. }
  1080. #ifdef COOKED_MODE
  1081. static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
  1082. {
  1083. cs4281_t *chip = gameport_get_port_data(gameport);
  1084. unsigned js1, js2, jst;
  1085. snd_assert(chip, return 0);
  1086. js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
  1087. js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
  1088. jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
  1089. *buttons = (~jst >> 4) & 0x0F;
  1090. axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
  1091. axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
  1092. axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
  1093. axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
  1094. for (jst = 0; jst < 4; ++jst)
  1095. if (axes[jst] == 0xFFFF) axes[jst] = -1;
  1096. return 0;
  1097. }
  1098. #else
  1099. #define snd_cs4281_gameport_cooked_read NULL
  1100. #endif
  1101. static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
  1102. {
  1103. switch (mode) {
  1104. #ifdef COOKED_MODE
  1105. case GAMEPORT_MODE_COOKED:
  1106. return 0;
  1107. #endif
  1108. case GAMEPORT_MODE_RAW:
  1109. return 0;
  1110. default:
  1111. return -1;
  1112. }
  1113. return 0;
  1114. }
  1115. static int __devinit snd_cs4281_create_gameport(cs4281_t *chip)
  1116. {
  1117. struct gameport *gp;
  1118. chip->gameport = gp = gameport_allocate_port();
  1119. if (!gp) {
  1120. printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n");
  1121. return -ENOMEM;
  1122. }
  1123. gameport_set_name(gp, "CS4281 Gameport");
  1124. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  1125. gameport_set_dev_parent(gp, &chip->pci->dev);
  1126. gp->open = snd_cs4281_gameport_open;
  1127. gp->read = snd_cs4281_gameport_read;
  1128. gp->trigger = snd_cs4281_gameport_trigger;
  1129. gp->cooked_read = snd_cs4281_gameport_cooked_read;
  1130. gameport_set_port_data(gp, chip);
  1131. snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
  1132. snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
  1133. gameport_register_port(gp);
  1134. return 0;
  1135. }
  1136. static void snd_cs4281_free_gameport(cs4281_t *chip)
  1137. {
  1138. if (chip->gameport) {
  1139. gameport_unregister_port(chip->gameport);
  1140. chip->gameport = NULL;
  1141. }
  1142. }
  1143. #else
  1144. static inline int snd_cs4281_create_gameport(cs4281_t *chip) { return -ENOSYS; }
  1145. static inline void snd_cs4281_free_gameport(cs4281_t *chip) { }
  1146. #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
  1147. static int snd_cs4281_free(cs4281_t *chip)
  1148. {
  1149. snd_cs4281_free_gameport(chip);
  1150. if (chip->irq >= 0)
  1151. synchronize_irq(chip->irq);
  1152. /* Mask interrupts */
  1153. snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
  1154. /* Stop the DLL Clock logic. */
  1155. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
  1156. /* Sound System Power Management - Turn Everything OFF */
  1157. snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
  1158. /* PCI interface - D3 state */
  1159. pci_set_power_state(chip->pci, 3);
  1160. if (chip->irq >= 0)
  1161. free_irq(chip->irq, (void *)chip);
  1162. if (chip->ba0)
  1163. iounmap(chip->ba0);
  1164. if (chip->ba1)
  1165. iounmap(chip->ba1);
  1166. pci_release_regions(chip->pci);
  1167. pci_disable_device(chip->pci);
  1168. kfree(chip);
  1169. return 0;
  1170. }
  1171. static int snd_cs4281_dev_free(snd_device_t *device)
  1172. {
  1173. cs4281_t *chip = device->device_data;
  1174. return snd_cs4281_free(chip);
  1175. }
  1176. static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */
  1177. #ifdef CONFIG_PM
  1178. static int cs4281_suspend(snd_card_t *card, pm_message_t state);
  1179. static int cs4281_resume(snd_card_t *card);
  1180. #endif
  1181. static int __devinit snd_cs4281_create(snd_card_t * card,
  1182. struct pci_dev *pci,
  1183. cs4281_t ** rchip,
  1184. int dual_codec)
  1185. {
  1186. cs4281_t *chip;
  1187. unsigned int tmp;
  1188. int err;
  1189. static snd_device_ops_t ops = {
  1190. .dev_free = snd_cs4281_dev_free,
  1191. };
  1192. *rchip = NULL;
  1193. if ((err = pci_enable_device(pci)) < 0)
  1194. return err;
  1195. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1196. if (chip == NULL) {
  1197. pci_disable_device(pci);
  1198. return -ENOMEM;
  1199. }
  1200. spin_lock_init(&chip->reg_lock);
  1201. chip->card = card;
  1202. chip->pci = pci;
  1203. chip->irq = -1;
  1204. pci_set_master(pci);
  1205. if (dual_codec < 0 || dual_codec > 3) {
  1206. snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
  1207. dual_codec = 0;
  1208. }
  1209. chip->dual_codec = dual_codec;
  1210. if ((err = pci_request_regions(pci, "CS4281")) < 0) {
  1211. kfree(chip);
  1212. pci_disable_device(pci);
  1213. return err;
  1214. }
  1215. chip->ba0_addr = pci_resource_start(pci, 0);
  1216. chip->ba1_addr = pci_resource_start(pci, 1);
  1217. if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) {
  1218. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1219. snd_cs4281_free(chip);
  1220. return -ENOMEM;
  1221. }
  1222. chip->irq = pci->irq;
  1223. chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0));
  1224. chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1));
  1225. if (!chip->ba0 || !chip->ba1) {
  1226. snd_cs4281_free(chip);
  1227. return -ENOMEM;
  1228. }
  1229. tmp = snd_cs4281_chip_init(chip);
  1230. if (tmp) {
  1231. snd_cs4281_free(chip);
  1232. return tmp;
  1233. }
  1234. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1235. snd_cs4281_free(chip);
  1236. return err;
  1237. }
  1238. snd_cs4281_proc_init(chip);
  1239. snd_card_set_pm_callback(card, cs4281_suspend, cs4281_resume, chip);
  1240. snd_card_set_dev(card, &pci->dev);
  1241. *rchip = chip;
  1242. return 0;
  1243. }
  1244. static int snd_cs4281_chip_init(cs4281_t *chip)
  1245. {
  1246. unsigned int tmp;
  1247. int timeout;
  1248. int retry_count = 2;
  1249. /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
  1250. tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
  1251. if (tmp & BA0_EPPMC_FPDN)
  1252. snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
  1253. __retry:
  1254. tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
  1255. if (tmp != BA0_CFLR_DEFAULT) {
  1256. snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
  1257. tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
  1258. if (tmp != BA0_CFLR_DEFAULT) {
  1259. snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
  1260. return -EIO;
  1261. }
  1262. }
  1263. /* Set the 'Configuration Write Protect' register
  1264. * to 4281h. Allows vendor-defined configuration
  1265. * space between 0e4h and 0ffh to be written. */
  1266. snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
  1267. if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
  1268. snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
  1269. return -EIO;
  1270. }
  1271. if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
  1272. snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
  1273. return -EIO;
  1274. }
  1275. /* Sound System Power Management */
  1276. snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
  1277. BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
  1278. BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
  1279. /* Serial Port Power Management */
  1280. /* Blast the clock control register to zero so that the
  1281. * PLL starts out in a known state, and blast the master serial
  1282. * port control register to zero so that the serial ports also
  1283. * start out in a known state. */
  1284. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
  1285. snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
  1286. /* Make ESYN go to zero to turn off
  1287. * the Sync pulse on the AC97 link. */
  1288. snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
  1289. udelay(50);
  1290. /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
  1291. * spec) and then drive it high. This is done for non AC97 modes since
  1292. * there might be logic external to the CS4281 that uses the ARST# line
  1293. * for a reset. */
  1294. snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
  1295. udelay(50);
  1296. snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
  1297. snd_cs4281_delay(50000);
  1298. if (chip->dual_codec)
  1299. snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
  1300. /*
  1301. * Set the serial port timing configuration.
  1302. */
  1303. snd_cs4281_pokeBA0(chip, BA0_SERMC,
  1304. (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
  1305. BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
  1306. /*
  1307. * Start the DLL Clock logic.
  1308. */
  1309. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
  1310. snd_cs4281_delay(50000);
  1311. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
  1312. /*
  1313. * Wait for the DLL ready signal from the clock logic.
  1314. */
  1315. timeout = HZ;
  1316. do {
  1317. /*
  1318. * Read the AC97 status register to see if we've seen a CODEC
  1319. * signal from the AC97 codec.
  1320. */
  1321. if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
  1322. goto __ok0;
  1323. snd_cs4281_delay_long();
  1324. } while (timeout-- > 0);
  1325. snd_printk(KERN_ERR "DLLRDY not seen\n");
  1326. return -EIO;
  1327. __ok0:
  1328. /*
  1329. * The first thing we do here is to enable sync generation. As soon
  1330. * as we start receiving bit clock, we'll start producing the SYNC
  1331. * signal.
  1332. */
  1333. snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
  1334. /*
  1335. * Wait for the codec ready signal from the AC97 codec.
  1336. */
  1337. timeout = HZ;
  1338. do {
  1339. /*
  1340. * Read the AC97 status register to see if we've seen a CODEC
  1341. * signal from the AC97 codec.
  1342. */
  1343. if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
  1344. goto __ok1;
  1345. snd_cs4281_delay_long();
  1346. } while (timeout-- > 0);
  1347. snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
  1348. return -EIO;
  1349. __ok1:
  1350. if (chip->dual_codec) {
  1351. timeout = HZ;
  1352. do {
  1353. if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
  1354. goto __codec2_ok;
  1355. snd_cs4281_delay_long();
  1356. } while (timeout-- > 0);
  1357. snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
  1358. chip->dual_codec = 0;
  1359. __codec2_ok: ;
  1360. }
  1361. /*
  1362. * Assert the valid frame signal so that we can start sending commands
  1363. * to the AC97 codec.
  1364. */
  1365. snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
  1366. /*
  1367. * Wait until we've sampled input slots 3 and 4 as valid, meaning that
  1368. * the codec is pumping ADC data across the AC-link.
  1369. */
  1370. timeout = HZ;
  1371. do {
  1372. /*
  1373. * Read the input slot valid register and see if input slots 3
  1374. * 4 are valid yet.
  1375. */
  1376. if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
  1377. goto __ok2;
  1378. snd_cs4281_delay_long();
  1379. } while (timeout-- > 0);
  1380. if (--retry_count > 0)
  1381. goto __retry;
  1382. snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
  1383. return -EIO;
  1384. __ok2:
  1385. /*
  1386. * Now, assert valid frame and the slot 3 and 4 valid bits. This will
  1387. * commense the transfer of digital audio data to the AC97 codec.
  1388. */
  1389. snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
  1390. /*
  1391. * Initialize DMA structures
  1392. */
  1393. for (tmp = 0; tmp < 4; tmp++) {
  1394. cs4281_dma_t *dma = &chip->dma[tmp];
  1395. dma->regDBA = BA0_DBA0 + (tmp * 0x10);
  1396. dma->regDCA = BA0_DCA0 + (tmp * 0x10);
  1397. dma->regDBC = BA0_DBC0 + (tmp * 0x10);
  1398. dma->regDCC = BA0_DCC0 + (tmp * 0x10);
  1399. dma->regDMR = BA0_DMR0 + (tmp * 8);
  1400. dma->regDCR = BA0_DCR0 + (tmp * 8);
  1401. dma->regHDSR = BA0_HDSR0 + (tmp * 4);
  1402. dma->regFCR = BA0_FCR0 + (tmp * 4);
  1403. dma->regFSIC = BA0_FSIC0 + (tmp * 4);
  1404. dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
  1405. snd_cs4281_pokeBA0(chip, dma->regFCR,
  1406. BA0_FCR_LS(31) |
  1407. BA0_FCR_RS(31) |
  1408. BA0_FCR_SZ(CS4281_FIFO_SIZE) |
  1409. BA0_FCR_OF(dma->fifo_offset));
  1410. }
  1411. chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
  1412. chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
  1413. chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
  1414. chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
  1415. /* Activate wave playback FIFO for FM playback */
  1416. chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
  1417. BA0_FCR_RS(1) |
  1418. BA0_FCR_SZ(CS4281_FIFO_SIZE) |
  1419. BA0_FCR_OF(chip->dma[0].fifo_offset);
  1420. snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
  1421. snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
  1422. (chip->src_right_play_slot << 8) |
  1423. (chip->src_left_rec_slot << 16) |
  1424. (chip->src_right_rec_slot << 24));
  1425. /* Initialize digital volume */
  1426. snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
  1427. snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
  1428. /* Enable IRQs */
  1429. snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
  1430. /* Unmask interrupts */
  1431. snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
  1432. BA0_HISR_MIDI |
  1433. BA0_HISR_DMAI |
  1434. BA0_HISR_DMA(0) |
  1435. BA0_HISR_DMA(1) |
  1436. BA0_HISR_DMA(2) |
  1437. BA0_HISR_DMA(3)));
  1438. synchronize_irq(chip->irq);
  1439. return 0;
  1440. }
  1441. /*
  1442. * MIDI section
  1443. */
  1444. static void snd_cs4281_midi_reset(cs4281_t *chip)
  1445. {
  1446. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
  1447. udelay(100);
  1448. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1449. }
  1450. static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream)
  1451. {
  1452. cs4281_t *chip = substream->rmidi->private_data;
  1453. spin_lock_irq(&chip->reg_lock);
  1454. chip->midcr |= BA0_MIDCR_RXE;
  1455. chip->midi_input = substream;
  1456. if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
  1457. snd_cs4281_midi_reset(chip);
  1458. } else {
  1459. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1460. }
  1461. spin_unlock_irq(&chip->reg_lock);
  1462. return 0;
  1463. }
  1464. static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream)
  1465. {
  1466. cs4281_t *chip = substream->rmidi->private_data;
  1467. spin_lock_irq(&chip->reg_lock);
  1468. chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
  1469. chip->midi_input = NULL;
  1470. if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
  1471. snd_cs4281_midi_reset(chip);
  1472. } else {
  1473. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1474. }
  1475. chip->uartm &= ~CS4281_MODE_INPUT;
  1476. spin_unlock_irq(&chip->reg_lock);
  1477. return 0;
  1478. }
  1479. static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream)
  1480. {
  1481. cs4281_t *chip = substream->rmidi->private_data;
  1482. spin_lock_irq(&chip->reg_lock);
  1483. chip->uartm |= CS4281_MODE_OUTPUT;
  1484. chip->midcr |= BA0_MIDCR_TXE;
  1485. chip->midi_output = substream;
  1486. if (!(chip->uartm & CS4281_MODE_INPUT)) {
  1487. snd_cs4281_midi_reset(chip);
  1488. } else {
  1489. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1490. }
  1491. spin_unlock_irq(&chip->reg_lock);
  1492. return 0;
  1493. }
  1494. static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream)
  1495. {
  1496. cs4281_t *chip = substream->rmidi->private_data;
  1497. spin_lock_irq(&chip->reg_lock);
  1498. chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
  1499. chip->midi_output = NULL;
  1500. if (!(chip->uartm & CS4281_MODE_INPUT)) {
  1501. snd_cs4281_midi_reset(chip);
  1502. } else {
  1503. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1504. }
  1505. chip->uartm &= ~CS4281_MODE_OUTPUT;
  1506. spin_unlock_irq(&chip->reg_lock);
  1507. return 0;
  1508. }
  1509. static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
  1510. {
  1511. unsigned long flags;
  1512. cs4281_t *chip = substream->rmidi->private_data;
  1513. spin_lock_irqsave(&chip->reg_lock, flags);
  1514. if (up) {
  1515. if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
  1516. chip->midcr |= BA0_MIDCR_RIE;
  1517. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1518. }
  1519. } else {
  1520. if (chip->midcr & BA0_MIDCR_RIE) {
  1521. chip->midcr &= ~BA0_MIDCR_RIE;
  1522. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1523. }
  1524. }
  1525. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1526. }
  1527. static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
  1528. {
  1529. unsigned long flags;
  1530. cs4281_t *chip = substream->rmidi->private_data;
  1531. unsigned char byte;
  1532. spin_lock_irqsave(&chip->reg_lock, flags);
  1533. if (up) {
  1534. if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
  1535. chip->midcr |= BA0_MIDCR_TIE;
  1536. /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
  1537. while ((chip->midcr & BA0_MIDCR_TIE) &&
  1538. (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
  1539. if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
  1540. chip->midcr &= ~BA0_MIDCR_TIE;
  1541. } else {
  1542. snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
  1543. }
  1544. }
  1545. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1546. }
  1547. } else {
  1548. if (chip->midcr & BA0_MIDCR_TIE) {
  1549. chip->midcr &= ~BA0_MIDCR_TIE;
  1550. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1551. }
  1552. }
  1553. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1554. }
  1555. static snd_rawmidi_ops_t snd_cs4281_midi_output =
  1556. {
  1557. .open = snd_cs4281_midi_output_open,
  1558. .close = snd_cs4281_midi_output_close,
  1559. .trigger = snd_cs4281_midi_output_trigger,
  1560. };
  1561. static snd_rawmidi_ops_t snd_cs4281_midi_input =
  1562. {
  1563. .open = snd_cs4281_midi_input_open,
  1564. .close = snd_cs4281_midi_input_close,
  1565. .trigger = snd_cs4281_midi_input_trigger,
  1566. };
  1567. static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi)
  1568. {
  1569. snd_rawmidi_t *rmidi;
  1570. int err;
  1571. if (rrawmidi)
  1572. *rrawmidi = NULL;
  1573. if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
  1574. return err;
  1575. strcpy(rmidi->name, "CS4281");
  1576. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
  1577. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
  1578. rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
  1579. rmidi->private_data = chip;
  1580. chip->rmidi = rmidi;
  1581. if (rrawmidi)
  1582. *rrawmidi = rmidi;
  1583. return 0;
  1584. }
  1585. /*
  1586. * Interrupt handler
  1587. */
  1588. static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  1589. {
  1590. cs4281_t *chip = dev_id;
  1591. unsigned int status, dma, val;
  1592. cs4281_dma_t *cdma;
  1593. if (chip == NULL)
  1594. return IRQ_NONE;
  1595. status = snd_cs4281_peekBA0(chip, BA0_HISR);
  1596. if ((status & 0x7fffffff) == 0) {
  1597. snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
  1598. return IRQ_NONE;
  1599. }
  1600. if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
  1601. for (dma = 0; dma < 4; dma++)
  1602. if (status & BA0_HISR_DMA(dma)) {
  1603. cdma = &chip->dma[dma];
  1604. spin_lock(&chip->reg_lock);
  1605. /* ack DMA IRQ */
  1606. val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
  1607. /* workaround, sometimes CS4281 acknowledges */
  1608. /* end or middle transfer position twice */
  1609. cdma->frag++;
  1610. if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
  1611. cdma->frag--;
  1612. chip->spurious_dhtc_irq++;
  1613. spin_unlock(&chip->reg_lock);
  1614. continue;
  1615. }
  1616. if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
  1617. cdma->frag--;
  1618. chip->spurious_dtc_irq++;
  1619. spin_unlock(&chip->reg_lock);
  1620. continue;
  1621. }
  1622. spin_unlock(&chip->reg_lock);
  1623. snd_pcm_period_elapsed(cdma->substream);
  1624. }
  1625. }
  1626. if ((status & BA0_HISR_MIDI) && chip->rmidi) {
  1627. unsigned char c;
  1628. spin_lock(&chip->reg_lock);
  1629. while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
  1630. c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
  1631. if ((chip->midcr & BA0_MIDCR_RIE) == 0)
  1632. continue;
  1633. snd_rawmidi_receive(chip->midi_input, &c, 1);
  1634. }
  1635. while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
  1636. if ((chip->midcr & BA0_MIDCR_TIE) == 0)
  1637. break;
  1638. if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
  1639. chip->midcr &= ~BA0_MIDCR_TIE;
  1640. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1641. break;
  1642. }
  1643. snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
  1644. }
  1645. spin_unlock(&chip->reg_lock);
  1646. }
  1647. /* EOI to the PCI part... reenables interrupts */
  1648. snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
  1649. return IRQ_HANDLED;
  1650. }
  1651. /*
  1652. * OPL3 command
  1653. */
  1654. static void snd_cs4281_opl3_command(opl3_t * opl3, unsigned short cmd, unsigned char val)
  1655. {
  1656. unsigned long flags;
  1657. cs4281_t *chip = opl3->private_data;
  1658. void __iomem *port;
  1659. if (cmd & OPL3_RIGHT)
  1660. port = chip->ba0 + BA0_B1AP; /* right port */
  1661. else
  1662. port = chip->ba0 + BA0_B0AP; /* left port */
  1663. spin_lock_irqsave(&opl3->reg_lock, flags);
  1664. writel((unsigned int)cmd, port);
  1665. udelay(10);
  1666. writel((unsigned int)val, port + 4);
  1667. udelay(30);
  1668. spin_unlock_irqrestore(&opl3->reg_lock, flags);
  1669. }
  1670. static int __devinit snd_cs4281_probe(struct pci_dev *pci,
  1671. const struct pci_device_id *pci_id)
  1672. {
  1673. static int dev;
  1674. snd_card_t *card;
  1675. cs4281_t *chip;
  1676. opl3_t *opl3;
  1677. int err;
  1678. if (dev >= SNDRV_CARDS)
  1679. return -ENODEV;
  1680. if (!enable[dev]) {
  1681. dev++;
  1682. return -ENOENT;
  1683. }
  1684. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
  1685. if (card == NULL)
  1686. return -ENOMEM;
  1687. if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
  1688. snd_card_free(card);
  1689. return err;
  1690. }
  1691. if ((err = snd_cs4281_mixer(chip)) < 0) {
  1692. snd_card_free(card);
  1693. return err;
  1694. }
  1695. if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
  1696. snd_card_free(card);
  1697. return err;
  1698. }
  1699. if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
  1700. snd_card_free(card);
  1701. return err;
  1702. }
  1703. if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
  1704. snd_card_free(card);
  1705. return err;
  1706. }
  1707. opl3->private_data = chip;
  1708. opl3->command = snd_cs4281_opl3_command;
  1709. snd_opl3_init(opl3);
  1710. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1711. snd_card_free(card);
  1712. return err;
  1713. }
  1714. snd_cs4281_create_gameport(chip);
  1715. strcpy(card->driver, "CS4281");
  1716. strcpy(card->shortname, "Cirrus Logic CS4281");
  1717. sprintf(card->longname, "%s at 0x%lx, irq %d",
  1718. card->shortname,
  1719. chip->ba0_addr,
  1720. chip->irq);
  1721. if ((err = snd_card_register(card)) < 0) {
  1722. snd_card_free(card);
  1723. return err;
  1724. }
  1725. pci_set_drvdata(pci, card);
  1726. dev++;
  1727. return 0;
  1728. }
  1729. static void __devexit snd_cs4281_remove(struct pci_dev *pci)
  1730. {
  1731. snd_card_free(pci_get_drvdata(pci));
  1732. pci_set_drvdata(pci, NULL);
  1733. }
  1734. /*
  1735. * Power Management
  1736. */
  1737. #ifdef CONFIG_PM
  1738. static int saved_regs[SUSPEND_REGISTERS] = {
  1739. BA0_JSCTL,
  1740. BA0_GPIOR,
  1741. BA0_SSCR,
  1742. BA0_MIDCR,
  1743. BA0_SRCSA,
  1744. BA0_PASR,
  1745. BA0_CASR,
  1746. BA0_DACSR,
  1747. BA0_ADCSR,
  1748. BA0_FMLVC,
  1749. BA0_FMRVC,
  1750. BA0_PPLVC,
  1751. BA0_PPRVC,
  1752. };
  1753. #define CLKCR1_CKRA 0x00010000L
  1754. static int cs4281_suspend(snd_card_t *card, pm_message_t state)
  1755. {
  1756. cs4281_t *chip = card->pm_private_data;
  1757. u32 ulCLK;
  1758. unsigned int i;
  1759. snd_pcm_suspend_all(chip->pcm);
  1760. if (chip->ac97)
  1761. snd_ac97_suspend(chip->ac97);
  1762. if (chip->ac97_secondary)
  1763. snd_ac97_suspend(chip->ac97_secondary);
  1764. ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
  1765. ulCLK |= CLKCR1_CKRA;
  1766. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
  1767. /* Disable interrupts. */
  1768. snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
  1769. /* remember the status registers */
  1770. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  1771. if (saved_regs[i])
  1772. chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
  1773. /* Turn off the serial ports. */
  1774. snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
  1775. /* Power off FM, Joystick, AC link, */
  1776. snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
  1777. /* DLL off. */
  1778. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
  1779. /* AC link off. */
  1780. snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
  1781. ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
  1782. ulCLK &= ~CLKCR1_CKRA;
  1783. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
  1784. pci_disable_device(chip->pci);
  1785. return 0;
  1786. }
  1787. static int cs4281_resume(snd_card_t *card)
  1788. {
  1789. cs4281_t *chip = card->pm_private_data;
  1790. unsigned int i;
  1791. u32 ulCLK;
  1792. pci_enable_device(chip->pci);
  1793. pci_set_master(chip->pci);
  1794. ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
  1795. ulCLK |= CLKCR1_CKRA;
  1796. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
  1797. snd_cs4281_chip_init(chip);
  1798. /* restore the status registers */
  1799. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  1800. if (saved_regs[i])
  1801. snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
  1802. if (chip->ac97)
  1803. snd_ac97_resume(chip->ac97);
  1804. if (chip->ac97_secondary)
  1805. snd_ac97_resume(chip->ac97_secondary);
  1806. ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
  1807. ulCLK &= ~CLKCR1_CKRA;
  1808. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
  1809. return 0;
  1810. }
  1811. #endif /* CONFIG_PM */
  1812. static struct pci_driver driver = {
  1813. .name = "CS4281",
  1814. .id_table = snd_cs4281_ids,
  1815. .probe = snd_cs4281_probe,
  1816. .remove = __devexit_p(snd_cs4281_remove),
  1817. SND_PCI_PM_CALLBACKS
  1818. };
  1819. static int __init alsa_card_cs4281_init(void)
  1820. {
  1821. return pci_register_driver(&driver);
  1822. }
  1823. static void __exit alsa_card_cs4281_exit(void)
  1824. {
  1825. pci_unregister_driver(&driver);
  1826. }
  1827. module_init(alsa_card_cs4281_init)
  1828. module_exit(alsa_card_cs4281_exit)