aaci.c 21 KB

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  1. /*
  2. * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
  3. *
  4. * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Documentation: ARM DDI 0173B
  11. */
  12. #include <linux/module.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/ioport.h>
  16. #include <linux/device.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/err.h>
  20. #include <asm/io.h>
  21. #include <asm/irq.h>
  22. #include <asm/sizes.h>
  23. #include <asm/hardware/amba.h>
  24. #include <sound/driver.h>
  25. #include <sound/core.h>
  26. #include <sound/initval.h>
  27. #include <sound/ac97_codec.h>
  28. #include <sound/pcm.h>
  29. #include <sound/pcm_params.h>
  30. #include "aaci.h"
  31. #include "devdma.h"
  32. #define DRIVER_NAME "aaci-pl041"
  33. /*
  34. * PM support is not complete. Turn it off.
  35. */
  36. #undef CONFIG_PM
  37. static void aaci_ac97_select_codec(struct aaci *aaci, ac97_t *ac97)
  38. {
  39. u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
  40. /*
  41. * Ensure that the slot 1/2 RX registers are empty.
  42. */
  43. v = readl(aaci->base + AACI_SLFR);
  44. if (v & SLFR_2RXV)
  45. readl(aaci->base + AACI_SL2RX);
  46. if (v & SLFR_1RXV)
  47. readl(aaci->base + AACI_SL1RX);
  48. writel(maincr, aaci->base + AACI_MAINCR);
  49. }
  50. /*
  51. * P29:
  52. * The recommended use of programming the external codec through slot 1
  53. * and slot 2 data is to use the channels during setup routines and the
  54. * slot register at any other time. The data written into slot 1, slot 2
  55. * and slot 12 registers is transmitted only when their corresponding
  56. * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
  57. * register.
  58. */
  59. static void aaci_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
  60. {
  61. struct aaci *aaci = ac97->private_data;
  62. u32 v;
  63. if (ac97->num >= 4)
  64. return;
  65. down(&aaci->ac97_sem);
  66. aaci_ac97_select_codec(aaci, ac97);
  67. /*
  68. * P54: You must ensure that AACI_SL2TX is always written
  69. * to, if required, before data is written to AACI_SL1TX.
  70. */
  71. writel(val << 4, aaci->base + AACI_SL2TX);
  72. writel(reg << 12, aaci->base + AACI_SL1TX);
  73. /*
  74. * Wait for the transmission of both slots to complete.
  75. */
  76. do {
  77. v = readl(aaci->base + AACI_SLFR);
  78. } while (v & (SLFR_1TXB|SLFR_2TXB));
  79. up(&aaci->ac97_sem);
  80. }
  81. /*
  82. * Read an AC'97 register.
  83. */
  84. static unsigned short aaci_ac97_read(ac97_t *ac97, unsigned short reg)
  85. {
  86. struct aaci *aaci = ac97->private_data;
  87. u32 v;
  88. if (ac97->num >= 4)
  89. return ~0;
  90. down(&aaci->ac97_sem);
  91. aaci_ac97_select_codec(aaci, ac97);
  92. /*
  93. * Write the register address to slot 1.
  94. */
  95. writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
  96. /*
  97. * Wait for the transmission to complete.
  98. */
  99. do {
  100. v = readl(aaci->base + AACI_SLFR);
  101. } while (v & SLFR_1TXB);
  102. /*
  103. * Give the AC'97 codec more than enough time
  104. * to respond. (42us = ~2 frames at 48kHz.)
  105. */
  106. udelay(42);
  107. /*
  108. * Wait for slot 2 to indicate data.
  109. */
  110. do {
  111. cond_resched();
  112. v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
  113. } while (v != (SLFR_1RXV|SLFR_2RXV));
  114. v = readl(aaci->base + AACI_SL1RX) >> 12;
  115. if (v == reg) {
  116. v = readl(aaci->base + AACI_SL2RX) >> 4;
  117. } else {
  118. dev_err(&aaci->dev->dev,
  119. "wrong ac97 register read back (%x != %x)\n",
  120. v, reg);
  121. v = ~0;
  122. }
  123. up(&aaci->ac97_sem);
  124. return v;
  125. }
  126. static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun)
  127. {
  128. u32 val;
  129. int timeout = 5000;
  130. do {
  131. val = readl(aacirun->base + AACI_SR);
  132. } while (val & (SR_TXB|SR_RXB) && timeout--);
  133. }
  134. /*
  135. * Interrupt support.
  136. */
  137. static void aaci_fifo_irq(struct aaci *aaci, u32 mask)
  138. {
  139. if (mask & ISR_URINTR) {
  140. writel(ICLR_TXUEC1, aaci->base + AACI_INTCLR);
  141. }
  142. if (mask & ISR_TXINTR) {
  143. struct aaci_runtime *aacirun = &aaci->playback;
  144. void *ptr;
  145. if (!aacirun->substream || !aacirun->start) {
  146. dev_warn(&aaci->dev->dev, "TX interrupt???");
  147. writel(0, aacirun->base + AACI_IE);
  148. return;
  149. }
  150. ptr = aacirun->ptr;
  151. do {
  152. unsigned int len = aacirun->fifosz;
  153. u32 val;
  154. if (aacirun->bytes <= 0) {
  155. aacirun->bytes += aacirun->period;
  156. aacirun->ptr = ptr;
  157. spin_unlock(&aaci->lock);
  158. snd_pcm_period_elapsed(aacirun->substream);
  159. spin_lock(&aaci->lock);
  160. }
  161. if (!(aacirun->cr & TXCR_TXEN))
  162. break;
  163. val = readl(aacirun->base + AACI_SR);
  164. if (!(val & SR_TXHE))
  165. break;
  166. if (!(val & SR_TXFE))
  167. len >>= 1;
  168. aacirun->bytes -= len;
  169. /* writing 16 bytes at a time */
  170. for ( ; len > 0; len -= 16) {
  171. asm(
  172. "ldmia %0!, {r0, r1, r2, r3}\n\t"
  173. "stmia %1, {r0, r1, r2, r3}"
  174. : "+r" (ptr)
  175. : "r" (aacirun->fifo)
  176. : "r0", "r1", "r2", "r3", "cc");
  177. if (ptr >= aacirun->end)
  178. ptr = aacirun->start;
  179. }
  180. } while (1);
  181. aacirun->ptr = ptr;
  182. }
  183. }
  184. static irqreturn_t aaci_irq(int irq, void *devid, struct pt_regs *regs)
  185. {
  186. struct aaci *aaci = devid;
  187. u32 mask;
  188. int i;
  189. spin_lock(&aaci->lock);
  190. mask = readl(aaci->base + AACI_ALLINTS);
  191. if (mask) {
  192. u32 m = mask;
  193. for (i = 0; i < 4; i++, m >>= 7) {
  194. if (m & 0x7f) {
  195. aaci_fifo_irq(aaci, m);
  196. }
  197. }
  198. }
  199. spin_unlock(&aaci->lock);
  200. return mask ? IRQ_HANDLED : IRQ_NONE;
  201. }
  202. /*
  203. * ALSA support.
  204. */
  205. struct aaci_stream {
  206. unsigned char codec_idx;
  207. unsigned char rate_idx;
  208. };
  209. static struct aaci_stream aaci_streams[] = {
  210. [ACSTREAM_FRONT] = {
  211. .codec_idx = 0,
  212. .rate_idx = AC97_RATES_FRONT_DAC,
  213. },
  214. [ACSTREAM_SURROUND] = {
  215. .codec_idx = 0,
  216. .rate_idx = AC97_RATES_SURR_DAC,
  217. },
  218. [ACSTREAM_LFE] = {
  219. .codec_idx = 0,
  220. .rate_idx = AC97_RATES_LFE_DAC,
  221. },
  222. };
  223. static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid)
  224. {
  225. struct aaci_stream *s = aaci_streams + streamid;
  226. return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx];
  227. }
  228. static unsigned int rate_list[] = {
  229. 5512, 8000, 11025, 16000, 22050, 32000, 44100,
  230. 48000, 64000, 88200, 96000, 176400, 192000
  231. };
  232. /*
  233. * Double-rate rule: we can support double rate iff channels == 2
  234. * (unimplemented)
  235. */
  236. static int
  237. aaci_rule_rate_by_channels(snd_pcm_hw_params_t *p, snd_pcm_hw_rule_t *rule)
  238. {
  239. struct aaci *aaci = rule->private;
  240. unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512;
  241. snd_interval_t *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS);
  242. switch (c->max) {
  243. case 6:
  244. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE);
  245. case 4:
  246. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND);
  247. case 2:
  248. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT);
  249. }
  250. return snd_interval_list(hw_param_interval(p, rule->var),
  251. ARRAY_SIZE(rate_list), rate_list,
  252. rate_mask);
  253. }
  254. static snd_pcm_hardware_t aaci_hw_info = {
  255. .info = SNDRV_PCM_INFO_MMAP |
  256. SNDRV_PCM_INFO_MMAP_VALID |
  257. SNDRV_PCM_INFO_INTERLEAVED |
  258. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  259. SNDRV_PCM_INFO_RESUME,
  260. /*
  261. * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
  262. * words. It also doesn't support 12-bit at all.
  263. */
  264. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  265. /* should this be continuous or knot? */
  266. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  267. .rate_max = 48000,
  268. .rate_min = 4000,
  269. .channels_min = 2,
  270. .channels_max = 6,
  271. .buffer_bytes_max = 64 * 1024,
  272. .period_bytes_min = 256,
  273. .period_bytes_max = PAGE_SIZE,
  274. .periods_min = 4,
  275. .periods_max = PAGE_SIZE / 16,
  276. };
  277. static int aaci_pcm_open(struct aaci *aaci, snd_pcm_substream_t *substream,
  278. struct aaci_runtime *aacirun)
  279. {
  280. snd_pcm_runtime_t *runtime = substream->runtime;
  281. int ret;
  282. aacirun->substream = substream;
  283. runtime->private_data = aacirun;
  284. runtime->hw = aaci_hw_info;
  285. /*
  286. * FIXME: ALSA specifies fifo_size in bytes. If we're in normal
  287. * mode, each 32-bit word contains one sample. If we're in
  288. * compact mode, each 32-bit word contains two samples, effectively
  289. * halving the FIFO size. However, we don't know for sure which
  290. * we'll be using at this point. We set this to the lower limit.
  291. */
  292. runtime->hw.fifo_size = aaci->fifosize * 2;
  293. /*
  294. * Add rule describing hardware rate dependency
  295. * on the number of channels.
  296. */
  297. ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  298. aaci_rule_rate_by_channels, aaci,
  299. SNDRV_PCM_HW_PARAM_CHANNELS,
  300. SNDRV_PCM_HW_PARAM_RATE, -1);
  301. if (ret)
  302. goto out;
  303. ret = request_irq(aaci->dev->irq[0], aaci_irq, SA_SHIRQ|SA_INTERRUPT,
  304. DRIVER_NAME, aaci);
  305. if (ret)
  306. goto out;
  307. return 0;
  308. out:
  309. return ret;
  310. }
  311. /*
  312. * Common ALSA stuff
  313. */
  314. static int aaci_pcm_close(snd_pcm_substream_t *substream)
  315. {
  316. struct aaci *aaci = substream->private_data;
  317. struct aaci_runtime *aacirun = substream->runtime->private_data;
  318. WARN_ON(aacirun->cr & TXCR_TXEN);
  319. aacirun->substream = NULL;
  320. free_irq(aaci->dev->irq[0], aaci);
  321. return 0;
  322. }
  323. static int aaci_pcm_hw_free(snd_pcm_substream_t *substream)
  324. {
  325. struct aaci_runtime *aacirun = substream->runtime->private_data;
  326. /*
  327. * This must not be called with the device enabled.
  328. */
  329. WARN_ON(aacirun->cr & TXCR_TXEN);
  330. if (aacirun->pcm_open)
  331. snd_ac97_pcm_close(aacirun->pcm);
  332. aacirun->pcm_open = 0;
  333. /*
  334. * Clear out the DMA and any allocated buffers.
  335. */
  336. devdma_hw_free(NULL, substream);
  337. return 0;
  338. }
  339. static int aaci_pcm_hw_params(snd_pcm_substream_t *substream,
  340. struct aaci_runtime *aacirun,
  341. snd_pcm_hw_params_t *params)
  342. {
  343. int err;
  344. aaci_pcm_hw_free(substream);
  345. err = devdma_hw_alloc(NULL, substream,
  346. params_buffer_bytes(params));
  347. if (err < 0)
  348. goto out;
  349. err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
  350. params_channels(params),
  351. aacirun->pcm->r[0].slots);
  352. if (err)
  353. goto out;
  354. aacirun->pcm_open = 1;
  355. out:
  356. return err;
  357. }
  358. static int aaci_pcm_prepare(snd_pcm_substream_t *substream)
  359. {
  360. snd_pcm_runtime_t *runtime = substream->runtime;
  361. struct aaci_runtime *aacirun = runtime->private_data;
  362. aacirun->start = (void *)runtime->dma_area;
  363. aacirun->end = aacirun->start + runtime->dma_bytes;
  364. aacirun->ptr = aacirun->start;
  365. aacirun->period =
  366. aacirun->bytes = frames_to_bytes(runtime, runtime->period_size);
  367. return 0;
  368. }
  369. static snd_pcm_uframes_t aaci_pcm_pointer(snd_pcm_substream_t *substream)
  370. {
  371. snd_pcm_runtime_t *runtime = substream->runtime;
  372. struct aaci_runtime *aacirun = runtime->private_data;
  373. ssize_t bytes = aacirun->ptr - aacirun->start;
  374. return bytes_to_frames(runtime, bytes);
  375. }
  376. static int aaci_pcm_mmap(snd_pcm_substream_t *substream, struct vm_area_struct *vma)
  377. {
  378. return devdma_mmap(NULL, substream, vma);
  379. }
  380. /*
  381. * Playback specific ALSA stuff
  382. */
  383. static const u32 channels_to_txmask[] = {
  384. [2] = TXCR_TX3 | TXCR_TX4,
  385. [4] = TXCR_TX3 | TXCR_TX4 | TXCR_TX7 | TXCR_TX8,
  386. [6] = TXCR_TX3 | TXCR_TX4 | TXCR_TX7 | TXCR_TX8 | TXCR_TX6 | TXCR_TX9,
  387. };
  388. /*
  389. * We can support two and four channel audio. Unfortunately
  390. * six channel audio requires a non-standard channel ordering:
  391. * 2 -> FL(3), FR(4)
  392. * 4 -> FL(3), FR(4), SL(7), SR(8)
  393. * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
  394. * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
  395. * This requires an ALSA configuration file to correct.
  396. */
  397. static unsigned int channel_list[] = { 2, 4, 6 };
  398. static int
  399. aaci_rule_channels(snd_pcm_hw_params_t *p, snd_pcm_hw_rule_t *rule)
  400. {
  401. struct aaci *aaci = rule->private;
  402. unsigned int chan_mask = 1 << 0, slots;
  403. /*
  404. * pcms[0] is the our 5.1 PCM instance.
  405. */
  406. slots = aaci->ac97_bus->pcms[0].r[0].slots;
  407. if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  408. chan_mask |= 1 << 1;
  409. if (slots & (1 << AC97_SLOT_LFE))
  410. chan_mask |= 1 << 2;
  411. }
  412. return snd_interval_list(hw_param_interval(p, rule->var),
  413. ARRAY_SIZE(channel_list), channel_list,
  414. chan_mask);
  415. }
  416. static int aaci_pcm_playback_open(snd_pcm_substream_t *substream)
  417. {
  418. struct aaci *aaci = substream->private_data;
  419. int ret;
  420. /*
  421. * Add rule describing channel dependency.
  422. */
  423. ret = snd_pcm_hw_rule_add(substream->runtime, 0,
  424. SNDRV_PCM_HW_PARAM_CHANNELS,
  425. aaci_rule_channels, aaci,
  426. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  427. if (ret)
  428. return ret;
  429. return aaci_pcm_open(aaci, substream, &aaci->playback);
  430. }
  431. static int aaci_pcm_playback_hw_params(snd_pcm_substream_t *substream,
  432. snd_pcm_hw_params_t *params)
  433. {
  434. struct aaci *aaci = substream->private_data;
  435. struct aaci_runtime *aacirun = substream->runtime->private_data;
  436. unsigned int channels = params_channels(params);
  437. int ret;
  438. WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
  439. !channels_to_txmask[channels]);
  440. ret = aaci_pcm_hw_params(substream, aacirun, params);
  441. /*
  442. * Enable FIFO, compact mode, 16 bits per sample.
  443. * FIXME: double rate slots?
  444. */
  445. if (ret >= 0) {
  446. aacirun->cr = TXCR_FEN | TXCR_COMPACT | TXCR_TSZ16;
  447. aacirun->cr |= channels_to_txmask[channels];
  448. aacirun->fifosz = aaci->fifosize * 4;
  449. if (aacirun->cr & TXCR_COMPACT)
  450. aacirun->fifosz >>= 1;
  451. }
  452. return ret;
  453. }
  454. static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
  455. {
  456. u32 ie;
  457. ie = readl(aacirun->base + AACI_IE);
  458. ie &= ~(IE_URIE|IE_TXIE);
  459. writel(ie, aacirun->base + AACI_IE);
  460. aacirun->cr &= ~TXCR_TXEN;
  461. aaci_chan_wait_ready(aacirun);
  462. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  463. }
  464. static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
  465. {
  466. u32 ie;
  467. aaci_chan_wait_ready(aacirun);
  468. aacirun->cr |= TXCR_TXEN;
  469. ie = readl(aacirun->base + AACI_IE);
  470. ie |= IE_URIE | IE_TXIE;
  471. writel(ie, aacirun->base + AACI_IE);
  472. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  473. }
  474. static int aaci_pcm_playback_trigger(snd_pcm_substream_t *substream, int cmd)
  475. {
  476. struct aaci *aaci = substream->private_data;
  477. struct aaci_runtime *aacirun = substream->runtime->private_data;
  478. unsigned long flags;
  479. int ret = 0;
  480. spin_lock_irqsave(&aaci->lock, flags);
  481. switch (cmd) {
  482. case SNDRV_PCM_TRIGGER_START:
  483. aaci_pcm_playback_start(aacirun);
  484. break;
  485. case SNDRV_PCM_TRIGGER_RESUME:
  486. aaci_pcm_playback_start(aacirun);
  487. break;
  488. case SNDRV_PCM_TRIGGER_STOP:
  489. aaci_pcm_playback_stop(aacirun);
  490. break;
  491. case SNDRV_PCM_TRIGGER_SUSPEND:
  492. aaci_pcm_playback_stop(aacirun);
  493. break;
  494. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  495. break;
  496. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  497. break;
  498. default:
  499. ret = -EINVAL;
  500. }
  501. spin_unlock_irqrestore(&aaci->lock, flags);
  502. return ret;
  503. }
  504. static snd_pcm_ops_t aaci_playback_ops = {
  505. .open = aaci_pcm_playback_open,
  506. .close = aaci_pcm_close,
  507. .ioctl = snd_pcm_lib_ioctl,
  508. .hw_params = aaci_pcm_playback_hw_params,
  509. .hw_free = aaci_pcm_hw_free,
  510. .prepare = aaci_pcm_prepare,
  511. .trigger = aaci_pcm_playback_trigger,
  512. .pointer = aaci_pcm_pointer,
  513. .mmap = aaci_pcm_mmap,
  514. };
  515. /*
  516. * Power Management.
  517. */
  518. #ifdef CONFIG_PM
  519. static int aaci_do_suspend(snd_card_t *card, unsigned int state)
  520. {
  521. struct aaci *aaci = card->private_data;
  522. if (aaci->card->power_state != SNDRV_CTL_POWER_D3cold) {
  523. snd_pcm_suspend_all(aaci->pcm);
  524. snd_power_change_state(aaci->card, SNDRV_CTL_POWER_D3cold);
  525. }
  526. return 0;
  527. }
  528. static int aaci_do_resume(snd_card_t *card, unsigned int state)
  529. {
  530. struct aaci *aaci = card->private_data;
  531. if (aaci->card->power_state != SNDRV_CTL_POWER_D0) {
  532. snd_power_change_state(aaci->card, SNDRV_CTL_POWER_D0);
  533. }
  534. return 0;
  535. }
  536. static int aaci_suspend(struct amba_device *dev, pm_message_t state)
  537. {
  538. snd_card_t *card = amba_get_drvdata(dev);
  539. return card ? aaci_do_suspend(card) : 0;
  540. }
  541. static int aaci_resume(struct amba_device *dev)
  542. {
  543. snd_card_t *card = amba_get_drvdata(dev);
  544. return card ? aaci_do_resume(card) : 0;
  545. }
  546. #else
  547. #define aaci_do_suspend NULL
  548. #define aaci_do_resume NULL
  549. #define aaci_suspend NULL
  550. #define aaci_resume NULL
  551. #endif
  552. static struct ac97_pcm ac97_defs[] __devinitdata = {
  553. [0] = { /* Front PCM */
  554. .exclusive = 1,
  555. .r = {
  556. [0] = {
  557. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  558. (1 << AC97_SLOT_PCM_RIGHT) |
  559. (1 << AC97_SLOT_PCM_CENTER) |
  560. (1 << AC97_SLOT_PCM_SLEFT) |
  561. (1 << AC97_SLOT_PCM_SRIGHT) |
  562. (1 << AC97_SLOT_LFE),
  563. },
  564. },
  565. },
  566. [1] = { /* PCM in */
  567. .stream = 1,
  568. .exclusive = 1,
  569. .r = {
  570. [0] = {
  571. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  572. (1 << AC97_SLOT_PCM_RIGHT),
  573. },
  574. },
  575. },
  576. [2] = { /* Mic in */
  577. .stream = 1,
  578. .exclusive = 1,
  579. .r = {
  580. [0] = {
  581. .slots = (1 << AC97_SLOT_MIC),
  582. },
  583. },
  584. }
  585. };
  586. static ac97_bus_ops_t aaci_bus_ops = {
  587. .write = aaci_ac97_write,
  588. .read = aaci_ac97_read,
  589. };
  590. static int __devinit aaci_probe_ac97(struct aaci *aaci)
  591. {
  592. ac97_template_t ac97_template;
  593. ac97_bus_t *ac97_bus;
  594. ac97_t *ac97;
  595. int ret;
  596. /*
  597. * Assert AACIRESET for 2us
  598. */
  599. writel(0, aaci->base + AACI_RESET);
  600. udelay(2);
  601. writel(RESET_NRST, aaci->base + AACI_RESET);
  602. /*
  603. * Give the AC'97 codec more than enough time
  604. * to wake up. (42us = ~2 frames at 48kHz.)
  605. */
  606. udelay(42);
  607. ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
  608. if (ret)
  609. goto out;
  610. ac97_bus->clock = 48000;
  611. aaci->ac97_bus = ac97_bus;
  612. memset(&ac97_template, 0, sizeof(ac97_template_t));
  613. ac97_template.private_data = aaci;
  614. ac97_template.num = 0;
  615. ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
  616. ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
  617. if (ret)
  618. goto out;
  619. /*
  620. * Disable AC97 PC Beep input on audio codecs.
  621. */
  622. if (ac97_is_audio(ac97))
  623. snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
  624. ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
  625. if (ret)
  626. goto out;
  627. aaci->playback.pcm = &ac97_bus->pcms[0];
  628. out:
  629. return ret;
  630. }
  631. static void aaci_free_card(snd_card_t *card)
  632. {
  633. struct aaci *aaci = card->private_data;
  634. if (aaci->base)
  635. iounmap(aaci->base);
  636. }
  637. static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
  638. {
  639. struct aaci *aaci;
  640. snd_card_t *card;
  641. card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  642. THIS_MODULE, sizeof(struct aaci));
  643. if (card == NULL)
  644. return ERR_PTR(-ENOMEM);
  645. card->private_free = aaci_free_card;
  646. snd_card_set_pm_callback(card, aaci_do_suspend, aaci_do_resume, NULL);
  647. strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
  648. strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
  649. snprintf(card->longname, sizeof(card->longname),
  650. "%s at 0x%08lx, irq %d",
  651. card->shortname, dev->res.start, dev->irq[0]);
  652. aaci = card->private_data;
  653. init_MUTEX(&aaci->ac97_sem);
  654. spin_lock_init(&aaci->lock);
  655. aaci->card = card;
  656. aaci->dev = dev;
  657. /* Set MAINCR to allow slot 1 and 2 data IO */
  658. aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
  659. MAINCR_SL2RXEN | MAINCR_SL2TXEN;
  660. return aaci;
  661. }
  662. static int __devinit aaci_init_pcm(struct aaci *aaci)
  663. {
  664. snd_pcm_t *pcm;
  665. int ret;
  666. ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 0, &pcm);
  667. if (ret == 0) {
  668. aaci->pcm = pcm;
  669. pcm->private_data = aaci;
  670. pcm->info_flags = 0;
  671. strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
  672. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
  673. }
  674. return ret;
  675. }
  676. static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
  677. {
  678. void __iomem *base = aaci->base + AACI_CSCH1;
  679. int i;
  680. writel(TXCR_FEN | TXCR_TSZ16 | TXCR_TXEN, base + AACI_TXCR);
  681. for (i = 0; !(readl(base + AACI_SR) & SR_TXFF) && i < 4096; i++)
  682. writel(0, aaci->base + AACI_DR1);
  683. writel(0, base + AACI_TXCR);
  684. /*
  685. * Re-initialise the AACI after the FIFO depth test, to
  686. * ensure that the FIFOs are empty. Unfortunately, merely
  687. * disabling the channel doesn't clear the FIFO.
  688. */
  689. writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
  690. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  691. /*
  692. * If we hit 4096, we failed. Go back to the specified
  693. * fifo depth.
  694. */
  695. if (i == 4096)
  696. i = 8;
  697. return i;
  698. }
  699. static int __devinit aaci_probe(struct amba_device *dev, void *id)
  700. {
  701. struct aaci *aaci;
  702. int ret, i;
  703. ret = amba_request_regions(dev, NULL);
  704. if (ret)
  705. return ret;
  706. aaci = aaci_init_card(dev);
  707. if (IS_ERR(aaci)) {
  708. ret = PTR_ERR(aaci);
  709. goto out;
  710. }
  711. aaci->base = ioremap(dev->res.start, SZ_4K);
  712. if (!aaci->base) {
  713. ret = -ENOMEM;
  714. goto out;
  715. }
  716. /*
  717. * Playback uses AACI channel 0
  718. */
  719. aaci->playback.base = aaci->base + AACI_CSCH1;
  720. aaci->playback.fifo = aaci->base + AACI_DR1;
  721. for (i = 0; i < 4; i++) {
  722. void __iomem *base = aaci->base + i * 0x14;
  723. writel(0, base + AACI_IE);
  724. writel(0, base + AACI_TXCR);
  725. writel(0, base + AACI_RXCR);
  726. }
  727. writel(0x1fff, aaci->base + AACI_INTCLR);
  728. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  729. /*
  730. * Size the FIFOs.
  731. */
  732. aaci->fifosize = aaci_size_fifo(aaci);
  733. ret = aaci_probe_ac97(aaci);
  734. if (ret)
  735. goto out;
  736. ret = aaci_init_pcm(aaci);
  737. if (ret)
  738. goto out;
  739. snd_card_set_dev(aaci->card, &dev->dev);
  740. ret = snd_card_register(aaci->card);
  741. if (ret == 0) {
  742. dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
  743. aaci->fifosize);
  744. amba_set_drvdata(dev, aaci->card);
  745. return ret;
  746. }
  747. out:
  748. if (aaci)
  749. snd_card_free(aaci->card);
  750. amba_release_regions(dev);
  751. return ret;
  752. }
  753. static int __devexit aaci_remove(struct amba_device *dev)
  754. {
  755. snd_card_t *card = amba_get_drvdata(dev);
  756. amba_set_drvdata(dev, NULL);
  757. if (card) {
  758. struct aaci *aaci = card->private_data;
  759. writel(0, aaci->base + AACI_MAINCR);
  760. snd_card_free(card);
  761. amba_release_regions(dev);
  762. }
  763. return 0;
  764. }
  765. static struct amba_id aaci_ids[] = {
  766. {
  767. .id = 0x00041041,
  768. .mask = 0x000fffff,
  769. },
  770. { 0, 0 },
  771. };
  772. static struct amba_driver aaci_driver = {
  773. .drv = {
  774. .name = DRIVER_NAME,
  775. },
  776. .probe = aaci_probe,
  777. .remove = __devexit_p(aaci_remove),
  778. .suspend = aaci_suspend,
  779. .resume = aaci_resume,
  780. .id_table = aaci_ids,
  781. };
  782. static int __init aaci_init(void)
  783. {
  784. return amba_driver_register(&aaci_driver);
  785. }
  786. static void __exit aaci_exit(void)
  787. {
  788. amba_driver_unregister(&aaci_driver);
  789. }
  790. module_init(aaci_init);
  791. module_exit(aaci_exit);
  792. MODULE_LICENSE("GPL");
  793. MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");