spinlock.h 6.2 KB

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  1. #ifndef __ASM_SPINLOCK_H
  2. #define __ASM_SPINLOCK_H
  3. /*
  4. * Simple spin lock operations.
  5. *
  6. * Copyright (C) 2001-2004 Paul Mackerras <paulus@au.ibm.com>, IBM
  7. * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
  8. * Copyright (C) 2002 Dave Engebretsen <engebret@us.ibm.com>, IBM
  9. * Rework to support virtual processors
  10. *
  11. * Type of int is used as a full 64b word is not necessary.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License
  15. * as published by the Free Software Foundation; either version
  16. * 2 of the License, or (at your option) any later version.
  17. *
  18. * (the type definitions are in asm/spinlock_types.h)
  19. */
  20. #ifdef CONFIG_PPC64
  21. #include <asm/paca.h>
  22. #include <asm/hvcall.h>
  23. #include <asm/iseries/hv_call.h>
  24. #endif
  25. #include <asm/asm-compat.h>
  26. #include <asm/synch.h>
  27. #define __raw_spin_is_locked(x) ((x)->slock != 0)
  28. #ifdef CONFIG_PPC64
  29. /* use 0x800000yy when locked, where yy == CPU number */
  30. #define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
  31. #else
  32. #define LOCK_TOKEN 1
  33. #endif
  34. /*
  35. * This returns the old value in the lock, so we succeeded
  36. * in getting the lock if the return value is 0.
  37. */
  38. static __inline__ unsigned long __spin_trylock(raw_spinlock_t *lock)
  39. {
  40. unsigned long tmp, token;
  41. token = LOCK_TOKEN;
  42. __asm__ __volatile__(
  43. "1: lwarx %0,0,%2 # __spin_trylock\n\
  44. cmpwi 0,%0,0\n\
  45. bne- 2f\n\
  46. stwcx. %1,0,%2\n\
  47. bne- 1b\n\
  48. isync\n\
  49. 2:" : "=&r" (tmp)
  50. : "r" (token), "r" (&lock->slock)
  51. : "cr0", "memory");
  52. return tmp;
  53. }
  54. static int __inline__ __raw_spin_trylock(raw_spinlock_t *lock)
  55. {
  56. return __spin_trylock(lock) == 0;
  57. }
  58. /*
  59. * On a system with shared processors (that is, where a physical
  60. * processor is multiplexed between several virtual processors),
  61. * there is no point spinning on a lock if the holder of the lock
  62. * isn't currently scheduled on a physical processor. Instead
  63. * we detect this situation and ask the hypervisor to give the
  64. * rest of our timeslice to the lock holder.
  65. *
  66. * So that we can tell which virtual processor is holding a lock,
  67. * we put 0x80000000 | smp_processor_id() in the lock when it is
  68. * held. Conveniently, we have a word in the paca that holds this
  69. * value.
  70. */
  71. #if defined(CONFIG_PPC_SPLPAR) || defined(CONFIG_PPC_ISERIES)
  72. /* We only yield to the hypervisor if we are in shared processor mode */
  73. #define SHARED_PROCESSOR (get_paca()->lppaca.shared_proc)
  74. extern void __spin_yield(raw_spinlock_t *lock);
  75. extern void __rw_yield(raw_rwlock_t *lock);
  76. #else /* SPLPAR || ISERIES */
  77. #define __spin_yield(x) barrier()
  78. #define __rw_yield(x) barrier()
  79. #define SHARED_PROCESSOR 0
  80. #endif
  81. static void __inline__ __raw_spin_lock(raw_spinlock_t *lock)
  82. {
  83. while (1) {
  84. if (likely(__spin_trylock(lock) == 0))
  85. break;
  86. do {
  87. HMT_low();
  88. if (SHARED_PROCESSOR)
  89. __spin_yield(lock);
  90. } while (unlikely(lock->slock != 0));
  91. HMT_medium();
  92. }
  93. }
  94. static void __inline__ __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
  95. {
  96. unsigned long flags_dis;
  97. while (1) {
  98. if (likely(__spin_trylock(lock) == 0))
  99. break;
  100. local_save_flags(flags_dis);
  101. local_irq_restore(flags);
  102. do {
  103. HMT_low();
  104. if (SHARED_PROCESSOR)
  105. __spin_yield(lock);
  106. } while (unlikely(lock->slock != 0));
  107. HMT_medium();
  108. local_irq_restore(flags_dis);
  109. }
  110. }
  111. static __inline__ void __raw_spin_unlock(raw_spinlock_t *lock)
  112. {
  113. __asm__ __volatile__(SYNC_ON_SMP" # __raw_spin_unlock"
  114. : : :"memory");
  115. lock->slock = 0;
  116. }
  117. #ifdef CONFIG_PPC64
  118. extern void __raw_spin_unlock_wait(raw_spinlock_t *lock);
  119. #else
  120. #define __raw_spin_unlock_wait(lock) \
  121. do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
  122. #endif
  123. /*
  124. * Read-write spinlocks, allowing multiple readers
  125. * but only one writer.
  126. *
  127. * NOTE! it is quite common to have readers in interrupts
  128. * but no interrupt writers. For those circumstances we
  129. * can "mix" irq-safe locks - any writer needs to get a
  130. * irq-safe write-lock, but readers can get non-irqsafe
  131. * read-locks.
  132. */
  133. #define __raw_read_can_lock(rw) ((rw)->lock >= 0)
  134. #define __raw_write_can_lock(rw) (!(rw)->lock)
  135. #ifdef CONFIG_PPC64
  136. #define __DO_SIGN_EXTEND "extsw %0,%0\n"
  137. #define WRLOCK_TOKEN LOCK_TOKEN /* it's negative */
  138. #else
  139. #define __DO_SIGN_EXTEND
  140. #define WRLOCK_TOKEN (-1)
  141. #endif
  142. /*
  143. * This returns the old value in the lock + 1,
  144. * so we got a read lock if the return value is > 0.
  145. */
  146. static long __inline__ __read_trylock(raw_rwlock_t *rw)
  147. {
  148. long tmp;
  149. __asm__ __volatile__(
  150. "1: lwarx %0,0,%1 # read_trylock\n"
  151. __DO_SIGN_EXTEND
  152. " addic. %0,%0,1\n\
  153. ble- 2f\n"
  154. PPC405_ERR77(0,%1)
  155. " stwcx. %0,0,%1\n\
  156. bne- 1b\n\
  157. isync\n\
  158. 2:" : "=&r" (tmp)
  159. : "r" (&rw->lock)
  160. : "cr0", "xer", "memory");
  161. return tmp;
  162. }
  163. /*
  164. * This returns the old value in the lock,
  165. * so we got the write lock if the return value is 0.
  166. */
  167. static __inline__ long __write_trylock(raw_rwlock_t *rw)
  168. {
  169. long tmp, token;
  170. token = WRLOCK_TOKEN;
  171. __asm__ __volatile__(
  172. "1: lwarx %0,0,%2 # write_trylock\n\
  173. cmpwi 0,%0,0\n\
  174. bne- 2f\n"
  175. PPC405_ERR77(0,%1)
  176. " stwcx. %1,0,%2\n\
  177. bne- 1b\n\
  178. isync\n\
  179. 2:" : "=&r" (tmp)
  180. : "r" (token), "r" (&rw->lock)
  181. : "cr0", "memory");
  182. return tmp;
  183. }
  184. static void __inline__ __raw_read_lock(raw_rwlock_t *rw)
  185. {
  186. while (1) {
  187. if (likely(__read_trylock(rw) > 0))
  188. break;
  189. do {
  190. HMT_low();
  191. if (SHARED_PROCESSOR)
  192. __rw_yield(rw);
  193. } while (unlikely(rw->lock < 0));
  194. HMT_medium();
  195. }
  196. }
  197. static void __inline__ __raw_write_lock(raw_rwlock_t *rw)
  198. {
  199. while (1) {
  200. if (likely(__write_trylock(rw) == 0))
  201. break;
  202. do {
  203. HMT_low();
  204. if (SHARED_PROCESSOR)
  205. __rw_yield(rw);
  206. } while (unlikely(rw->lock != 0));
  207. HMT_medium();
  208. }
  209. }
  210. static int __inline__ __raw_read_trylock(raw_rwlock_t *rw)
  211. {
  212. return __read_trylock(rw) > 0;
  213. }
  214. static int __inline__ __raw_write_trylock(raw_rwlock_t *rw)
  215. {
  216. return __write_trylock(rw) == 0;
  217. }
  218. static void __inline__ __raw_read_unlock(raw_rwlock_t *rw)
  219. {
  220. long tmp;
  221. __asm__ __volatile__(
  222. "eieio # read_unlock\n\
  223. 1: lwarx %0,0,%1\n\
  224. addic %0,%0,-1\n"
  225. PPC405_ERR77(0,%1)
  226. " stwcx. %0,0,%1\n\
  227. bne- 1b"
  228. : "=&r"(tmp)
  229. : "r"(&rw->lock)
  230. : "cr0", "memory");
  231. }
  232. static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
  233. {
  234. __asm__ __volatile__(SYNC_ON_SMP" # write_unlock"
  235. : : :"memory");
  236. rw->lock = 0;
  237. }
  238. #endif /* __ASM_SPINLOCK_H */