pci.c 23 KB

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  1. /*
  2. * Copyright (C) 2001 Allan Trautman, IBM Corporation
  3. *
  4. * iSeries specific routines for PCI.
  5. *
  6. * Based on code from pci.c and iSeries_pci.c 32bit
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/list.h>
  24. #include <linux/string.h>
  25. #include <linux/init.h>
  26. #include <linux/module.h>
  27. #include <linux/ide.h>
  28. #include <linux/pci.h>
  29. #include <asm/io.h>
  30. #include <asm/irq.h>
  31. #include <asm/prom.h>
  32. #include <asm/machdep.h>
  33. #include <asm/pci-bridge.h>
  34. #include <asm/iommu.h>
  35. #include <asm/abs_addr.h>
  36. #include <asm/iseries/hv_call_xm.h>
  37. #include <asm/iseries/mf.h>
  38. #include <asm/ppc-pci.h>
  39. #include "irq.h"
  40. #include "pci.h"
  41. #include "call_pci.h"
  42. extern unsigned long io_page_mask;
  43. /*
  44. * Forward declares of prototypes.
  45. */
  46. static struct device_node *find_Device_Node(int bus, int devfn);
  47. static void scan_PHB_slots(struct pci_controller *Phb);
  48. static void scan_EADS_bridge(HvBusNumber Bus, HvSubBusNumber SubBus, int IdSel);
  49. static int scan_bridge_slot(HvBusNumber Bus, struct HvCallPci_BridgeInfo *Info);
  50. LIST_HEAD(iSeries_Global_Device_List);
  51. static int DeviceCount;
  52. /* Counters and control flags. */
  53. static long Pci_Io_Read_Count;
  54. static long Pci_Io_Write_Count;
  55. #if 0
  56. static long Pci_Cfg_Read_Count;
  57. static long Pci_Cfg_Write_Count;
  58. #endif
  59. static long Pci_Error_Count;
  60. static int Pci_Retry_Max = 3; /* Only retry 3 times */
  61. static int Pci_Error_Flag = 1; /* Set Retry Error on. */
  62. static struct pci_ops iSeries_pci_ops;
  63. /*
  64. * Table defines
  65. * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
  66. */
  67. #define IOMM_TABLE_MAX_ENTRIES 1024
  68. #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
  69. #define BASE_IO_MEMORY 0xE000000000000000UL
  70. static unsigned long max_io_memory = 0xE000000000000000UL;
  71. static long current_iomm_table_entry;
  72. /*
  73. * Lookup Tables.
  74. */
  75. static struct device_node **iomm_table;
  76. static u8 *iobar_table;
  77. /*
  78. * Static and Global variables
  79. */
  80. static char *pci_io_text = "iSeries PCI I/O";
  81. static DEFINE_SPINLOCK(iomm_table_lock);
  82. /*
  83. * iomm_table_initialize
  84. *
  85. * Allocates and initalizes the Address Translation Table and Bar
  86. * Tables to get them ready for use. Must be called before any
  87. * I/O space is handed out to the device BARs.
  88. */
  89. static void iomm_table_initialize(void)
  90. {
  91. spin_lock(&iomm_table_lock);
  92. iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES,
  93. GFP_KERNEL);
  94. iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES,
  95. GFP_KERNEL);
  96. spin_unlock(&iomm_table_lock);
  97. if ((iomm_table == NULL) || (iobar_table == NULL))
  98. panic("PCI: I/O tables allocation failed.\n");
  99. }
  100. /*
  101. * iomm_table_allocate_entry
  102. *
  103. * Adds pci_dev entry in address translation table
  104. *
  105. * - Allocates the number of entries required in table base on BAR
  106. * size.
  107. * - Allocates starting at BASE_IO_MEMORY and increases.
  108. * - The size is round up to be a multiple of entry size.
  109. * - CurrentIndex is incremented to keep track of the last entry.
  110. * - Builds the resource entry for allocated BARs.
  111. */
  112. static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
  113. {
  114. struct resource *bar_res = &dev->resource[bar_num];
  115. long bar_size = pci_resource_len(dev, bar_num);
  116. /*
  117. * No space to allocate, quick exit, skip Allocation.
  118. */
  119. if (bar_size == 0)
  120. return;
  121. /*
  122. * Set Resource values.
  123. */
  124. spin_lock(&iomm_table_lock);
  125. bar_res->name = pci_io_text;
  126. bar_res->start =
  127. IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
  128. bar_res->start += BASE_IO_MEMORY;
  129. bar_res->end = bar_res->start + bar_size - 1;
  130. /*
  131. * Allocate the number of table entries needed for BAR.
  132. */
  133. while (bar_size > 0 ) {
  134. iomm_table[current_iomm_table_entry] = dev->sysdata;
  135. iobar_table[current_iomm_table_entry] = bar_num;
  136. bar_size -= IOMM_TABLE_ENTRY_SIZE;
  137. ++current_iomm_table_entry;
  138. }
  139. max_io_memory = BASE_IO_MEMORY +
  140. (IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry);
  141. spin_unlock(&iomm_table_lock);
  142. }
  143. /*
  144. * allocate_device_bars
  145. *
  146. * - Allocates ALL pci_dev BAR's and updates the resources with the
  147. * BAR value. BARS with zero length will have the resources
  148. * The HvCallPci_getBarParms is used to get the size of the BAR
  149. * space. It calls iomm_table_allocate_entry to allocate
  150. * each entry.
  151. * - Loops through The Bar resources(0 - 5) including the ROM
  152. * is resource(6).
  153. */
  154. static void allocate_device_bars(struct pci_dev *dev)
  155. {
  156. struct resource *bar_res;
  157. int bar_num;
  158. for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) {
  159. bar_res = &dev->resource[bar_num];
  160. iomm_table_allocate_entry(dev, bar_num);
  161. }
  162. }
  163. /*
  164. * Log error information to system console.
  165. * Filter out the device not there errors.
  166. * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
  167. * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
  168. * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
  169. */
  170. static void pci_Log_Error(char *Error_Text, int Bus, int SubBus,
  171. int AgentId, int HvRc)
  172. {
  173. if (HvRc == 0x0302)
  174. return;
  175. printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
  176. Error_Text, Bus, SubBus, AgentId, HvRc);
  177. }
  178. /*
  179. * build_device_node(u16 Bus, int SubBus, u8 DevFn)
  180. */
  181. static struct device_node *build_device_node(HvBusNumber Bus,
  182. HvSubBusNumber SubBus, int AgentId, int Function)
  183. {
  184. struct device_node *node;
  185. struct pci_dn *pdn;
  186. node = kmalloc(sizeof(struct device_node), GFP_KERNEL);
  187. if (node == NULL)
  188. return NULL;
  189. memset(node, 0, sizeof(struct device_node));
  190. pdn = kzalloc(sizeof(*pdn), GFP_KERNEL);
  191. if (pdn == NULL) {
  192. kfree(node);
  193. return NULL;
  194. }
  195. node->data = pdn;
  196. pdn->node = node;
  197. list_add_tail(&pdn->Device_List, &iSeries_Global_Device_List);
  198. pdn->busno = Bus;
  199. pdn->bussubno = SubBus;
  200. pdn->devfn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function);
  201. return node;
  202. }
  203. /*
  204. * unsigned long __init find_and_init_phbs(void)
  205. *
  206. * Description:
  207. * This function checks for all possible system PCI host bridges that connect
  208. * PCI buses. The system hypervisor is queried as to the guest partition
  209. * ownership status. A pci_controller is built for any bus which is partially
  210. * owned or fully owned by this guest partition.
  211. */
  212. unsigned long __init find_and_init_phbs(void)
  213. {
  214. struct pci_controller *phb;
  215. HvBusNumber bus;
  216. /* Check all possible buses. */
  217. for (bus = 0; bus < 256; bus++) {
  218. int ret = HvCallXm_testBus(bus);
  219. if (ret == 0) {
  220. printk("bus %d appears to exist\n", bus);
  221. phb = pcibios_alloc_controller(NULL);
  222. if (phb == NULL)
  223. return -ENOMEM;
  224. phb->pci_mem_offset = phb->local_number = bus;
  225. phb->first_busno = bus;
  226. phb->last_busno = bus;
  227. phb->ops = &iSeries_pci_ops;
  228. /* Find and connect the devices. */
  229. scan_PHB_slots(phb);
  230. }
  231. /*
  232. * Check for Unexpected Return code, a clue that something
  233. * has gone wrong.
  234. */
  235. else if (ret != 0x0301)
  236. printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X",
  237. bus, ret);
  238. }
  239. return 0;
  240. }
  241. /*
  242. * iSeries_pcibios_init
  243. *
  244. * Chance to initialize and structures or variable before PCI Bus walk.
  245. */
  246. void iSeries_pcibios_init(void)
  247. {
  248. iomm_table_initialize();
  249. find_and_init_phbs();
  250. io_page_mask = -1;
  251. }
  252. /*
  253. * iSeries_pci_final_fixup(void)
  254. */
  255. void __init iSeries_pci_final_fixup(void)
  256. {
  257. struct pci_dev *pdev = NULL;
  258. struct device_node *node;
  259. int DeviceCount = 0;
  260. /* Fix up at the device node and pci_dev relationship */
  261. mf_display_src(0xC9000100);
  262. printk("pcibios_final_fixup\n");
  263. for_each_pci_dev(pdev) {
  264. node = find_Device_Node(pdev->bus->number, pdev->devfn);
  265. printk("pci dev %p (%x.%x), node %p\n", pdev,
  266. pdev->bus->number, pdev->devfn, node);
  267. if (node != NULL) {
  268. ++DeviceCount;
  269. pdev->sysdata = (void *)node;
  270. PCI_DN(node)->pcidev = pdev;
  271. allocate_device_bars(pdev);
  272. iSeries_Device_Information(pdev, DeviceCount);
  273. iommu_devnode_init_iSeries(node);
  274. } else
  275. printk("PCI: Device Tree not found for 0x%016lX\n",
  276. (unsigned long)pdev);
  277. pdev->irq = PCI_DN(node)->Irq;
  278. }
  279. iSeries_activate_IRQs();
  280. mf_display_src(0xC9000200);
  281. }
  282. void pcibios_fixup_bus(struct pci_bus *PciBus)
  283. {
  284. }
  285. void pcibios_fixup_resources(struct pci_dev *pdev)
  286. {
  287. }
  288. /*
  289. * Loop through each node function to find usable EADs bridges.
  290. */
  291. static void scan_PHB_slots(struct pci_controller *Phb)
  292. {
  293. struct HvCallPci_DeviceInfo *DevInfo;
  294. HvBusNumber bus = Phb->local_number; /* System Bus */
  295. const HvSubBusNumber SubBus = 0; /* EADs is always 0. */
  296. int HvRc = 0;
  297. int IdSel;
  298. const int MaxAgents = 8;
  299. DevInfo = (struct HvCallPci_DeviceInfo*)
  300. kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL);
  301. if (DevInfo == NULL)
  302. return;
  303. /*
  304. * Probe for EADs Bridges
  305. */
  306. for (IdSel = 1; IdSel < MaxAgents; ++IdSel) {
  307. HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel,
  308. iseries_hv_addr(DevInfo),
  309. sizeof(struct HvCallPci_DeviceInfo));
  310. if (HvRc == 0) {
  311. if (DevInfo->deviceType == HvCallPci_NodeDevice)
  312. scan_EADS_bridge(bus, SubBus, IdSel);
  313. else
  314. printk("PCI: Invalid System Configuration(0x%02X)"
  315. " for bus 0x%02x id 0x%02x.\n",
  316. DevInfo->deviceType, bus, IdSel);
  317. }
  318. else
  319. pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc);
  320. }
  321. kfree(DevInfo);
  322. }
  323. static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus,
  324. int IdSel)
  325. {
  326. struct HvCallPci_BridgeInfo *BridgeInfo;
  327. HvAgentId AgentId;
  328. int Function;
  329. int HvRc;
  330. BridgeInfo = (struct HvCallPci_BridgeInfo *)
  331. kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL);
  332. if (BridgeInfo == NULL)
  333. return;
  334. /* Note: hvSubBus and irq is always be 0 at this level! */
  335. for (Function = 0; Function < 8; ++Function) {
  336. AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
  337. HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0);
  338. if (HvRc == 0) {
  339. printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
  340. bus, IdSel, Function, AgentId);
  341. /* Connect EADs: 0x18.00.12 = 0x00 */
  342. HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId,
  343. iseries_hv_addr(BridgeInfo),
  344. sizeof(struct HvCallPci_BridgeInfo));
  345. if (HvRc == 0) {
  346. printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
  347. BridgeInfo->busUnitInfo.deviceType,
  348. BridgeInfo->subBusNumber,
  349. BridgeInfo->maxAgents,
  350. BridgeInfo->maxSubBusNumber,
  351. BridgeInfo->logicalSlotNumber);
  352. if (BridgeInfo->busUnitInfo.deviceType ==
  353. HvCallPci_BridgeDevice) {
  354. /* Scan_Bridge_Slot...: 0x18.00.12 */
  355. scan_bridge_slot(bus, BridgeInfo);
  356. } else
  357. printk("PCI: Invalid Bridge Configuration(0x%02X)",
  358. BridgeInfo->busUnitInfo.deviceType);
  359. }
  360. } else if (HvRc != 0x000B)
  361. pci_Log_Error("EADs Connect",
  362. bus, SubBus, AgentId, HvRc);
  363. }
  364. kfree(BridgeInfo);
  365. }
  366. /*
  367. * This assumes that the node slot is always on the primary bus!
  368. */
  369. static int scan_bridge_slot(HvBusNumber Bus,
  370. struct HvCallPci_BridgeInfo *BridgeInfo)
  371. {
  372. struct device_node *node;
  373. HvSubBusNumber SubBus = BridgeInfo->subBusNumber;
  374. u16 VendorId = 0;
  375. int HvRc = 0;
  376. u8 Irq = 0;
  377. int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus);
  378. int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus);
  379. HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function);
  380. /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
  381. Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel);
  382. /*
  383. * Connect all functions of any device found.
  384. */
  385. for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) {
  386. for (Function = 0; Function < 8; ++Function) {
  387. HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
  388. HvRc = HvCallXm_connectBusUnit(Bus, SubBus,
  389. AgentId, Irq);
  390. if (HvRc != 0) {
  391. pci_Log_Error("Connect Bus Unit",
  392. Bus, SubBus, AgentId, HvRc);
  393. continue;
  394. }
  395. HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId,
  396. PCI_VENDOR_ID, &VendorId);
  397. if (HvRc != 0) {
  398. pci_Log_Error("Read Vendor",
  399. Bus, SubBus, AgentId, HvRc);
  400. continue;
  401. }
  402. printk("read vendor ID: %x\n", VendorId);
  403. /* FoundDevice: 0x18.28.10 = 0x12AE */
  404. HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId,
  405. PCI_INTERRUPT_LINE, Irq);
  406. if (HvRc != 0)
  407. pci_Log_Error("PciCfgStore Irq Failed!",
  408. Bus, SubBus, AgentId, HvRc);
  409. ++DeviceCount;
  410. node = build_device_node(Bus, SubBus, EADsIdSel, Function);
  411. PCI_DN(node)->Irq = Irq;
  412. PCI_DN(node)->LogicalSlot = BridgeInfo->logicalSlotNumber;
  413. } /* for (Function = 0; Function < 8; ++Function) */
  414. } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
  415. return HvRc;
  416. }
  417. /*
  418. * I/0 Memory copy MUST use mmio commands on iSeries
  419. * To do; For performance, include the hv call directly
  420. */
  421. void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count)
  422. {
  423. u8 ByteValue = c;
  424. long NumberOfBytes = Count;
  425. while (NumberOfBytes > 0) {
  426. iSeries_Write_Byte(ByteValue, dest++);
  427. -- NumberOfBytes;
  428. }
  429. }
  430. EXPORT_SYMBOL(iSeries_memset_io);
  431. void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count)
  432. {
  433. char *src = source;
  434. long NumberOfBytes = count;
  435. while (NumberOfBytes > 0) {
  436. iSeries_Write_Byte(*src++, dest++);
  437. -- NumberOfBytes;
  438. }
  439. }
  440. EXPORT_SYMBOL(iSeries_memcpy_toio);
  441. void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count)
  442. {
  443. char *dst = dest;
  444. long NumberOfBytes = count;
  445. while (NumberOfBytes > 0) {
  446. *dst++ = iSeries_Read_Byte(src++);
  447. -- NumberOfBytes;
  448. }
  449. }
  450. EXPORT_SYMBOL(iSeries_memcpy_fromio);
  451. /*
  452. * Look down the chain to find the matching Device Device
  453. */
  454. static struct device_node *find_Device_Node(int bus, int devfn)
  455. {
  456. struct pci_dn *pdn;
  457. list_for_each_entry(pdn, &iSeries_Global_Device_List, Device_List) {
  458. if ((bus == pdn->busno) && (devfn == pdn->devfn))
  459. return pdn->node;
  460. }
  461. return NULL;
  462. }
  463. #if 0
  464. /*
  465. * Returns the device node for the passed pci_dev
  466. * Sanity Check Node PciDev to passed pci_dev
  467. * If none is found, returns a NULL which the client must handle.
  468. */
  469. static struct device_node *get_Device_Node(struct pci_dev *pdev)
  470. {
  471. struct device_node *node;
  472. node = pdev->sysdata;
  473. if (node == NULL || PCI_DN(node)->pcidev != pdev)
  474. node = find_Device_Node(pdev->bus->number, pdev->devfn);
  475. return node;
  476. }
  477. #endif
  478. /*
  479. * Config space read and write functions.
  480. * For now at least, we look for the device node for the bus and devfn
  481. * that we are asked to access. It may be possible to translate the devfn
  482. * to a subbus and deviceid more directly.
  483. */
  484. static u64 hv_cfg_read_func[4] = {
  485. HvCallPciConfigLoad8, HvCallPciConfigLoad16,
  486. HvCallPciConfigLoad32, HvCallPciConfigLoad32
  487. };
  488. static u64 hv_cfg_write_func[4] = {
  489. HvCallPciConfigStore8, HvCallPciConfigStore16,
  490. HvCallPciConfigStore32, HvCallPciConfigStore32
  491. };
  492. /*
  493. * Read PCI config space
  494. */
  495. static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  496. int offset, int size, u32 *val)
  497. {
  498. struct device_node *node = find_Device_Node(bus->number, devfn);
  499. u64 fn;
  500. struct HvCallPci_LoadReturn ret;
  501. if (node == NULL)
  502. return PCIBIOS_DEVICE_NOT_FOUND;
  503. if (offset > 255) {
  504. *val = ~0;
  505. return PCIBIOS_BAD_REGISTER_NUMBER;
  506. }
  507. fn = hv_cfg_read_func[(size - 1) & 3];
  508. HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0);
  509. if (ret.rc != 0) {
  510. *val = ~0;
  511. return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
  512. }
  513. *val = ret.value;
  514. return 0;
  515. }
  516. /*
  517. * Write PCI config space
  518. */
  519. static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
  520. int offset, int size, u32 val)
  521. {
  522. struct device_node *node = find_Device_Node(bus->number, devfn);
  523. u64 fn;
  524. u64 ret;
  525. if (node == NULL)
  526. return PCIBIOS_DEVICE_NOT_FOUND;
  527. if (offset > 255)
  528. return PCIBIOS_BAD_REGISTER_NUMBER;
  529. fn = hv_cfg_write_func[(size - 1) & 3];
  530. ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0);
  531. if (ret != 0)
  532. return PCIBIOS_DEVICE_NOT_FOUND;
  533. return 0;
  534. }
  535. static struct pci_ops iSeries_pci_ops = {
  536. .read = iSeries_pci_read_config,
  537. .write = iSeries_pci_write_config
  538. };
  539. /*
  540. * Check Return Code
  541. * -> On Failure, print and log information.
  542. * Increment Retry Count, if exceeds max, panic partition.
  543. *
  544. * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
  545. * PCI: Device 23.90 ReadL Retry( 1)
  546. * PCI: Device 23.90 ReadL Retry Successful(1)
  547. */
  548. static int CheckReturnCode(char *TextHdr, struct device_node *DevNode,
  549. int *retry, u64 ret)
  550. {
  551. if (ret != 0) {
  552. struct pci_dn *pdn = PCI_DN(DevNode);
  553. ++Pci_Error_Count;
  554. (*retry)++;
  555. printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
  556. TextHdr, pdn->busno, pdn->devfn,
  557. *retry, (int)ret);
  558. /*
  559. * Bump the retry and check for retry count exceeded.
  560. * If, Exceeded, panic the system.
  561. */
  562. if (((*retry) > Pci_Retry_Max) &&
  563. (Pci_Error_Flag > 0)) {
  564. mf_display_src(0xB6000103);
  565. panic_timeout = 0;
  566. panic("PCI: Hardware I/O Error, SRC B6000103, "
  567. "Automatic Reboot Disabled.\n");
  568. }
  569. return -1; /* Retry Try */
  570. }
  571. return 0;
  572. }
  573. /*
  574. * Translate the I/O Address into a device node, bar, and bar offset.
  575. * Note: Make sure the passed variable end up on the stack to avoid
  576. * the exposure of being device global.
  577. */
  578. static inline struct device_node *xlate_iomm_address(
  579. const volatile void __iomem *IoAddress,
  580. u64 *dsaptr, u64 *BarOffsetPtr)
  581. {
  582. unsigned long OrigIoAddr;
  583. unsigned long BaseIoAddr;
  584. unsigned long TableIndex;
  585. struct device_node *DevNode;
  586. OrigIoAddr = (unsigned long __force)IoAddress;
  587. if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory))
  588. return NULL;
  589. BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY;
  590. TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE;
  591. DevNode = iomm_table[TableIndex];
  592. if (DevNode != NULL) {
  593. int barnum = iobar_table[TableIndex];
  594. *dsaptr = iseries_ds_addr(DevNode) | (barnum << 24);
  595. *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE;
  596. } else
  597. panic("PCI: Invalid PCI IoAddress detected!\n");
  598. return DevNode;
  599. }
  600. /*
  601. * Read MM I/O Instructions for the iSeries
  602. * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
  603. * else, data is returned in big Endian format.
  604. *
  605. * iSeries_Read_Byte = Read Byte ( 8 bit)
  606. * iSeries_Read_Word = Read Word (16 bit)
  607. * iSeries_Read_Long = Read Long (32 bit)
  608. */
  609. u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress)
  610. {
  611. u64 BarOffset;
  612. u64 dsa;
  613. int retry = 0;
  614. struct HvCallPci_LoadReturn ret;
  615. struct device_node *DevNode =
  616. xlate_iomm_address(IoAddress, &dsa, &BarOffset);
  617. if (DevNode == NULL) {
  618. static unsigned long last_jiffies;
  619. static int num_printed;
  620. if ((jiffies - last_jiffies) > 60 * HZ) {
  621. last_jiffies = jiffies;
  622. num_printed = 0;
  623. }
  624. if (num_printed++ < 10)
  625. printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress);
  626. return 0xff;
  627. }
  628. do {
  629. ++Pci_Io_Read_Count;
  630. HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
  631. } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0);
  632. return (u8)ret.value;
  633. }
  634. EXPORT_SYMBOL(iSeries_Read_Byte);
  635. u16 iSeries_Read_Word(const volatile void __iomem *IoAddress)
  636. {
  637. u64 BarOffset;
  638. u64 dsa;
  639. int retry = 0;
  640. struct HvCallPci_LoadReturn ret;
  641. struct device_node *DevNode =
  642. xlate_iomm_address(IoAddress, &dsa, &BarOffset);
  643. if (DevNode == NULL) {
  644. static unsigned long last_jiffies;
  645. static int num_printed;
  646. if ((jiffies - last_jiffies) > 60 * HZ) {
  647. last_jiffies = jiffies;
  648. num_printed = 0;
  649. }
  650. if (num_printed++ < 10)
  651. printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress);
  652. return 0xffff;
  653. }
  654. do {
  655. ++Pci_Io_Read_Count;
  656. HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
  657. BarOffset, 0);
  658. } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0);
  659. return swab16((u16)ret.value);
  660. }
  661. EXPORT_SYMBOL(iSeries_Read_Word);
  662. u32 iSeries_Read_Long(const volatile void __iomem *IoAddress)
  663. {
  664. u64 BarOffset;
  665. u64 dsa;
  666. int retry = 0;
  667. struct HvCallPci_LoadReturn ret;
  668. struct device_node *DevNode =
  669. xlate_iomm_address(IoAddress, &dsa, &BarOffset);
  670. if (DevNode == NULL) {
  671. static unsigned long last_jiffies;
  672. static int num_printed;
  673. if ((jiffies - last_jiffies) > 60 * HZ) {
  674. last_jiffies = jiffies;
  675. num_printed = 0;
  676. }
  677. if (num_printed++ < 10)
  678. printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress);
  679. return 0xffffffff;
  680. }
  681. do {
  682. ++Pci_Io_Read_Count;
  683. HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
  684. BarOffset, 0);
  685. } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0);
  686. return swab32((u32)ret.value);
  687. }
  688. EXPORT_SYMBOL(iSeries_Read_Long);
  689. /*
  690. * Write MM I/O Instructions for the iSeries
  691. *
  692. * iSeries_Write_Byte = Write Byte (8 bit)
  693. * iSeries_Write_Word = Write Word(16 bit)
  694. * iSeries_Write_Long = Write Long(32 bit)
  695. */
  696. void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress)
  697. {
  698. u64 BarOffset;
  699. u64 dsa;
  700. int retry = 0;
  701. u64 rc;
  702. struct device_node *DevNode =
  703. xlate_iomm_address(IoAddress, &dsa, &BarOffset);
  704. if (DevNode == NULL) {
  705. static unsigned long last_jiffies;
  706. static int num_printed;
  707. if ((jiffies - last_jiffies) > 60 * HZ) {
  708. last_jiffies = jiffies;
  709. num_printed = 0;
  710. }
  711. if (num_printed++ < 10)
  712. printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress);
  713. return;
  714. }
  715. do {
  716. ++Pci_Io_Write_Count;
  717. rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
  718. } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0);
  719. }
  720. EXPORT_SYMBOL(iSeries_Write_Byte);
  721. void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress)
  722. {
  723. u64 BarOffset;
  724. u64 dsa;
  725. int retry = 0;
  726. u64 rc;
  727. struct device_node *DevNode =
  728. xlate_iomm_address(IoAddress, &dsa, &BarOffset);
  729. if (DevNode == NULL) {
  730. static unsigned long last_jiffies;
  731. static int num_printed;
  732. if ((jiffies - last_jiffies) > 60 * HZ) {
  733. last_jiffies = jiffies;
  734. num_printed = 0;
  735. }
  736. if (num_printed++ < 10)
  737. printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress);
  738. return;
  739. }
  740. do {
  741. ++Pci_Io_Write_Count;
  742. rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
  743. } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0);
  744. }
  745. EXPORT_SYMBOL(iSeries_Write_Word);
  746. void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress)
  747. {
  748. u64 BarOffset;
  749. u64 dsa;
  750. int retry = 0;
  751. u64 rc;
  752. struct device_node *DevNode =
  753. xlate_iomm_address(IoAddress, &dsa, &BarOffset);
  754. if (DevNode == NULL) {
  755. static unsigned long last_jiffies;
  756. static int num_printed;
  757. if ((jiffies - last_jiffies) > 60 * HZ) {
  758. last_jiffies = jiffies;
  759. num_printed = 0;
  760. }
  761. if (num_printed++ < 10)
  762. printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress);
  763. return;
  764. }
  765. do {
  766. ++Pci_Io_Write_Count;
  767. rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
  768. } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0);
  769. }
  770. EXPORT_SYMBOL(iSeries_Write_Long);