head_32.S 38 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382
  1. /*
  2. * PowerPC version
  3. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  4. *
  5. * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
  6. * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  7. * Adapted for Power Macintosh by Paul Mackerras.
  8. * Low-level exception handlers and MMU support
  9. * rewritten by Paul Mackerras.
  10. * Copyright (C) 1996 Paul Mackerras.
  11. * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
  12. * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
  13. *
  14. * This file contains the low-level support and setup for the
  15. * PowerPC platform, including trap and interrupt dispatch.
  16. * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
  17. *
  18. * This program is free software; you can redistribute it and/or
  19. * modify it under the terms of the GNU General Public License
  20. * as published by the Free Software Foundation; either version
  21. * 2 of the License, or (at your option) any later version.
  22. *
  23. */
  24. #include <linux/config.h>
  25. #include <asm/reg.h>
  26. #include <asm/page.h>
  27. #include <asm/mmu.h>
  28. #include <asm/pgtable.h>
  29. #include <asm/cputable.h>
  30. #include <asm/cache.h>
  31. #include <asm/thread_info.h>
  32. #include <asm/ppc_asm.h>
  33. #include <asm/asm-offsets.h>
  34. #ifdef CONFIG_APUS
  35. #include <asm/amigappc.h>
  36. #endif
  37. /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
  38. #define LOAD_BAT(n, reg, RA, RB) \
  39. /* see the comment for clear_bats() -- Cort */ \
  40. li RA,0; \
  41. mtspr SPRN_IBAT##n##U,RA; \
  42. mtspr SPRN_DBAT##n##U,RA; \
  43. lwz RA,(n*16)+0(reg); \
  44. lwz RB,(n*16)+4(reg); \
  45. mtspr SPRN_IBAT##n##U,RA; \
  46. mtspr SPRN_IBAT##n##L,RB; \
  47. beq 1f; \
  48. lwz RA,(n*16)+8(reg); \
  49. lwz RB,(n*16)+12(reg); \
  50. mtspr SPRN_DBAT##n##U,RA; \
  51. mtspr SPRN_DBAT##n##L,RB; \
  52. 1:
  53. .text
  54. .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
  55. .stabs "head_32.S",N_SO,0,0,0f
  56. 0:
  57. .globl _stext
  58. _stext:
  59. /*
  60. * _start is defined this way because the XCOFF loader in the OpenFirmware
  61. * on the powermac expects the entry point to be a procedure descriptor.
  62. */
  63. .text
  64. .globl _start
  65. _start:
  66. /*
  67. * These are here for legacy reasons, the kernel used to
  68. * need to look like a coff function entry for the pmac
  69. * but we're always started by some kind of bootloader now.
  70. * -- Cort
  71. */
  72. nop /* used by __secondary_hold on prep (mtx) and chrp smp */
  73. nop /* used by __secondary_hold on prep (mtx) and chrp smp */
  74. nop
  75. /* PMAC
  76. * Enter here with the kernel text, data and bss loaded starting at
  77. * 0, running with virtual == physical mapping.
  78. * r5 points to the prom entry point (the client interface handler
  79. * address). Address translation is turned on, with the prom
  80. * managing the hash table. Interrupts are disabled. The stack
  81. * pointer (r1) points to just below the end of the half-meg region
  82. * from 0x380000 - 0x400000, which is mapped in already.
  83. *
  84. * If we are booted from MacOS via BootX, we enter with the kernel
  85. * image loaded somewhere, and the following values in registers:
  86. * r3: 'BooX' (0x426f6f58)
  87. * r4: virtual address of boot_infos_t
  88. * r5: 0
  89. *
  90. * APUS
  91. * r3: 'APUS'
  92. * r4: physical address of memory base
  93. * Linux/m68k style BootInfo structure at &_end.
  94. *
  95. * PREP
  96. * This is jumped to on prep systems right after the kernel is relocated
  97. * to its proper place in memory by the boot loader. The expected layout
  98. * of the regs is:
  99. * r3: ptr to residual data
  100. * r4: initrd_start or if no initrd then 0
  101. * r5: initrd_end - unused if r4 is 0
  102. * r6: Start of command line string
  103. * r7: End of command line string
  104. *
  105. * This just gets a minimal mmu environment setup so we can call
  106. * start_here() to do the real work.
  107. * -- Cort
  108. */
  109. .globl __start
  110. __start:
  111. /*
  112. * We have to do any OF calls before we map ourselves to KERNELBASE,
  113. * because OF may have I/O devices mapped into that area
  114. * (particularly on CHRP).
  115. */
  116. cmpwi 0,r5,0
  117. beq 1f
  118. bl prom_init
  119. trap
  120. 1: mr r31,r3 /* save parameters */
  121. mr r30,r4
  122. li r24,0 /* cpu # */
  123. /*
  124. * early_init() does the early machine identification and does
  125. * the necessary low-level setup and clears the BSS
  126. * -- Cort <cort@fsmlabs.com>
  127. */
  128. bl early_init
  129. #ifdef CONFIG_APUS
  130. /* On APUS the __va/__pa constants need to be set to the correct
  131. * values before continuing.
  132. */
  133. mr r4,r30
  134. bl fix_mem_constants
  135. #endif /* CONFIG_APUS */
  136. /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
  137. * the physical address we are running at, returned by early_init()
  138. */
  139. bl mmu_off
  140. __after_mmu_off:
  141. bl clear_bats
  142. bl flush_tlbs
  143. bl initial_bats
  144. /*
  145. * Call setup_cpu for CPU 0 and initialize 6xx Idle
  146. */
  147. bl reloc_offset
  148. li r24,0 /* cpu# */
  149. bl call_setup_cpu /* Call setup_cpu for this CPU */
  150. #ifdef CONFIG_6xx
  151. bl reloc_offset
  152. bl init_idle_6xx
  153. #endif /* CONFIG_6xx */
  154. #ifndef CONFIG_APUS
  155. /*
  156. * We need to run with _start at physical address 0.
  157. * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
  158. * the exception vectors at 0 (and therefore this copy
  159. * overwrites OF's exception vectors with our own).
  160. * The MMU is off at this point.
  161. */
  162. bl reloc_offset
  163. mr r26,r3
  164. addis r4,r3,KERNELBASE@h /* current address of _start */
  165. cmpwi 0,r4,0 /* are we already running at 0? */
  166. bne relocate_kernel
  167. #endif /* CONFIG_APUS */
  168. /*
  169. * we now have the 1st 16M of ram mapped with the bats.
  170. * prep needs the mmu to be turned on here, but pmac already has it on.
  171. * this shouldn't bother the pmac since it just gets turned on again
  172. * as we jump to our code at KERNELBASE. -- Cort
  173. * Actually no, pmac doesn't have it on any more. BootX enters with MMU
  174. * off, and in other cases, we now turn it off before changing BATs above.
  175. */
  176. turn_on_mmu:
  177. mfmsr r0
  178. ori r0,r0,MSR_DR|MSR_IR
  179. mtspr SPRN_SRR1,r0
  180. lis r0,start_here@h
  181. ori r0,r0,start_here@l
  182. mtspr SPRN_SRR0,r0
  183. SYNC
  184. RFI /* enables MMU */
  185. /*
  186. * We need __secondary_hold as a place to hold the other cpus on
  187. * an SMP machine, even when we are running a UP kernel.
  188. */
  189. . = 0xc0 /* for prep bootloader */
  190. li r3,1 /* MTX only has 1 cpu */
  191. .globl __secondary_hold
  192. __secondary_hold:
  193. /* tell the master we're here */
  194. stw r3,__secondary_hold_acknowledge@l(0)
  195. #ifdef CONFIG_SMP
  196. 100: lwz r4,0(0)
  197. /* wait until we're told to start */
  198. cmpw 0,r4,r3
  199. bne 100b
  200. /* our cpu # was at addr 0 - go */
  201. mr r24,r3 /* cpu # */
  202. b __secondary_start
  203. #else
  204. b .
  205. #endif /* CONFIG_SMP */
  206. .globl __secondary_hold_spinloop
  207. __secondary_hold_spinloop:
  208. .long 0
  209. .globl __secondary_hold_acknowledge
  210. __secondary_hold_acknowledge:
  211. .long -1
  212. /*
  213. * Exception entry code. This code runs with address translation
  214. * turned off, i.e. using physical addresses.
  215. * We assume sprg3 has the physical address of the current
  216. * task's thread_struct.
  217. */
  218. #define EXCEPTION_PROLOG \
  219. mtspr SPRN_SPRG0,r10; \
  220. mtspr SPRN_SPRG1,r11; \
  221. mfcr r10; \
  222. EXCEPTION_PROLOG_1; \
  223. EXCEPTION_PROLOG_2
  224. #define EXCEPTION_PROLOG_1 \
  225. mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
  226. andi. r11,r11,MSR_PR; \
  227. tophys(r11,r1); /* use tophys(r1) if kernel */ \
  228. beq 1f; \
  229. mfspr r11,SPRN_SPRG3; \
  230. lwz r11,THREAD_INFO-THREAD(r11); \
  231. addi r11,r11,THREAD_SIZE; \
  232. tophys(r11,r11); \
  233. 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
  234. #define EXCEPTION_PROLOG_2 \
  235. CLR_TOP32(r11); \
  236. stw r10,_CCR(r11); /* save registers */ \
  237. stw r12,GPR12(r11); \
  238. stw r9,GPR9(r11); \
  239. mfspr r10,SPRN_SPRG0; \
  240. stw r10,GPR10(r11); \
  241. mfspr r12,SPRN_SPRG1; \
  242. stw r12,GPR11(r11); \
  243. mflr r10; \
  244. stw r10,_LINK(r11); \
  245. mfspr r12,SPRN_SRR0; \
  246. mfspr r9,SPRN_SRR1; \
  247. stw r1,GPR1(r11); \
  248. stw r1,0(r11); \
  249. tovirt(r1,r11); /* set new kernel sp */ \
  250. li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
  251. MTMSRD(r10); /* (except for mach check in rtas) */ \
  252. stw r0,GPR0(r11); \
  253. lis r10,0x7265; /* put exception frame marker */ \
  254. addi r10,r10,0x6773; \
  255. stw r10,8(r11); \
  256. SAVE_4GPRS(3, r11); \
  257. SAVE_2GPRS(7, r11)
  258. /*
  259. * Note: code which follows this uses cr0.eq (set if from kernel),
  260. * r11, r12 (SRR0), and r9 (SRR1).
  261. *
  262. * Note2: once we have set r1 we are in a position to take exceptions
  263. * again, and we could thus set MSR:RI at that point.
  264. */
  265. /*
  266. * Exception vectors.
  267. */
  268. #define EXCEPTION(n, label, hdlr, xfer) \
  269. . = n; \
  270. label: \
  271. EXCEPTION_PROLOG; \
  272. addi r3,r1,STACK_FRAME_OVERHEAD; \
  273. xfer(n, hdlr)
  274. #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
  275. li r10,trap; \
  276. stw r10,_TRAP(r11); \
  277. li r10,MSR_KERNEL; \
  278. copyee(r10, r9); \
  279. bl tfer; \
  280. i##n: \
  281. .long hdlr; \
  282. .long ret
  283. #define COPY_EE(d, s) rlwimi d,s,0,16,16
  284. #define NOCOPY(d, s)
  285. #define EXC_XFER_STD(n, hdlr) \
  286. EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
  287. ret_from_except_full)
  288. #define EXC_XFER_LITE(n, hdlr) \
  289. EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
  290. ret_from_except)
  291. #define EXC_XFER_EE(n, hdlr) \
  292. EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
  293. ret_from_except_full)
  294. #define EXC_XFER_EE_LITE(n, hdlr) \
  295. EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
  296. ret_from_except)
  297. /* System reset */
  298. /* core99 pmac starts the seconary here by changing the vector, and
  299. putting it back to what it was (unknown_exception) when done. */
  300. #if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
  301. . = 0x100
  302. b __secondary_start_gemini
  303. #else
  304. EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
  305. #endif
  306. /* Machine check */
  307. /*
  308. * On CHRP, this is complicated by the fact that we could get a
  309. * machine check inside RTAS, and we have no guarantee that certain
  310. * critical registers will have the values we expect. The set of
  311. * registers that might have bad values includes all the GPRs
  312. * and all the BATs. We indicate that we are in RTAS by putting
  313. * a non-zero value, the address of the exception frame to use,
  314. * in SPRG2. The machine check handler checks SPRG2 and uses its
  315. * value if it is non-zero. If we ever needed to free up SPRG2,
  316. * we could use a field in the thread_info or thread_struct instead.
  317. * (Other exception handlers assume that r1 is a valid kernel stack
  318. * pointer when we take an exception from supervisor mode.)
  319. * -- paulus.
  320. */
  321. . = 0x200
  322. mtspr SPRN_SPRG0,r10
  323. mtspr SPRN_SPRG1,r11
  324. mfcr r10
  325. #ifdef CONFIG_PPC_CHRP
  326. mfspr r11,SPRN_SPRG2
  327. cmpwi 0,r11,0
  328. bne 7f
  329. #endif /* CONFIG_PPC_CHRP */
  330. EXCEPTION_PROLOG_1
  331. 7: EXCEPTION_PROLOG_2
  332. addi r3,r1,STACK_FRAME_OVERHEAD
  333. #ifdef CONFIG_PPC_CHRP
  334. mfspr r4,SPRN_SPRG2
  335. cmpwi cr1,r4,0
  336. bne cr1,1f
  337. #endif
  338. EXC_XFER_STD(0x200, machine_check_exception)
  339. #ifdef CONFIG_PPC_CHRP
  340. 1: b machine_check_in_rtas
  341. #endif
  342. /* Data access exception. */
  343. . = 0x300
  344. DataAccess:
  345. EXCEPTION_PROLOG
  346. mfspr r10,SPRN_DSISR
  347. andis. r0,r10,0xa470 /* weird error? */
  348. bne 1f /* if not, try to put a PTE */
  349. mfspr r4,SPRN_DAR /* into the hash table */
  350. rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
  351. bl hash_page
  352. 1: stw r10,_DSISR(r11)
  353. mr r5,r10
  354. mfspr r4,SPRN_DAR
  355. EXC_XFER_EE_LITE(0x300, handle_page_fault)
  356. /* Instruction access exception. */
  357. . = 0x400
  358. InstructionAccess:
  359. EXCEPTION_PROLOG
  360. andis. r0,r9,0x4000 /* no pte found? */
  361. beq 1f /* if so, try to put a PTE */
  362. li r3,0 /* into the hash table */
  363. mr r4,r12 /* SRR0 is fault address */
  364. bl hash_page
  365. 1: mr r4,r12
  366. mr r5,r9
  367. EXC_XFER_EE_LITE(0x400, handle_page_fault)
  368. /* External interrupt */
  369. EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
  370. /* Alignment exception */
  371. . = 0x600
  372. Alignment:
  373. EXCEPTION_PROLOG
  374. mfspr r4,SPRN_DAR
  375. stw r4,_DAR(r11)
  376. mfspr r5,SPRN_DSISR
  377. stw r5,_DSISR(r11)
  378. addi r3,r1,STACK_FRAME_OVERHEAD
  379. EXC_XFER_EE(0x600, alignment_exception)
  380. /* Program check exception */
  381. EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
  382. /* Floating-point unavailable */
  383. . = 0x800
  384. FPUnavailable:
  385. EXCEPTION_PROLOG
  386. bne load_up_fpu /* if from user, just load it up */
  387. addi r3,r1,STACK_FRAME_OVERHEAD
  388. EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
  389. /* Decrementer */
  390. EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
  391. EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
  392. EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
  393. /* System call */
  394. . = 0xc00
  395. SystemCall:
  396. EXCEPTION_PROLOG
  397. EXC_XFER_EE_LITE(0xc00, DoSyscall)
  398. /* Single step - not used on 601 */
  399. EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
  400. EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
  401. /*
  402. * The Altivec unavailable trap is at 0x0f20. Foo.
  403. * We effectively remap it to 0x3000.
  404. * We include an altivec unavailable exception vector even if
  405. * not configured for Altivec, so that you can't panic a
  406. * non-altivec kernel running on a machine with altivec just
  407. * by executing an altivec instruction.
  408. */
  409. . = 0xf00
  410. b Trap_0f
  411. . = 0xf20
  412. b AltiVecUnavailable
  413. Trap_0f:
  414. EXCEPTION_PROLOG
  415. addi r3,r1,STACK_FRAME_OVERHEAD
  416. EXC_XFER_EE(0xf00, unknown_exception)
  417. /*
  418. * Handle TLB miss for instruction on 603/603e.
  419. * Note: we get an alternate set of r0 - r3 to use automatically.
  420. */
  421. . = 0x1000
  422. InstructionTLBMiss:
  423. /*
  424. * r0: stored ctr
  425. * r1: linux style pte ( later becomes ppc hardware pte )
  426. * r2: ptr to linux-style pte
  427. * r3: scratch
  428. */
  429. mfctr r0
  430. /* Get PTE (linux-style) and check access */
  431. mfspr r3,SPRN_IMISS
  432. lis r1,KERNELBASE@h /* check if kernel address */
  433. cmplw 0,r3,r1
  434. mfspr r2,SPRN_SPRG3
  435. li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
  436. lwz r2,PGDIR(r2)
  437. blt+ 112f
  438. lis r2,swapper_pg_dir@ha /* if kernel address, use */
  439. addi r2,r2,swapper_pg_dir@l /* kernel page table */
  440. mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
  441. rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
  442. 112: tophys(r2,r2)
  443. rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
  444. lwz r2,0(r2) /* get pmd entry */
  445. rlwinm. r2,r2,0,0,19 /* extract address of pte page */
  446. beq- InstructionAddressInvalid /* return if no mapping */
  447. rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
  448. lwz r3,0(r2) /* get linux-style pte */
  449. andc. r1,r1,r3 /* check access & ~permission */
  450. bne- InstructionAddressInvalid /* return if access not permitted */
  451. ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
  452. /*
  453. * NOTE! We are assuming this is not an SMP system, otherwise
  454. * we would need to update the pte atomically with lwarx/stwcx.
  455. */
  456. stw r3,0(r2) /* update PTE (accessed bit) */
  457. /* Convert linux-style PTE to low word of PPC-style PTE */
  458. rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
  459. rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
  460. and r1,r1,r2 /* writable if _RW and _DIRTY */
  461. rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
  462. rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
  463. ori r1,r1,0xe14 /* clear out reserved bits and M */
  464. andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
  465. mtspr SPRN_RPA,r1
  466. mfspr r3,SPRN_IMISS
  467. tlbli r3
  468. mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
  469. mtcrf 0x80,r3
  470. rfi
  471. InstructionAddressInvalid:
  472. mfspr r3,SPRN_SRR1
  473. rlwinm r1,r3,9,6,6 /* Get load/store bit */
  474. addis r1,r1,0x2000
  475. mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
  476. mtctr r0 /* Restore CTR */
  477. andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
  478. or r2,r2,r1
  479. mtspr SPRN_SRR1,r2
  480. mfspr r1,SPRN_IMISS /* Get failing address */
  481. rlwinm. r2,r2,0,31,31 /* Check for little endian access */
  482. rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
  483. xor r1,r1,r2
  484. mtspr SPRN_DAR,r1 /* Set fault address */
  485. mfmsr r0 /* Restore "normal" registers */
  486. xoris r0,r0,MSR_TGPR>>16
  487. mtcrf 0x80,r3 /* Restore CR0 */
  488. mtmsr r0
  489. b InstructionAccess
  490. /*
  491. * Handle TLB miss for DATA Load operation on 603/603e
  492. */
  493. . = 0x1100
  494. DataLoadTLBMiss:
  495. /*
  496. * r0: stored ctr
  497. * r1: linux style pte ( later becomes ppc hardware pte )
  498. * r2: ptr to linux-style pte
  499. * r3: scratch
  500. */
  501. mfctr r0
  502. /* Get PTE (linux-style) and check access */
  503. mfspr r3,SPRN_DMISS
  504. lis r1,KERNELBASE@h /* check if kernel address */
  505. cmplw 0,r3,r1
  506. mfspr r2,SPRN_SPRG3
  507. li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
  508. lwz r2,PGDIR(r2)
  509. blt+ 112f
  510. lis r2,swapper_pg_dir@ha /* if kernel address, use */
  511. addi r2,r2,swapper_pg_dir@l /* kernel page table */
  512. mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
  513. rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
  514. 112: tophys(r2,r2)
  515. rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
  516. lwz r2,0(r2) /* get pmd entry */
  517. rlwinm. r2,r2,0,0,19 /* extract address of pte page */
  518. beq- DataAddressInvalid /* return if no mapping */
  519. rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
  520. lwz r3,0(r2) /* get linux-style pte */
  521. andc. r1,r1,r3 /* check access & ~permission */
  522. bne- DataAddressInvalid /* return if access not permitted */
  523. ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
  524. /*
  525. * NOTE! We are assuming this is not an SMP system, otherwise
  526. * we would need to update the pte atomically with lwarx/stwcx.
  527. */
  528. stw r3,0(r2) /* update PTE (accessed bit) */
  529. /* Convert linux-style PTE to low word of PPC-style PTE */
  530. rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
  531. rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
  532. and r1,r1,r2 /* writable if _RW and _DIRTY */
  533. rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
  534. rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
  535. ori r1,r1,0xe14 /* clear out reserved bits and M */
  536. andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
  537. mtspr SPRN_RPA,r1
  538. mfspr r3,SPRN_DMISS
  539. tlbld r3
  540. mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
  541. mtcrf 0x80,r3
  542. rfi
  543. DataAddressInvalid:
  544. mfspr r3,SPRN_SRR1
  545. rlwinm r1,r3,9,6,6 /* Get load/store bit */
  546. addis r1,r1,0x2000
  547. mtspr SPRN_DSISR,r1
  548. mtctr r0 /* Restore CTR */
  549. andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
  550. mtspr SPRN_SRR1,r2
  551. mfspr r1,SPRN_DMISS /* Get failing address */
  552. rlwinm. r2,r2,0,31,31 /* Check for little endian access */
  553. beq 20f /* Jump if big endian */
  554. xori r1,r1,3
  555. 20: mtspr SPRN_DAR,r1 /* Set fault address */
  556. mfmsr r0 /* Restore "normal" registers */
  557. xoris r0,r0,MSR_TGPR>>16
  558. mtcrf 0x80,r3 /* Restore CR0 */
  559. mtmsr r0
  560. b DataAccess
  561. /*
  562. * Handle TLB miss for DATA Store on 603/603e
  563. */
  564. . = 0x1200
  565. DataStoreTLBMiss:
  566. /*
  567. * r0: stored ctr
  568. * r1: linux style pte ( later becomes ppc hardware pte )
  569. * r2: ptr to linux-style pte
  570. * r3: scratch
  571. */
  572. mfctr r0
  573. /* Get PTE (linux-style) and check access */
  574. mfspr r3,SPRN_DMISS
  575. lis r1,KERNELBASE@h /* check if kernel address */
  576. cmplw 0,r3,r1
  577. mfspr r2,SPRN_SPRG3
  578. li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
  579. lwz r2,PGDIR(r2)
  580. blt+ 112f
  581. lis r2,swapper_pg_dir@ha /* if kernel address, use */
  582. addi r2,r2,swapper_pg_dir@l /* kernel page table */
  583. mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
  584. rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
  585. 112: tophys(r2,r2)
  586. rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
  587. lwz r2,0(r2) /* get pmd entry */
  588. rlwinm. r2,r2,0,0,19 /* extract address of pte page */
  589. beq- DataAddressInvalid /* return if no mapping */
  590. rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
  591. lwz r3,0(r2) /* get linux-style pte */
  592. andc. r1,r1,r3 /* check access & ~permission */
  593. bne- DataAddressInvalid /* return if access not permitted */
  594. ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
  595. /*
  596. * NOTE! We are assuming this is not an SMP system, otherwise
  597. * we would need to update the pte atomically with lwarx/stwcx.
  598. */
  599. stw r3,0(r2) /* update PTE (accessed/dirty bits) */
  600. /* Convert linux-style PTE to low word of PPC-style PTE */
  601. rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
  602. li r1,0xe15 /* clear out reserved bits and M */
  603. andc r1,r3,r1 /* PP = user? 2: 0 */
  604. mtspr SPRN_RPA,r1
  605. mfspr r3,SPRN_DMISS
  606. tlbld r3
  607. mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
  608. mtcrf 0x80,r3
  609. rfi
  610. #ifndef CONFIG_ALTIVEC
  611. #define altivec_assist_exception unknown_exception
  612. #endif
  613. EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
  614. EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
  615. EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
  616. EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
  617. EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
  618. EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
  619. EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
  620. EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
  621. EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
  622. EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
  623. EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
  624. EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
  625. EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
  626. EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
  627. EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
  628. EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
  629. EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
  630. EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
  631. EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
  632. EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
  633. EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
  634. EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
  635. EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
  636. EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
  637. EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
  638. EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
  639. EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
  640. EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
  641. EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
  642. .globl mol_trampoline
  643. .set mol_trampoline, i0x2f00
  644. . = 0x3000
  645. AltiVecUnavailable:
  646. EXCEPTION_PROLOG
  647. #ifdef CONFIG_ALTIVEC
  648. bne load_up_altivec /* if from user, just load it up */
  649. #endif /* CONFIG_ALTIVEC */
  650. EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
  651. #ifdef CONFIG_ALTIVEC
  652. /* Note that the AltiVec support is closely modeled after the FP
  653. * support. Changes to one are likely to be applicable to the
  654. * other! */
  655. load_up_altivec:
  656. /*
  657. * Disable AltiVec for the task which had AltiVec previously,
  658. * and save its AltiVec registers in its thread_struct.
  659. * Enables AltiVec for use in the kernel on return.
  660. * On SMP we know the AltiVec units are free, since we give it up every
  661. * switch. -- Kumar
  662. */
  663. mfmsr r5
  664. oris r5,r5,MSR_VEC@h
  665. MTMSRD(r5) /* enable use of AltiVec now */
  666. isync
  667. /*
  668. * For SMP, we don't do lazy AltiVec switching because it just gets too
  669. * horrendously complex, especially when a task switches from one CPU
  670. * to another. Instead we call giveup_altivec in switch_to.
  671. */
  672. #ifndef CONFIG_SMP
  673. tophys(r6,0)
  674. addis r3,r6,last_task_used_altivec@ha
  675. lwz r4,last_task_used_altivec@l(r3)
  676. cmpwi 0,r4,0
  677. beq 1f
  678. add r4,r4,r6
  679. addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
  680. SAVE_32VRS(0,r10,r4)
  681. mfvscr vr0
  682. li r10,THREAD_VSCR
  683. stvx vr0,r10,r4
  684. lwz r5,PT_REGS(r4)
  685. add r5,r5,r6
  686. lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
  687. lis r10,MSR_VEC@h
  688. andc r4,r4,r10 /* disable altivec for previous task */
  689. stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
  690. 1:
  691. #endif /* CONFIG_SMP */
  692. /* enable use of AltiVec after return */
  693. oris r9,r9,MSR_VEC@h
  694. mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
  695. li r4,1
  696. li r10,THREAD_VSCR
  697. stw r4,THREAD_USED_VR(r5)
  698. lvx vr0,r10,r5
  699. mtvscr vr0
  700. REST_32VRS(0,r10,r5)
  701. #ifndef CONFIG_SMP
  702. subi r4,r5,THREAD
  703. sub r4,r4,r6
  704. stw r4,last_task_used_altivec@l(r3)
  705. #endif /* CONFIG_SMP */
  706. /* restore registers and return */
  707. /* we haven't used ctr or xer or lr */
  708. b fast_exception_return
  709. /*
  710. * AltiVec unavailable trap from kernel - print a message, but let
  711. * the task use AltiVec in the kernel until it returns to user mode.
  712. */
  713. KernelAltiVec:
  714. lwz r3,_MSR(r1)
  715. oris r3,r3,MSR_VEC@h
  716. stw r3,_MSR(r1) /* enable use of AltiVec after return */
  717. lis r3,87f@h
  718. ori r3,r3,87f@l
  719. mr r4,r2 /* current */
  720. lwz r5,_NIP(r1)
  721. bl printk
  722. b ret_from_except
  723. 87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
  724. .align 4,0
  725. /*
  726. * giveup_altivec(tsk)
  727. * Disable AltiVec for the task given as the argument,
  728. * and save the AltiVec registers in its thread_struct.
  729. * Enables AltiVec for use in the kernel on return.
  730. */
  731. .globl giveup_altivec
  732. giveup_altivec:
  733. mfmsr r5
  734. oris r5,r5,MSR_VEC@h
  735. SYNC
  736. MTMSRD(r5) /* enable use of AltiVec now */
  737. isync
  738. cmpwi 0,r3,0
  739. beqlr- /* if no previous owner, done */
  740. addi r3,r3,THREAD /* want THREAD of task */
  741. lwz r5,PT_REGS(r3)
  742. cmpwi 0,r5,0
  743. SAVE_32VRS(0, r4, r3)
  744. mfvscr vr0
  745. li r4,THREAD_VSCR
  746. stvx vr0,r4,r3
  747. beq 1f
  748. lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
  749. lis r3,MSR_VEC@h
  750. andc r4,r4,r3 /* disable AltiVec for previous task */
  751. stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
  752. 1:
  753. #ifndef CONFIG_SMP
  754. li r5,0
  755. lis r4,last_task_used_altivec@ha
  756. stw r5,last_task_used_altivec@l(r4)
  757. #endif /* CONFIG_SMP */
  758. blr
  759. #endif /* CONFIG_ALTIVEC */
  760. /*
  761. * This code is jumped to from the startup code to copy
  762. * the kernel image to physical address 0.
  763. */
  764. relocate_kernel:
  765. addis r9,r26,klimit@ha /* fetch klimit */
  766. lwz r25,klimit@l(r9)
  767. addis r25,r25,-KERNELBASE@h
  768. li r3,0 /* Destination base address */
  769. li r6,0 /* Destination offset */
  770. li r5,0x4000 /* # bytes of memory to copy */
  771. bl copy_and_flush /* copy the first 0x4000 bytes */
  772. addi r0,r3,4f@l /* jump to the address of 4f */
  773. mtctr r0 /* in copy and do the rest. */
  774. bctr /* jump to the copy */
  775. 4: mr r5,r25
  776. bl copy_and_flush /* copy the rest */
  777. b turn_on_mmu
  778. /*
  779. * Copy routine used to copy the kernel to start at physical address 0
  780. * and flush and invalidate the caches as needed.
  781. * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
  782. * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
  783. */
  784. _GLOBAL(copy_and_flush)
  785. addi r5,r5,-4
  786. addi r6,r6,-4
  787. 4: li r0,L1_CACHE_BYTES/4
  788. mtctr r0
  789. 3: addi r6,r6,4 /* copy a cache line */
  790. lwzx r0,r6,r4
  791. stwx r0,r6,r3
  792. bdnz 3b
  793. dcbst r6,r3 /* write it to memory */
  794. sync
  795. icbi r6,r3 /* flush the icache line */
  796. cmplw 0,r6,r5
  797. blt 4b
  798. sync /* additional sync needed on g4 */
  799. isync
  800. addi r5,r5,4
  801. addi r6,r6,4
  802. blr
  803. #ifdef CONFIG_APUS
  804. /*
  805. * On APUS the physical base address of the kernel is not known at compile
  806. * time, which means the __pa/__va constants used are incorrect. In the
  807. * __init section is recorded the virtual addresses of instructions using
  808. * these constants, so all that has to be done is fix these before
  809. * continuing the kernel boot.
  810. *
  811. * r4 = The physical address of the kernel base.
  812. */
  813. fix_mem_constants:
  814. mr r10,r4
  815. addis r10,r10,-KERNELBASE@h /* virt_to_phys constant */
  816. neg r11,r10 /* phys_to_virt constant */
  817. lis r12,__vtop_table_begin@h
  818. ori r12,r12,__vtop_table_begin@l
  819. add r12,r12,r10 /* table begin phys address */
  820. lis r13,__vtop_table_end@h
  821. ori r13,r13,__vtop_table_end@l
  822. add r13,r13,r10 /* table end phys address */
  823. subi r12,r12,4
  824. subi r13,r13,4
  825. 1: lwzu r14,4(r12) /* virt address of instruction */
  826. add r14,r14,r10 /* phys address of instruction */
  827. lwz r15,0(r14) /* instruction, now insert top */
  828. rlwimi r15,r10,16,16,31 /* half of vp const in low half */
  829. stw r15,0(r14) /* of instruction and restore. */
  830. dcbst r0,r14 /* write it to memory */
  831. sync
  832. icbi r0,r14 /* flush the icache line */
  833. cmpw r12,r13
  834. bne 1b
  835. sync /* additional sync needed on g4 */
  836. isync
  837. /*
  838. * Map the memory where the exception handlers will
  839. * be copied to when hash constants have been patched.
  840. */
  841. #ifdef CONFIG_APUS_FAST_EXCEPT
  842. lis r8,0xfff0
  843. #else
  844. lis r8,0
  845. #endif
  846. ori r8,r8,0x2 /* 128KB, supervisor */
  847. mtspr SPRN_DBAT3U,r8
  848. mtspr SPRN_DBAT3L,r8
  849. lis r12,__ptov_table_begin@h
  850. ori r12,r12,__ptov_table_begin@l
  851. add r12,r12,r10 /* table begin phys address */
  852. lis r13,__ptov_table_end@h
  853. ori r13,r13,__ptov_table_end@l
  854. add r13,r13,r10 /* table end phys address */
  855. subi r12,r12,4
  856. subi r13,r13,4
  857. 1: lwzu r14,4(r12) /* virt address of instruction */
  858. add r14,r14,r10 /* phys address of instruction */
  859. lwz r15,0(r14) /* instruction, now insert top */
  860. rlwimi r15,r11,16,16,31 /* half of pv const in low half*/
  861. stw r15,0(r14) /* of instruction and restore. */
  862. dcbst r0,r14 /* write it to memory */
  863. sync
  864. icbi r0,r14 /* flush the icache line */
  865. cmpw r12,r13
  866. bne 1b
  867. sync /* additional sync needed on g4 */
  868. isync /* No speculative loading until now */
  869. blr
  870. /***********************************************************************
  871. * Please note that on APUS the exception handlers are located at the
  872. * physical address 0xfff0000. For this reason, the exception handlers
  873. * cannot use relative branches to access the code below.
  874. ***********************************************************************/
  875. #endif /* CONFIG_APUS */
  876. #ifdef CONFIG_SMP
  877. #ifdef CONFIG_GEMINI
  878. .globl __secondary_start_gemini
  879. __secondary_start_gemini:
  880. mfspr r4,SPRN_HID0
  881. ori r4,r4,HID0_ICFI
  882. li r3,0
  883. ori r3,r3,HID0_ICE
  884. andc r4,r4,r3
  885. mtspr SPRN_HID0,r4
  886. sync
  887. b __secondary_start
  888. #endif /* CONFIG_GEMINI */
  889. .globl __secondary_start_pmac_0
  890. __secondary_start_pmac_0:
  891. /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
  892. li r24,0
  893. b 1f
  894. li r24,1
  895. b 1f
  896. li r24,2
  897. b 1f
  898. li r24,3
  899. 1:
  900. /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
  901. set to map the 0xf0000000 - 0xffffffff region */
  902. mfmsr r0
  903. rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
  904. SYNC
  905. mtmsr r0
  906. isync
  907. .globl __secondary_start
  908. __secondary_start:
  909. /* Copy some CPU settings from CPU 0 */
  910. bl __restore_cpu_setup
  911. lis r3,-KERNELBASE@h
  912. mr r4,r24
  913. bl call_setup_cpu /* Call setup_cpu for this CPU */
  914. #ifdef CONFIG_6xx
  915. lis r3,-KERNELBASE@h
  916. bl init_idle_6xx
  917. #endif /* CONFIG_6xx */
  918. /* get current_thread_info and current */
  919. lis r1,secondary_ti@ha
  920. tophys(r1,r1)
  921. lwz r1,secondary_ti@l(r1)
  922. tophys(r2,r1)
  923. lwz r2,TI_TASK(r2)
  924. /* stack */
  925. addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
  926. li r0,0
  927. tophys(r3,r1)
  928. stw r0,0(r3)
  929. /* load up the MMU */
  930. bl load_up_mmu
  931. /* ptr to phys current thread */
  932. tophys(r4,r2)
  933. addi r4,r4,THREAD /* phys address of our thread_struct */
  934. CLR_TOP32(r4)
  935. mtspr SPRN_SPRG3,r4
  936. li r3,0
  937. mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
  938. /* enable MMU and jump to start_secondary */
  939. li r4,MSR_KERNEL
  940. FIX_SRR1(r4,r5)
  941. lis r3,start_secondary@h
  942. ori r3,r3,start_secondary@l
  943. mtspr SPRN_SRR0,r3
  944. mtspr SPRN_SRR1,r4
  945. SYNC
  946. RFI
  947. #endif /* CONFIG_SMP */
  948. /*
  949. * Those generic dummy functions are kept for CPUs not
  950. * included in CONFIG_6xx
  951. */
  952. #if !defined(CONFIG_6xx)
  953. _GLOBAL(__save_cpu_setup)
  954. blr
  955. _GLOBAL(__restore_cpu_setup)
  956. blr
  957. #endif /* !defined(CONFIG_6xx) */
  958. /*
  959. * Load stuff into the MMU. Intended to be called with
  960. * IR=0 and DR=0.
  961. */
  962. load_up_mmu:
  963. sync /* Force all PTE updates to finish */
  964. isync
  965. tlbia /* Clear all TLB entries */
  966. sync /* wait for tlbia/tlbie to finish */
  967. TLBSYNC /* ... on all CPUs */
  968. /* Load the SDR1 register (hash table base & size) */
  969. lis r6,_SDR1@ha
  970. tophys(r6,r6)
  971. lwz r6,_SDR1@l(r6)
  972. mtspr SPRN_SDR1,r6
  973. li r0,16 /* load up segment register values */
  974. mtctr r0 /* for context 0 */
  975. lis r3,0x2000 /* Ku = 1, VSID = 0 */
  976. li r4,0
  977. 3: mtsrin r3,r4
  978. addi r3,r3,0x111 /* increment VSID */
  979. addis r4,r4,0x1000 /* address of next segment */
  980. bdnz 3b
  981. /* Load the BAT registers with the values set up by MMU_init.
  982. MMU_init takes care of whether we're on a 601 or not. */
  983. mfpvr r3
  984. srwi r3,r3,16
  985. cmpwi r3,1
  986. lis r3,BATS@ha
  987. addi r3,r3,BATS@l
  988. tophys(r3,r3)
  989. LOAD_BAT(0,r3,r4,r5)
  990. LOAD_BAT(1,r3,r4,r5)
  991. LOAD_BAT(2,r3,r4,r5)
  992. LOAD_BAT(3,r3,r4,r5)
  993. blr
  994. /*
  995. * This is where the main kernel code starts.
  996. */
  997. start_here:
  998. /* ptr to current */
  999. lis r2,init_task@h
  1000. ori r2,r2,init_task@l
  1001. /* Set up for using our exception vectors */
  1002. /* ptr to phys current thread */
  1003. tophys(r4,r2)
  1004. addi r4,r4,THREAD /* init task's THREAD */
  1005. CLR_TOP32(r4)
  1006. mtspr SPRN_SPRG3,r4
  1007. li r3,0
  1008. mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
  1009. /* stack */
  1010. lis r1,init_thread_union@ha
  1011. addi r1,r1,init_thread_union@l
  1012. li r0,0
  1013. stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
  1014. /*
  1015. * Do early platform-specific initialization,
  1016. * and set up the MMU.
  1017. */
  1018. mr r3,r31
  1019. mr r4,r30
  1020. bl machine_init
  1021. bl __save_cpu_setup
  1022. bl MMU_init
  1023. #ifdef CONFIG_APUS
  1024. /* Copy exception code to exception vector base on APUS. */
  1025. lis r4,KERNELBASE@h
  1026. #ifdef CONFIG_APUS_FAST_EXCEPT
  1027. lis r3,0xfff0 /* Copy to 0xfff00000 */
  1028. #else
  1029. lis r3,0 /* Copy to 0x00000000 */
  1030. #endif
  1031. li r5,0x4000 /* # bytes of memory to copy */
  1032. li r6,0
  1033. bl copy_and_flush /* copy the first 0x4000 bytes */
  1034. #endif /* CONFIG_APUS */
  1035. /*
  1036. * Go back to running unmapped so we can load up new values
  1037. * for SDR1 (hash table pointer) and the segment registers
  1038. * and change to using our exception vectors.
  1039. */
  1040. lis r4,2f@h
  1041. ori r4,r4,2f@l
  1042. tophys(r4,r4)
  1043. li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
  1044. FIX_SRR1(r3,r5)
  1045. mtspr SPRN_SRR0,r4
  1046. mtspr SPRN_SRR1,r3
  1047. SYNC
  1048. RFI
  1049. /* Load up the kernel context */
  1050. 2: bl load_up_mmu
  1051. #ifdef CONFIG_BDI_SWITCH
  1052. /* Add helper information for the Abatron bdiGDB debugger.
  1053. * We do this here because we know the mmu is disabled, and
  1054. * will be enabled for real in just a few instructions.
  1055. */
  1056. lis r5, abatron_pteptrs@h
  1057. ori r5, r5, abatron_pteptrs@l
  1058. stw r5, 0xf0(r0) /* This much match your Abatron config */
  1059. lis r6, swapper_pg_dir@h
  1060. ori r6, r6, swapper_pg_dir@l
  1061. tophys(r5, r5)
  1062. stw r6, 0(r5)
  1063. #endif /* CONFIG_BDI_SWITCH */
  1064. /* Now turn on the MMU for real! */
  1065. li r4,MSR_KERNEL
  1066. FIX_SRR1(r4,r5)
  1067. lis r3,start_kernel@h
  1068. ori r3,r3,start_kernel@l
  1069. mtspr SPRN_SRR0,r3
  1070. mtspr SPRN_SRR1,r4
  1071. SYNC
  1072. RFI
  1073. /*
  1074. * Set up the segment registers for a new context.
  1075. */
  1076. _GLOBAL(set_context)
  1077. mulli r3,r3,897 /* multiply context by skew factor */
  1078. rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
  1079. addis r3,r3,0x6000 /* Set Ks, Ku bits */
  1080. li r0,NUM_USER_SEGMENTS
  1081. mtctr r0
  1082. #ifdef CONFIG_BDI_SWITCH
  1083. /* Context switch the PTE pointer for the Abatron BDI2000.
  1084. * The PGDIR is passed as second argument.
  1085. */
  1086. lis r5, KERNELBASE@h
  1087. lwz r5, 0xf0(r5)
  1088. stw r4, 0x4(r5)
  1089. #endif
  1090. li r4,0
  1091. isync
  1092. 3:
  1093. mtsrin r3,r4
  1094. addi r3,r3,0x111 /* next VSID */
  1095. rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
  1096. addis r4,r4,0x1000 /* address of next segment */
  1097. bdnz 3b
  1098. sync
  1099. isync
  1100. blr
  1101. /*
  1102. * An undocumented "feature" of 604e requires that the v bit
  1103. * be cleared before changing BAT values.
  1104. *
  1105. * Also, newer IBM firmware does not clear bat3 and 4 so
  1106. * this makes sure it's done.
  1107. * -- Cort
  1108. */
  1109. clear_bats:
  1110. li r10,0
  1111. mfspr r9,SPRN_PVR
  1112. rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
  1113. cmpwi r9, 1
  1114. beq 1f
  1115. mtspr SPRN_DBAT0U,r10
  1116. mtspr SPRN_DBAT0L,r10
  1117. mtspr SPRN_DBAT1U,r10
  1118. mtspr SPRN_DBAT1L,r10
  1119. mtspr SPRN_DBAT2U,r10
  1120. mtspr SPRN_DBAT2L,r10
  1121. mtspr SPRN_DBAT3U,r10
  1122. mtspr SPRN_DBAT3L,r10
  1123. 1:
  1124. mtspr SPRN_IBAT0U,r10
  1125. mtspr SPRN_IBAT0L,r10
  1126. mtspr SPRN_IBAT1U,r10
  1127. mtspr SPRN_IBAT1L,r10
  1128. mtspr SPRN_IBAT2U,r10
  1129. mtspr SPRN_IBAT2L,r10
  1130. mtspr SPRN_IBAT3U,r10
  1131. mtspr SPRN_IBAT3L,r10
  1132. BEGIN_FTR_SECTION
  1133. /* Here's a tweak: at this point, CPU setup have
  1134. * not been called yet, so HIGH_BAT_EN may not be
  1135. * set in HID0 for the 745x processors. However, it
  1136. * seems that doesn't affect our ability to actually
  1137. * write to these SPRs.
  1138. */
  1139. mtspr SPRN_DBAT4U,r10
  1140. mtspr SPRN_DBAT4L,r10
  1141. mtspr SPRN_DBAT5U,r10
  1142. mtspr SPRN_DBAT5L,r10
  1143. mtspr SPRN_DBAT6U,r10
  1144. mtspr SPRN_DBAT6L,r10
  1145. mtspr SPRN_DBAT7U,r10
  1146. mtspr SPRN_DBAT7L,r10
  1147. mtspr SPRN_IBAT4U,r10
  1148. mtspr SPRN_IBAT4L,r10
  1149. mtspr SPRN_IBAT5U,r10
  1150. mtspr SPRN_IBAT5L,r10
  1151. mtspr SPRN_IBAT6U,r10
  1152. mtspr SPRN_IBAT6L,r10
  1153. mtspr SPRN_IBAT7U,r10
  1154. mtspr SPRN_IBAT7L,r10
  1155. END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
  1156. blr
  1157. flush_tlbs:
  1158. lis r10, 0x40
  1159. 1: addic. r10, r10, -0x1000
  1160. tlbie r10
  1161. blt 1b
  1162. sync
  1163. blr
  1164. mmu_off:
  1165. addi r4, r3, __after_mmu_off - _start
  1166. mfmsr r3
  1167. andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
  1168. beqlr
  1169. andc r3,r3,r0
  1170. mtspr SPRN_SRR0,r4
  1171. mtspr SPRN_SRR1,r3
  1172. sync
  1173. RFI
  1174. /*
  1175. * Use the first pair of BAT registers to map the 1st 16MB
  1176. * of RAM to KERNELBASE. From this point on we can't safely
  1177. * call OF any more.
  1178. */
  1179. initial_bats:
  1180. lis r11,KERNELBASE@h
  1181. mfspr r9,SPRN_PVR
  1182. rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
  1183. cmpwi 0,r9,1
  1184. bne 4f
  1185. ori r11,r11,4 /* set up BAT registers for 601 */
  1186. li r8,0x7f /* valid, block length = 8MB */
  1187. oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
  1188. oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
  1189. mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
  1190. mtspr SPRN_IBAT0L,r8 /* lower BAT register */
  1191. mtspr SPRN_IBAT1U,r9
  1192. mtspr SPRN_IBAT1L,r10
  1193. isync
  1194. blr
  1195. 4: tophys(r8,r11)
  1196. #ifdef CONFIG_SMP
  1197. ori r8,r8,0x12 /* R/W access, M=1 */
  1198. #else
  1199. ori r8,r8,2 /* R/W access */
  1200. #endif /* CONFIG_SMP */
  1201. #ifdef CONFIG_APUS
  1202. ori r11,r11,BL_8M<<2|0x2 /* set up 8MB BAT registers for 604 */
  1203. #else
  1204. ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
  1205. #endif /* CONFIG_APUS */
  1206. mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
  1207. mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
  1208. mtspr SPRN_IBAT0L,r8
  1209. mtspr SPRN_IBAT0U,r11
  1210. isync
  1211. blr
  1212. #ifdef CONFIG_8260
  1213. /* Jump into the system reset for the rom.
  1214. * We first disable the MMU, and then jump to the ROM reset address.
  1215. *
  1216. * r3 is the board info structure, r4 is the location for starting.
  1217. * I use this for building a small kernel that can load other kernels,
  1218. * rather than trying to write or rely on a rom monitor that can tftp load.
  1219. */
  1220. .globl m8260_gorom
  1221. m8260_gorom:
  1222. mfmsr r0
  1223. rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
  1224. sync
  1225. mtmsr r0
  1226. sync
  1227. mfspr r11, SPRN_HID0
  1228. lis r10, 0
  1229. ori r10,r10,HID0_ICE|HID0_DCE
  1230. andc r11, r11, r10
  1231. mtspr SPRN_HID0, r11
  1232. isync
  1233. li r5, MSR_ME|MSR_RI
  1234. lis r6,2f@h
  1235. addis r6,r6,-KERNELBASE@h
  1236. ori r6,r6,2f@l
  1237. mtspr SPRN_SRR0,r6
  1238. mtspr SPRN_SRR1,r5
  1239. isync
  1240. sync
  1241. rfi
  1242. 2:
  1243. mtlr r4
  1244. blr
  1245. #endif
  1246. /*
  1247. * We put a few things here that have to be page-aligned.
  1248. * This stuff goes at the beginning of the data segment,
  1249. * which is page-aligned.
  1250. */
  1251. .data
  1252. .globl sdata
  1253. sdata:
  1254. .globl empty_zero_page
  1255. empty_zero_page:
  1256. .space 4096
  1257. .globl swapper_pg_dir
  1258. swapper_pg_dir:
  1259. .space 4096
  1260. /*
  1261. * This space gets a copy of optional info passed to us by the bootstrap
  1262. * Used to pass parameters into the kernel like root=/dev/sda1, etc.
  1263. */
  1264. .globl cmd_line
  1265. cmd_line:
  1266. .space 512
  1267. .globl intercept_table
  1268. intercept_table:
  1269. .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
  1270. .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
  1271. .long 0, 0, 0, i0x1300, 0, 0, 0, 0
  1272. .long 0, 0, 0, 0, 0, 0, 0, 0
  1273. .long 0, 0, 0, 0, 0, 0, 0, 0
  1274. .long 0, 0, 0, 0, 0, 0, 0, 0
  1275. /* Room for two PTE pointers, usually the kernel and current user pointers
  1276. * to their respective root page table.
  1277. */
  1278. abatron_pteptrs:
  1279. .space 8