mainstone.c 11 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/mainstone.c
  3. *
  4. * Support for the Intel HCDDBBVA0 Development Platform.
  5. * (go figure how they came up with such name...)
  6. *
  7. * Author: Nicolas Pitre
  8. * Created: Nov 05, 2002
  9. * Copyright: MontaVista Software Inc.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/sysdev.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/sched.h>
  20. #include <linux/bitops.h>
  21. #include <linux/fb.h>
  22. #include <linux/ioport.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <asm/types.h>
  26. #include <asm/setup.h>
  27. #include <asm/memory.h>
  28. #include <asm/mach-types.h>
  29. #include <asm/hardware.h>
  30. #include <asm/irq.h>
  31. #include <asm/sizes.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/mach/map.h>
  34. #include <asm/mach/irq.h>
  35. #include <asm/mach/flash.h>
  36. #include <asm/arch/pxa-regs.h>
  37. #include <asm/arch/mainstone.h>
  38. #include <asm/arch/audio.h>
  39. #include <asm/arch/pxafb.h>
  40. #include <asm/arch/mmc.h>
  41. #include <asm/arch/irda.h>
  42. #include "generic.h"
  43. static unsigned long mainstone_irq_enabled;
  44. static void mainstone_mask_irq(unsigned int irq)
  45. {
  46. int mainstone_irq = (irq - MAINSTONE_IRQ(0));
  47. MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
  48. }
  49. static void mainstone_unmask_irq(unsigned int irq)
  50. {
  51. int mainstone_irq = (irq - MAINSTONE_IRQ(0));
  52. /* the irq can be acknowledged only if deasserted, so it's done here */
  53. MST_INTSETCLR &= ~(1 << mainstone_irq);
  54. MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
  55. }
  56. static struct irqchip mainstone_irq_chip = {
  57. .ack = mainstone_mask_irq,
  58. .mask = mainstone_mask_irq,
  59. .unmask = mainstone_unmask_irq,
  60. };
  61. static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc,
  62. struct pt_regs *regs)
  63. {
  64. unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
  65. do {
  66. GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
  67. if (likely(pending)) {
  68. irq = MAINSTONE_IRQ(0) + __ffs(pending);
  69. desc = irq_desc + irq;
  70. desc_handle_irq(irq, desc, regs);
  71. }
  72. pending = MST_INTSETCLR & mainstone_irq_enabled;
  73. } while (pending);
  74. }
  75. static void __init mainstone_init_irq(void)
  76. {
  77. int irq;
  78. pxa_init_irq();
  79. /* setup extra Mainstone irqs */
  80. for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
  81. set_irq_chip(irq, &mainstone_irq_chip);
  82. set_irq_handler(irq, do_level_IRQ);
  83. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  84. }
  85. set_irq_flags(MAINSTONE_IRQ(8), 0);
  86. set_irq_flags(MAINSTONE_IRQ(12), 0);
  87. MST_INTMSKENA = 0;
  88. MST_INTSETCLR = 0;
  89. set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
  90. set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
  91. }
  92. #ifdef CONFIG_PM
  93. static int mainstone_irq_resume(struct sys_device *dev)
  94. {
  95. MST_INTMSKENA = mainstone_irq_enabled;
  96. return 0;
  97. }
  98. static struct sysdev_class mainstone_irq_sysclass = {
  99. set_kset_name("cpld_irq"),
  100. .resume = mainstone_irq_resume,
  101. };
  102. static struct sys_device mainstone_irq_device = {
  103. .cls = &mainstone_irq_sysclass,
  104. };
  105. static int __init mainstone_irq_device_init(void)
  106. {
  107. int ret = sysdev_class_register(&mainstone_irq_sysclass);
  108. if (ret == 0)
  109. ret = sysdev_register(&mainstone_irq_device);
  110. return ret;
  111. }
  112. device_initcall(mainstone_irq_device_init);
  113. #endif
  114. static struct resource smc91x_resources[] = {
  115. [0] = {
  116. .start = (MST_ETH_PHYS + 0x300),
  117. .end = (MST_ETH_PHYS + 0xfffff),
  118. .flags = IORESOURCE_MEM,
  119. },
  120. [1] = {
  121. .start = MAINSTONE_IRQ(3),
  122. .end = MAINSTONE_IRQ(3),
  123. .flags = IORESOURCE_IRQ,
  124. }
  125. };
  126. static struct platform_device smc91x_device = {
  127. .name = "smc91x",
  128. .id = 0,
  129. .num_resources = ARRAY_SIZE(smc91x_resources),
  130. .resource = smc91x_resources,
  131. };
  132. static int mst_audio_startup(snd_pcm_substream_t *substream, void *priv)
  133. {
  134. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  135. MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
  136. return 0;
  137. }
  138. static void mst_audio_shutdown(snd_pcm_substream_t *substream, void *priv)
  139. {
  140. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  141. MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
  142. }
  143. static long mst_audio_suspend_mask;
  144. static void mst_audio_suspend(void *priv)
  145. {
  146. mst_audio_suspend_mask = MST_MSCWR2;
  147. MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
  148. }
  149. static void mst_audio_resume(void *priv)
  150. {
  151. MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
  152. }
  153. static pxa2xx_audio_ops_t mst_audio_ops = {
  154. .startup = mst_audio_startup,
  155. .shutdown = mst_audio_shutdown,
  156. .suspend = mst_audio_suspend,
  157. .resume = mst_audio_resume,
  158. };
  159. static struct platform_device mst_audio_device = {
  160. .name = "pxa2xx-ac97",
  161. .id = -1,
  162. .dev = { .platform_data = &mst_audio_ops },
  163. };
  164. static struct resource flash_resources[] = {
  165. [0] = {
  166. .start = PXA_CS0_PHYS,
  167. .end = PXA_CS0_PHYS + SZ_64M - 1,
  168. .flags = IORESOURCE_MEM,
  169. },
  170. [1] = {
  171. .start = PXA_CS1_PHYS,
  172. .end = PXA_CS1_PHYS + SZ_64M - 1,
  173. .flags = IORESOURCE_MEM,
  174. },
  175. };
  176. static struct mtd_partition mainstoneflash0_partitions[] = {
  177. {
  178. .name = "Bootloader",
  179. .size = 0x00040000,
  180. .offset = 0,
  181. .mask_flags = MTD_WRITEABLE /* force read-only */
  182. },{
  183. .name = "Kernel",
  184. .size = 0x00400000,
  185. .offset = 0x00040000,
  186. },{
  187. .name = "Filesystem",
  188. .size = MTDPART_SIZ_FULL,
  189. .offset = 0x00440000
  190. }
  191. };
  192. static struct flash_platform_data mst_flash_data[2] = {
  193. {
  194. .map_name = "cfi_probe",
  195. .parts = mainstoneflash0_partitions,
  196. .nr_parts = ARRAY_SIZE(mainstoneflash0_partitions),
  197. }, {
  198. .map_name = "cfi_probe",
  199. .parts = NULL,
  200. .nr_parts = 0,
  201. }
  202. };
  203. static struct platform_device mst_flash_device[2] = {
  204. {
  205. .name = "pxa2xx-flash",
  206. .id = 0,
  207. .dev = {
  208. .platform_data = &mst_flash_data[0],
  209. },
  210. .resource = &flash_resources[0],
  211. .num_resources = 1,
  212. },
  213. {
  214. .name = "pxa2xx-flash",
  215. .id = 1,
  216. .dev = {
  217. .platform_data = &mst_flash_data[1],
  218. },
  219. .resource = &flash_resources[1],
  220. .num_resources = 1,
  221. },
  222. };
  223. static void mainstone_backlight_power(int on)
  224. {
  225. if (on) {
  226. pxa_gpio_mode(GPIO16_PWM0_MD);
  227. pxa_set_cken(CKEN0_PWM0, 1);
  228. PWM_CTRL0 = 0;
  229. PWM_PWDUTY0 = 0x3ff;
  230. PWM_PERVAL0 = 0x3ff;
  231. } else {
  232. PWM_CTRL0 = 0;
  233. PWM_PWDUTY0 = 0x0;
  234. PWM_PERVAL0 = 0x3FF;
  235. pxa_set_cken(CKEN0_PWM0, 0);
  236. }
  237. }
  238. static struct pxafb_mach_info toshiba_ltm04c380k __initdata = {
  239. .pixclock = 50000,
  240. .xres = 640,
  241. .yres = 480,
  242. .bpp = 16,
  243. .hsync_len = 1,
  244. .left_margin = 0x9f,
  245. .right_margin = 1,
  246. .vsync_len = 44,
  247. .upper_margin = 0,
  248. .lower_margin = 0,
  249. .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
  250. .lccr0 = LCCR0_Act,
  251. .lccr3 = LCCR3_PCP,
  252. .pxafb_backlight_power = mainstone_backlight_power,
  253. };
  254. static struct pxafb_mach_info toshiba_ltm035a776c __initdata = {
  255. .pixclock = 110000,
  256. .xres = 240,
  257. .yres = 320,
  258. .bpp = 16,
  259. .hsync_len = 4,
  260. .left_margin = 8,
  261. .right_margin = 20,
  262. .vsync_len = 3,
  263. .upper_margin = 1,
  264. .lower_margin = 10,
  265. .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
  266. .lccr0 = LCCR0_Act,
  267. .lccr3 = LCCR3_PCP,
  268. .pxafb_backlight_power = mainstone_backlight_power,
  269. };
  270. static int mainstone_mci_init(struct device *dev, irqreturn_t (*mstone_detect_int)(int, void *, struct pt_regs *), void *data)
  271. {
  272. int err;
  273. /*
  274. * setup GPIO for PXA27x MMC controller
  275. */
  276. pxa_gpio_mode(GPIO32_MMCCLK_MD);
  277. pxa_gpio_mode(GPIO112_MMCCMD_MD);
  278. pxa_gpio_mode(GPIO92_MMCDAT0_MD);
  279. pxa_gpio_mode(GPIO109_MMCDAT1_MD);
  280. pxa_gpio_mode(GPIO110_MMCDAT2_MD);
  281. pxa_gpio_mode(GPIO111_MMCDAT3_MD);
  282. /* make sure SD/Memory Stick multiplexer's signals
  283. * are routed to MMC controller
  284. */
  285. MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
  286. err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, SA_INTERRUPT,
  287. "MMC card detect", data);
  288. if (err) {
  289. printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
  290. return -1;
  291. }
  292. return 0;
  293. }
  294. static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
  295. {
  296. struct pxamci_platform_data* p_d = dev->platform_data;
  297. if (( 1 << vdd) & p_d->ocr_mask) {
  298. printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
  299. MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
  300. MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
  301. } else {
  302. printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
  303. MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
  304. }
  305. }
  306. static void mainstone_mci_exit(struct device *dev, void *data)
  307. {
  308. free_irq(MAINSTONE_MMC_IRQ, data);
  309. }
  310. static struct pxamci_platform_data mainstone_mci_platform_data = {
  311. .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
  312. .init = mainstone_mci_init,
  313. .setpower = mainstone_mci_setpower,
  314. .exit = mainstone_mci_exit,
  315. };
  316. static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
  317. {
  318. unsigned long flags;
  319. local_irq_save(flags);
  320. if (mode & IR_SIRMODE) {
  321. MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
  322. } else if (mode & IR_FIRMODE) {
  323. MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
  324. }
  325. if (mode & IR_OFF) {
  326. MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
  327. } else {
  328. MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
  329. }
  330. local_irq_restore(flags);
  331. }
  332. static struct pxaficp_platform_data mainstone_ficp_platform_data = {
  333. .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
  334. .transceiver_mode = mainstone_irda_transceiver_mode,
  335. };
  336. static struct platform_device *platform_devices[] __initdata = {
  337. &smc91x_device,
  338. &mst_audio_device,
  339. &mst_flash_device[0],
  340. &mst_flash_device[1],
  341. };
  342. static void __init mainstone_init(void)
  343. {
  344. int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
  345. mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
  346. mst_flash_data[1].width = 4;
  347. /* Compensate for SW7 which swaps the flash banks */
  348. mst_flash_data[SW7].name = "processor-flash";
  349. mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
  350. printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
  351. mst_flash_data[0].name);
  352. /*
  353. * On Mainstone, we route AC97_SYSCLK via GPIO45 to
  354. * the audio daughter card
  355. */
  356. pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
  357. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  358. /* reading Mainstone's "Virtual Configuration Register"
  359. might be handy to select LCD type here */
  360. if (0)
  361. set_pxa_fb_info(&toshiba_ltm04c380k);
  362. else
  363. set_pxa_fb_info(&toshiba_ltm035a776c);
  364. pxa_set_mci_info(&mainstone_mci_platform_data);
  365. pxa_set_ficp_info(&mainstone_ficp_platform_data);
  366. }
  367. static struct map_desc mainstone_io_desc[] __initdata = {
  368. { /* CPLD */
  369. .virtual = MST_FPGA_VIRT,
  370. .pfn = __phys_to_pfn(MST_FPGA_PHYS),
  371. .length = 0x00100000,
  372. .type = MT_DEVICE
  373. }
  374. };
  375. static void __init mainstone_map_io(void)
  376. {
  377. pxa_map_io();
  378. iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
  379. /* initialize sleep mode regs (wake-up sources, etc) */
  380. PGSR0 = 0x00008800;
  381. PGSR1 = 0x00000002;
  382. PGSR2 = 0x0001FC00;
  383. PGSR3 = 0x00001F81;
  384. PWER = 0xC0000002;
  385. PRER = 0x00000002;
  386. PFER = 0x00000002;
  387. /* for use I SRAM as framebuffer. */
  388. PSLR |= 0xF04;
  389. PCFR = 0x66;
  390. /* For Keypad wakeup. */
  391. KPC &=~KPC_ASACT;
  392. KPC |=KPC_AS;
  393. PKWR = 0x000FD000;
  394. /* Need read PKWR back after set it. */
  395. PKWR;
  396. }
  397. MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
  398. /* Maintainer: MontaVista Software Inc. */
  399. .phys_ram = 0xa0000000,
  400. .phys_io = 0x40000000,
  401. .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
  402. .map_io = mainstone_map_io,
  403. .init_irq = mainstone_init_irq,
  404. .timer = &pxa_timer,
  405. .init_machine = mainstone_init,
  406. MACHINE_END