cx23885-cards.c 45 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/delay.h>
  25. #include <media/cx25840.h>
  26. #include <linux/firmware.h>
  27. #include <misc/altera.h>
  28. #include "cx23885.h"
  29. #include "tuner-xc2028.h"
  30. #include "netup-eeprom.h"
  31. #include "netup-init.h"
  32. #include "altera-ci.h"
  33. #include "xc4000.h"
  34. #include "xc5000.h"
  35. #include "cx23888-ir.h"
  36. static unsigned int netup_card_rev = 1;
  37. module_param(netup_card_rev, int, 0644);
  38. MODULE_PARM_DESC(netup_card_rev,
  39. "NetUP Dual DVB-T/C CI card revision");
  40. static unsigned int enable_885_ir;
  41. module_param(enable_885_ir, int, 0644);
  42. MODULE_PARM_DESC(enable_885_ir,
  43. "Enable integrated IR controller for supported\n"
  44. "\t\t CX2388[57] boards that are wired for it:\n"
  45. "\t\t\tHVR-1250 (reported safe)\n"
  46. "\t\t\tTeVii S470 (reported unsafe)\n"
  47. "\t\t This can cause an interrupt storm with some cards.\n"
  48. "\t\t Default: 0 [Disabled]");
  49. /* ------------------------------------------------------------------ */
  50. /* board config info */
  51. struct cx23885_board cx23885_boards[] = {
  52. [CX23885_BOARD_UNKNOWN] = {
  53. .name = "UNKNOWN/GENERIC",
  54. /* Ensure safe default for unknown boards */
  55. .clk_freq = 0,
  56. .input = {{
  57. .type = CX23885_VMUX_COMPOSITE1,
  58. .vmux = 0,
  59. }, {
  60. .type = CX23885_VMUX_COMPOSITE2,
  61. .vmux = 1,
  62. }, {
  63. .type = CX23885_VMUX_COMPOSITE3,
  64. .vmux = 2,
  65. }, {
  66. .type = CX23885_VMUX_COMPOSITE4,
  67. .vmux = 3,
  68. } },
  69. },
  70. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  71. .name = "Hauppauge WinTV-HVR1800lp",
  72. .portc = CX23885_MPEG_DVB,
  73. .input = {{
  74. .type = CX23885_VMUX_TELEVISION,
  75. .vmux = 0,
  76. .gpio0 = 0xff00,
  77. }, {
  78. .type = CX23885_VMUX_DEBUG,
  79. .vmux = 0,
  80. .gpio0 = 0xff01,
  81. }, {
  82. .type = CX23885_VMUX_COMPOSITE1,
  83. .vmux = 1,
  84. .gpio0 = 0xff02,
  85. }, {
  86. .type = CX23885_VMUX_SVIDEO,
  87. .vmux = 2,
  88. .gpio0 = 0xff02,
  89. } },
  90. },
  91. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  92. .name = "Hauppauge WinTV-HVR1800",
  93. .porta = CX23885_ANALOG_VIDEO,
  94. .portb = CX23885_MPEG_ENCODER,
  95. .portc = CX23885_MPEG_DVB,
  96. .tuner_type = TUNER_PHILIPS_TDA8290,
  97. .tuner_addr = 0x42, /* 0x84 >> 1 */
  98. .tuner_bus = 1,
  99. .input = {{
  100. .type = CX23885_VMUX_TELEVISION,
  101. .vmux = CX25840_VIN7_CH3 |
  102. CX25840_VIN5_CH2 |
  103. CX25840_VIN2_CH1,
  104. .amux = CX25840_AUDIO8,
  105. .gpio0 = 0,
  106. }, {
  107. .type = CX23885_VMUX_COMPOSITE1,
  108. .vmux = CX25840_VIN7_CH3 |
  109. CX25840_VIN4_CH2 |
  110. CX25840_VIN6_CH1,
  111. .amux = CX25840_AUDIO7,
  112. .gpio0 = 0,
  113. }, {
  114. .type = CX23885_VMUX_SVIDEO,
  115. .vmux = CX25840_VIN7_CH3 |
  116. CX25840_VIN4_CH2 |
  117. CX25840_VIN8_CH1 |
  118. CX25840_SVIDEO_ON,
  119. .amux = CX25840_AUDIO7,
  120. .gpio0 = 0,
  121. } },
  122. },
  123. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  124. .name = "Hauppauge WinTV-HVR1250",
  125. .porta = CX23885_ANALOG_VIDEO,
  126. .portc = CX23885_MPEG_DVB,
  127. #ifdef MT2131_NO_ANALOG_SUPPORT_YET
  128. .tuner_type = TUNER_PHILIPS_TDA8290,
  129. .tuner_addr = 0x42, /* 0x84 >> 1 */
  130. .tuner_bus = 1,
  131. #endif
  132. .force_bff = 1,
  133. .input = {{
  134. #ifdef MT2131_NO_ANALOG_SUPPORT_YET
  135. .type = CX23885_VMUX_TELEVISION,
  136. .vmux = CX25840_VIN7_CH3 |
  137. CX25840_VIN5_CH2 |
  138. CX25840_VIN2_CH1,
  139. .amux = CX25840_AUDIO8,
  140. .gpio0 = 0xff00,
  141. }, {
  142. #endif
  143. .type = CX23885_VMUX_COMPOSITE1,
  144. .vmux = CX25840_VIN7_CH3 |
  145. CX25840_VIN4_CH2 |
  146. CX25840_VIN6_CH1,
  147. .amux = CX25840_AUDIO7,
  148. .gpio0 = 0xff02,
  149. }, {
  150. .type = CX23885_VMUX_SVIDEO,
  151. .vmux = CX25840_VIN7_CH3 |
  152. CX25840_VIN4_CH2 |
  153. CX25840_VIN8_CH1 |
  154. CX25840_SVIDEO_ON,
  155. .amux = CX25840_AUDIO7,
  156. .gpio0 = 0xff02,
  157. } },
  158. },
  159. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  160. .name = "DViCO FusionHDTV5 Express",
  161. .portb = CX23885_MPEG_DVB,
  162. },
  163. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  164. .name = "Hauppauge WinTV-HVR1500Q",
  165. .portc = CX23885_MPEG_DVB,
  166. },
  167. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  168. .name = "Hauppauge WinTV-HVR1500",
  169. .porta = CX23885_ANALOG_VIDEO,
  170. .portc = CX23885_MPEG_DVB,
  171. .tuner_type = TUNER_XC2028,
  172. .tuner_addr = 0x61, /* 0xc2 >> 1 */
  173. .input = {{
  174. .type = CX23885_VMUX_TELEVISION,
  175. .vmux = CX25840_VIN7_CH3 |
  176. CX25840_VIN5_CH2 |
  177. CX25840_VIN2_CH1,
  178. .gpio0 = 0,
  179. }, {
  180. .type = CX23885_VMUX_COMPOSITE1,
  181. .vmux = CX25840_VIN7_CH3 |
  182. CX25840_VIN4_CH2 |
  183. CX25840_VIN6_CH1,
  184. .gpio0 = 0,
  185. }, {
  186. .type = CX23885_VMUX_SVIDEO,
  187. .vmux = CX25840_VIN7_CH3 |
  188. CX25840_VIN4_CH2 |
  189. CX25840_VIN8_CH1 |
  190. CX25840_SVIDEO_ON,
  191. .gpio0 = 0,
  192. } },
  193. },
  194. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  195. .name = "Hauppauge WinTV-HVR1200",
  196. .portc = CX23885_MPEG_DVB,
  197. },
  198. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  199. .name = "Hauppauge WinTV-HVR1700",
  200. .portc = CX23885_MPEG_DVB,
  201. },
  202. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  203. .name = "Hauppauge WinTV-HVR1400",
  204. .portc = CX23885_MPEG_DVB,
  205. },
  206. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  207. .name = "DViCO FusionHDTV7 Dual Express",
  208. .portb = CX23885_MPEG_DVB,
  209. .portc = CX23885_MPEG_DVB,
  210. },
  211. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  212. .name = "DViCO FusionHDTV DVB-T Dual Express",
  213. .portb = CX23885_MPEG_DVB,
  214. .portc = CX23885_MPEG_DVB,
  215. },
  216. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  217. .name = "Leadtek Winfast PxDVR3200 H",
  218. .portc = CX23885_MPEG_DVB,
  219. },
  220. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
  221. .name = "Leadtek Winfast PxDVR3200 H XC4000",
  222. .porta = CX23885_ANALOG_VIDEO,
  223. .portc = CX23885_MPEG_DVB,
  224. .tuner_type = TUNER_XC4000,
  225. .tuner_addr = 0x61,
  226. .radio_type = UNSET,
  227. .radio_addr = ADDR_UNSET,
  228. .input = {{
  229. .type = CX23885_VMUX_TELEVISION,
  230. .vmux = CX25840_VIN2_CH1 |
  231. CX25840_VIN5_CH2 |
  232. CX25840_NONE0_CH3,
  233. }, {
  234. .type = CX23885_VMUX_COMPOSITE1,
  235. .vmux = CX25840_COMPOSITE1,
  236. }, {
  237. .type = CX23885_VMUX_SVIDEO,
  238. .vmux = CX25840_SVIDEO_LUMA3 |
  239. CX25840_SVIDEO_CHROMA4,
  240. }, {
  241. .type = CX23885_VMUX_COMPONENT,
  242. .vmux = CX25840_VIN7_CH1 |
  243. CX25840_VIN6_CH2 |
  244. CX25840_VIN8_CH3 |
  245. CX25840_COMPONENT_ON,
  246. } },
  247. },
  248. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  249. .name = "Compro VideoMate E650F",
  250. .portc = CX23885_MPEG_DVB,
  251. },
  252. [CX23885_BOARD_TBS_6920] = {
  253. .name = "TurboSight TBS 6920",
  254. .portb = CX23885_MPEG_DVB,
  255. },
  256. [CX23885_BOARD_TEVII_S470] = {
  257. .name = "TeVii S470",
  258. .portb = CX23885_MPEG_DVB,
  259. },
  260. [CX23885_BOARD_DVBWORLD_2005] = {
  261. .name = "DVBWorld DVB-S2 2005",
  262. .portb = CX23885_MPEG_DVB,
  263. },
  264. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  265. .ci_type = 1,
  266. .name = "NetUP Dual DVB-S2 CI",
  267. .portb = CX23885_MPEG_DVB,
  268. .portc = CX23885_MPEG_DVB,
  269. },
  270. [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
  271. .name = "Hauppauge WinTV-HVR1270",
  272. .portc = CX23885_MPEG_DVB,
  273. },
  274. [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
  275. .name = "Hauppauge WinTV-HVR1275",
  276. .portc = CX23885_MPEG_DVB,
  277. },
  278. [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
  279. .name = "Hauppauge WinTV-HVR1255",
  280. .portc = CX23885_MPEG_DVB,
  281. },
  282. [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
  283. .name = "Hauppauge WinTV-HVR1210",
  284. .portc = CX23885_MPEG_DVB,
  285. },
  286. [CX23885_BOARD_MYGICA_X8506] = {
  287. .name = "Mygica X8506 DMB-TH",
  288. .tuner_type = TUNER_XC5000,
  289. .tuner_addr = 0x61,
  290. .tuner_bus = 1,
  291. .porta = CX23885_ANALOG_VIDEO,
  292. .portb = CX23885_MPEG_DVB,
  293. .input = {
  294. {
  295. .type = CX23885_VMUX_TELEVISION,
  296. .vmux = CX25840_COMPOSITE2,
  297. },
  298. {
  299. .type = CX23885_VMUX_COMPOSITE1,
  300. .vmux = CX25840_COMPOSITE8,
  301. },
  302. {
  303. .type = CX23885_VMUX_SVIDEO,
  304. .vmux = CX25840_SVIDEO_LUMA3 |
  305. CX25840_SVIDEO_CHROMA4,
  306. },
  307. {
  308. .type = CX23885_VMUX_COMPONENT,
  309. .vmux = CX25840_COMPONENT_ON |
  310. CX25840_VIN1_CH1 |
  311. CX25840_VIN6_CH2 |
  312. CX25840_VIN7_CH3,
  313. },
  314. },
  315. },
  316. [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
  317. .name = "Magic-Pro ProHDTV Extreme 2",
  318. .tuner_type = TUNER_XC5000,
  319. .tuner_addr = 0x61,
  320. .tuner_bus = 1,
  321. .porta = CX23885_ANALOG_VIDEO,
  322. .portb = CX23885_MPEG_DVB,
  323. .input = {
  324. {
  325. .type = CX23885_VMUX_TELEVISION,
  326. .vmux = CX25840_COMPOSITE2,
  327. },
  328. {
  329. .type = CX23885_VMUX_COMPOSITE1,
  330. .vmux = CX25840_COMPOSITE8,
  331. },
  332. {
  333. .type = CX23885_VMUX_SVIDEO,
  334. .vmux = CX25840_SVIDEO_LUMA3 |
  335. CX25840_SVIDEO_CHROMA4,
  336. },
  337. {
  338. .type = CX23885_VMUX_COMPONENT,
  339. .vmux = CX25840_COMPONENT_ON |
  340. CX25840_VIN1_CH1 |
  341. CX25840_VIN6_CH2 |
  342. CX25840_VIN7_CH3,
  343. },
  344. },
  345. },
  346. [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
  347. .name = "Hauppauge WinTV-HVR1850",
  348. .porta = CX23885_ANALOG_VIDEO,
  349. .portb = CX23885_MPEG_ENCODER,
  350. .portc = CX23885_MPEG_DVB,
  351. .tuner_type = TUNER_ABSENT,
  352. .tuner_addr = 0x42, /* 0x84 >> 1 */
  353. .force_bff = 1,
  354. .input = {{
  355. .type = CX23885_VMUX_TELEVISION,
  356. .vmux = CX25840_VIN7_CH3 |
  357. CX25840_VIN5_CH2 |
  358. CX25840_VIN2_CH1 |
  359. CX25840_DIF_ON,
  360. .amux = CX25840_AUDIO8,
  361. }, {
  362. .type = CX23885_VMUX_COMPOSITE1,
  363. .vmux = CX25840_VIN7_CH3 |
  364. CX25840_VIN4_CH2 |
  365. CX25840_VIN6_CH1,
  366. .amux = CX25840_AUDIO7,
  367. }, {
  368. .type = CX23885_VMUX_SVIDEO,
  369. .vmux = CX25840_VIN7_CH3 |
  370. CX25840_VIN4_CH2 |
  371. CX25840_VIN8_CH1 |
  372. CX25840_SVIDEO_ON,
  373. .amux = CX25840_AUDIO7,
  374. } },
  375. },
  376. [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
  377. .name = "Compro VideoMate E800",
  378. .portc = CX23885_MPEG_DVB,
  379. },
  380. [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
  381. .name = "Hauppauge WinTV-HVR1290",
  382. .portc = CX23885_MPEG_DVB,
  383. },
  384. [CX23885_BOARD_MYGICA_X8558PRO] = {
  385. .name = "Mygica X8558 PRO DMB-TH",
  386. .portb = CX23885_MPEG_DVB,
  387. .portc = CX23885_MPEG_DVB,
  388. },
  389. [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
  390. .name = "LEADTEK WinFast PxTV1200",
  391. .porta = CX23885_ANALOG_VIDEO,
  392. .tuner_type = TUNER_XC2028,
  393. .tuner_addr = 0x61,
  394. .tuner_bus = 1,
  395. .input = {{
  396. .type = CX23885_VMUX_TELEVISION,
  397. .vmux = CX25840_VIN2_CH1 |
  398. CX25840_VIN5_CH2 |
  399. CX25840_NONE0_CH3,
  400. }, {
  401. .type = CX23885_VMUX_COMPOSITE1,
  402. .vmux = CX25840_COMPOSITE1,
  403. }, {
  404. .type = CX23885_VMUX_SVIDEO,
  405. .vmux = CX25840_SVIDEO_LUMA3 |
  406. CX25840_SVIDEO_CHROMA4,
  407. }, {
  408. .type = CX23885_VMUX_COMPONENT,
  409. .vmux = CX25840_VIN7_CH1 |
  410. CX25840_VIN6_CH2 |
  411. CX25840_VIN8_CH3 |
  412. CX25840_COMPONENT_ON,
  413. } },
  414. },
  415. [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
  416. .name = "GoTView X5 3D Hybrid",
  417. .tuner_type = TUNER_XC5000,
  418. .tuner_addr = 0x64,
  419. .tuner_bus = 1,
  420. .porta = CX23885_ANALOG_VIDEO,
  421. .portb = CX23885_MPEG_DVB,
  422. .input = {{
  423. .type = CX23885_VMUX_TELEVISION,
  424. .vmux = CX25840_VIN2_CH1 |
  425. CX25840_VIN5_CH2,
  426. .gpio0 = 0x02,
  427. }, {
  428. .type = CX23885_VMUX_COMPOSITE1,
  429. .vmux = CX23885_VMUX_COMPOSITE1,
  430. }, {
  431. .type = CX23885_VMUX_SVIDEO,
  432. .vmux = CX25840_SVIDEO_LUMA3 |
  433. CX25840_SVIDEO_CHROMA4,
  434. } },
  435. },
  436. [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
  437. .ci_type = 2,
  438. .name = "NetUP Dual DVB-T/C-CI RF",
  439. .porta = CX23885_ANALOG_VIDEO,
  440. .portb = CX23885_MPEG_DVB,
  441. .portc = CX23885_MPEG_DVB,
  442. .num_fds_portb = 2,
  443. .num_fds_portc = 2,
  444. .tuner_type = TUNER_XC5000,
  445. .tuner_addr = 0x64,
  446. .input = { {
  447. .type = CX23885_VMUX_TELEVISION,
  448. .vmux = CX25840_COMPOSITE1,
  449. } },
  450. },
  451. [CX23885_BOARD_MPX885] = {
  452. .name = "MPX-885",
  453. .porta = CX23885_ANALOG_VIDEO,
  454. .input = {{
  455. .type = CX23885_VMUX_COMPOSITE1,
  456. .vmux = CX25840_COMPOSITE1,
  457. .amux = CX25840_AUDIO6,
  458. .gpio0 = 0,
  459. }, {
  460. .type = CX23885_VMUX_COMPOSITE2,
  461. .vmux = CX25840_COMPOSITE2,
  462. .amux = CX25840_AUDIO6,
  463. .gpio0 = 0,
  464. }, {
  465. .type = CX23885_VMUX_COMPOSITE3,
  466. .vmux = CX25840_COMPOSITE3,
  467. .amux = CX25840_AUDIO7,
  468. .gpio0 = 0,
  469. }, {
  470. .type = CX23885_VMUX_COMPOSITE4,
  471. .vmux = CX25840_COMPOSITE4,
  472. .amux = CX25840_AUDIO7,
  473. .gpio0 = 0,
  474. } },
  475. },
  476. [CX23885_BOARD_MYGICA_X8507] = {
  477. .name = "Mygica X8507",
  478. .tuner_type = TUNER_XC5000,
  479. .tuner_addr = 0x61,
  480. .tuner_bus = 1,
  481. .porta = CX23885_ANALOG_VIDEO,
  482. .input = {
  483. {
  484. .type = CX23885_VMUX_TELEVISION,
  485. .vmux = CX25840_COMPOSITE2,
  486. .amux = CX25840_AUDIO8,
  487. },
  488. {
  489. .type = CX23885_VMUX_COMPOSITE1,
  490. .vmux = CX25840_COMPOSITE8,
  491. },
  492. {
  493. .type = CX23885_VMUX_SVIDEO,
  494. .vmux = CX25840_SVIDEO_LUMA3 |
  495. CX25840_SVIDEO_CHROMA4,
  496. },
  497. {
  498. .type = CX23885_VMUX_COMPONENT,
  499. .vmux = CX25840_COMPONENT_ON |
  500. CX25840_VIN1_CH1 |
  501. CX25840_VIN6_CH2 |
  502. CX25840_VIN7_CH3,
  503. },
  504. },
  505. },
  506. [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
  507. .name = "TerraTec Cinergy T PCIe Dual",
  508. .portb = CX23885_MPEG_DVB,
  509. .portc = CX23885_MPEG_DVB,
  510. },
  511. [CX23885_BOARD_TEVII_S471] = {
  512. .name = "TeVii S471",
  513. .portb = CX23885_MPEG_DVB,
  514. }
  515. };
  516. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  517. /* ------------------------------------------------------------------ */
  518. /* PCI subsystem IDs */
  519. struct cx23885_subid cx23885_subids[] = {
  520. {
  521. .subvendor = 0x0070,
  522. .subdevice = 0x3400,
  523. .card = CX23885_BOARD_UNKNOWN,
  524. }, {
  525. .subvendor = 0x0070,
  526. .subdevice = 0x7600,
  527. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  528. }, {
  529. .subvendor = 0x0070,
  530. .subdevice = 0x7800,
  531. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  532. }, {
  533. .subvendor = 0x0070,
  534. .subdevice = 0x7801,
  535. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  536. }, {
  537. .subvendor = 0x0070,
  538. .subdevice = 0x7809,
  539. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  540. }, {
  541. .subvendor = 0x0070,
  542. .subdevice = 0x7911,
  543. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  544. }, {
  545. .subvendor = 0x18ac,
  546. .subdevice = 0xd500,
  547. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  548. }, {
  549. .subvendor = 0x0070,
  550. .subdevice = 0x7790,
  551. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  552. }, {
  553. .subvendor = 0x0070,
  554. .subdevice = 0x7797,
  555. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  556. }, {
  557. .subvendor = 0x0070,
  558. .subdevice = 0x7710,
  559. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  560. }, {
  561. .subvendor = 0x0070,
  562. .subdevice = 0x7717,
  563. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  564. }, {
  565. .subvendor = 0x0070,
  566. .subdevice = 0x71d1,
  567. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  568. }, {
  569. .subvendor = 0x0070,
  570. .subdevice = 0x71d3,
  571. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  572. }, {
  573. .subvendor = 0x0070,
  574. .subdevice = 0x8101,
  575. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  576. }, {
  577. .subvendor = 0x0070,
  578. .subdevice = 0x8010,
  579. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  580. }, {
  581. .subvendor = 0x18ac,
  582. .subdevice = 0xd618,
  583. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  584. }, {
  585. .subvendor = 0x18ac,
  586. .subdevice = 0xdb78,
  587. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  588. }, {
  589. .subvendor = 0x107d,
  590. .subdevice = 0x6681,
  591. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  592. }, {
  593. .subvendor = 0x107d,
  594. .subdevice = 0x6f39,
  595. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
  596. }, {
  597. .subvendor = 0x185b,
  598. .subdevice = 0xe800,
  599. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  600. }, {
  601. .subvendor = 0x6920,
  602. .subdevice = 0x8888,
  603. .card = CX23885_BOARD_TBS_6920,
  604. }, {
  605. .subvendor = 0xd470,
  606. .subdevice = 0x9022,
  607. .card = CX23885_BOARD_TEVII_S470,
  608. }, {
  609. .subvendor = 0x0001,
  610. .subdevice = 0x2005,
  611. .card = CX23885_BOARD_DVBWORLD_2005,
  612. }, {
  613. .subvendor = 0x1b55,
  614. .subdevice = 0x2a2c,
  615. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  616. }, {
  617. .subvendor = 0x0070,
  618. .subdevice = 0x2211,
  619. .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
  620. }, {
  621. .subvendor = 0x0070,
  622. .subdevice = 0x2215,
  623. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  624. }, {
  625. .subvendor = 0x0070,
  626. .subdevice = 0x221d,
  627. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  628. }, {
  629. .subvendor = 0x0070,
  630. .subdevice = 0x2251,
  631. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  632. }, {
  633. .subvendor = 0x0070,
  634. .subdevice = 0x2259,
  635. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  636. }, {
  637. .subvendor = 0x0070,
  638. .subdevice = 0x2291,
  639. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  640. }, {
  641. .subvendor = 0x0070,
  642. .subdevice = 0x2295,
  643. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  644. }, {
  645. .subvendor = 0x0070,
  646. .subdevice = 0x2299,
  647. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  648. }, {
  649. .subvendor = 0x0070,
  650. .subdevice = 0x229d,
  651. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  652. }, {
  653. .subvendor = 0x0070,
  654. .subdevice = 0x22f0,
  655. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  656. }, {
  657. .subvendor = 0x0070,
  658. .subdevice = 0x22f1,
  659. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  660. }, {
  661. .subvendor = 0x0070,
  662. .subdevice = 0x22f2,
  663. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  664. }, {
  665. .subvendor = 0x0070,
  666. .subdevice = 0x22f3,
  667. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  668. }, {
  669. .subvendor = 0x0070,
  670. .subdevice = 0x22f4,
  671. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  672. }, {
  673. .subvendor = 0x0070,
  674. .subdevice = 0x22f5,
  675. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  676. }, {
  677. .subvendor = 0x14f1,
  678. .subdevice = 0x8651,
  679. .card = CX23885_BOARD_MYGICA_X8506,
  680. }, {
  681. .subvendor = 0x14f1,
  682. .subdevice = 0x8657,
  683. .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
  684. }, {
  685. .subvendor = 0x0070,
  686. .subdevice = 0x8541,
  687. .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
  688. }, {
  689. .subvendor = 0x1858,
  690. .subdevice = 0xe800,
  691. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
  692. }, {
  693. .subvendor = 0x0070,
  694. .subdevice = 0x8551,
  695. .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
  696. }, {
  697. .subvendor = 0x14f1,
  698. .subdevice = 0x8578,
  699. .card = CX23885_BOARD_MYGICA_X8558PRO,
  700. }, {
  701. .subvendor = 0x107d,
  702. .subdevice = 0x6f22,
  703. .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
  704. }, {
  705. .subvendor = 0x5654,
  706. .subdevice = 0x2390,
  707. .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
  708. }, {
  709. .subvendor = 0x1b55,
  710. .subdevice = 0xe2e4,
  711. .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
  712. }, {
  713. .subvendor = 0x14f1,
  714. .subdevice = 0x8502,
  715. .card = CX23885_BOARD_MYGICA_X8507,
  716. }, {
  717. .subvendor = 0x153b,
  718. .subdevice = 0x117e,
  719. .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
  720. }, {
  721. .subvendor = 0xd471,
  722. .subdevice = 0x9022,
  723. .card = CX23885_BOARD_TEVII_S471,
  724. },
  725. };
  726. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  727. void cx23885_card_list(struct cx23885_dev *dev)
  728. {
  729. int i;
  730. if (0 == dev->pci->subsystem_vendor &&
  731. 0 == dev->pci->subsystem_device) {
  732. printk(KERN_INFO
  733. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  734. "%s: be autodetected. Pass card=<n> insmod option\n"
  735. "%s: to workaround that. Redirect complaints to the\n"
  736. "%s: vendor of the TV card. Best regards,\n"
  737. "%s: -- tux\n",
  738. dev->name, dev->name, dev->name, dev->name, dev->name);
  739. } else {
  740. printk(KERN_INFO
  741. "%s: Your board isn't known (yet) to the driver.\n"
  742. "%s: Try to pick one of the existing card configs via\n"
  743. "%s: card=<n> insmod option. Updating to the latest\n"
  744. "%s: version might help as well.\n",
  745. dev->name, dev->name, dev->name, dev->name);
  746. }
  747. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  748. dev->name);
  749. for (i = 0; i < cx23885_bcount; i++)
  750. printk(KERN_INFO "%s: card=%d -> %s\n",
  751. dev->name, i, cx23885_boards[i].name);
  752. }
  753. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  754. {
  755. struct tveeprom tv;
  756. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  757. eeprom_data);
  758. /* Make sure we support the board model */
  759. switch (tv.model) {
  760. case 22001:
  761. /* WinTV-HVR1270 (PCIe, Retail, half height)
  762. * ATSC/QAM and basic analog, IR Blast */
  763. case 22009:
  764. /* WinTV-HVR1210 (PCIe, Retail, half height)
  765. * DVB-T and basic analog, IR Blast */
  766. case 22011:
  767. /* WinTV-HVR1270 (PCIe, Retail, half height)
  768. * ATSC/QAM and basic analog, IR Recv */
  769. case 22019:
  770. /* WinTV-HVR1210 (PCIe, Retail, half height)
  771. * DVB-T and basic analog, IR Recv */
  772. case 22021:
  773. /* WinTV-HVR1275 (PCIe, Retail, half height)
  774. * ATSC/QAM and basic analog, IR Recv */
  775. case 22029:
  776. /* WinTV-HVR1210 (PCIe, Retail, half height)
  777. * DVB-T and basic analog, IR Recv */
  778. case 22101:
  779. /* WinTV-HVR1270 (PCIe, Retail, full height)
  780. * ATSC/QAM and basic analog, IR Blast */
  781. case 22109:
  782. /* WinTV-HVR1210 (PCIe, Retail, full height)
  783. * DVB-T and basic analog, IR Blast */
  784. case 22111:
  785. /* WinTV-HVR1270 (PCIe, Retail, full height)
  786. * ATSC/QAM and basic analog, IR Recv */
  787. case 22119:
  788. /* WinTV-HVR1210 (PCIe, Retail, full height)
  789. * DVB-T and basic analog, IR Recv */
  790. case 22121:
  791. /* WinTV-HVR1275 (PCIe, Retail, full height)
  792. * ATSC/QAM and basic analog, IR Recv */
  793. case 22129:
  794. /* WinTV-HVR1210 (PCIe, Retail, full height)
  795. * DVB-T and basic analog, IR Recv */
  796. case 71009:
  797. /* WinTV-HVR1200 (PCIe, Retail, full height)
  798. * DVB-T and basic analog */
  799. case 71359:
  800. /* WinTV-HVR1200 (PCIe, OEM, half height)
  801. * DVB-T and basic analog */
  802. case 71439:
  803. /* WinTV-HVR1200 (PCIe, OEM, half height)
  804. * DVB-T and basic analog */
  805. case 71449:
  806. /* WinTV-HVR1200 (PCIe, OEM, full height)
  807. * DVB-T and basic analog */
  808. case 71939:
  809. /* WinTV-HVR1200 (PCIe, OEM, half height)
  810. * DVB-T and basic analog */
  811. case 71949:
  812. /* WinTV-HVR1200 (PCIe, OEM, full height)
  813. * DVB-T and basic analog */
  814. case 71959:
  815. /* WinTV-HVR1200 (PCIe, OEM, full height)
  816. * DVB-T and basic analog */
  817. case 71979:
  818. /* WinTV-HVR1200 (PCIe, OEM, half height)
  819. * DVB-T and basic analog */
  820. case 71999:
  821. /* WinTV-HVR1200 (PCIe, OEM, full height)
  822. * DVB-T and basic analog */
  823. case 76601:
  824. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  825. channel ATSC and MPEG2 HW Encoder */
  826. case 77001:
  827. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  828. and Basic analog */
  829. case 77011:
  830. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  831. and Basic analog */
  832. case 77041:
  833. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  834. and Basic analog */
  835. case 77051:
  836. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  837. and Basic analog */
  838. case 78011:
  839. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  840. Dual channel ATSC and MPEG2 HW Encoder */
  841. case 78501:
  842. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  843. Dual channel ATSC and MPEG2 HW Encoder */
  844. case 78521:
  845. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  846. Dual channel ATSC and MPEG2 HW Encoder */
  847. case 78531:
  848. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  849. Dual channel ATSC and MPEG2 HW Encoder */
  850. case 78631:
  851. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  852. Dual channel ATSC and MPEG2 HW Encoder */
  853. case 79001:
  854. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  855. ATSC and Basic analog */
  856. case 79101:
  857. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  858. ATSC and Basic analog */
  859. case 79501:
  860. /* WinTV-HVR1250 (PCIe, No IR, half height,
  861. ATSC [at least] and Basic analog) */
  862. case 79561:
  863. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  864. ATSC and Basic analog */
  865. case 79571:
  866. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  867. ATSC and Basic analog */
  868. case 79671:
  869. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  870. ATSC and Basic analog */
  871. case 80019:
  872. /* WinTV-HVR1400 (Express Card, Retail, IR,
  873. * DVB-T and Basic analog */
  874. case 81509:
  875. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  876. * DVB-T and MPEG2 HW Encoder */
  877. case 81519:
  878. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  879. * DVB-T and MPEG2 HW Encoder */
  880. break;
  881. case 85021:
  882. /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
  883. Dual channel ATSC and MPEG2 HW Encoder */
  884. break;
  885. case 85721:
  886. /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
  887. Dual channel ATSC and Basic analog */
  888. break;
  889. default:
  890. printk(KERN_WARNING "%s: warning: "
  891. "unknown hauppauge model #%d\n",
  892. dev->name, tv.model);
  893. break;
  894. }
  895. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  896. dev->name, tv.model);
  897. }
  898. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  899. {
  900. struct cx23885_tsport *port = priv;
  901. struct cx23885_dev *dev = port->dev;
  902. u32 bitmask = 0;
  903. if (command == XC2028_RESET_CLK)
  904. return 0;
  905. if (command != 0) {
  906. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  907. __func__, command);
  908. return -EINVAL;
  909. }
  910. switch (dev->board) {
  911. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  912. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  913. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  914. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  915. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  916. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  917. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  918. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  919. /* Tuner Reset Command */
  920. bitmask = 0x04;
  921. break;
  922. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  923. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  924. /* Two identical tuners on two different i2c buses,
  925. * we need to reset the correct gpio. */
  926. if (port->nr == 1)
  927. bitmask = 0x01;
  928. else if (port->nr == 2)
  929. bitmask = 0x04;
  930. break;
  931. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  932. /* Tuner Reset Command */
  933. bitmask = 0x02;
  934. break;
  935. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  936. altera_ci_tuner_reset(dev, port->nr);
  937. break;
  938. }
  939. if (bitmask) {
  940. /* Drive the tuner into reset and back out */
  941. cx_clear(GP0_IO, bitmask);
  942. mdelay(200);
  943. cx_set(GP0_IO, bitmask);
  944. }
  945. return 0;
  946. }
  947. void cx23885_gpio_setup(struct cx23885_dev *dev)
  948. {
  949. switch (dev->board) {
  950. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  951. /* GPIO-0 cx24227 demodulator reset */
  952. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  953. break;
  954. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  955. /* GPIO-0 cx24227 demodulator */
  956. /* GPIO-2 xc3028 tuner */
  957. /* Put the parts into reset */
  958. cx_set(GP0_IO, 0x00050000);
  959. cx_clear(GP0_IO, 0x00000005);
  960. msleep(5);
  961. /* Bring the parts out of reset */
  962. cx_set(GP0_IO, 0x00050005);
  963. break;
  964. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  965. /* GPIO-0 cx24227 demodulator reset */
  966. /* GPIO-2 xc5000 tuner reset */
  967. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  968. break;
  969. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  970. /* GPIO-0 656_CLK */
  971. /* GPIO-1 656_D0 */
  972. /* GPIO-2 8295A Reset */
  973. /* GPIO-3-10 cx23417 data0-7 */
  974. /* GPIO-11-14 cx23417 addr0-3 */
  975. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  976. /* GPIO-19 IR_RX */
  977. /* CX23417 GPIO's */
  978. /* EIO15 Zilog Reset */
  979. /* EIO14 S5H1409/CX24227 Reset */
  980. mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
  981. /* Put the demod into reset and protect the eeprom */
  982. mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
  983. mdelay(100);
  984. /* Bring the demod and blaster out of reset */
  985. mc417_gpio_set(dev, GPIO_15 | GPIO_14);
  986. mdelay(100);
  987. /* Force the TDA8295A into reset and back */
  988. cx23885_gpio_enable(dev, GPIO_2, 1);
  989. cx23885_gpio_set(dev, GPIO_2);
  990. mdelay(20);
  991. cx23885_gpio_clear(dev, GPIO_2);
  992. mdelay(20);
  993. cx23885_gpio_set(dev, GPIO_2);
  994. mdelay(20);
  995. break;
  996. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  997. /* GPIO-0 tda10048 demodulator reset */
  998. /* GPIO-2 tda18271 tuner reset */
  999. /* Put the parts into reset and back */
  1000. cx_set(GP0_IO, 0x00050000);
  1001. mdelay(20);
  1002. cx_clear(GP0_IO, 0x00000005);
  1003. mdelay(20);
  1004. cx_set(GP0_IO, 0x00050005);
  1005. break;
  1006. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1007. /* GPIO-0 TDA10048 demodulator reset */
  1008. /* GPIO-2 TDA8295A Reset */
  1009. /* GPIO-3-10 cx23417 data0-7 */
  1010. /* GPIO-11-14 cx23417 addr0-3 */
  1011. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1012. /* The following GPIO's are on the interna AVCore (cx25840) */
  1013. /* GPIO-19 IR_RX */
  1014. /* GPIO-20 IR_TX 416/DVBT Select */
  1015. /* GPIO-21 IIS DAT */
  1016. /* GPIO-22 IIS WCLK */
  1017. /* GPIO-23 IIS BCLK */
  1018. /* Put the parts into reset and back */
  1019. cx_set(GP0_IO, 0x00050000);
  1020. mdelay(20);
  1021. cx_clear(GP0_IO, 0x00000005);
  1022. mdelay(20);
  1023. cx_set(GP0_IO, 0x00050005);
  1024. break;
  1025. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1026. /* GPIO-0 Dibcom7000p demodulator reset */
  1027. /* GPIO-2 xc3028L tuner reset */
  1028. /* GPIO-13 LED */
  1029. /* Put the parts into reset and back */
  1030. cx_set(GP0_IO, 0x00050000);
  1031. mdelay(20);
  1032. cx_clear(GP0_IO, 0x00000005);
  1033. mdelay(20);
  1034. cx_set(GP0_IO, 0x00050005);
  1035. break;
  1036. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1037. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  1038. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  1039. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  1040. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  1041. /* Put the parts into reset and back */
  1042. cx_set(GP0_IO, 0x000f0000);
  1043. mdelay(20);
  1044. cx_clear(GP0_IO, 0x0000000f);
  1045. mdelay(20);
  1046. cx_set(GP0_IO, 0x000f000f);
  1047. break;
  1048. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1049. /* GPIO-0 portb xc3028 reset */
  1050. /* GPIO-1 portb zl10353 reset */
  1051. /* GPIO-2 portc xc3028 reset */
  1052. /* GPIO-3 portc zl10353 reset */
  1053. /* Put the parts into reset and back */
  1054. cx_set(GP0_IO, 0x000f0000);
  1055. mdelay(20);
  1056. cx_clear(GP0_IO, 0x0000000f);
  1057. mdelay(20);
  1058. cx_set(GP0_IO, 0x000f000f);
  1059. break;
  1060. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1061. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1062. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1063. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1064. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1065. /* GPIO-2 xc3028 tuner reset */
  1066. /* The following GPIO's are on the internal AVCore (cx25840) */
  1067. /* GPIO-? zl10353 demod reset */
  1068. /* Put the parts into reset and back */
  1069. cx_set(GP0_IO, 0x00040000);
  1070. mdelay(20);
  1071. cx_clear(GP0_IO, 0x00000004);
  1072. mdelay(20);
  1073. cx_set(GP0_IO, 0x00040004);
  1074. break;
  1075. case CX23885_BOARD_TBS_6920:
  1076. cx_write(MC417_CTL, 0x00000036);
  1077. cx_write(MC417_OEN, 0x00001000);
  1078. cx_set(MC417_RWD, 0x00000002);
  1079. mdelay(200);
  1080. cx_clear(MC417_RWD, 0x00000800);
  1081. mdelay(200);
  1082. cx_set(MC417_RWD, 0x00000800);
  1083. mdelay(200);
  1084. break;
  1085. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1086. /* GPIO-0 INTA from CiMax1
  1087. GPIO-1 INTB from CiMax2
  1088. GPIO-2 reset chips
  1089. GPIO-3 to GPIO-10 data/addr for CA
  1090. GPIO-11 ~CS0 to CiMax1
  1091. GPIO-12 ~CS1 to CiMax2
  1092. GPIO-13 ADL0 load LSB addr
  1093. GPIO-14 ADL1 load MSB addr
  1094. GPIO-15 ~RDY from CiMax
  1095. GPIO-17 ~RD to CiMax
  1096. GPIO-18 ~WR to CiMax
  1097. */
  1098. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  1099. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  1100. cx_clear(GP0_IO, 0x00030004);
  1101. mdelay(100);/* reset delay */
  1102. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  1103. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  1104. /* GPIO-15 IN as ~ACK, rest as OUT */
  1105. cx_write(MC417_OEN, 0x00001000);
  1106. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  1107. cx_write(MC417_RWD, 0x0000c300);
  1108. /* enable irq */
  1109. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1110. break;
  1111. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1112. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1113. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1114. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1115. /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
  1116. /* GPIO-6 I2C Gate which can isolate the demod from the bus */
  1117. /* GPIO-9 Demod reset */
  1118. /* Put the parts into reset and back */
  1119. cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
  1120. cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
  1121. cx23885_gpio_clear(dev, GPIO_9);
  1122. mdelay(20);
  1123. cx23885_gpio_set(dev, GPIO_9);
  1124. break;
  1125. case CX23885_BOARD_MYGICA_X8506:
  1126. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1127. case CX23885_BOARD_MYGICA_X8507:
  1128. /* GPIO-0 (0)Analog / (1)Digital TV */
  1129. /* GPIO-1 reset XC5000 */
  1130. /* GPIO-2 reset LGS8GL5 / LGS8G75 */
  1131. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
  1132. cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
  1133. mdelay(100);
  1134. cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
  1135. mdelay(100);
  1136. break;
  1137. case CX23885_BOARD_MYGICA_X8558PRO:
  1138. /* GPIO-0 reset first ATBM8830 */
  1139. /* GPIO-1 reset second ATBM8830 */
  1140. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
  1141. cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
  1142. mdelay(100);
  1143. cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
  1144. mdelay(100);
  1145. break;
  1146. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1147. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1148. /* GPIO-0 656_CLK */
  1149. /* GPIO-1 656_D0 */
  1150. /* GPIO-2 Wake# */
  1151. /* GPIO-3-10 cx23417 data0-7 */
  1152. /* GPIO-11-14 cx23417 addr0-3 */
  1153. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1154. /* GPIO-19 IR_RX */
  1155. /* GPIO-20 C_IR_TX */
  1156. /* GPIO-21 I2S DAT */
  1157. /* GPIO-22 I2S WCLK */
  1158. /* GPIO-23 I2S BCLK */
  1159. /* ALT GPIO: EXP GPIO LATCH */
  1160. /* CX23417 GPIO's */
  1161. /* GPIO-14 S5H1411/CX24228 Reset */
  1162. /* GPIO-13 EEPROM write protect */
  1163. mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
  1164. /* Put the demod into reset and protect the eeprom */
  1165. mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
  1166. mdelay(100);
  1167. /* Bring the demod out of reset */
  1168. mc417_gpio_set(dev, GPIO_14);
  1169. mdelay(100);
  1170. /* CX24228 GPIO */
  1171. /* Connected to IF / Mux */
  1172. break;
  1173. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1174. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  1175. break;
  1176. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1177. /* GPIO-0 ~INT in
  1178. GPIO-1 TMS out
  1179. GPIO-2 ~reset chips out
  1180. GPIO-3 to GPIO-10 data/addr for CA in/out
  1181. GPIO-11 ~CS out
  1182. GPIO-12 ADDR out
  1183. GPIO-13 ~WR out
  1184. GPIO-14 ~RD out
  1185. GPIO-15 ~RDY in
  1186. GPIO-16 TCK out
  1187. GPIO-17 TDO in
  1188. GPIO-18 TDI out
  1189. */
  1190. cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
  1191. /* GPIO-0 as INT, reset & TMS low */
  1192. cx_clear(GP0_IO, 0x00010006);
  1193. mdelay(100);/* reset delay */
  1194. cx_set(GP0_IO, 0x00000004); /* reset high */
  1195. cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
  1196. /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
  1197. cx_write(MC417_OEN, 0x00005000);
  1198. /* ~RD, ~WR high; ADDR low; ~CS high */
  1199. cx_write(MC417_RWD, 0x00000d00);
  1200. /* enable irq */
  1201. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1202. break;
  1203. }
  1204. }
  1205. int cx23885_ir_init(struct cx23885_dev *dev)
  1206. {
  1207. static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
  1208. {
  1209. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1210. .pin = CX23885_PIN_IR_RX_GPIO19,
  1211. .function = CX23885_PAD_IR_RX,
  1212. .value = 0,
  1213. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1214. }, {
  1215. .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
  1216. .pin = CX23885_PIN_IR_TX_GPIO20,
  1217. .function = CX23885_PAD_IR_TX,
  1218. .value = 0,
  1219. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1220. }
  1221. };
  1222. const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
  1223. static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
  1224. {
  1225. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1226. .pin = CX23885_PIN_IR_RX_GPIO19,
  1227. .function = CX23885_PAD_IR_RX,
  1228. .value = 0,
  1229. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1230. }
  1231. };
  1232. const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
  1233. struct v4l2_subdev_ir_parameters params;
  1234. int ret = 0;
  1235. switch (dev->board) {
  1236. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1237. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1238. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1239. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1240. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1241. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1242. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1243. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1244. /* FIXME: Implement me */
  1245. break;
  1246. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1247. ret = cx23888_ir_probe(dev);
  1248. if (ret)
  1249. break;
  1250. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1251. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1252. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1253. break;
  1254. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1255. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1256. ret = cx23888_ir_probe(dev);
  1257. if (ret)
  1258. break;
  1259. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1260. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1261. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1262. /*
  1263. * For these boards we need to invert the Tx output via the
  1264. * IR controller to have the LED off while idle
  1265. */
  1266. v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
  1267. params.enable = false;
  1268. params.shutdown = false;
  1269. params.invert_level = true;
  1270. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1271. params.shutdown = true;
  1272. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1273. break;
  1274. case CX23885_BOARD_TEVII_S470:
  1275. if (!enable_885_ir)
  1276. break;
  1277. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1278. if (dev->sd_ir == NULL) {
  1279. ret = -ENODEV;
  1280. break;
  1281. }
  1282. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1283. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1284. break;
  1285. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1286. if (!enable_885_ir)
  1287. break;
  1288. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1289. if (dev->sd_ir == NULL) {
  1290. ret = -ENODEV;
  1291. break;
  1292. }
  1293. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1294. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1295. break;
  1296. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1297. request_module("ir-kbd-i2c");
  1298. break;
  1299. }
  1300. return ret;
  1301. }
  1302. void cx23885_ir_fini(struct cx23885_dev *dev)
  1303. {
  1304. switch (dev->board) {
  1305. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1306. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1307. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1308. cx23885_irq_remove(dev, PCI_MSK_IR);
  1309. cx23888_ir_remove(dev);
  1310. dev->sd_ir = NULL;
  1311. break;
  1312. case CX23885_BOARD_TEVII_S470:
  1313. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1314. cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
  1315. /* sd_ir is a duplicate pointer to the AV Core, just clear it */
  1316. dev->sd_ir = NULL;
  1317. break;
  1318. }
  1319. }
  1320. int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
  1321. {
  1322. int data;
  1323. int tdo = 0;
  1324. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  1325. /*TMS*/
  1326. data = ((cx_read(GP0_IO)) & (~0x00000002));
  1327. data |= (tms ? 0x00020002 : 0x00020000);
  1328. cx_write(GP0_IO, data);
  1329. /*TDI*/
  1330. data = ((cx_read(MC417_RWD)) & (~0x0000a000));
  1331. data |= (tdi ? 0x00008000 : 0);
  1332. cx_write(MC417_RWD, data);
  1333. if (read_tdo)
  1334. tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
  1335. cx_write(MC417_RWD, data | 0x00002000);
  1336. udelay(1);
  1337. /*TCK*/
  1338. cx_write(MC417_RWD, data);
  1339. return tdo;
  1340. }
  1341. void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
  1342. {
  1343. switch (dev->board) {
  1344. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1345. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1346. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1347. if (dev->sd_ir)
  1348. cx23885_irq_add_enable(dev, PCI_MSK_IR);
  1349. break;
  1350. case CX23885_BOARD_TEVII_S470:
  1351. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1352. if (dev->sd_ir)
  1353. cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
  1354. break;
  1355. }
  1356. }
  1357. void cx23885_card_setup(struct cx23885_dev *dev)
  1358. {
  1359. struct cx23885_tsport *ts1 = &dev->ts1;
  1360. struct cx23885_tsport *ts2 = &dev->ts2;
  1361. static u8 eeprom[256];
  1362. if (dev->i2c_bus[0].i2c_rc == 0) {
  1363. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1364. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  1365. eeprom, sizeof(eeprom));
  1366. }
  1367. switch (dev->board) {
  1368. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1369. if (dev->i2c_bus[0].i2c_rc == 0) {
  1370. if (eeprom[0x80] != 0x84)
  1371. hauppauge_eeprom(dev, eeprom+0xc0);
  1372. else
  1373. hauppauge_eeprom(dev, eeprom+0x80);
  1374. }
  1375. break;
  1376. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1377. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1378. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1379. if (dev->i2c_bus[0].i2c_rc == 0)
  1380. hauppauge_eeprom(dev, eeprom+0x80);
  1381. break;
  1382. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1383. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1384. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1385. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1386. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1387. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1388. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1389. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1390. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1391. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1392. if (dev->i2c_bus[0].i2c_rc == 0)
  1393. hauppauge_eeprom(dev, eeprom+0xc0);
  1394. break;
  1395. }
  1396. switch (dev->board) {
  1397. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1398. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1399. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1400. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1401. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1402. /* break omitted intentionally */
  1403. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  1404. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1405. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1406. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1407. break;
  1408. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1409. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1410. /* Defaults for VID B - Analog encoder */
  1411. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  1412. ts1->gen_ctrl_val = 0x10e;
  1413. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1414. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1415. /* APB_TSVALERR_POL (active low)*/
  1416. ts1->vld_misc_val = 0x2000;
  1417. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  1418. cx_write(0x130184, 0xc);
  1419. /* Defaults for VID C */
  1420. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1421. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1422. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1423. break;
  1424. case CX23885_BOARD_TBS_6920:
  1425. ts1->gen_ctrl_val = 0x4; /* Parallel */
  1426. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1427. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1428. break;
  1429. case CX23885_BOARD_TEVII_S470:
  1430. case CX23885_BOARD_TEVII_S471:
  1431. case CX23885_BOARD_DVBWORLD_2005:
  1432. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1433. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1434. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1435. break;
  1436. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1437. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1438. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1439. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1440. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1441. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1442. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1443. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1444. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1445. break;
  1446. case CX23885_BOARD_MYGICA_X8506:
  1447. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1448. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1449. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1450. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1451. break;
  1452. case CX23885_BOARD_MYGICA_X8558PRO:
  1453. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1454. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1455. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1456. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1457. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1458. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1459. break;
  1460. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1461. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1462. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1463. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1464. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1465. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1466. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1467. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1468. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1469. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1470. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1471. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1472. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1473. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1474. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1475. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1476. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1477. default:
  1478. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1479. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1480. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1481. }
  1482. /* Certain boards support analog, or require the avcore to be
  1483. * loaded, ensure this happens.
  1484. */
  1485. switch (dev->board) {
  1486. case CX23885_BOARD_TEVII_S470:
  1487. /* Currently only enabled for the integrated IR controller */
  1488. if (!enable_885_ir)
  1489. break;
  1490. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1491. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1492. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1493. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1494. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1495. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1496. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1497. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1498. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1499. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1500. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1501. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1502. case CX23885_BOARD_MYGICA_X8506:
  1503. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1504. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1505. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1506. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1507. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1508. case CX23885_BOARD_MPX885:
  1509. case CX23885_BOARD_MYGICA_X8507:
  1510. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1511. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
  1512. &dev->i2c_bus[2].i2c_adap,
  1513. "cx25840", 0x88 >> 1, NULL);
  1514. if (dev->sd_cx25840) {
  1515. dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
  1516. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  1517. }
  1518. break;
  1519. }
  1520. /* AUX-PLL 27MHz CLK */
  1521. switch (dev->board) {
  1522. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1523. netup_initialize(dev);
  1524. break;
  1525. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1526. int ret;
  1527. const struct firmware *fw;
  1528. const char *filename = "dvb-netup-altera-01.fw";
  1529. char *action = "configure";
  1530. static struct netup_card_info cinfo;
  1531. struct altera_config netup_config = {
  1532. .dev = dev,
  1533. .action = action,
  1534. .jtag_io = netup_jtag_io,
  1535. };
  1536. netup_initialize(dev);
  1537. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1538. if (netup_card_rev)
  1539. cinfo.rev = netup_card_rev;
  1540. switch (cinfo.rev) {
  1541. case 0x4:
  1542. filename = "dvb-netup-altera-04.fw";
  1543. break;
  1544. default:
  1545. filename = "dvb-netup-altera-01.fw";
  1546. break;
  1547. }
  1548. printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
  1549. cinfo.rev, filename);
  1550. ret = request_firmware(&fw, filename, &dev->pci->dev);
  1551. if (ret != 0)
  1552. printk(KERN_ERR "did not find the firmware file. (%s) "
  1553. "Please see linux/Documentation/dvb/ for more details "
  1554. "on firmware-problems.", filename);
  1555. else
  1556. altera_init(&netup_config, fw);
  1557. release_firmware(fw);
  1558. break;
  1559. }
  1560. }
  1561. }
  1562. /* ------------------------------------------------------------------ */