smsc95xx.c 50 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/bitrev.h>
  29. #include <linux/crc16.h>
  30. #include <linux/crc32.h>
  31. #include <linux/usb/usbnet.h>
  32. #include <linux/slab.h>
  33. #include "smsc95xx.h"
  34. #define SMSC_CHIPNAME "smsc95xx"
  35. #define SMSC_DRIVER_VERSION "1.0.4"
  36. #define HS_USB_PKT_SIZE (512)
  37. #define FS_USB_PKT_SIZE (64)
  38. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  39. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  40. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  41. #define MAX_SINGLE_PACKET_SIZE (2048)
  42. #define LAN95XX_EEPROM_MAGIC (0x9500)
  43. #define EEPROM_MAC_OFFSET (0x01)
  44. #define DEFAULT_TX_CSUM_ENABLE (true)
  45. #define DEFAULT_RX_CSUM_ENABLE (true)
  46. #define SMSC95XX_INTERNAL_PHY_ID (1)
  47. #define SMSC95XX_TX_OVERHEAD (8)
  48. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  49. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  50. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  51. #define FEATURE_8_WAKEUP_FILTERS (0x01)
  52. #define FEATURE_PHY_NLP_CROSSOVER (0x02)
  53. #define FEATURE_AUTOSUSPEND (0x04)
  54. #define SUSPEND_SUSPEND0 (0x01)
  55. #define SUSPEND_SUSPEND1 (0x02)
  56. #define SUSPEND_SUSPEND2 (0x04)
  57. #define SUSPEND_SUSPEND3 (0x08)
  58. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  59. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  60. struct smsc95xx_priv {
  61. u32 mac_cr;
  62. u32 hash_hi;
  63. u32 hash_lo;
  64. u32 wolopts;
  65. spinlock_t mac_cr_lock;
  66. u8 features;
  67. u8 suspend_flags;
  68. };
  69. static bool turbo_mode = true;
  70. module_param(turbo_mode, bool, 0644);
  71. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  72. static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
  73. u32 *data, int in_pm)
  74. {
  75. u32 buf;
  76. int ret;
  77. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  78. BUG_ON(!dev);
  79. if (!in_pm)
  80. fn = usbnet_read_cmd;
  81. else
  82. fn = usbnet_read_cmd_nopm;
  83. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  84. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  85. 0, index, &buf, 4);
  86. if (unlikely(ret < 0))
  87. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  88. index, ret);
  89. le32_to_cpus(&buf);
  90. *data = buf;
  91. return ret;
  92. }
  93. static int __must_check __smsc95xx_write_reg(struct usbnet *dev, u32 index,
  94. u32 data, int in_pm)
  95. {
  96. u32 buf;
  97. int ret;
  98. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  99. BUG_ON(!dev);
  100. if (!in_pm)
  101. fn = usbnet_write_cmd;
  102. else
  103. fn = usbnet_write_cmd_nopm;
  104. buf = data;
  105. cpu_to_le32s(&buf);
  106. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  107. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  108. 0, index, &buf, 4);
  109. if (unlikely(ret < 0))
  110. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  111. index, ret);
  112. return ret;
  113. }
  114. static int __must_check smsc95xx_read_reg_nopm(struct usbnet *dev, u32 index,
  115. u32 *data)
  116. {
  117. return __smsc95xx_read_reg(dev, index, data, 1);
  118. }
  119. static int __must_check smsc95xx_write_reg_nopm(struct usbnet *dev, u32 index,
  120. u32 data)
  121. {
  122. return __smsc95xx_write_reg(dev, index, data, 1);
  123. }
  124. static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index,
  125. u32 *data)
  126. {
  127. return __smsc95xx_read_reg(dev, index, data, 0);
  128. }
  129. static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index,
  130. u32 data)
  131. {
  132. return __smsc95xx_write_reg(dev, index, data, 0);
  133. }
  134. /* Loop until the read is completed with timeout
  135. * called with phy_mutex held */
  136. static int __must_check __smsc95xx_phy_wait_not_busy(struct usbnet *dev,
  137. int in_pm)
  138. {
  139. unsigned long start_time = jiffies;
  140. u32 val;
  141. int ret;
  142. do {
  143. ret = __smsc95xx_read_reg(dev, MII_ADDR, &val, in_pm);
  144. if (ret < 0) {
  145. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  146. return ret;
  147. }
  148. if (!(val & MII_BUSY_))
  149. return 0;
  150. } while (!time_after(jiffies, start_time + HZ));
  151. return -EIO;
  152. }
  153. static int __smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  154. int in_pm)
  155. {
  156. struct usbnet *dev = netdev_priv(netdev);
  157. u32 val, addr;
  158. int ret;
  159. mutex_lock(&dev->phy_mutex);
  160. /* confirm MII not busy */
  161. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  162. if (ret < 0) {
  163. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_read\n");
  164. goto done;
  165. }
  166. /* set the address, index & direction (read from PHY) */
  167. phy_id &= dev->mii.phy_id_mask;
  168. idx &= dev->mii.reg_num_mask;
  169. addr = (phy_id << 11) | (idx << 6) | MII_READ_ | MII_BUSY_;
  170. ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm);
  171. if (ret < 0) {
  172. netdev_warn(dev->net, "Error writing MII_ADDR\n");
  173. goto done;
  174. }
  175. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  176. if (ret < 0) {
  177. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  178. goto done;
  179. }
  180. ret = __smsc95xx_read_reg(dev, MII_DATA, &val, in_pm);
  181. if (ret < 0) {
  182. netdev_warn(dev->net, "Error reading MII_DATA\n");
  183. goto done;
  184. }
  185. ret = (u16)(val & 0xFFFF);
  186. done:
  187. mutex_unlock(&dev->phy_mutex);
  188. return ret;
  189. }
  190. static void __smsc95xx_mdio_write(struct net_device *netdev, int phy_id,
  191. int idx, int regval, int in_pm)
  192. {
  193. struct usbnet *dev = netdev_priv(netdev);
  194. u32 val, addr;
  195. int ret;
  196. mutex_lock(&dev->phy_mutex);
  197. /* confirm MII not busy */
  198. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  199. if (ret < 0) {
  200. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_write\n");
  201. goto done;
  202. }
  203. val = regval;
  204. ret = __smsc95xx_write_reg(dev, MII_DATA, val, in_pm);
  205. if (ret < 0) {
  206. netdev_warn(dev->net, "Error writing MII_DATA\n");
  207. goto done;
  208. }
  209. /* set the address, index & direction (write to PHY) */
  210. phy_id &= dev->mii.phy_id_mask;
  211. idx &= dev->mii.reg_num_mask;
  212. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_ | MII_BUSY_;
  213. ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm);
  214. if (ret < 0) {
  215. netdev_warn(dev->net, "Error writing MII_ADDR\n");
  216. goto done;
  217. }
  218. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  219. if (ret < 0) {
  220. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  221. goto done;
  222. }
  223. done:
  224. mutex_unlock(&dev->phy_mutex);
  225. }
  226. static int smsc95xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  227. int idx)
  228. {
  229. return __smsc95xx_mdio_read(netdev, phy_id, idx, 1);
  230. }
  231. static void smsc95xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  232. int idx, int regval)
  233. {
  234. __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 1);
  235. }
  236. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  237. {
  238. return __smsc95xx_mdio_read(netdev, phy_id, idx, 0);
  239. }
  240. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  241. int regval)
  242. {
  243. __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 0);
  244. }
  245. static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev)
  246. {
  247. unsigned long start_time = jiffies;
  248. u32 val;
  249. int ret;
  250. do {
  251. ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
  252. if (ret < 0) {
  253. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  254. return ret;
  255. }
  256. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  257. break;
  258. udelay(40);
  259. } while (!time_after(jiffies, start_time + HZ));
  260. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  261. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  262. return -EIO;
  263. }
  264. return 0;
  265. }
  266. static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  267. {
  268. unsigned long start_time = jiffies;
  269. u32 val;
  270. int ret;
  271. do {
  272. ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
  273. if (ret < 0) {
  274. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  275. return ret;
  276. }
  277. if (!(val & E2P_CMD_BUSY_))
  278. return 0;
  279. udelay(40);
  280. } while (!time_after(jiffies, start_time + HZ));
  281. netdev_warn(dev->net, "EEPROM is busy\n");
  282. return -EIO;
  283. }
  284. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  285. u8 *data)
  286. {
  287. u32 val;
  288. int i, ret;
  289. BUG_ON(!dev);
  290. BUG_ON(!data);
  291. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  292. if (ret)
  293. return ret;
  294. for (i = 0; i < length; i++) {
  295. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  296. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  297. if (ret < 0) {
  298. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  299. return ret;
  300. }
  301. ret = smsc95xx_wait_eeprom(dev);
  302. if (ret < 0)
  303. return ret;
  304. ret = smsc95xx_read_reg(dev, E2P_DATA, &val);
  305. if (ret < 0) {
  306. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  307. return ret;
  308. }
  309. data[i] = val & 0xFF;
  310. offset++;
  311. }
  312. return 0;
  313. }
  314. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  315. u8 *data)
  316. {
  317. u32 val;
  318. int i, ret;
  319. BUG_ON(!dev);
  320. BUG_ON(!data);
  321. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  322. if (ret)
  323. return ret;
  324. /* Issue write/erase enable command */
  325. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  326. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  327. if (ret < 0) {
  328. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  329. return ret;
  330. }
  331. ret = smsc95xx_wait_eeprom(dev);
  332. if (ret < 0)
  333. return ret;
  334. for (i = 0; i < length; i++) {
  335. /* Fill data register */
  336. val = data[i];
  337. ret = smsc95xx_write_reg(dev, E2P_DATA, val);
  338. if (ret < 0) {
  339. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  340. return ret;
  341. }
  342. /* Send "write" command */
  343. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  344. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  345. if (ret < 0) {
  346. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  347. return ret;
  348. }
  349. ret = smsc95xx_wait_eeprom(dev);
  350. if (ret < 0)
  351. return ret;
  352. offset++;
  353. }
  354. return 0;
  355. }
  356. static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index,
  357. u32 data)
  358. {
  359. const u16 size = 4;
  360. u32 buf;
  361. int ret;
  362. buf = data;
  363. cpu_to_le32s(&buf);
  364. ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER,
  365. USB_DIR_OUT | USB_TYPE_VENDOR |
  366. USB_RECIP_DEVICE,
  367. 0, index, &buf, size);
  368. if (ret < 0)
  369. netdev_warn(dev->net, "Error write async cmd, sts=%d\n",
  370. ret);
  371. return ret;
  372. }
  373. /* returns hash bit number for given MAC address
  374. * example:
  375. * 01 00 5E 00 00 01 -> returns bit number 31 */
  376. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  377. {
  378. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  379. }
  380. static void smsc95xx_set_multicast(struct net_device *netdev)
  381. {
  382. struct usbnet *dev = netdev_priv(netdev);
  383. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  384. unsigned long flags;
  385. int ret;
  386. pdata->hash_hi = 0;
  387. pdata->hash_lo = 0;
  388. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  389. if (dev->net->flags & IFF_PROMISC) {
  390. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  391. pdata->mac_cr |= MAC_CR_PRMS_;
  392. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  393. } else if (dev->net->flags & IFF_ALLMULTI) {
  394. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  395. pdata->mac_cr |= MAC_CR_MCPAS_;
  396. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  397. } else if (!netdev_mc_empty(dev->net)) {
  398. struct netdev_hw_addr *ha;
  399. pdata->mac_cr |= MAC_CR_HPFILT_;
  400. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  401. netdev_for_each_mc_addr(ha, netdev) {
  402. u32 bitnum = smsc95xx_hash(ha->addr);
  403. u32 mask = 0x01 << (bitnum & 0x1F);
  404. if (bitnum & 0x20)
  405. pdata->hash_hi |= mask;
  406. else
  407. pdata->hash_lo |= mask;
  408. }
  409. netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
  410. pdata->hash_hi, pdata->hash_lo);
  411. } else {
  412. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  413. pdata->mac_cr &=
  414. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  415. }
  416. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  417. /* Initiate async writes, as we can't wait for completion here */
  418. ret = smsc95xx_write_reg_async(dev, HASHH, pdata->hash_hi);
  419. if (ret < 0)
  420. netdev_warn(dev->net, "failed to initiate async write to HASHH\n");
  421. ret = smsc95xx_write_reg_async(dev, HASHL, pdata->hash_lo);
  422. if (ret < 0)
  423. netdev_warn(dev->net, "failed to initiate async write to HASHL\n");
  424. ret = smsc95xx_write_reg_async(dev, MAC_CR, pdata->mac_cr);
  425. if (ret < 0)
  426. netdev_warn(dev->net, "failed to initiate async write to MAC_CR\n");
  427. }
  428. static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  429. u16 lcladv, u16 rmtadv)
  430. {
  431. u32 flow, afc_cfg = 0;
  432. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  433. if (ret < 0)
  434. return ret;
  435. if (duplex == DUPLEX_FULL) {
  436. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  437. if (cap & FLOW_CTRL_RX)
  438. flow = 0xFFFF0002;
  439. else
  440. flow = 0;
  441. if (cap & FLOW_CTRL_TX)
  442. afc_cfg |= 0xF;
  443. else
  444. afc_cfg &= ~0xF;
  445. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  446. cap & FLOW_CTRL_RX ? "enabled" : "disabled",
  447. cap & FLOW_CTRL_TX ? "enabled" : "disabled");
  448. } else {
  449. netif_dbg(dev, link, dev->net, "half duplex\n");
  450. flow = 0;
  451. afc_cfg |= 0xF;
  452. }
  453. ret = smsc95xx_write_reg(dev, FLOW, flow);
  454. if (ret < 0)
  455. return ret;
  456. return smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  457. }
  458. static int smsc95xx_link_reset(struct usbnet *dev)
  459. {
  460. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  461. struct mii_if_info *mii = &dev->mii;
  462. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  463. unsigned long flags;
  464. u16 lcladv, rmtadv;
  465. int ret;
  466. /* clear interrupt status */
  467. ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  468. if (ret < 0)
  469. return ret;
  470. ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
  471. if (ret < 0)
  472. return ret;
  473. mii_check_media(mii, 1, 1);
  474. mii_ethtool_gset(&dev->mii, &ecmd);
  475. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  476. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  477. netif_dbg(dev, link, dev->net,
  478. "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  479. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  480. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  481. if (ecmd.duplex != DUPLEX_FULL) {
  482. pdata->mac_cr &= ~MAC_CR_FDPX_;
  483. pdata->mac_cr |= MAC_CR_RCVOWN_;
  484. } else {
  485. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  486. pdata->mac_cr |= MAC_CR_FDPX_;
  487. }
  488. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  489. ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  490. if (ret < 0)
  491. return ret;
  492. ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  493. if (ret < 0)
  494. netdev_warn(dev->net, "Error updating PHY flow control\n");
  495. return ret;
  496. }
  497. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  498. {
  499. u32 intdata;
  500. if (urb->actual_length != 4) {
  501. netdev_warn(dev->net, "unexpected urb length %d\n",
  502. urb->actual_length);
  503. return;
  504. }
  505. memcpy(&intdata, urb->transfer_buffer, 4);
  506. le32_to_cpus(&intdata);
  507. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  508. if (intdata & INT_ENP_PHY_INT_)
  509. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  510. else
  511. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  512. intdata);
  513. }
  514. /* Enable or disable Tx & Rx checksum offload engines */
  515. static int smsc95xx_set_features(struct net_device *netdev,
  516. netdev_features_t features)
  517. {
  518. struct usbnet *dev = netdev_priv(netdev);
  519. u32 read_buf;
  520. int ret;
  521. ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  522. if (ret < 0)
  523. return ret;
  524. if (features & NETIF_F_HW_CSUM)
  525. read_buf |= Tx_COE_EN_;
  526. else
  527. read_buf &= ~Tx_COE_EN_;
  528. if (features & NETIF_F_RXCSUM)
  529. read_buf |= Rx_COE_EN_;
  530. else
  531. read_buf &= ~Rx_COE_EN_;
  532. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  533. if (ret < 0)
  534. return ret;
  535. netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
  536. return 0;
  537. }
  538. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  539. {
  540. return MAX_EEPROM_SIZE;
  541. }
  542. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  543. struct ethtool_eeprom *ee, u8 *data)
  544. {
  545. struct usbnet *dev = netdev_priv(netdev);
  546. ee->magic = LAN95XX_EEPROM_MAGIC;
  547. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  548. }
  549. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  550. struct ethtool_eeprom *ee, u8 *data)
  551. {
  552. struct usbnet *dev = netdev_priv(netdev);
  553. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  554. netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
  555. ee->magic);
  556. return -EINVAL;
  557. }
  558. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  559. }
  560. static int smsc95xx_ethtool_getregslen(struct net_device *netdev)
  561. {
  562. /* all smsc95xx registers */
  563. return COE_CR - ID_REV + sizeof(u32);
  564. }
  565. static void
  566. smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs,
  567. void *buf)
  568. {
  569. struct usbnet *dev = netdev_priv(netdev);
  570. unsigned int i, j;
  571. int retval;
  572. u32 *data = buf;
  573. retval = smsc95xx_read_reg(dev, ID_REV, &regs->version);
  574. if (retval < 0) {
  575. netdev_warn(netdev, "REGS: cannot read ID_REV\n");
  576. return;
  577. }
  578. for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) {
  579. retval = smsc95xx_read_reg(dev, i, &data[j]);
  580. if (retval < 0) {
  581. netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i);
  582. return;
  583. }
  584. }
  585. }
  586. static void smsc95xx_ethtool_get_wol(struct net_device *net,
  587. struct ethtool_wolinfo *wolinfo)
  588. {
  589. struct usbnet *dev = netdev_priv(net);
  590. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  591. wolinfo->supported = SUPPORTED_WAKE;
  592. wolinfo->wolopts = pdata->wolopts;
  593. }
  594. static int smsc95xx_ethtool_set_wol(struct net_device *net,
  595. struct ethtool_wolinfo *wolinfo)
  596. {
  597. struct usbnet *dev = netdev_priv(net);
  598. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  599. int ret;
  600. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  601. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  602. if (ret < 0)
  603. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  604. return ret;
  605. }
  606. static const struct ethtool_ops smsc95xx_ethtool_ops = {
  607. .get_link = usbnet_get_link,
  608. .nway_reset = usbnet_nway_reset,
  609. .get_drvinfo = usbnet_get_drvinfo,
  610. .get_msglevel = usbnet_get_msglevel,
  611. .set_msglevel = usbnet_set_msglevel,
  612. .get_settings = usbnet_get_settings,
  613. .set_settings = usbnet_set_settings,
  614. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  615. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  616. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  617. .get_regs_len = smsc95xx_ethtool_getregslen,
  618. .get_regs = smsc95xx_ethtool_getregs,
  619. .get_wol = smsc95xx_ethtool_get_wol,
  620. .set_wol = smsc95xx_ethtool_set_wol,
  621. };
  622. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  623. {
  624. struct usbnet *dev = netdev_priv(netdev);
  625. if (!netif_running(netdev))
  626. return -EINVAL;
  627. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  628. }
  629. static void smsc95xx_init_mac_address(struct usbnet *dev)
  630. {
  631. /* try reading mac address from EEPROM */
  632. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  633. dev->net->dev_addr) == 0) {
  634. if (is_valid_ether_addr(dev->net->dev_addr)) {
  635. /* eeprom values are valid so use them */
  636. netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
  637. return;
  638. }
  639. }
  640. /* no eeprom, or eeprom values are invalid. generate random MAC */
  641. eth_hw_addr_random(dev->net);
  642. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  643. }
  644. static int smsc95xx_set_mac_address(struct usbnet *dev)
  645. {
  646. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  647. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  648. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  649. int ret;
  650. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  651. if (ret < 0)
  652. return ret;
  653. return smsc95xx_write_reg(dev, ADDRH, addr_hi);
  654. }
  655. /* starts the TX path */
  656. static int smsc95xx_start_tx_path(struct usbnet *dev)
  657. {
  658. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  659. unsigned long flags;
  660. int ret;
  661. /* Enable Tx at MAC */
  662. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  663. pdata->mac_cr |= MAC_CR_TXEN_;
  664. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  665. ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  666. if (ret < 0)
  667. return ret;
  668. /* Enable Tx at SCSRs */
  669. return smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_);
  670. }
  671. /* Starts the Receive path */
  672. static int smsc95xx_start_rx_path(struct usbnet *dev, int in_pm)
  673. {
  674. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  675. unsigned long flags;
  676. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  677. pdata->mac_cr |= MAC_CR_RXEN_;
  678. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  679. return __smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr, in_pm);
  680. }
  681. static int smsc95xx_phy_initialize(struct usbnet *dev)
  682. {
  683. int bmcr, ret, timeout = 0;
  684. /* Initialize MII structure */
  685. dev->mii.dev = dev->net;
  686. dev->mii.mdio_read = smsc95xx_mdio_read;
  687. dev->mii.mdio_write = smsc95xx_mdio_write;
  688. dev->mii.phy_id_mask = 0x1f;
  689. dev->mii.reg_num_mask = 0x1f;
  690. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  691. /* reset phy and wait for reset to complete */
  692. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  693. do {
  694. msleep(10);
  695. bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  696. timeout++;
  697. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  698. if (timeout >= 100) {
  699. netdev_warn(dev->net, "timeout on PHY Reset");
  700. return -EIO;
  701. }
  702. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  703. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  704. ADVERTISE_PAUSE_ASYM);
  705. /* read to clear */
  706. ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  707. if (ret < 0) {
  708. netdev_warn(dev->net, "Failed to read PHY_INT_SRC during init\n");
  709. return ret;
  710. }
  711. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  712. PHY_INT_MASK_DEFAULT_);
  713. mii_nway_restart(&dev->mii);
  714. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  715. return 0;
  716. }
  717. static int smsc95xx_reset(struct usbnet *dev)
  718. {
  719. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  720. u32 read_buf, write_buf, burst_cap;
  721. int ret = 0, timeout;
  722. netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
  723. ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_);
  724. if (ret < 0)
  725. return ret;
  726. timeout = 0;
  727. do {
  728. msleep(10);
  729. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  730. if (ret < 0)
  731. return ret;
  732. timeout++;
  733. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  734. if (timeout >= 100) {
  735. netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
  736. return ret;
  737. }
  738. ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_);
  739. if (ret < 0)
  740. return ret;
  741. timeout = 0;
  742. do {
  743. msleep(10);
  744. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  745. if (ret < 0)
  746. return ret;
  747. timeout++;
  748. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  749. if (timeout >= 100) {
  750. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  751. return ret;
  752. }
  753. ret = smsc95xx_set_mac_address(dev);
  754. if (ret < 0)
  755. return ret;
  756. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  757. dev->net->dev_addr);
  758. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  759. if (ret < 0)
  760. return ret;
  761. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  762. read_buf);
  763. read_buf |= HW_CFG_BIR_;
  764. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  765. if (ret < 0)
  766. return ret;
  767. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  768. if (ret < 0)
  769. return ret;
  770. netif_dbg(dev, ifup, dev->net,
  771. "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
  772. read_buf);
  773. if (!turbo_mode) {
  774. burst_cap = 0;
  775. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  776. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  777. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  778. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  779. } else {
  780. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  781. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  782. }
  783. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  784. (ulong)dev->rx_urb_size);
  785. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  786. if (ret < 0)
  787. return ret;
  788. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  789. if (ret < 0)
  790. return ret;
  791. netif_dbg(dev, ifup, dev->net,
  792. "Read Value from BURST_CAP after writing: 0x%08x\n",
  793. read_buf);
  794. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  795. if (ret < 0)
  796. return ret;
  797. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  798. if (ret < 0)
  799. return ret;
  800. netif_dbg(dev, ifup, dev->net,
  801. "Read Value from BULK_IN_DLY after writing: 0x%08x\n",
  802. read_buf);
  803. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  804. if (ret < 0)
  805. return ret;
  806. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG: 0x%08x\n",
  807. read_buf);
  808. if (turbo_mode)
  809. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  810. read_buf &= ~HW_CFG_RXDOFF_;
  811. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  812. read_buf |= NET_IP_ALIGN << 9;
  813. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  814. if (ret < 0)
  815. return ret;
  816. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  817. if (ret < 0)
  818. return ret;
  819. netif_dbg(dev, ifup, dev->net,
  820. "Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  821. ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
  822. if (ret < 0)
  823. return ret;
  824. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  825. if (ret < 0)
  826. return ret;
  827. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf);
  828. /* Configure GPIO pins as LED outputs */
  829. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  830. LED_GPIO_CFG_FDX_LED;
  831. ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
  832. if (ret < 0)
  833. return ret;
  834. /* Init Tx */
  835. ret = smsc95xx_write_reg(dev, FLOW, 0);
  836. if (ret < 0)
  837. return ret;
  838. ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT);
  839. if (ret < 0)
  840. return ret;
  841. /* Don't need mac_cr_lock during initialisation */
  842. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  843. if (ret < 0)
  844. return ret;
  845. /* Init Rx */
  846. /* Set Vlan */
  847. ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q);
  848. if (ret < 0)
  849. return ret;
  850. /* Enable or disable checksum offload engines */
  851. ret = smsc95xx_set_features(dev->net, dev->net->features);
  852. if (ret < 0) {
  853. netdev_warn(dev->net, "Failed to set checksum offload features\n");
  854. return ret;
  855. }
  856. smsc95xx_set_multicast(dev->net);
  857. ret = smsc95xx_phy_initialize(dev);
  858. if (ret < 0) {
  859. netdev_warn(dev->net, "Failed to init PHY\n");
  860. return ret;
  861. }
  862. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  863. if (ret < 0)
  864. return ret;
  865. /* enable PHY interrupts */
  866. read_buf |= INT_EP_CTL_PHY_INT_;
  867. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  868. if (ret < 0)
  869. return ret;
  870. ret = smsc95xx_start_tx_path(dev);
  871. if (ret < 0) {
  872. netdev_warn(dev->net, "Failed to start TX path\n");
  873. return ret;
  874. }
  875. ret = smsc95xx_start_rx_path(dev, 0);
  876. if (ret < 0) {
  877. netdev_warn(dev->net, "Failed to start RX path\n");
  878. return ret;
  879. }
  880. netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n");
  881. return 0;
  882. }
  883. static const struct net_device_ops smsc95xx_netdev_ops = {
  884. .ndo_open = usbnet_open,
  885. .ndo_stop = usbnet_stop,
  886. .ndo_start_xmit = usbnet_start_xmit,
  887. .ndo_tx_timeout = usbnet_tx_timeout,
  888. .ndo_change_mtu = usbnet_change_mtu,
  889. .ndo_set_mac_address = eth_mac_addr,
  890. .ndo_validate_addr = eth_validate_addr,
  891. .ndo_do_ioctl = smsc95xx_ioctl,
  892. .ndo_set_rx_mode = smsc95xx_set_multicast,
  893. .ndo_set_features = smsc95xx_set_features,
  894. };
  895. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  896. {
  897. struct smsc95xx_priv *pdata = NULL;
  898. u32 val;
  899. int ret;
  900. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  901. ret = usbnet_get_endpoints(dev, intf);
  902. if (ret < 0) {
  903. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  904. return ret;
  905. }
  906. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  907. GFP_KERNEL);
  908. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  909. if (!pdata)
  910. return -ENOMEM;
  911. spin_lock_init(&pdata->mac_cr_lock);
  912. if (DEFAULT_TX_CSUM_ENABLE)
  913. dev->net->features |= NETIF_F_HW_CSUM;
  914. if (DEFAULT_RX_CSUM_ENABLE)
  915. dev->net->features |= NETIF_F_RXCSUM;
  916. dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
  917. smsc95xx_init_mac_address(dev);
  918. /* Init all registers */
  919. ret = smsc95xx_reset(dev);
  920. /* detect device revision as different features may be available */
  921. ret = smsc95xx_read_reg(dev, ID_REV, &val);
  922. if (ret < 0)
  923. return ret;
  924. val >>= 16;
  925. if ((val == ID_REV_CHIP_ID_9500A_) || (val == ID_REV_CHIP_ID_9530_) ||
  926. (val == ID_REV_CHIP_ID_89530_) || (val == ID_REV_CHIP_ID_9730_))
  927. pdata->features = (FEATURE_8_WAKEUP_FILTERS |
  928. FEATURE_PHY_NLP_CROSSOVER |
  929. FEATURE_AUTOSUSPEND);
  930. else if (val == ID_REV_CHIP_ID_9512_)
  931. pdata->features = FEATURE_8_WAKEUP_FILTERS;
  932. dev->net->netdev_ops = &smsc95xx_netdev_ops;
  933. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  934. dev->net->flags |= IFF_MULTICAST;
  935. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM;
  936. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  937. return 0;
  938. }
  939. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  940. {
  941. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  942. if (pdata) {
  943. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  944. kfree(pdata);
  945. pdata = NULL;
  946. dev->data[0] = 0;
  947. }
  948. }
  949. static u32 smsc_crc(const u8 *buffer, size_t len, int filter)
  950. {
  951. u32 crc = bitrev16(crc16(0xFFFF, buffer, len));
  952. return crc << ((filter % 2) * 16);
  953. }
  954. static int smsc95xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  955. {
  956. struct mii_if_info *mii = &dev->mii;
  957. int ret;
  958. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  959. /* read to clear */
  960. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  961. if (ret < 0)
  962. return ret;
  963. /* enable interrupt source */
  964. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  965. if (ret < 0)
  966. return ret;
  967. ret |= mask;
  968. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  969. return 0;
  970. }
  971. static int smsc95xx_link_ok_nopm(struct usbnet *dev)
  972. {
  973. struct mii_if_info *mii = &dev->mii;
  974. int ret;
  975. /* first, a dummy read, needed to latch some MII phys */
  976. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  977. if (ret < 0)
  978. return ret;
  979. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  980. if (ret < 0)
  981. return ret;
  982. return !!(ret & BMSR_LSTATUS);
  983. }
  984. static int smsc95xx_enter_suspend0(struct usbnet *dev)
  985. {
  986. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  987. u32 val;
  988. int ret;
  989. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  990. if (ret < 0)
  991. return ret;
  992. val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_));
  993. val |= PM_CTL_SUS_MODE_0;
  994. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  995. if (ret < 0)
  996. return ret;
  997. /* clear wol status */
  998. val &= ~PM_CTL_WUPS_;
  999. val |= PM_CTL_WUPS_WOL_;
  1000. /* enable energy detection */
  1001. if (pdata->wolopts & WAKE_PHY)
  1002. val |= PM_CTL_WUPS_ED_;
  1003. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1004. if (ret < 0)
  1005. return ret;
  1006. /* read back PM_CTRL */
  1007. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1008. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1009. return ret;
  1010. }
  1011. static int smsc95xx_enter_suspend1(struct usbnet *dev)
  1012. {
  1013. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1014. struct mii_if_info *mii = &dev->mii;
  1015. u32 val;
  1016. int ret;
  1017. /* reconfigure link pulse detection timing for
  1018. * compatibility with non-standard link partners
  1019. */
  1020. if (pdata->features & FEATURE_PHY_NLP_CROSSOVER)
  1021. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_EDPD_CONFIG,
  1022. PHY_EDPD_CONFIG_DEFAULT);
  1023. /* enable energy detect power-down mode */
  1024. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS);
  1025. if (ret < 0)
  1026. return ret;
  1027. ret |= MODE_CTRL_STS_EDPWRDOWN_;
  1028. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS, ret);
  1029. /* enter SUSPEND1 mode */
  1030. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1031. if (ret < 0)
  1032. return ret;
  1033. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1034. val |= PM_CTL_SUS_MODE_1;
  1035. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1036. if (ret < 0)
  1037. return ret;
  1038. /* clear wol status, enable energy detection */
  1039. val &= ~PM_CTL_WUPS_;
  1040. val |= (PM_CTL_WUPS_ED_ | PM_CTL_ED_EN_);
  1041. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1042. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1043. return ret;
  1044. }
  1045. static int smsc95xx_enter_suspend2(struct usbnet *dev)
  1046. {
  1047. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1048. u32 val;
  1049. int ret;
  1050. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1051. if (ret < 0)
  1052. return ret;
  1053. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1054. val |= PM_CTL_SUS_MODE_2;
  1055. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1056. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1057. return ret;
  1058. }
  1059. static int smsc95xx_enter_suspend3(struct usbnet *dev)
  1060. {
  1061. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1062. u32 val;
  1063. int ret;
  1064. ret = smsc95xx_read_reg_nopm(dev, RX_FIFO_INF, &val);
  1065. if (ret < 0)
  1066. return ret;
  1067. if (val & 0xFFFF) {
  1068. netdev_info(dev->net, "rx fifo not empty in autosuspend\n");
  1069. return -EBUSY;
  1070. }
  1071. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1072. if (ret < 0)
  1073. return ret;
  1074. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1075. val |= PM_CTL_SUS_MODE_3 | PM_CTL_RES_CLR_WKP_STS;
  1076. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1077. if (ret < 0)
  1078. return ret;
  1079. /* clear wol status */
  1080. val &= ~PM_CTL_WUPS_;
  1081. val |= PM_CTL_WUPS_WOL_;
  1082. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1083. if (ret < 0)
  1084. return ret;
  1085. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1086. return 0;
  1087. }
  1088. static int smsc95xx_autosuspend(struct usbnet *dev, u32 link_up)
  1089. {
  1090. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1091. int ret;
  1092. if (!netif_running(dev->net)) {
  1093. /* interface is ifconfig down so fully power down hw */
  1094. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1095. return smsc95xx_enter_suspend2(dev);
  1096. }
  1097. if (!link_up) {
  1098. /* link is down so enter EDPD mode, but only if device can
  1099. * reliably resume from it. This check should be redundant
  1100. * as current FEATURE_AUTOSUSPEND parts also support
  1101. * FEATURE_PHY_NLP_CROSSOVER but it's included for clarity */
  1102. if (!(pdata->features & FEATURE_PHY_NLP_CROSSOVER)) {
  1103. netdev_warn(dev->net, "EDPD not supported\n");
  1104. return -EBUSY;
  1105. }
  1106. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1107. /* enable PHY wakeup events for if cable is attached */
  1108. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1109. PHY_INT_MASK_ANEG_COMP_);
  1110. if (ret < 0) {
  1111. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1112. return ret;
  1113. }
  1114. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1115. return smsc95xx_enter_suspend1(dev);
  1116. }
  1117. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1118. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1119. PHY_INT_MASK_LINK_DOWN_);
  1120. if (ret < 0) {
  1121. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1122. return ret;
  1123. }
  1124. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1125. return smsc95xx_enter_suspend3(dev);
  1126. }
  1127. static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message)
  1128. {
  1129. struct usbnet *dev = usb_get_intfdata(intf);
  1130. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1131. u32 val, link_up;
  1132. int ret;
  1133. /* TODO: don't indicate this feature to usb framework if
  1134. * our current hardware doesn't have the capability
  1135. */
  1136. if ((message.event == PM_EVENT_AUTO_SUSPEND) &&
  1137. (!(pdata->features & FEATURE_AUTOSUSPEND))) {
  1138. netdev_warn(dev->net, "autosuspend not supported\n");
  1139. return -EBUSY;
  1140. }
  1141. ret = usbnet_suspend(intf, message);
  1142. if (ret < 0) {
  1143. netdev_warn(dev->net, "usbnet_suspend error\n");
  1144. return ret;
  1145. }
  1146. if (pdata->suspend_flags) {
  1147. netdev_warn(dev->net, "error during last resume\n");
  1148. pdata->suspend_flags = 0;
  1149. }
  1150. /* determine if link is up using only _nopm functions */
  1151. link_up = smsc95xx_link_ok_nopm(dev);
  1152. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1153. ret = smsc95xx_autosuspend(dev, link_up);
  1154. goto done;
  1155. }
  1156. /* if we get this far we're not autosuspending */
  1157. /* if no wol options set, or if link is down and we're not waking on
  1158. * PHY activity, enter lowest power SUSPEND2 mode
  1159. */
  1160. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1161. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1162. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1163. /* disable energy detect (link up) & wake up events */
  1164. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1165. if (ret < 0)
  1166. goto done;
  1167. val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_);
  1168. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1169. if (ret < 0)
  1170. goto done;
  1171. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1172. if (ret < 0)
  1173. goto done;
  1174. val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_);
  1175. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1176. if (ret < 0)
  1177. goto done;
  1178. ret = smsc95xx_enter_suspend2(dev);
  1179. goto done;
  1180. }
  1181. if (pdata->wolopts & WAKE_PHY) {
  1182. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1183. (PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_LINK_DOWN_));
  1184. if (ret < 0) {
  1185. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1186. goto done;
  1187. }
  1188. /* if link is down then configure EDPD and enter SUSPEND1,
  1189. * otherwise enter SUSPEND0 below
  1190. */
  1191. if (!link_up) {
  1192. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1193. ret = smsc95xx_enter_suspend1(dev);
  1194. goto done;
  1195. }
  1196. }
  1197. if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
  1198. u32 *filter_mask = kzalloc(sizeof(u32) * 32, GFP_KERNEL);
  1199. u32 command[2];
  1200. u32 offset[2];
  1201. u32 crc[4];
  1202. int wuff_filter_count =
  1203. (pdata->features & FEATURE_8_WAKEUP_FILTERS) ?
  1204. LAN9500A_WUFF_NUM : LAN9500_WUFF_NUM;
  1205. int i, filter = 0;
  1206. if (!filter_mask) {
  1207. netdev_warn(dev->net, "Unable to allocate filter_mask\n");
  1208. ret = -ENOMEM;
  1209. goto done;
  1210. }
  1211. memset(command, 0, sizeof(command));
  1212. memset(offset, 0, sizeof(offset));
  1213. memset(crc, 0, sizeof(crc));
  1214. if (pdata->wolopts & WAKE_BCAST) {
  1215. const u8 bcast[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
  1216. netdev_info(dev->net, "enabling broadcast detection\n");
  1217. filter_mask[filter * 4] = 0x003F;
  1218. filter_mask[filter * 4 + 1] = 0x00;
  1219. filter_mask[filter * 4 + 2] = 0x00;
  1220. filter_mask[filter * 4 + 3] = 0x00;
  1221. command[filter/4] |= 0x05UL << ((filter % 4) * 8);
  1222. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1223. crc[filter/2] |= smsc_crc(bcast, 6, filter);
  1224. filter++;
  1225. }
  1226. if (pdata->wolopts & WAKE_MCAST) {
  1227. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1228. netdev_info(dev->net, "enabling multicast detection\n");
  1229. filter_mask[filter * 4] = 0x0007;
  1230. filter_mask[filter * 4 + 1] = 0x00;
  1231. filter_mask[filter * 4 + 2] = 0x00;
  1232. filter_mask[filter * 4 + 3] = 0x00;
  1233. command[filter/4] |= 0x09UL << ((filter % 4) * 8);
  1234. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1235. crc[filter/2] |= smsc_crc(mcast, 3, filter);
  1236. filter++;
  1237. }
  1238. if (pdata->wolopts & WAKE_ARP) {
  1239. const u8 arp[] = {0x08, 0x06};
  1240. netdev_info(dev->net, "enabling ARP detection\n");
  1241. filter_mask[filter * 4] = 0x0003;
  1242. filter_mask[filter * 4 + 1] = 0x00;
  1243. filter_mask[filter * 4 + 2] = 0x00;
  1244. filter_mask[filter * 4 + 3] = 0x00;
  1245. command[filter/4] |= 0x05UL << ((filter % 4) * 8);
  1246. offset[filter/4] |= 0x0C << ((filter % 4) * 8);
  1247. crc[filter/2] |= smsc_crc(arp, 2, filter);
  1248. filter++;
  1249. }
  1250. if (pdata->wolopts & WAKE_UCAST) {
  1251. netdev_info(dev->net, "enabling unicast detection\n");
  1252. filter_mask[filter * 4] = 0x003F;
  1253. filter_mask[filter * 4 + 1] = 0x00;
  1254. filter_mask[filter * 4 + 2] = 0x00;
  1255. filter_mask[filter * 4 + 3] = 0x00;
  1256. command[filter/4] |= 0x01UL << ((filter % 4) * 8);
  1257. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1258. crc[filter/2] |= smsc_crc(dev->net->dev_addr, ETH_ALEN, filter);
  1259. filter++;
  1260. }
  1261. for (i = 0; i < (wuff_filter_count * 4); i++) {
  1262. ret = smsc95xx_write_reg_nopm(dev, WUFF, filter_mask[i]);
  1263. if (ret < 0) {
  1264. kfree(filter_mask);
  1265. goto done;
  1266. }
  1267. }
  1268. kfree(filter_mask);
  1269. for (i = 0; i < (wuff_filter_count / 4); i++) {
  1270. ret = smsc95xx_write_reg_nopm(dev, WUFF, command[i]);
  1271. if (ret < 0)
  1272. goto done;
  1273. }
  1274. for (i = 0; i < (wuff_filter_count / 4); i++) {
  1275. ret = smsc95xx_write_reg_nopm(dev, WUFF, offset[i]);
  1276. if (ret < 0)
  1277. goto done;
  1278. }
  1279. for (i = 0; i < (wuff_filter_count / 2); i++) {
  1280. ret = smsc95xx_write_reg_nopm(dev, WUFF, crc[i]);
  1281. if (ret < 0)
  1282. goto done;
  1283. }
  1284. /* clear any pending pattern match packet status */
  1285. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1286. if (ret < 0)
  1287. goto done;
  1288. val |= WUCSR_WUFR_;
  1289. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1290. if (ret < 0)
  1291. goto done;
  1292. }
  1293. if (pdata->wolopts & WAKE_MAGIC) {
  1294. /* clear any pending magic packet status */
  1295. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1296. if (ret < 0)
  1297. goto done;
  1298. val |= WUCSR_MPR_;
  1299. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1300. if (ret < 0)
  1301. goto done;
  1302. }
  1303. /* enable/disable wakeup sources */
  1304. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1305. if (ret < 0)
  1306. goto done;
  1307. if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
  1308. netdev_info(dev->net, "enabling pattern match wakeup\n");
  1309. val |= WUCSR_WAKE_EN_;
  1310. } else {
  1311. netdev_info(dev->net, "disabling pattern match wakeup\n");
  1312. val &= ~WUCSR_WAKE_EN_;
  1313. }
  1314. if (pdata->wolopts & WAKE_MAGIC) {
  1315. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1316. val |= WUCSR_MPEN_;
  1317. } else {
  1318. netdev_info(dev->net, "disabling magic packet wakeup\n");
  1319. val &= ~WUCSR_MPEN_;
  1320. }
  1321. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1322. if (ret < 0)
  1323. goto done;
  1324. /* enable wol wakeup source */
  1325. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1326. if (ret < 0)
  1327. goto done;
  1328. val |= PM_CTL_WOL_EN_;
  1329. /* phy energy detect wakeup source */
  1330. if (pdata->wolopts & WAKE_PHY)
  1331. val |= PM_CTL_ED_EN_;
  1332. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1333. if (ret < 0)
  1334. goto done;
  1335. /* enable receiver to enable frame reception */
  1336. smsc95xx_start_rx_path(dev, 1);
  1337. /* some wol options are enabled, so enter SUSPEND0 */
  1338. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1339. ret = smsc95xx_enter_suspend0(dev);
  1340. done:
  1341. if (ret)
  1342. usbnet_resume(intf);
  1343. return ret;
  1344. }
  1345. static int smsc95xx_resume(struct usb_interface *intf)
  1346. {
  1347. struct usbnet *dev = usb_get_intfdata(intf);
  1348. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1349. u8 suspend_flags = pdata->suspend_flags;
  1350. int ret;
  1351. u32 val;
  1352. BUG_ON(!dev);
  1353. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1354. /* do this first to ensure it's cleared even in error case */
  1355. pdata->suspend_flags = 0;
  1356. if (suspend_flags & SUSPEND_ALLMODES) {
  1357. /* clear wake-up sources */
  1358. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1359. if (ret < 0)
  1360. return ret;
  1361. val &= ~(WUCSR_WAKE_EN_ | WUCSR_MPEN_);
  1362. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1363. if (ret < 0)
  1364. return ret;
  1365. /* clear wake-up status */
  1366. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1367. if (ret < 0)
  1368. return ret;
  1369. val &= ~PM_CTL_WOL_EN_;
  1370. val |= PM_CTL_WUPS_;
  1371. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1372. if (ret < 0)
  1373. return ret;
  1374. }
  1375. ret = usbnet_resume(intf);
  1376. if (ret < 0)
  1377. netdev_warn(dev->net, "usbnet_resume error\n");
  1378. return ret;
  1379. }
  1380. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  1381. {
  1382. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  1383. skb->ip_summed = CHECKSUM_COMPLETE;
  1384. skb_trim(skb, skb->len - 2);
  1385. }
  1386. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1387. {
  1388. while (skb->len > 0) {
  1389. u32 header, align_count;
  1390. struct sk_buff *ax_skb;
  1391. unsigned char *packet;
  1392. u16 size;
  1393. memcpy(&header, skb->data, sizeof(header));
  1394. le32_to_cpus(&header);
  1395. skb_pull(skb, 4 + NET_IP_ALIGN);
  1396. packet = skb->data;
  1397. /* get the packet length */
  1398. size = (u16)((header & RX_STS_FL_) >> 16);
  1399. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  1400. if (unlikely(header & RX_STS_ES_)) {
  1401. netif_dbg(dev, rx_err, dev->net,
  1402. "Error header=0x%08x\n", header);
  1403. dev->net->stats.rx_errors++;
  1404. dev->net->stats.rx_dropped++;
  1405. if (header & RX_STS_CRC_) {
  1406. dev->net->stats.rx_crc_errors++;
  1407. } else {
  1408. if (header & (RX_STS_TL_ | RX_STS_RF_))
  1409. dev->net->stats.rx_frame_errors++;
  1410. if ((header & RX_STS_LE_) &&
  1411. (!(header & RX_STS_FT_)))
  1412. dev->net->stats.rx_length_errors++;
  1413. }
  1414. } else {
  1415. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  1416. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  1417. netif_dbg(dev, rx_err, dev->net,
  1418. "size err header=0x%08x\n", header);
  1419. return 0;
  1420. }
  1421. /* last frame in this batch */
  1422. if (skb->len == size) {
  1423. if (dev->net->features & NETIF_F_RXCSUM)
  1424. smsc95xx_rx_csum_offload(skb);
  1425. skb_trim(skb, skb->len - 4); /* remove fcs */
  1426. skb->truesize = size + sizeof(struct sk_buff);
  1427. return 1;
  1428. }
  1429. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1430. if (unlikely(!ax_skb)) {
  1431. netdev_warn(dev->net, "Error allocating skb\n");
  1432. return 0;
  1433. }
  1434. ax_skb->len = size;
  1435. ax_skb->data = packet;
  1436. skb_set_tail_pointer(ax_skb, size);
  1437. if (dev->net->features & NETIF_F_RXCSUM)
  1438. smsc95xx_rx_csum_offload(ax_skb);
  1439. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1440. ax_skb->truesize = size + sizeof(struct sk_buff);
  1441. usbnet_skb_return(dev, ax_skb);
  1442. }
  1443. skb_pull(skb, size);
  1444. /* padding bytes before the next frame starts */
  1445. if (skb->len)
  1446. skb_pull(skb, align_count);
  1447. }
  1448. if (unlikely(skb->len < 0)) {
  1449. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  1450. return 0;
  1451. }
  1452. return 1;
  1453. }
  1454. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  1455. {
  1456. u16 low_16 = (u16)skb_checksum_start_offset(skb);
  1457. u16 high_16 = low_16 + skb->csum_offset;
  1458. return (high_16 << 16) | low_16;
  1459. }
  1460. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  1461. struct sk_buff *skb, gfp_t flags)
  1462. {
  1463. bool csum = skb->ip_summed == CHECKSUM_PARTIAL;
  1464. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  1465. u32 tx_cmd_a, tx_cmd_b;
  1466. /* We do not advertise SG, so skbs should be already linearized */
  1467. BUG_ON(skb_shinfo(skb)->nr_frags);
  1468. if (skb_headroom(skb) < overhead) {
  1469. struct sk_buff *skb2 = skb_copy_expand(skb,
  1470. overhead, 0, flags);
  1471. dev_kfree_skb_any(skb);
  1472. skb = skb2;
  1473. if (!skb)
  1474. return NULL;
  1475. }
  1476. if (csum) {
  1477. if (skb->len <= 45) {
  1478. /* workaround - hardware tx checksum does not work
  1479. * properly with extremely small packets */
  1480. long csstart = skb_checksum_start_offset(skb);
  1481. __wsum calc = csum_partial(skb->data + csstart,
  1482. skb->len - csstart, 0);
  1483. *((__sum16 *)(skb->data + csstart
  1484. + skb->csum_offset)) = csum_fold(calc);
  1485. csum = false;
  1486. } else {
  1487. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  1488. skb_push(skb, 4);
  1489. cpu_to_le32s(&csum_preamble);
  1490. memcpy(skb->data, &csum_preamble, 4);
  1491. }
  1492. }
  1493. skb_push(skb, 4);
  1494. tx_cmd_b = (u32)(skb->len - 4);
  1495. if (csum)
  1496. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  1497. cpu_to_le32s(&tx_cmd_b);
  1498. memcpy(skb->data, &tx_cmd_b, 4);
  1499. skb_push(skb, 4);
  1500. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  1501. TX_CMD_A_LAST_SEG_;
  1502. cpu_to_le32s(&tx_cmd_a);
  1503. memcpy(skb->data, &tx_cmd_a, 4);
  1504. return skb;
  1505. }
  1506. static int smsc95xx_manage_power(struct usbnet *dev, int on)
  1507. {
  1508. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1509. dev->intf->needs_remote_wakeup = on;
  1510. if (pdata->features & FEATURE_AUTOSUSPEND)
  1511. return 0;
  1512. /* this chip revision doesn't support autosuspend */
  1513. netdev_info(dev->net, "hardware doesn't support USB autosuspend\n");
  1514. if (on)
  1515. usb_autopm_get_interface_no_resume(dev->intf);
  1516. else
  1517. usb_autopm_put_interface(dev->intf);
  1518. return 0;
  1519. }
  1520. static const struct driver_info smsc95xx_info = {
  1521. .description = "smsc95xx USB 2.0 Ethernet",
  1522. .bind = smsc95xx_bind,
  1523. .unbind = smsc95xx_unbind,
  1524. .link_reset = smsc95xx_link_reset,
  1525. .reset = smsc95xx_reset,
  1526. .rx_fixup = smsc95xx_rx_fixup,
  1527. .tx_fixup = smsc95xx_tx_fixup,
  1528. .status = smsc95xx_status,
  1529. .manage_power = smsc95xx_manage_power,
  1530. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1531. };
  1532. static const struct usb_device_id products[] = {
  1533. {
  1534. /* SMSC9500 USB Ethernet Device */
  1535. USB_DEVICE(0x0424, 0x9500),
  1536. .driver_info = (unsigned long) &smsc95xx_info,
  1537. },
  1538. {
  1539. /* SMSC9505 USB Ethernet Device */
  1540. USB_DEVICE(0x0424, 0x9505),
  1541. .driver_info = (unsigned long) &smsc95xx_info,
  1542. },
  1543. {
  1544. /* SMSC9500A USB Ethernet Device */
  1545. USB_DEVICE(0x0424, 0x9E00),
  1546. .driver_info = (unsigned long) &smsc95xx_info,
  1547. },
  1548. {
  1549. /* SMSC9505A USB Ethernet Device */
  1550. USB_DEVICE(0x0424, 0x9E01),
  1551. .driver_info = (unsigned long) &smsc95xx_info,
  1552. },
  1553. {
  1554. /* SMSC9512/9514 USB Hub & Ethernet Device */
  1555. USB_DEVICE(0x0424, 0xec00),
  1556. .driver_info = (unsigned long) &smsc95xx_info,
  1557. },
  1558. {
  1559. /* SMSC9500 USB Ethernet Device (SAL10) */
  1560. USB_DEVICE(0x0424, 0x9900),
  1561. .driver_info = (unsigned long) &smsc95xx_info,
  1562. },
  1563. {
  1564. /* SMSC9505 USB Ethernet Device (SAL10) */
  1565. USB_DEVICE(0x0424, 0x9901),
  1566. .driver_info = (unsigned long) &smsc95xx_info,
  1567. },
  1568. {
  1569. /* SMSC9500A USB Ethernet Device (SAL10) */
  1570. USB_DEVICE(0x0424, 0x9902),
  1571. .driver_info = (unsigned long) &smsc95xx_info,
  1572. },
  1573. {
  1574. /* SMSC9505A USB Ethernet Device (SAL10) */
  1575. USB_DEVICE(0x0424, 0x9903),
  1576. .driver_info = (unsigned long) &smsc95xx_info,
  1577. },
  1578. {
  1579. /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
  1580. USB_DEVICE(0x0424, 0x9904),
  1581. .driver_info = (unsigned long) &smsc95xx_info,
  1582. },
  1583. {
  1584. /* SMSC9500A USB Ethernet Device (HAL) */
  1585. USB_DEVICE(0x0424, 0x9905),
  1586. .driver_info = (unsigned long) &smsc95xx_info,
  1587. },
  1588. {
  1589. /* SMSC9505A USB Ethernet Device (HAL) */
  1590. USB_DEVICE(0x0424, 0x9906),
  1591. .driver_info = (unsigned long) &smsc95xx_info,
  1592. },
  1593. {
  1594. /* SMSC9500 USB Ethernet Device (Alternate ID) */
  1595. USB_DEVICE(0x0424, 0x9907),
  1596. .driver_info = (unsigned long) &smsc95xx_info,
  1597. },
  1598. {
  1599. /* SMSC9500A USB Ethernet Device (Alternate ID) */
  1600. USB_DEVICE(0x0424, 0x9908),
  1601. .driver_info = (unsigned long) &smsc95xx_info,
  1602. },
  1603. {
  1604. /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
  1605. USB_DEVICE(0x0424, 0x9909),
  1606. .driver_info = (unsigned long) &smsc95xx_info,
  1607. },
  1608. {
  1609. /* SMSC LAN9530 USB Ethernet Device */
  1610. USB_DEVICE(0x0424, 0x9530),
  1611. .driver_info = (unsigned long) &smsc95xx_info,
  1612. },
  1613. {
  1614. /* SMSC LAN9730 USB Ethernet Device */
  1615. USB_DEVICE(0x0424, 0x9730),
  1616. .driver_info = (unsigned long) &smsc95xx_info,
  1617. },
  1618. {
  1619. /* SMSC LAN89530 USB Ethernet Device */
  1620. USB_DEVICE(0x0424, 0x9E08),
  1621. .driver_info = (unsigned long) &smsc95xx_info,
  1622. },
  1623. { }, /* END */
  1624. };
  1625. MODULE_DEVICE_TABLE(usb, products);
  1626. static struct usb_driver smsc95xx_driver = {
  1627. .name = "smsc95xx",
  1628. .id_table = products,
  1629. .probe = usbnet_probe,
  1630. .suspend = smsc95xx_suspend,
  1631. .resume = smsc95xx_resume,
  1632. .reset_resume = smsc95xx_resume,
  1633. .disconnect = usbnet_disconnect,
  1634. .disable_hub_initiated_lpm = 1,
  1635. .supports_autosuspend = 1,
  1636. };
  1637. module_usb_driver(smsc95xx_driver);
  1638. MODULE_AUTHOR("Nancy Lin");
  1639. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1640. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1641. MODULE_LICENSE("GPL");