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mach-omap2
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prcm_mpu44xx.h

prcm_mpu44xx.h 4.2 KB
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  1. /*
    2. 

  2.  * OMAP44xx PRCM MPU instance offset macros
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2010 Texas Instruments, Inc.
    5. 

  5.  * Copyright (C) 2010 Nokia Corporation
    6. 

  6.  *
    7. 

  7.  * Paul Walmsley (paul@pwsan.com)
    8. 

  8.  * Rajendra Nayak (rnayak@ti.com)
    9. 

  9.  * Benoit Cousson (b-cousson@ti.com)
    10. 

  10.  *
    11. 

  11.  * This file is automatically generated from the OMAP hardware databases.
    12. 

  12.  * We respectfully ask that any modifications to this file be coordinated
    13. 

  13.  * with the public linux-omap@vger.kernel.org mailing list and the
    14. 

  14.  * authors above to ensure that the autogeneration scripts are kept
    15. 

  15.  * up-to-date with the file contents.
    16. 

  16.  *
    17. 

  17.  * This program is free software; you can redistribute it and/or modify
    18. 

  18.  * it under the terms of the GNU General Public License version 2 as
    19. 

  19.  * published by the Free Software Foundation.
    20. 

  20.  *
    21. 

  21.  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
    22. 

  22.  *     or "OMAP4430".
    23. 

  23.  */
    24. 

  24. 

  25. #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
    26. 

  26. #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
    27. 

  27. 

  28. #define OMAP4430_PRCM_MPU_BASE			0x48243000
    29. 

  29. 

  30. #define OMAP44XX_PRCM_MPU_REGADDR(module, reg)				\
    31. 

  31. 	OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
    32. 

  32. 

  33. /* PRCM_MPU instances */
    34. 

  34. 

  35. #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD	0x0000
    36. 

  36. #define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD	0x0200
    37. 

  37. #define OMAP4430_PRCM_MPU_CPU0_MOD		0x0400
    38. 

  38. #define OMAP4430_PRCM_MPU_CPU1_MOD		0x0800
    39. 

  39. 

  40. /*
    41. 

  41.  * PRCM_MPU
    42. 

  42.  *
    43. 

  43.  * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
    44. 

  44.  * point of view the PRCM_MPU is a single entity. It shares the same
    45. 

  45.  * programming model as the global PRCM and thus can be assimilate as two new
    46. 

  46.  * MOD inside the PRCM
    47. 

  47.  */
    48. 

  48. 

  49. /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
    50. 

  50. #define OMAP4_REVISION_PRCM_OFFSET			0x0000
    51. 

  51. #define OMAP4430_REVISION_PRCM				OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000)
    52. 

  52. 

  53. /* PRCM_MPU.DEVICE_PRM register offsets */
    54. 

  54. #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET			0x0000
    55. 

  55. #define OMAP4430_PRCM_MPU_PRM_RSTST			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
    56. 

  56. #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET		0x0004
    57. 

  57. #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
    58. 

  58. 

  59. /* PRCM_MPU.CPU0 register offsets */
    60. 

  60. #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET			0x0000
    61. 

  61. #define OMAP4430_PM_CPU0_PWRSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000)
    62. 

  62. #define OMAP4_PM_CPU0_PWRSTST_OFFSET			0x0004
    63. 

  63. #define OMAP4430_PM_CPU0_PWRSTST			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004)
    64. 

  64. #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET		0x0008
    65. 

  65. #define OMAP4430_RM_CPU0_CPU0_CONTEXT			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008)
    66. 

  66. #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET		0x000c
    67. 

  67. #define OMAP4430_RM_CPU0_CPU0_RSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c)
    68. 

  68. #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET			0x0010
    69. 

  69. #define OMAP4430_RM_CPU0_CPU0_RSTST			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010)
    70. 

  70. #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET		0x0014
    71. 

  71. #define OMAP4430_CM_CPU0_CPU0_CLKCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014)
    72. 

  72. #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET			0x0018
    73. 

  73. #define OMAP4430_CM_CPU0_CLKSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018)
    74. 

  74. 

  75. /* PRCM_MPU.CPU1 register offsets */
    76. 

  76. #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET			0x0000
    77. 

  77. #define OMAP4430_PM_CPU1_PWRSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000)
    78. 

  78. #define OMAP4_PM_CPU1_PWRSTST_OFFSET			0x0004
    79. 

  79. #define OMAP4430_PM_CPU1_PWRSTST			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004)
    80. 

  80. #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET		0x0008
    81. 

  81. #define OMAP4430_RM_CPU1_CPU1_CONTEXT			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008)
    82. 

  82. #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET		0x000c
    83. 

  83. #define OMAP4430_RM_CPU1_CPU1_RSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c)
    84. 

  84. #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET			0x0010
    85. 

  85. #define OMAP4430_RM_CPU1_CPU1_RSTST			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010)
    86. 

  86. #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET		0x0014
    87. 

  87. #define OMAP4430_CM_CPU1_CPU1_CLKCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014)
    88. 

  88. #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET			0x0018
    89. 

  89. #define OMAP4430_CM_CPU1_CLKSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018)
    90. 

  90. 

  91. #endif
    92.