netxen_nic_init.c 36 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. unsigned long last_schedule_time;
  43. #define NETXEN_MAX_CRB_XFORM 60
  44. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  45. #define NETXEN_ADDR_ERROR (0xffffffff)
  46. #define crb_addr_transform(name) \
  47. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  48. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  49. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  50. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  51. uint32_t ctx, uint32_t ringid);
  52. #if 0
  53. static void netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  54. unsigned long off, int *data)
  55. {
  56. void __iomem *addr = pci_base_offset(adapter, off);
  57. writel(*data, addr);
  58. }
  59. #endif /* 0 */
  60. static void crb_addr_transform_setup(void)
  61. {
  62. crb_addr_transform(XDMA);
  63. crb_addr_transform(TIMR);
  64. crb_addr_transform(SRE);
  65. crb_addr_transform(SQN3);
  66. crb_addr_transform(SQN2);
  67. crb_addr_transform(SQN1);
  68. crb_addr_transform(SQN0);
  69. crb_addr_transform(SQS3);
  70. crb_addr_transform(SQS2);
  71. crb_addr_transform(SQS1);
  72. crb_addr_transform(SQS0);
  73. crb_addr_transform(RPMX7);
  74. crb_addr_transform(RPMX6);
  75. crb_addr_transform(RPMX5);
  76. crb_addr_transform(RPMX4);
  77. crb_addr_transform(RPMX3);
  78. crb_addr_transform(RPMX2);
  79. crb_addr_transform(RPMX1);
  80. crb_addr_transform(RPMX0);
  81. crb_addr_transform(ROMUSB);
  82. crb_addr_transform(SN);
  83. crb_addr_transform(QMN);
  84. crb_addr_transform(QMS);
  85. crb_addr_transform(PGNI);
  86. crb_addr_transform(PGND);
  87. crb_addr_transform(PGN3);
  88. crb_addr_transform(PGN2);
  89. crb_addr_transform(PGN1);
  90. crb_addr_transform(PGN0);
  91. crb_addr_transform(PGSI);
  92. crb_addr_transform(PGSD);
  93. crb_addr_transform(PGS3);
  94. crb_addr_transform(PGS2);
  95. crb_addr_transform(PGS1);
  96. crb_addr_transform(PGS0);
  97. crb_addr_transform(PS);
  98. crb_addr_transform(PH);
  99. crb_addr_transform(NIU);
  100. crb_addr_transform(I2Q);
  101. crb_addr_transform(EG);
  102. crb_addr_transform(MN);
  103. crb_addr_transform(MS);
  104. crb_addr_transform(CAS2);
  105. crb_addr_transform(CAS1);
  106. crb_addr_transform(CAS0);
  107. crb_addr_transform(CAM);
  108. crb_addr_transform(C2C1);
  109. crb_addr_transform(C2C0);
  110. crb_addr_transform(SMB);
  111. }
  112. int netxen_init_firmware(struct netxen_adapter *adapter)
  113. {
  114. u32 state = 0, loops = 0, err = 0;
  115. /* Window 1 call */
  116. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  117. if (state == PHAN_INITIALIZE_ACK)
  118. return 0;
  119. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  120. udelay(100);
  121. /* Window 1 call */
  122. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  123. loops++;
  124. }
  125. if (loops >= 2000) {
  126. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  127. state);
  128. err = -EIO;
  129. return err;
  130. }
  131. /* Window 1 call */
  132. writel(INTR_SCHEME_PERPORT,
  133. NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_HOST));
  134. writel(MSI_MODE_MULTIFUNC,
  135. NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_HOST));
  136. writel(MPORT_MULTI_FUNCTION_MODE,
  137. NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE));
  138. writel(PHAN_INITIALIZE_ACK,
  139. NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  140. return err;
  141. }
  142. #define NETXEN_ADDR_LIMIT 0xffffffffULL
  143. void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
  144. struct pci_dev **used_dev)
  145. {
  146. void *addr;
  147. addr = pci_alloc_consistent(pdev, sz, ptr);
  148. if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) {
  149. *used_dev = pdev;
  150. return addr;
  151. }
  152. pci_free_consistent(pdev, sz, addr, *ptr);
  153. addr = pci_alloc_consistent(NULL, sz, ptr);
  154. *used_dev = NULL;
  155. return addr;
  156. }
  157. void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
  158. {
  159. int ctxid, ring;
  160. u32 i;
  161. u32 num_rx_bufs = 0;
  162. struct netxen_rcv_desc_ctx *rcv_desc;
  163. DPRINTK(INFO, "initializing some queues: %p\n", adapter);
  164. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  165. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  166. struct netxen_rx_buffer *rx_buf;
  167. rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring];
  168. rcv_desc->begin_alloc = 0;
  169. rx_buf = rcv_desc->rx_buf_arr;
  170. num_rx_bufs = rcv_desc->max_rx_desc_count;
  171. /*
  172. * Now go through all of them, set reference handles
  173. * and put them in the queues.
  174. */
  175. for (i = 0; i < num_rx_bufs; i++) {
  176. rx_buf->ref_handle = i;
  177. rx_buf->state = NETXEN_BUFFER_FREE;
  178. DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
  179. "%p\n", ctxid, i, rx_buf);
  180. rx_buf++;
  181. }
  182. }
  183. }
  184. }
  185. void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
  186. {
  187. int ports = 0;
  188. struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
  189. if (netxen_nic_get_board_info(adapter) != 0)
  190. printk("%s: Error getting board config info.\n",
  191. netxen_nic_driver_name);
  192. get_brd_port_by_type(board_info->board_type, &ports);
  193. if (ports == 0)
  194. printk(KERN_ERR "%s: Unknown board type\n",
  195. netxen_nic_driver_name);
  196. adapter->ahw.max_ports = ports;
  197. }
  198. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  199. {
  200. switch (adapter->ahw.board_type) {
  201. case NETXEN_NIC_GBE:
  202. adapter->enable_phy_interrupts =
  203. netxen_niu_gbe_enable_phy_interrupts;
  204. adapter->disable_phy_interrupts =
  205. netxen_niu_gbe_disable_phy_interrupts;
  206. adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
  207. adapter->macaddr_set = netxen_niu_macaddr_set;
  208. adapter->set_mtu = netxen_nic_set_mtu_gb;
  209. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  210. adapter->unset_promisc = netxen_niu_set_promiscuous_mode;
  211. adapter->phy_read = netxen_niu_gbe_phy_read;
  212. adapter->phy_write = netxen_niu_gbe_phy_write;
  213. adapter->init_niu = netxen_nic_init_niu_gb;
  214. adapter->stop_port = netxen_niu_disable_gbe_port;
  215. break;
  216. case NETXEN_NIC_XGBE:
  217. adapter->enable_phy_interrupts =
  218. netxen_niu_xgbe_enable_phy_interrupts;
  219. adapter->disable_phy_interrupts =
  220. netxen_niu_xgbe_disable_phy_interrupts;
  221. adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
  222. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  223. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  224. adapter->init_port = netxen_niu_xg_init_port;
  225. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  226. adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
  227. adapter->stop_port = netxen_niu_disable_xg_port;
  228. break;
  229. default:
  230. break;
  231. }
  232. }
  233. /*
  234. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  235. * address to external PCI CRB address.
  236. */
  237. static u32 netxen_decode_crb_addr(u32 addr)
  238. {
  239. int i;
  240. u32 base_addr, offset, pci_base;
  241. crb_addr_transform_setup();
  242. pci_base = NETXEN_ADDR_ERROR;
  243. base_addr = addr & 0xfff00000;
  244. offset = addr & 0x000fffff;
  245. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  246. if (crb_addr_xform[i] == base_addr) {
  247. pci_base = i << 20;
  248. break;
  249. }
  250. }
  251. if (pci_base == NETXEN_ADDR_ERROR)
  252. return pci_base;
  253. else
  254. return (pci_base + offset);
  255. }
  256. static long rom_max_timeout = 100;
  257. static long rom_lock_timeout = 10000;
  258. static long rom_write_timeout = 700;
  259. static int rom_lock(struct netxen_adapter *adapter)
  260. {
  261. int iter;
  262. u32 done = 0;
  263. int timeout = 0;
  264. while (!done) {
  265. /* acquire semaphore2 from PCI HW block */
  266. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  267. &done);
  268. if (done == 1)
  269. break;
  270. if (timeout >= rom_lock_timeout)
  271. return -EIO;
  272. timeout++;
  273. /*
  274. * Yield CPU
  275. */
  276. if (!in_atomic())
  277. schedule();
  278. else {
  279. for (iter = 0; iter < 20; iter++)
  280. cpu_relax(); /*This a nop instr on i386 */
  281. }
  282. }
  283. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  284. return 0;
  285. }
  286. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  287. {
  288. long timeout = 0;
  289. long done = 0;
  290. while (done == 0) {
  291. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  292. done &= 2;
  293. timeout++;
  294. if (timeout >= rom_max_timeout) {
  295. printk("Timeout reached waiting for rom done");
  296. return -EIO;
  297. }
  298. }
  299. return 0;
  300. }
  301. static int netxen_rom_wren(struct netxen_adapter *adapter)
  302. {
  303. /* Set write enable latch in ROM status register */
  304. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  305. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  306. M25P_INSTR_WREN);
  307. if (netxen_wait_rom_done(adapter)) {
  308. return -1;
  309. }
  310. return 0;
  311. }
  312. static unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  313. unsigned int addr)
  314. {
  315. unsigned int data = 0xdeaddead;
  316. data = netxen_nic_reg_read(adapter, addr);
  317. return data;
  318. }
  319. static int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  320. {
  321. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  322. M25P_INSTR_RDSR);
  323. if (netxen_wait_rom_done(adapter)) {
  324. return -1;
  325. }
  326. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  327. }
  328. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  329. {
  330. u32 val;
  331. /* release semaphore2 */
  332. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  333. }
  334. static int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  335. {
  336. long timeout = 0;
  337. long wip = 1;
  338. int val;
  339. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  340. while (wip != 0) {
  341. val = netxen_do_rom_rdsr(adapter);
  342. wip = val & 1;
  343. timeout++;
  344. if (timeout > rom_max_timeout) {
  345. return -1;
  346. }
  347. }
  348. return 0;
  349. }
  350. static int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  351. int data)
  352. {
  353. if (netxen_rom_wren(adapter)) {
  354. return -1;
  355. }
  356. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  357. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  358. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  359. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  360. M25P_INSTR_PP);
  361. if (netxen_wait_rom_done(adapter)) {
  362. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  363. return -1;
  364. }
  365. return netxen_rom_wip_poll(adapter);
  366. }
  367. static int do_rom_fast_read(struct netxen_adapter *adapter,
  368. int addr, int *valp)
  369. {
  370. cond_resched();
  371. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  372. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  373. udelay(100); /* prevent bursting on CRB */
  374. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  375. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  376. if (netxen_wait_rom_done(adapter)) {
  377. printk("Error waiting for rom done\n");
  378. return -EIO;
  379. }
  380. /* reset abyte_cnt and dummy_byte_cnt */
  381. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  382. udelay(100); /* prevent bursting on CRB */
  383. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  384. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  385. return 0;
  386. }
  387. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  388. u8 *bytes, size_t size)
  389. {
  390. int addridx;
  391. int ret = 0;
  392. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  393. int v;
  394. ret = do_rom_fast_read(adapter, addridx, &v);
  395. if (ret != 0)
  396. break;
  397. *(__le32 *)bytes = cpu_to_le32(v);
  398. bytes += 4;
  399. }
  400. return ret;
  401. }
  402. int
  403. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  404. u8 *bytes, size_t size)
  405. {
  406. int ret;
  407. ret = rom_lock(adapter);
  408. if (ret < 0)
  409. return ret;
  410. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  411. netxen_rom_unlock(adapter);
  412. return ret;
  413. }
  414. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  415. {
  416. int ret;
  417. if (rom_lock(adapter) != 0)
  418. return -EIO;
  419. ret = do_rom_fast_read(adapter, addr, valp);
  420. netxen_rom_unlock(adapter);
  421. return ret;
  422. }
  423. #if 0
  424. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  425. {
  426. int ret = 0;
  427. if (rom_lock(adapter) != 0) {
  428. return -1;
  429. }
  430. ret = do_rom_fast_write(adapter, addr, data);
  431. netxen_rom_unlock(adapter);
  432. return ret;
  433. }
  434. #endif /* 0 */
  435. static int do_rom_fast_write_words(struct netxen_adapter *adapter,
  436. int addr, u8 *bytes, size_t size)
  437. {
  438. int addridx = addr;
  439. int ret = 0;
  440. while (addridx < (addr + size)) {
  441. int last_attempt = 0;
  442. int timeout = 0;
  443. int data;
  444. data = le32_to_cpu((*(__le32*)bytes));
  445. ret = do_rom_fast_write(adapter, addridx, data);
  446. if (ret < 0)
  447. return ret;
  448. while(1) {
  449. int data1;
  450. ret = do_rom_fast_read(adapter, addridx, &data1);
  451. if (ret < 0)
  452. return ret;
  453. if (data1 == data)
  454. break;
  455. if (timeout++ >= rom_write_timeout) {
  456. if (last_attempt++ < 4) {
  457. ret = do_rom_fast_write(adapter,
  458. addridx, data);
  459. if (ret < 0)
  460. return ret;
  461. }
  462. else {
  463. printk(KERN_INFO "Data write did not "
  464. "succeed at address 0x%x\n", addridx);
  465. break;
  466. }
  467. }
  468. }
  469. bytes += 4;
  470. addridx += 4;
  471. }
  472. return ret;
  473. }
  474. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  475. u8 *bytes, size_t size)
  476. {
  477. int ret = 0;
  478. ret = rom_lock(adapter);
  479. if (ret < 0)
  480. return ret;
  481. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  482. netxen_rom_unlock(adapter);
  483. return ret;
  484. }
  485. static int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  486. {
  487. int ret;
  488. ret = netxen_rom_wren(adapter);
  489. if (ret < 0)
  490. return ret;
  491. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  492. netxen_crb_writelit_adapter(adapter,
  493. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  494. ret = netxen_wait_rom_done(adapter);
  495. if (ret < 0)
  496. return ret;
  497. return netxen_rom_wip_poll(adapter);
  498. }
  499. static int netxen_rom_rdsr(struct netxen_adapter *adapter)
  500. {
  501. int ret;
  502. ret = rom_lock(adapter);
  503. if (ret < 0)
  504. return ret;
  505. ret = netxen_do_rom_rdsr(adapter);
  506. netxen_rom_unlock(adapter);
  507. return ret;
  508. }
  509. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  510. {
  511. int ret = FLASH_SUCCESS;
  512. int val;
  513. char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL);
  514. if (!buffer)
  515. return -ENOMEM;
  516. /* unlock sector 63 */
  517. val = netxen_rom_rdsr(adapter);
  518. val = val & 0xe3;
  519. ret = netxen_rom_wrsr(adapter, val);
  520. if (ret != FLASH_SUCCESS)
  521. goto out_kfree;
  522. ret = netxen_rom_wip_poll(adapter);
  523. if (ret != FLASH_SUCCESS)
  524. goto out_kfree;
  525. /* copy sector 0 to sector 63 */
  526. ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START,
  527. buffer, NETXEN_FLASH_SECTOR_SIZE);
  528. if (ret != FLASH_SUCCESS)
  529. goto out_kfree;
  530. ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START,
  531. buffer, NETXEN_FLASH_SECTOR_SIZE);
  532. if (ret != FLASH_SUCCESS)
  533. goto out_kfree;
  534. /* lock sector 63 */
  535. val = netxen_rom_rdsr(adapter);
  536. if (!(val & 0x8)) {
  537. val |= (0x1 << 2);
  538. /* lock sector 63 */
  539. if (netxen_rom_wrsr(adapter, val) == 0) {
  540. ret = netxen_rom_wip_poll(adapter);
  541. if (ret != FLASH_SUCCESS)
  542. goto out_kfree;
  543. /* lock SR writes */
  544. ret = netxen_rom_wip_poll(adapter);
  545. if (ret != FLASH_SUCCESS)
  546. goto out_kfree;
  547. }
  548. }
  549. out_kfree:
  550. kfree(buffer);
  551. return ret;
  552. }
  553. static int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  554. {
  555. netxen_rom_wren(adapter);
  556. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  557. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  558. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  559. M25P_INSTR_SE);
  560. if (netxen_wait_rom_done(adapter)) {
  561. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  562. return -1;
  563. }
  564. return netxen_rom_wip_poll(adapter);
  565. }
  566. static void check_erased_flash(struct netxen_adapter *adapter, int addr)
  567. {
  568. int i;
  569. int val;
  570. int count = 0, erased_errors = 0;
  571. int range;
  572. range = (addr == NETXEN_USER_START) ?
  573. NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE;
  574. for (i = addr; i < range; i += 4) {
  575. netxen_rom_fast_read(adapter, i, &val);
  576. if (val != 0xffffffff)
  577. erased_errors++;
  578. count++;
  579. }
  580. if (erased_errors)
  581. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  582. "for sector address: %x\n", erased_errors, count, addr);
  583. }
  584. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  585. {
  586. int ret = 0;
  587. if (rom_lock(adapter) != 0) {
  588. return -1;
  589. }
  590. ret = netxen_do_rom_se(adapter, addr);
  591. netxen_rom_unlock(adapter);
  592. msleep(30);
  593. check_erased_flash(adapter, addr);
  594. return ret;
  595. }
  596. static int netxen_flash_erase_sections(struct netxen_adapter *adapter,
  597. int start, int end)
  598. {
  599. int ret = FLASH_SUCCESS;
  600. int i;
  601. for (i = start; i < end; i++) {
  602. ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE);
  603. if (ret)
  604. break;
  605. ret = netxen_rom_wip_poll(adapter);
  606. if (ret < 0)
  607. return ret;
  608. }
  609. return ret;
  610. }
  611. int
  612. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  613. {
  614. int ret = FLASH_SUCCESS;
  615. int start, end;
  616. start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  617. end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE;
  618. ret = netxen_flash_erase_sections(adapter, start, end);
  619. return ret;
  620. }
  621. int
  622. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  623. {
  624. int ret = FLASH_SUCCESS;
  625. int start, end;
  626. start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE;
  627. end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  628. ret = netxen_flash_erase_sections(adapter, start, end);
  629. return ret;
  630. }
  631. void netxen_halt_pegs(struct netxen_adapter *adapter)
  632. {
  633. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  634. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  635. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  636. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  637. }
  638. int netxen_flash_unlock(struct netxen_adapter *adapter)
  639. {
  640. int ret = 0;
  641. ret = netxen_rom_wrsr(adapter, 0);
  642. if (ret < 0)
  643. return ret;
  644. ret = netxen_rom_wren(adapter);
  645. if (ret < 0)
  646. return ret;
  647. return ret;
  648. }
  649. #define NETXEN_BOARDTYPE 0x4008
  650. #define NETXEN_BOARDNUM 0x400c
  651. #define NETXEN_CHIPNUM 0x4010
  652. #define NETXEN_ROMBUS_RESET 0xFFFFFFFF
  653. #define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL
  654. #define NETXEN_ROM_FOUND_INIT 0x400
  655. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  656. {
  657. int addr, val, status;
  658. int n, i;
  659. int init_delay = 0;
  660. struct crb_addr_pair *buf;
  661. u32 off;
  662. /* resetall */
  663. status = netxen_nic_get_board_info(adapter);
  664. if (status)
  665. printk("%s: netxen_pinit_from_rom: Error getting board info\n",
  666. netxen_nic_driver_name);
  667. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  668. NETXEN_ROMBUS_RESET);
  669. if (verbose) {
  670. int val;
  671. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  672. printk("P2 ROM board type: 0x%08x\n", val);
  673. else
  674. printk("Could not read board type\n");
  675. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  676. printk("P2 ROM board num: 0x%08x\n", val);
  677. else
  678. printk("Could not read board number\n");
  679. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  680. printk("P2 ROM chip num: 0x%08x\n", val);
  681. else
  682. printk("Could not read chip number\n");
  683. }
  684. if (netxen_rom_fast_read(adapter, 0, &n) == 0
  685. && (n & NETXEN_ROM_FIRST_BARRIER)) {
  686. n &= ~NETXEN_ROM_ROUNDUP;
  687. if (n < NETXEN_ROM_FOUND_INIT) {
  688. if (verbose)
  689. printk("%s: %d CRB init values found"
  690. " in ROM.\n", netxen_nic_driver_name, n);
  691. } else {
  692. printk("%s:n=0x%x Error! NetXen card flash not"
  693. " initialized.\n", __FUNCTION__, n);
  694. return -EIO;
  695. }
  696. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  697. if (buf == NULL) {
  698. printk("%s: netxen_pinit_from_rom: Unable to calloc "
  699. "memory.\n", netxen_nic_driver_name);
  700. return -ENOMEM;
  701. }
  702. for (i = 0; i < n; i++) {
  703. if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0
  704. || netxen_rom_fast_read(adapter, 8 * i + 8,
  705. &addr) != 0)
  706. return -EIO;
  707. buf[i].addr = addr;
  708. buf[i].data = val;
  709. if (verbose)
  710. printk("%s: PCI: 0x%08x == 0x%08x\n",
  711. netxen_nic_driver_name, (unsigned int)
  712. netxen_decode_crb_addr(addr), val);
  713. }
  714. for (i = 0; i < n; i++) {
  715. off = netxen_decode_crb_addr(buf[i].addr);
  716. if (off == NETXEN_ADDR_ERROR) {
  717. printk(KERN_ERR"CRB init value out of range %x\n",
  718. buf[i].addr);
  719. continue;
  720. }
  721. off += NETXEN_PCI_CRBSPACE;
  722. /* skipping cold reboot MAGIC */
  723. if (off == NETXEN_CAM_RAM(0x1fc))
  724. continue;
  725. /* After writing this register, HW needs time for CRB */
  726. /* to quiet down (else crb_window returns 0xffffffff) */
  727. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  728. init_delay = 1;
  729. /* hold xdma in reset also */
  730. buf[i].data = NETXEN_NIC_XDMA_RESET;
  731. }
  732. if (ADDR_IN_WINDOW1(off)) {
  733. writel(buf[i].data,
  734. NETXEN_CRB_NORMALIZE(adapter, off));
  735. } else {
  736. netxen_nic_pci_change_crbwindow(adapter, 0);
  737. writel(buf[i].data,
  738. pci_base_offset(adapter, off));
  739. netxen_nic_pci_change_crbwindow(adapter, 1);
  740. }
  741. if (init_delay == 1) {
  742. msleep(2000);
  743. init_delay = 0;
  744. }
  745. msleep(20);
  746. }
  747. kfree(buf);
  748. /* disable_peg_cache_all */
  749. /* unreset_net_cache */
  750. netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
  751. 4);
  752. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  753. (val & 0xffffff0f));
  754. /* p2dn replyCount */
  755. netxen_crb_writelit_adapter(adapter,
  756. NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  757. /* disable_peg_cache 0 */
  758. netxen_crb_writelit_adapter(adapter,
  759. NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  760. /* disable_peg_cache 1 */
  761. netxen_crb_writelit_adapter(adapter,
  762. NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  763. /* peg_clr_all */
  764. /* peg_clr 0 */
  765. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8,
  766. 0);
  767. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc,
  768. 0);
  769. /* peg_clr 1 */
  770. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8,
  771. 0);
  772. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc,
  773. 0);
  774. /* peg_clr 2 */
  775. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8,
  776. 0);
  777. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc,
  778. 0);
  779. /* peg_clr 3 */
  780. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8,
  781. 0);
  782. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc,
  783. 0);
  784. }
  785. return 0;
  786. }
  787. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  788. {
  789. uint64_t addr;
  790. uint32_t hi;
  791. uint32_t lo;
  792. adapter->dummy_dma.addr =
  793. pci_alloc_consistent(adapter->ahw.pdev,
  794. NETXEN_HOST_DUMMY_DMA_SIZE,
  795. &adapter->dummy_dma.phys_addr);
  796. if (adapter->dummy_dma.addr == NULL) {
  797. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  798. __FUNCTION__);
  799. return -ENOMEM;
  800. }
  801. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  802. hi = (addr >> 32) & 0xffffffff;
  803. lo = addr & 0xffffffff;
  804. writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI));
  805. writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO));
  806. return 0;
  807. }
  808. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  809. {
  810. if (adapter->dummy_dma.addr) {
  811. pci_free_consistent(adapter->ahw.pdev,
  812. NETXEN_HOST_DUMMY_DMA_SIZE,
  813. adapter->dummy_dma.addr,
  814. adapter->dummy_dma.phys_addr);
  815. adapter->dummy_dma.addr = NULL;
  816. }
  817. }
  818. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  819. {
  820. u32 val = 0;
  821. int retries = 30;
  822. if (!pegtune_val) {
  823. do {
  824. val = readl(NETXEN_CRB_NORMALIZE
  825. (adapter, CRB_CMDPEG_STATE));
  826. pegtune_val = readl(NETXEN_CRB_NORMALIZE
  827. (adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE));
  828. if (val == PHAN_INITIALIZE_COMPLETE ||
  829. val == PHAN_INITIALIZE_ACK)
  830. return 0;
  831. msleep(1000);
  832. } while (--retries);
  833. if (!retries) {
  834. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  835. "pegtune_val=%x\n", pegtune_val);
  836. return -1;
  837. }
  838. }
  839. return 0;
  840. }
  841. static int netxen_nic_check_temp(struct netxen_adapter *adapter)
  842. {
  843. struct net_device *netdev = adapter->netdev;
  844. uint32_t temp, temp_state, temp_val;
  845. int rv = 0;
  846. temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE));
  847. temp_state = nx_get_temp_state(temp);
  848. temp_val = nx_get_temp_val(temp);
  849. if (temp_state == NX_TEMP_PANIC) {
  850. printk(KERN_ALERT
  851. "%s: Device temperature %d degrees C exceeds"
  852. " maximum allowed. Hardware has been shut down.\n",
  853. netxen_nic_driver_name, temp_val);
  854. netif_carrier_off(netdev);
  855. netif_stop_queue(netdev);
  856. rv = 1;
  857. } else if (temp_state == NX_TEMP_WARN) {
  858. if (adapter->temp == NX_TEMP_NORMAL) {
  859. printk(KERN_ALERT
  860. "%s: Device temperature %d degrees C "
  861. "exceeds operating range."
  862. " Immediate action needed.\n",
  863. netxen_nic_driver_name, temp_val);
  864. }
  865. } else {
  866. if (adapter->temp == NX_TEMP_WARN) {
  867. printk(KERN_INFO
  868. "%s: Device temperature is now %d degrees C"
  869. " in normal range.\n", netxen_nic_driver_name,
  870. temp_val);
  871. }
  872. }
  873. adapter->temp = temp_state;
  874. return rv;
  875. }
  876. void netxen_watchdog_task(struct work_struct *work)
  877. {
  878. struct netxen_adapter *adapter =
  879. container_of(work, struct netxen_adapter, watchdog_task);
  880. if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter))
  881. return;
  882. if (adapter->handle_phy_intr)
  883. adapter->handle_phy_intr(adapter);
  884. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  885. }
  886. /*
  887. * netxen_process_rcv() send the received packet to the protocol stack.
  888. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  889. * invoke the routine to send more rx buffers to the Phantom...
  890. */
  891. static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  892. struct status_desc *desc)
  893. {
  894. struct pci_dev *pdev = adapter->pdev;
  895. struct net_device *netdev = adapter->netdev;
  896. u64 sts_data = le64_to_cpu(desc->status_desc_data);
  897. int index = netxen_get_sts_refhandle(sts_data);
  898. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  899. struct netxen_rx_buffer *buffer;
  900. struct sk_buff *skb;
  901. u32 length = netxen_get_sts_totallength(sts_data);
  902. u32 desc_ctx;
  903. struct netxen_rcv_desc_ctx *rcv_desc;
  904. int ret;
  905. desc_ctx = netxen_get_sts_type(sts_data);
  906. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  907. printk("%s: %s Bad Rcv descriptor ring\n",
  908. netxen_nic_driver_name, netdev->name);
  909. return;
  910. }
  911. rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
  912. if (unlikely(index > rcv_desc->max_rx_desc_count)) {
  913. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  914. index, rcv_desc->max_rx_desc_count);
  915. return;
  916. }
  917. buffer = &rcv_desc->rx_buf_arr[index];
  918. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  919. buffer->lro_current_frags++;
  920. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  921. buffer->lro_expected_frags =
  922. netxen_get_sts_desc_lro_cnt(desc);
  923. buffer->lro_length = length;
  924. }
  925. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  926. if (buffer->lro_expected_frags != 0) {
  927. printk("LRO: (refhandle:%x) recv frag. "
  928. "wait for last. flags: %x expected:%d "
  929. "have:%d\n", index,
  930. netxen_get_sts_desc_lro_last_frag(desc),
  931. buffer->lro_expected_frags,
  932. buffer->lro_current_frags);
  933. }
  934. return;
  935. }
  936. }
  937. pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
  938. PCI_DMA_FROMDEVICE);
  939. skb = (struct sk_buff *)buffer->skb;
  940. if (likely(adapter->rx_csum &&
  941. netxen_get_sts_status(sts_data) == STATUS_CKSUM_OK)) {
  942. adapter->stats.csummed++;
  943. skb->ip_summed = CHECKSUM_UNNECESSARY;
  944. } else
  945. skb->ip_summed = CHECKSUM_NONE;
  946. skb->dev = netdev;
  947. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  948. /* True length was only available on the last pkt */
  949. skb_put(skb, buffer->lro_length);
  950. } else {
  951. skb_put(skb, length);
  952. }
  953. skb->protocol = eth_type_trans(skb, netdev);
  954. ret = netif_receive_skb(skb);
  955. netdev->last_rx = jiffies;
  956. rcv_desc->rcv_pending--;
  957. /*
  958. * We just consumed one buffer so post a buffer.
  959. */
  960. buffer->skb = NULL;
  961. buffer->state = NETXEN_BUFFER_FREE;
  962. buffer->lro_current_frags = 0;
  963. buffer->lro_expected_frags = 0;
  964. adapter->stats.no_rcv++;
  965. adapter->stats.rxbytes += length;
  966. }
  967. /* Process Receive status ring */
  968. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  969. {
  970. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  971. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  972. struct status_desc *desc; /* used to read status desc here */
  973. u32 consumer = recv_ctx->status_rx_consumer;
  974. u32 producer = 0;
  975. int count = 0, ring;
  976. while (count < max) {
  977. desc = &desc_head[consumer];
  978. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  979. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  980. netxen_get_sts_owner(desc));
  981. break;
  982. }
  983. netxen_process_rcv(adapter, ctxid, desc);
  984. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  985. consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
  986. count++;
  987. }
  988. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  989. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  990. }
  991. /* update the consumer index in phantom */
  992. if (count) {
  993. recv_ctx->status_rx_consumer = consumer;
  994. recv_ctx->status_rx_producer = producer;
  995. /* Window = 1 */
  996. writel(consumer,
  997. NETXEN_CRB_NORMALIZE(adapter,
  998. recv_crb_registers[adapter->portnum].
  999. crb_rcv_status_consumer));
  1000. }
  1001. return count;
  1002. }
  1003. /* Process Command status ring */
  1004. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1005. {
  1006. u32 last_consumer, consumer;
  1007. int count = 0, i;
  1008. struct netxen_cmd_buffer *buffer;
  1009. struct pci_dev *pdev = adapter->pdev;
  1010. struct net_device *netdev = adapter->netdev;
  1011. struct netxen_skb_frag *frag;
  1012. int done = 0;
  1013. last_consumer = adapter->last_cmd_consumer;
  1014. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1015. while (last_consumer != consumer) {
  1016. buffer = &adapter->cmd_buf_arr[last_consumer];
  1017. if (buffer->skb) {
  1018. frag = &buffer->frag_array[0];
  1019. pci_unmap_single(pdev, frag->dma, frag->length,
  1020. PCI_DMA_TODEVICE);
  1021. frag->dma = 0ULL;
  1022. for (i = 1; i < buffer->frag_count; i++) {
  1023. frag++; /* Get the next frag */
  1024. pci_unmap_page(pdev, frag->dma, frag->length,
  1025. PCI_DMA_TODEVICE);
  1026. frag->dma = 0ULL;
  1027. }
  1028. adapter->stats.xmitfinished++;
  1029. dev_kfree_skb_any(buffer->skb);
  1030. buffer->skb = NULL;
  1031. }
  1032. last_consumer = get_next_index(last_consumer,
  1033. adapter->max_tx_desc_count);
  1034. if (++count >= MAX_STATUS_HANDLE)
  1035. break;
  1036. }
  1037. if (count) {
  1038. adapter->last_cmd_consumer = last_consumer;
  1039. smp_mb();
  1040. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  1041. netif_tx_lock(netdev);
  1042. netif_wake_queue(netdev);
  1043. smp_mb();
  1044. netif_tx_unlock(netdev);
  1045. }
  1046. }
  1047. /*
  1048. * If everything is freed up to consumer then check if the ring is full
  1049. * If the ring is full then check if more needs to be freed and
  1050. * schedule the call back again.
  1051. *
  1052. * This happens when there are 2 CPUs. One could be freeing and the
  1053. * other filling it. If the ring is full when we get out of here and
  1054. * the card has already interrupted the host then the host can miss the
  1055. * interrupt.
  1056. *
  1057. * There is still a possible race condition and the host could miss an
  1058. * interrupt. The card has to take care of this.
  1059. */
  1060. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1061. done = (last_consumer == consumer);
  1062. return (done);
  1063. }
  1064. /*
  1065. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1066. */
  1067. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1068. {
  1069. struct pci_dev *pdev = adapter->ahw.pdev;
  1070. struct sk_buff *skb;
  1071. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1072. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1073. uint producer;
  1074. struct rcv_desc *pdesc;
  1075. struct netxen_rx_buffer *buffer;
  1076. int count = 0;
  1077. int index = 0;
  1078. netxen_ctx_msg msg = 0;
  1079. dma_addr_t dma;
  1080. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1081. producer = rcv_desc->producer;
  1082. index = rcv_desc->begin_alloc;
  1083. buffer = &rcv_desc->rx_buf_arr[index];
  1084. /* We can start writing rx descriptors into the phantom memory. */
  1085. while (buffer->state == NETXEN_BUFFER_FREE) {
  1086. skb = dev_alloc_skb(rcv_desc->skb_size);
  1087. if (unlikely(!skb)) {
  1088. /*
  1089. * TODO
  1090. * We need to schedule the posting of buffers to the pegs.
  1091. */
  1092. rcv_desc->begin_alloc = index;
  1093. DPRINTK(ERR, "netxen_post_rx_buffers: "
  1094. " allocated only %d buffers\n", count);
  1095. break;
  1096. }
  1097. count++; /* now there should be no failure */
  1098. pdesc = &rcv_desc->desc_head[producer];
  1099. #if defined(XGB_DEBUG)
  1100. *(unsigned long *)(skb->head) = 0xc0debabe;
  1101. if (skb_is_nonlinear(skb)) {
  1102. printk("Allocated SKB @%p is nonlinear\n");
  1103. }
  1104. #endif
  1105. skb_reserve(skb, 2);
  1106. /* This will be setup when we receive the
  1107. * buffer after it has been filled FSL TBD TBD
  1108. * skb->dev = netdev;
  1109. */
  1110. dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
  1111. PCI_DMA_FROMDEVICE);
  1112. pdesc->addr_buffer = cpu_to_le64(dma);
  1113. buffer->skb = skb;
  1114. buffer->state = NETXEN_BUFFER_BUSY;
  1115. buffer->dma = dma;
  1116. /* make a rcv descriptor */
  1117. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1118. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1119. DPRINTK(INFO, "done writing descripter\n");
  1120. producer =
  1121. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1122. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1123. buffer = &rcv_desc->rx_buf_arr[index];
  1124. }
  1125. /* if we did allocate buffers, then write the count to Phantom */
  1126. if (count) {
  1127. rcv_desc->begin_alloc = index;
  1128. rcv_desc->rcv_pending += count;
  1129. rcv_desc->producer = producer;
  1130. /* Window = 1 */
  1131. writel((producer - 1) &
  1132. (rcv_desc->max_rx_desc_count - 1),
  1133. NETXEN_CRB_NORMALIZE(adapter,
  1134. recv_crb_registers[
  1135. adapter->portnum].
  1136. rcv_desc_crb[ringid].
  1137. crb_rcv_producer_offset));
  1138. /*
  1139. * Write a doorbell msg to tell phanmon of change in
  1140. * receive ring producer
  1141. */
  1142. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1143. netxen_set_msg_privid(msg);
  1144. netxen_set_msg_count(msg,
  1145. ((producer -
  1146. 1) & (rcv_desc->
  1147. max_rx_desc_count - 1)));
  1148. netxen_set_msg_ctxid(msg, adapter->portnum);
  1149. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1150. writel(msg,
  1151. DB_NORMALIZE(adapter,
  1152. NETXEN_RCV_PRODUCER_OFFSET));
  1153. }
  1154. }
  1155. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1156. uint32_t ctx, uint32_t ringid)
  1157. {
  1158. struct pci_dev *pdev = adapter->ahw.pdev;
  1159. struct sk_buff *skb;
  1160. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1161. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1162. u32 producer;
  1163. struct rcv_desc *pdesc;
  1164. struct netxen_rx_buffer *buffer;
  1165. int count = 0;
  1166. int index = 0;
  1167. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1168. producer = rcv_desc->producer;
  1169. index = rcv_desc->begin_alloc;
  1170. buffer = &rcv_desc->rx_buf_arr[index];
  1171. /* We can start writing rx descriptors into the phantom memory. */
  1172. while (buffer->state == NETXEN_BUFFER_FREE) {
  1173. skb = dev_alloc_skb(rcv_desc->skb_size);
  1174. if (unlikely(!skb)) {
  1175. /*
  1176. * We need to schedule the posting of buffers to the pegs.
  1177. */
  1178. rcv_desc->begin_alloc = index;
  1179. DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
  1180. " allocated only %d buffers\n", count);
  1181. break;
  1182. }
  1183. count++; /* now there should be no failure */
  1184. pdesc = &rcv_desc->desc_head[producer];
  1185. skb_reserve(skb, 2);
  1186. /*
  1187. * This will be setup when we receive the
  1188. * buffer after it has been filled
  1189. * skb->dev = netdev;
  1190. */
  1191. buffer->skb = skb;
  1192. buffer->state = NETXEN_BUFFER_BUSY;
  1193. buffer->dma = pci_map_single(pdev, skb->data,
  1194. rcv_desc->dma_size,
  1195. PCI_DMA_FROMDEVICE);
  1196. /* make a rcv descriptor */
  1197. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1198. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1199. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1200. DPRINTK(INFO, "done writing descripter\n");
  1201. producer =
  1202. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1203. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1204. buffer = &rcv_desc->rx_buf_arr[index];
  1205. }
  1206. /* if we did allocate buffers, then write the count to Phantom */
  1207. if (count) {
  1208. rcv_desc->begin_alloc = index;
  1209. rcv_desc->rcv_pending += count;
  1210. rcv_desc->producer = producer;
  1211. /* Window = 1 */
  1212. writel((producer - 1) &
  1213. (rcv_desc->max_rx_desc_count - 1),
  1214. NETXEN_CRB_NORMALIZE(adapter,
  1215. recv_crb_registers[
  1216. adapter->portnum].
  1217. rcv_desc_crb[ringid].
  1218. crb_rcv_producer_offset));
  1219. wmb();
  1220. }
  1221. }
  1222. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1223. {
  1224. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1225. return;
  1226. }