tifm_ms.c 17 KB

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  1. /*
  2. * TI FlashMedia driver
  3. *
  4. * Copyright (C) 2007 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Special thanks to Carlos Corbacho for providing various MemoryStick cards
  11. * that made this driver possible.
  12. *
  13. */
  14. #include <linux/tifm.h>
  15. #include <linux/memstick.h>
  16. #include <linux/highmem.h>
  17. #include <linux/scatterlist.h>
  18. #include <linux/log2.h>
  19. #include <asm/io.h>
  20. #define DRIVER_NAME "tifm_ms"
  21. #define DRIVER_VERSION "0.1"
  22. static int no_dma;
  23. module_param(no_dma, bool, 0644);
  24. #define TIFM_MS_TIMEOUT 0x00100
  25. #define TIFM_MS_BADCRC 0x00200
  26. #define TIFM_MS_EOTPC 0x01000
  27. #define TIFM_MS_INT 0x02000
  28. /* The meaning of the bit majority in this constant is unknown. */
  29. #define TIFM_MS_SERIAL 0x04010
  30. #define TIFM_MS_SYS_LATCH 0x00100
  31. #define TIFM_MS_SYS_NOT_RDY 0x00800
  32. #define TIFM_MS_SYS_DATA 0x10000
  33. /* Hardware flags */
  34. enum {
  35. CMD_READY = 0x0001,
  36. FIFO_READY = 0x0002,
  37. CARD_READY = 0x0004,
  38. DATA_CARRY = 0x0008
  39. };
  40. struct tifm_ms {
  41. struct tifm_dev *dev;
  42. unsigned short eject:1,
  43. no_dma:1;
  44. unsigned short cmd_flags;
  45. unsigned int mode_mask;
  46. unsigned int block_pos;
  47. unsigned long timeout_jiffies;
  48. struct timer_list timer;
  49. struct memstick_request *req;
  50. unsigned int io_word;
  51. };
  52. static void tifm_ms_read_fifo(struct tifm_ms *host, unsigned int fifo_offset,
  53. struct page *pg, unsigned int page_off,
  54. unsigned int length)
  55. {
  56. struct tifm_dev *sock = host->dev;
  57. unsigned int cnt = 0, off = 0;
  58. unsigned char *buf = kmap_atomic(pg, KM_BIO_DST_IRQ) + page_off;
  59. if (host->cmd_flags & DATA_CARRY) {
  60. while ((fifo_offset & 3) && length) {
  61. buf[off++] = host->io_word & 0xff;
  62. host->io_word >>= 8;
  63. length--;
  64. fifo_offset++;
  65. }
  66. if (!(fifo_offset & 3))
  67. host->cmd_flags &= ~DATA_CARRY;
  68. if (!length)
  69. return;
  70. }
  71. do {
  72. host->io_word = readl(sock->addr + SOCK_FIFO_ACCESS
  73. + fifo_offset);
  74. cnt = 4;
  75. while (length && cnt) {
  76. buf[off++] = (host->io_word >> 8) & 0xff;
  77. cnt--;
  78. length--;
  79. }
  80. fifo_offset += 4 - cnt;
  81. } while (length);
  82. if (cnt)
  83. host->cmd_flags |= DATA_CARRY;
  84. kunmap_atomic(buf - page_off, KM_BIO_DST_IRQ);
  85. }
  86. static void tifm_ms_write_fifo(struct tifm_ms *host, unsigned int fifo_offset,
  87. struct page *pg, unsigned int page_off,
  88. unsigned int length)
  89. {
  90. struct tifm_dev *sock = host->dev;
  91. unsigned int cnt = 0, off = 0;
  92. unsigned char *buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + page_off;
  93. if (host->cmd_flags & DATA_CARRY) {
  94. while (fifo_offset & 3) {
  95. host->io_word |= buf[off++] << (8 * (fifo_offset & 3));
  96. length--;
  97. fifo_offset++;
  98. }
  99. if (!(fifo_offset & 3)) {
  100. writel(host->io_word, sock->addr + SOCK_FIFO_ACCESS
  101. + fifo_offset - 4);
  102. host->cmd_flags &= ~DATA_CARRY;
  103. }
  104. if (!length)
  105. return;
  106. }
  107. do {
  108. cnt = 4;
  109. host->io_word = 0;
  110. while (length && cnt) {
  111. host->io_word |= buf[off++] << (4 - cnt);
  112. cnt--;
  113. length--;
  114. }
  115. fifo_offset += 4 - cnt;
  116. if (!cnt)
  117. writel(host->io_word, sock->addr + SOCK_FIFO_ACCESS
  118. + fifo_offset - 4);
  119. } while (length);
  120. if (cnt)
  121. host->cmd_flags |= DATA_CARRY;
  122. kunmap_atomic(buf - page_off, KM_BIO_SRC_IRQ);
  123. }
  124. static void tifm_ms_move_block(struct tifm_ms *host, unsigned int length)
  125. {
  126. unsigned int t_size;
  127. unsigned int off = host->req->sg.offset + host->block_pos;
  128. unsigned int p_off, p_cnt;
  129. struct page *pg;
  130. unsigned long flags;
  131. dev_dbg(&host->dev->dev, "moving block\n");
  132. local_irq_save(flags);
  133. t_size = length;
  134. while (t_size) {
  135. pg = nth_page(sg_page(&host->req->sg), off >> PAGE_SHIFT);
  136. p_off = offset_in_page(off);
  137. p_cnt = PAGE_SIZE - p_off;
  138. p_cnt = min(p_cnt, t_size);
  139. if (host->req->data_dir == WRITE)
  140. tifm_ms_write_fifo(host, length - t_size,
  141. pg, p_off, p_cnt);
  142. else
  143. tifm_ms_read_fifo(host, length - t_size,
  144. pg, p_off, p_cnt);
  145. t_size -= p_cnt;
  146. }
  147. local_irq_restore(flags);
  148. }
  149. static int tifm_ms_transfer_data(struct tifm_ms *host, int skip)
  150. {
  151. struct tifm_dev *sock = host->dev;
  152. unsigned int length = host->req->sg.length - host->block_pos;
  153. if (!length)
  154. return 1;
  155. if (length > TIFM_FIFO_SIZE)
  156. length = TIFM_FIFO_SIZE;
  157. if (!skip) {
  158. tifm_ms_move_block(host, length);
  159. host->block_pos += length;
  160. }
  161. if ((host->req->data_dir == READ)
  162. && (host->block_pos == host->req->sg.length))
  163. return 1;
  164. writel(ilog2(length) - 2, sock->addr + SOCK_FIFO_PAGE_SIZE);
  165. if (host->req->data_dir == WRITE)
  166. writel((1 << 8) | TIFM_DMA_TX, sock->addr + SOCK_DMA_CONTROL);
  167. else
  168. writel((1 << 8), sock->addr + SOCK_DMA_CONTROL);
  169. return 0;
  170. }
  171. static int tifm_ms_issue_cmd(struct tifm_ms *host)
  172. {
  173. struct tifm_dev *sock = host->dev;
  174. unsigned char *data;
  175. unsigned int data_len = 0, cmd = 0, cmd_mask = 0, cnt, tval = 0;
  176. host->cmd_flags = 0;
  177. if (host->req->long_data) {
  178. if (!host->no_dma) {
  179. if (1 != tifm_map_sg(sock, &host->req->sg, 1,
  180. host->req->data_dir == READ
  181. ? PCI_DMA_FROMDEVICE
  182. : PCI_DMA_TODEVICE)) {
  183. host->req->error = -ENOMEM;
  184. return host->req->error;
  185. }
  186. data_len = sg_dma_len(&host->req->sg);
  187. } else
  188. data_len = host->req->sg.length;
  189. writel(TIFM_FIFO_INT_SETALL,
  190. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  191. writel(TIFM_FIFO_ENABLE,
  192. sock->addr + SOCK_FIFO_CONTROL);
  193. writel(TIFM_FIFO_INTMASK,
  194. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  195. if (!host->no_dma) {
  196. writel(ilog2(data_len) - 2,
  197. sock->addr + SOCK_FIFO_PAGE_SIZE);
  198. writel(sg_dma_address(&host->req->sg),
  199. sock->addr + SOCK_DMA_ADDRESS);
  200. if (host->req->data_dir == WRITE)
  201. writel((1 << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
  202. sock->addr + SOCK_DMA_CONTROL);
  203. else
  204. writel((1 << 8) | TIFM_DMA_EN,
  205. sock->addr + SOCK_DMA_CONTROL);
  206. } else {
  207. tifm_ms_transfer_data(host,
  208. host->req->data_dir == READ);
  209. }
  210. cmd_mask = readl(sock->addr + SOCK_MS_SYSTEM);
  211. cmd_mask |= TIFM_MS_SYS_DATA | TIFM_MS_SYS_NOT_RDY;
  212. writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM);
  213. } else {
  214. data = host->req->data;
  215. data_len = host->req->data_len;
  216. cmd_mask = host->mode_mask | 0x2607; /* unknown constant */
  217. if (host->req->data_dir == WRITE) {
  218. cmd_mask |= TIFM_MS_SYS_LATCH;
  219. writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM);
  220. for (cnt = 0; (data_len - cnt) >= 4; cnt += 4) {
  221. writel(TIFM_MS_SYS_LATCH
  222. | readl(sock->addr + SOCK_MS_SYSTEM),
  223. sock->addr + SOCK_MS_SYSTEM);
  224. __raw_writel(*(unsigned int *)(data + cnt),
  225. sock->addr + SOCK_MS_DATA);
  226. dev_dbg(&sock->dev, "writing %x\n",
  227. *(int *)(data + cnt));
  228. }
  229. switch (data_len - cnt) {
  230. case 3:
  231. tval |= data[cnt + 2] << 16;
  232. case 2:
  233. tval |= data[cnt + 1] << 8;
  234. case 1:
  235. tval |= data[cnt];
  236. writel(TIFM_MS_SYS_LATCH
  237. | readl(sock->addr + SOCK_MS_SYSTEM),
  238. sock->addr + SOCK_MS_SYSTEM);
  239. writel(tval, sock->addr + SOCK_MS_DATA);
  240. dev_dbg(&sock->dev, "writing %x\n", tval);
  241. }
  242. writel(TIFM_MS_SYS_LATCH
  243. | readl(sock->addr + SOCK_MS_SYSTEM),
  244. sock->addr + SOCK_MS_SYSTEM);
  245. writel(0, sock->addr + SOCK_MS_DATA);
  246. dev_dbg(&sock->dev, "writing %x\n", 0);
  247. } else
  248. writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM);
  249. cmd_mask = readl(sock->addr + SOCK_MS_SYSTEM);
  250. cmd_mask &= ~TIFM_MS_SYS_DATA;
  251. cmd_mask |= TIFM_MS_SYS_NOT_RDY;
  252. dev_dbg(&sock->dev, "mask %x\n", cmd_mask);
  253. writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM);
  254. }
  255. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  256. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  257. sock->addr + SOCK_CONTROL);
  258. host->req->error = 0;
  259. cmd = (host->req->tpc & 0xf) << 12;
  260. cmd |= data_len;
  261. writel(cmd, sock->addr + SOCK_MS_COMMAND);
  262. dev_dbg(&sock->dev, "executing TPC %x, %x\n", cmd, cmd_mask);
  263. return 0;
  264. }
  265. static void tifm_ms_complete_cmd(struct tifm_ms *host)
  266. {
  267. struct tifm_dev *sock = host->dev;
  268. struct memstick_host *msh = tifm_get_drvdata(sock);
  269. unsigned int tval = 0, data_len;
  270. unsigned char *data;
  271. int rc;
  272. del_timer(&host->timer);
  273. if (host->req->long_data) {
  274. if (!host->no_dma)
  275. tifm_unmap_sg(sock, &host->req->sg, 1,
  276. host->req->data_dir == READ
  277. ? PCI_DMA_FROMDEVICE
  278. : PCI_DMA_TODEVICE);
  279. } else {
  280. writel(~TIFM_MS_SYS_DATA & readl(sock->addr + SOCK_MS_SYSTEM),
  281. sock->addr + SOCK_MS_SYSTEM);
  282. data = host->req->data;
  283. data_len = host->req->data_len;
  284. if (host->req->data_dir == READ) {
  285. for (rc = 0; (data_len - rc) >= 4; rc += 4)
  286. *(int *)(data + rc)
  287. = __raw_readl(sock->addr
  288. + SOCK_MS_DATA);
  289. if (data_len - rc)
  290. tval = readl(sock->addr + SOCK_MS_DATA);
  291. switch (data_len - rc) {
  292. case 3:
  293. data[rc + 2] = (tval >> 16) & 0xff;
  294. case 2:
  295. data[rc + 1] = (tval >> 8) & 0xff;
  296. case 1:
  297. data[rc] = tval & 0xff;
  298. }
  299. readl(sock->addr + SOCK_MS_DATA);
  300. }
  301. }
  302. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  303. sock->addr + SOCK_CONTROL);
  304. do {
  305. rc = memstick_next_req(msh, &host->req);
  306. } while (!rc && tifm_ms_issue_cmd(host));
  307. }
  308. static int tifm_ms_check_status(struct tifm_ms *host)
  309. {
  310. if (!host->req->error) {
  311. if (!(host->cmd_flags & CMD_READY))
  312. return 1;
  313. if (host->req->long_data
  314. && !(host->cmd_flags & FIFO_READY))
  315. return 1;
  316. if (host->req->need_card_int
  317. && !(host->cmd_flags & CARD_READY))
  318. return 1;
  319. }
  320. return 0;
  321. }
  322. /* Called from interrupt handler */
  323. static void tifm_ms_data_event(struct tifm_dev *sock)
  324. {
  325. struct tifm_ms *host;
  326. unsigned int fifo_status = 0;
  327. int rc = 1;
  328. spin_lock(&sock->lock);
  329. host = memstick_priv((struct memstick_host *)tifm_get_drvdata(sock));
  330. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  331. dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
  332. fifo_status, host->cmd_flags);
  333. if (host->req) {
  334. if (fifo_status & TIFM_FIFO_READY) {
  335. if (!host->no_dma || tifm_ms_transfer_data(host, 0)) {
  336. host->cmd_flags |= FIFO_READY;
  337. rc = tifm_ms_check_status(host);
  338. }
  339. }
  340. }
  341. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  342. if (!rc)
  343. tifm_ms_complete_cmd(host);
  344. spin_unlock(&sock->lock);
  345. }
  346. /* Called from interrupt handler */
  347. static void tifm_ms_card_event(struct tifm_dev *sock)
  348. {
  349. struct tifm_ms *host;
  350. unsigned int host_status = 0;
  351. int rc = 1;
  352. spin_lock(&sock->lock);
  353. host = memstick_priv((struct memstick_host *)tifm_get_drvdata(sock));
  354. host_status = readl(sock->addr + SOCK_MS_STATUS);
  355. dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
  356. host_status, host->cmd_flags);
  357. if (host->req) {
  358. if (host_status & TIFM_MS_TIMEOUT)
  359. host->req->error = -ETIME;
  360. else if (host_status & TIFM_MS_BADCRC)
  361. host->req->error = -EILSEQ;
  362. if (host->req->error) {
  363. writel(TIFM_FIFO_INT_SETALL,
  364. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  365. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  366. }
  367. if (host_status & TIFM_MS_EOTPC)
  368. host->cmd_flags |= CMD_READY;
  369. if (host_status & TIFM_MS_INT)
  370. host->cmd_flags |= CARD_READY;
  371. rc = tifm_ms_check_status(host);
  372. }
  373. writel(TIFM_MS_SYS_NOT_RDY | readl(sock->addr + SOCK_MS_SYSTEM),
  374. sock->addr + SOCK_MS_SYSTEM);
  375. writel((~TIFM_MS_SYS_DATA) & readl(sock->addr + SOCK_MS_SYSTEM),
  376. sock->addr + SOCK_MS_SYSTEM);
  377. if (!rc)
  378. tifm_ms_complete_cmd(host);
  379. spin_unlock(&sock->lock);
  380. return;
  381. }
  382. static void tifm_ms_request(struct memstick_host *msh)
  383. {
  384. struct tifm_ms *host = memstick_priv(msh);
  385. struct tifm_dev *sock = host->dev;
  386. unsigned long flags;
  387. int rc;
  388. spin_lock_irqsave(&sock->lock, flags);
  389. if (host->req) {
  390. printk(KERN_ERR "%s : unfinished request detected\n",
  391. sock->dev.bus_id);
  392. spin_unlock_irqrestore(&sock->lock, flags);
  393. tifm_eject(host->dev);
  394. return;
  395. }
  396. if (host->eject) {
  397. do {
  398. rc = memstick_next_req(msh, &host->req);
  399. if (!rc)
  400. host->req->error = -ETIME;
  401. } while (!rc);
  402. spin_unlock_irqrestore(&sock->lock, flags);
  403. return;
  404. }
  405. do {
  406. rc = memstick_next_req(msh, &host->req);
  407. } while (!rc && tifm_ms_issue_cmd(host));
  408. spin_unlock_irqrestore(&sock->lock, flags);
  409. return;
  410. }
  411. static void tifm_ms_set_param(struct memstick_host *msh,
  412. enum memstick_param param,
  413. int value)
  414. {
  415. struct tifm_ms *host = memstick_priv(msh);
  416. struct tifm_dev *sock = host->dev;
  417. unsigned long flags;
  418. spin_lock_irqsave(&sock->lock, flags);
  419. switch (param) {
  420. case MEMSTICK_POWER:
  421. /* this is set by card detection mechanism */
  422. break;
  423. case MEMSTICK_INTERFACE:
  424. if (value == MEMSTICK_SERIAL) {
  425. host->mode_mask = TIFM_MS_SERIAL;
  426. writel((~TIFM_CTRL_FAST_CLK)
  427. & readl(sock->addr + SOCK_CONTROL),
  428. sock->addr + SOCK_CONTROL);
  429. } else if (value == MEMSTICK_PAR4) {
  430. host->mode_mask = 0;
  431. writel(TIFM_CTRL_FAST_CLK
  432. | readl(sock->addr + SOCK_CONTROL),
  433. sock->addr + SOCK_CONTROL);
  434. }
  435. break;
  436. };
  437. spin_unlock_irqrestore(&sock->lock, flags);
  438. }
  439. static void tifm_ms_abort(unsigned long data)
  440. {
  441. struct tifm_ms *host = (struct tifm_ms *)data;
  442. dev_dbg(&host->dev->dev, "status %x\n",
  443. readl(host->dev->addr + SOCK_MS_STATUS));
  444. printk(KERN_ERR
  445. "%s : card failed to respond for a long period of time "
  446. "(%x, %x)\n",
  447. host->dev->dev.bus_id, host->req ? host->req->tpc : 0,
  448. host->cmd_flags);
  449. tifm_eject(host->dev);
  450. }
  451. static int tifm_ms_initialize_host(struct tifm_ms *host)
  452. {
  453. struct tifm_dev *sock = host->dev;
  454. struct memstick_host *msh = tifm_get_drvdata(sock);
  455. host->mode_mask = TIFM_MS_SERIAL;
  456. writel(0x8000, sock->addr + SOCK_MS_SYSTEM);
  457. writel(0x0200 | TIFM_MS_SYS_NOT_RDY, sock->addr + SOCK_MS_SYSTEM);
  458. writel(0xffffffff, sock->addr + SOCK_MS_STATUS);
  459. if (tifm_has_ms_pif(sock))
  460. msh->caps |= MEMSTICK_CAP_PAR4;
  461. return 0;
  462. }
  463. static int tifm_ms_probe(struct tifm_dev *sock)
  464. {
  465. struct memstick_host *msh;
  466. struct tifm_ms *host;
  467. int rc = -EIO;
  468. if (!(TIFM_SOCK_STATE_OCCUPIED
  469. & readl(sock->addr + SOCK_PRESENT_STATE))) {
  470. printk(KERN_WARNING "%s : card gone, unexpectedly\n",
  471. sock->dev.bus_id);
  472. return rc;
  473. }
  474. msh = memstick_alloc_host(sizeof(struct tifm_ms), &sock->dev);
  475. if (!msh)
  476. return -ENOMEM;
  477. host = memstick_priv(msh);
  478. tifm_set_drvdata(sock, msh);
  479. host->dev = sock;
  480. host->timeout_jiffies = msecs_to_jiffies(1000);
  481. host->no_dma = no_dma;
  482. setup_timer(&host->timer, tifm_ms_abort, (unsigned long)host);
  483. msh->request = tifm_ms_request;
  484. msh->set_param = tifm_ms_set_param;
  485. sock->card_event = tifm_ms_card_event;
  486. sock->data_event = tifm_ms_data_event;
  487. rc = tifm_ms_initialize_host(host);
  488. if (!rc)
  489. rc = memstick_add_host(msh);
  490. if (!rc)
  491. return 0;
  492. memstick_free_host(msh);
  493. return rc;
  494. }
  495. static void tifm_ms_remove(struct tifm_dev *sock)
  496. {
  497. struct memstick_host *msh = tifm_get_drvdata(sock);
  498. struct tifm_ms *host = memstick_priv(msh);
  499. int rc = 0;
  500. unsigned long flags;
  501. spin_lock_irqsave(&sock->lock, flags);
  502. host->eject = 1;
  503. if (host->req) {
  504. del_timer(&host->timer);
  505. writel(TIFM_FIFO_INT_SETALL,
  506. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  507. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  508. if (host->req->long_data && !host->no_dma)
  509. tifm_unmap_sg(sock, &host->req->sg, 1,
  510. host->req->data_dir == READ
  511. ? PCI_DMA_TODEVICE
  512. : PCI_DMA_FROMDEVICE);
  513. host->req->error = -ETIME;
  514. do {
  515. rc = memstick_next_req(msh, &host->req);
  516. if (!rc)
  517. host->req->error = -ETIME;
  518. } while (!rc);
  519. }
  520. spin_unlock_irqrestore(&sock->lock, flags);
  521. memstick_remove_host(msh);
  522. writel(0x0200 | TIFM_MS_SYS_NOT_RDY, sock->addr + SOCK_MS_SYSTEM);
  523. writel(0xffffffff, sock->addr + SOCK_MS_STATUS);
  524. memstick_free_host(msh);
  525. }
  526. #ifdef CONFIG_PM
  527. static int tifm_ms_suspend(struct tifm_dev *sock, pm_message_t state)
  528. {
  529. struct memstick_host *msh = tifm_get_drvdata(sock);
  530. memstick_suspend_host(msh);
  531. return 0;
  532. }
  533. static int tifm_ms_resume(struct tifm_dev *sock)
  534. {
  535. struct memstick_host *msh = tifm_get_drvdata(sock);
  536. memstick_resume_host(msh);
  537. return 0;
  538. }
  539. #else
  540. #define tifm_ms_suspend NULL
  541. #define tifm_ms_resume NULL
  542. #endif /* CONFIG_PM */
  543. static struct tifm_device_id tifm_ms_id_tbl[] = {
  544. { TIFM_TYPE_MS }, { 0 }
  545. };
  546. static struct tifm_driver tifm_ms_driver = {
  547. .driver = {
  548. .name = DRIVER_NAME,
  549. .owner = THIS_MODULE
  550. },
  551. .id_table = tifm_ms_id_tbl,
  552. .probe = tifm_ms_probe,
  553. .remove = tifm_ms_remove,
  554. .suspend = tifm_ms_suspend,
  555. .resume = tifm_ms_resume
  556. };
  557. static int __init tifm_ms_init(void)
  558. {
  559. return tifm_register_driver(&tifm_ms_driver);
  560. }
  561. static void __exit tifm_ms_exit(void)
  562. {
  563. tifm_unregister_driver(&tifm_ms_driver);
  564. }
  565. MODULE_AUTHOR("Alex Dubov");
  566. MODULE_DESCRIPTION("TI FlashMedia MemoryStick driver");
  567. MODULE_LICENSE("GPL");
  568. MODULE_DEVICE_TABLE(tifm, tifm_ms_id_tbl);
  569. MODULE_VERSION(DRIVER_VERSION);
  570. module_init(tifm_ms_init);
  571. module_exit(tifm_ms_exit);