mthca_av.c 6.1 KB

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  1. /*
  2. * Copyright (c) 2004 Topspin Communications. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. * $Id: mthca_av.c 1349 2004-12-16 21:09:43Z roland $
  33. */
  34. #include <linux/init.h>
  35. #include <ib_verbs.h>
  36. #include <ib_cache.h>
  37. #include "mthca_dev.h"
  38. struct mthca_av {
  39. u32 port_pd;
  40. u8 reserved1;
  41. u8 g_slid;
  42. u16 dlid;
  43. u8 reserved2;
  44. u8 gid_index;
  45. u8 msg_sr;
  46. u8 hop_limit;
  47. u32 sl_tclass_flowlabel;
  48. u32 dgid[4];
  49. };
  50. int mthca_create_ah(struct mthca_dev *dev,
  51. struct mthca_pd *pd,
  52. struct ib_ah_attr *ah_attr,
  53. struct mthca_ah *ah)
  54. {
  55. u32 index = -1;
  56. struct mthca_av *av = NULL;
  57. ah->type = MTHCA_AH_PCI_POOL;
  58. if (mthca_is_memfree(dev)) {
  59. ah->av = kmalloc(sizeof *ah->av, GFP_ATOMIC);
  60. if (!ah->av)
  61. return -ENOMEM;
  62. ah->type = MTHCA_AH_KMALLOC;
  63. av = ah->av;
  64. } else if (!atomic_read(&pd->sqp_count) &&
  65. !(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
  66. index = mthca_alloc(&dev->av_table.alloc);
  67. /* fall back to allocate in host memory */
  68. if (index == -1)
  69. goto on_hca_fail;
  70. av = kmalloc(sizeof *av, GFP_ATOMIC);
  71. if (!av)
  72. goto on_hca_fail;
  73. ah->type = MTHCA_AH_ON_HCA;
  74. ah->avdma = dev->av_table.ddr_av_base +
  75. index * MTHCA_AV_SIZE;
  76. }
  77. on_hca_fail:
  78. if (ah->type == MTHCA_AH_PCI_POOL) {
  79. ah->av = pci_pool_alloc(dev->av_table.pool,
  80. SLAB_ATOMIC, &ah->avdma);
  81. if (!ah->av)
  82. return -ENOMEM;
  83. av = ah->av;
  84. }
  85. ah->key = pd->ntmr.ibmr.lkey;
  86. memset(av, 0, MTHCA_AV_SIZE);
  87. av->port_pd = cpu_to_be32(pd->pd_num | (ah_attr->port_num << 24));
  88. av->g_slid = ah_attr->src_path_bits;
  89. av->dlid = cpu_to_be16(ah_attr->dlid);
  90. av->msg_sr = (3 << 4) | /* 2K message */
  91. ah_attr->static_rate;
  92. av->sl_tclass_flowlabel = cpu_to_be32(ah_attr->sl << 28);
  93. if (ah_attr->ah_flags & IB_AH_GRH) {
  94. av->g_slid |= 0x80;
  95. av->gid_index = (ah_attr->port_num - 1) * dev->limits.gid_table_len +
  96. ah_attr->grh.sgid_index;
  97. av->hop_limit = ah_attr->grh.hop_limit;
  98. av->sl_tclass_flowlabel |=
  99. cpu_to_be32((ah_attr->grh.traffic_class << 20) |
  100. ah_attr->grh.flow_label);
  101. memcpy(av->dgid, ah_attr->grh.dgid.raw, 16);
  102. } else {
  103. /* Arbel workaround -- low byte of GID must be 2 */
  104. av->dgid[3] = cpu_to_be32(2);
  105. }
  106. if (0) {
  107. int j;
  108. mthca_dbg(dev, "Created UDAV at %p/%08lx:\n",
  109. av, (unsigned long) ah->avdma);
  110. for (j = 0; j < 8; ++j)
  111. printk(KERN_DEBUG " [%2x] %08x\n",
  112. j * 4, be32_to_cpu(((u32 *) av)[j]));
  113. }
  114. if (ah->type == MTHCA_AH_ON_HCA) {
  115. memcpy_toio(dev->av_table.av_map + index * MTHCA_AV_SIZE,
  116. av, MTHCA_AV_SIZE);
  117. kfree(av);
  118. }
  119. return 0;
  120. }
  121. int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah)
  122. {
  123. switch (ah->type) {
  124. case MTHCA_AH_ON_HCA:
  125. mthca_free(&dev->av_table.alloc,
  126. (ah->avdma - dev->av_table.ddr_av_base) /
  127. MTHCA_AV_SIZE);
  128. break;
  129. case MTHCA_AH_PCI_POOL:
  130. pci_pool_free(dev->av_table.pool, ah->av, ah->avdma);
  131. break;
  132. case MTHCA_AH_KMALLOC:
  133. kfree(ah->av);
  134. break;
  135. }
  136. return 0;
  137. }
  138. int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
  139. struct ib_ud_header *header)
  140. {
  141. if (ah->type == MTHCA_AH_ON_HCA)
  142. return -EINVAL;
  143. header->lrh.service_level = be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 28;
  144. header->lrh.destination_lid = ah->av->dlid;
  145. header->lrh.source_lid = ah->av->g_slid & 0x7f;
  146. if (ah->av->g_slid & 0x80) {
  147. header->grh_present = 1;
  148. header->grh.traffic_class =
  149. (be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 20) & 0xff;
  150. header->grh.flow_label =
  151. ah->av->sl_tclass_flowlabel & cpu_to_be32(0xfffff);
  152. ib_get_cached_gid(&dev->ib_dev,
  153. be32_to_cpu(ah->av->port_pd) >> 24,
  154. ah->av->gid_index,
  155. &header->grh.source_gid);
  156. memcpy(header->grh.destination_gid.raw,
  157. ah->av->dgid, 16);
  158. } else {
  159. header->grh_present = 0;
  160. }
  161. return 0;
  162. }
  163. int __devinit mthca_init_av_table(struct mthca_dev *dev)
  164. {
  165. int err;
  166. if (mthca_is_memfree(dev))
  167. return 0;
  168. err = mthca_alloc_init(&dev->av_table.alloc,
  169. dev->av_table.num_ddr_avs,
  170. dev->av_table.num_ddr_avs - 1,
  171. 0);
  172. if (err)
  173. return err;
  174. dev->av_table.pool = pci_pool_create("mthca_av", dev->pdev,
  175. MTHCA_AV_SIZE,
  176. MTHCA_AV_SIZE, 0);
  177. if (!dev->av_table.pool)
  178. goto out_free_alloc;
  179. if (!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
  180. dev->av_table.av_map = ioremap(pci_resource_start(dev->pdev, 4) +
  181. dev->av_table.ddr_av_base -
  182. dev->ddr_start,
  183. dev->av_table.num_ddr_avs *
  184. MTHCA_AV_SIZE);
  185. if (!dev->av_table.av_map)
  186. goto out_free_pool;
  187. } else
  188. dev->av_table.av_map = NULL;
  189. return 0;
  190. out_free_pool:
  191. pci_pool_destroy(dev->av_table.pool);
  192. out_free_alloc:
  193. mthca_alloc_cleanup(&dev->av_table.alloc);
  194. return -ENOMEM;
  195. }
  196. void __devexit mthca_cleanup_av_table(struct mthca_dev *dev)
  197. {
  198. if (mthca_is_memfree(dev))
  199. return;
  200. if (dev->av_table.av_map)
  201. iounmap(dev->av_table.av_map);
  202. pci_pool_destroy(dev->av_table.pool);
  203. mthca_alloc_cleanup(&dev->av_table.alloc);
  204. }