atiixp.c 45 KB

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  1. /*
  2. * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
  3. *
  4. * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #include <sound/driver.h>
  22. #include <asm/io.h>
  23. #include <linux/delay.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/init.h>
  26. #include <linux/pci.h>
  27. #include <linux/slab.h>
  28. #include <linux/moduleparam.h>
  29. #include <linux/mutex.h>
  30. #include <sound/core.h>
  31. #include <sound/pcm.h>
  32. #include <sound/pcm_params.h>
  33. #include <sound/info.h>
  34. #include <sound/ac97_codec.h>
  35. #include <sound/initval.h>
  36. MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  37. MODULE_DESCRIPTION("ATI IXP AC97 controller");
  38. MODULE_LICENSE("GPL");
  39. MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250/300/400}}");
  40. static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
  41. static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
  42. static int ac97_clock = 48000;
  43. static char *ac97_quirk;
  44. static int spdif_aclink = 1;
  45. module_param(index, int, 0444);
  46. MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
  47. module_param(id, charp, 0444);
  48. MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
  49. module_param(ac97_clock, int, 0444);
  50. MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
  51. module_param(ac97_quirk, charp, 0444);
  52. MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  53. module_param(spdif_aclink, bool, 0444);
  54. MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  55. /* just for backward compatibility */
  56. static int enable;
  57. module_param(enable, bool, 0444);
  58. /*
  59. */
  60. #define ATI_REG_ISR 0x00 /* interrupt source */
  61. #define ATI_REG_ISR_IN_XRUN (1U<<0)
  62. #define ATI_REG_ISR_IN_STATUS (1U<<1)
  63. #define ATI_REG_ISR_OUT_XRUN (1U<<2)
  64. #define ATI_REG_ISR_OUT_STATUS (1U<<3)
  65. #define ATI_REG_ISR_SPDF_XRUN (1U<<4)
  66. #define ATI_REG_ISR_SPDF_STATUS (1U<<5)
  67. #define ATI_REG_ISR_PHYS_INTR (1U<<8)
  68. #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
  69. #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
  70. #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
  71. #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
  72. #define ATI_REG_ISR_NEW_FRAME (1U<<13)
  73. #define ATI_REG_IER 0x04 /* interrupt enable */
  74. #define ATI_REG_IER_IN_XRUN_EN (1U<<0)
  75. #define ATI_REG_IER_IO_STATUS_EN (1U<<1)
  76. #define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
  77. #define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
  78. #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
  79. #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
  80. #define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
  81. #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
  82. #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
  83. #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
  84. #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
  85. #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
  86. #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
  87. #define ATI_REG_CMD 0x08 /* command */
  88. #define ATI_REG_CMD_POWERDOWN (1U<<0)
  89. #define ATI_REG_CMD_RECEIVE_EN (1U<<1)
  90. #define ATI_REG_CMD_SEND_EN (1U<<2)
  91. #define ATI_REG_CMD_STATUS_MEM (1U<<3)
  92. #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
  93. #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
  94. #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
  95. #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
  96. #define ATI_REG_CMD_IN_DMA_EN (1U<<8)
  97. #define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
  98. #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
  99. #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
  100. #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
  101. #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
  102. #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
  103. #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
  104. #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
  105. #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
  106. #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
  107. #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
  108. #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
  109. #define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
  110. #define ATI_REG_CMD_PACKED_DIS (1U<<24)
  111. #define ATI_REG_CMD_BURST_EN (1U<<25)
  112. #define ATI_REG_CMD_PANIC_EN (1U<<26)
  113. #define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
  114. #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
  115. #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
  116. #define ATI_REG_CMD_AC_SYNC (1U<<30)
  117. #define ATI_REG_CMD_AC_RESET (1U<<31)
  118. #define ATI_REG_PHYS_OUT_ADDR 0x0c
  119. #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
  120. #define ATI_REG_PHYS_OUT_RW (1U<<2)
  121. #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
  122. #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
  123. #define ATI_REG_PHYS_OUT_DATA_SHIFT 16
  124. #define ATI_REG_PHYS_IN_ADDR 0x10
  125. #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
  126. #define ATI_REG_PHYS_IN_ADDR_SHIFT 9
  127. #define ATI_REG_PHYS_IN_DATA_SHIFT 16
  128. #define ATI_REG_SLOTREQ 0x14
  129. #define ATI_REG_COUNTER 0x18
  130. #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
  131. #define ATI_REG_COUNTER_BITCLOCK (31U<<8)
  132. #define ATI_REG_IN_FIFO_THRESHOLD 0x1c
  133. #define ATI_REG_IN_DMA_LINKPTR 0x20
  134. #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
  135. #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
  136. #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
  137. #define ATI_REG_IN_DMA_DT_SIZE 0x30
  138. #define ATI_REG_OUT_DMA_SLOT 0x34
  139. #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
  140. #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
  141. #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
  142. #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
  143. #define ATI_REG_OUT_DMA_LINKPTR 0x38
  144. #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
  145. #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
  146. #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
  147. #define ATI_REG_OUT_DMA_DT_SIZE 0x48
  148. #define ATI_REG_SPDF_CMD 0x4c
  149. #define ATI_REG_SPDF_CMD_LFSR (1U<<4)
  150. #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
  151. #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
  152. #define ATI_REG_SPDF_DMA_LINKPTR 0x50
  153. #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
  154. #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
  155. #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
  156. #define ATI_REG_SPDF_DMA_DT_SIZE 0x60
  157. #define ATI_REG_MODEM_MIRROR 0x7c
  158. #define ATI_REG_AUDIO_MIRROR 0x80
  159. #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
  160. #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
  161. #define ATI_REG_FIFO_FLUSH 0x88
  162. #define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
  163. #define ATI_REG_FIFO_IN_FLUSH (1U<<1)
  164. /* LINKPTR */
  165. #define ATI_REG_LINKPTR_EN (1U<<0)
  166. /* [INT|OUT|SPDIF]_DMA_DT_SIZE */
  167. #define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
  168. #define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
  169. #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
  170. #define ATI_REG_DMA_STATE (7U<<26)
  171. #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
  172. struct atiixp;
  173. /*
  174. * DMA packate descriptor
  175. */
  176. struct atiixp_dma_desc {
  177. u32 addr; /* DMA buffer address */
  178. u16 status; /* status bits */
  179. u16 size; /* size of the packet in dwords */
  180. u32 next; /* address of the next packet descriptor */
  181. };
  182. /*
  183. * stream enum
  184. */
  185. enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
  186. enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
  187. enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
  188. #define NUM_ATI_CODECS 3
  189. /*
  190. * constants and callbacks for each DMA type
  191. */
  192. struct atiixp_dma_ops {
  193. int type; /* ATI_DMA_XXX */
  194. unsigned int llp_offset; /* LINKPTR offset */
  195. unsigned int dt_cur; /* DT_CUR offset */
  196. /* called from open callback */
  197. void (*enable_dma)(struct atiixp *chip, int on);
  198. /* called from trigger (START/STOP) */
  199. void (*enable_transfer)(struct atiixp *chip, int on);
  200. /* called from trigger (STOP only) */
  201. void (*flush_dma)(struct atiixp *chip);
  202. };
  203. /*
  204. * DMA stream
  205. */
  206. struct atiixp_dma {
  207. const struct atiixp_dma_ops *ops;
  208. struct snd_dma_buffer desc_buf;
  209. struct snd_pcm_substream *substream; /* assigned PCM substream */
  210. unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
  211. unsigned int period_bytes, periods;
  212. int opened;
  213. int running;
  214. int suspended;
  215. int pcm_open_flag;
  216. int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
  217. unsigned int saved_curptr;
  218. };
  219. /*
  220. * ATI IXP chip
  221. */
  222. struct atiixp {
  223. struct snd_card *card;
  224. struct pci_dev *pci;
  225. unsigned long addr;
  226. void __iomem *remap_addr;
  227. int irq;
  228. struct snd_ac97_bus *ac97_bus;
  229. struct snd_ac97 *ac97[NUM_ATI_CODECS];
  230. spinlock_t reg_lock;
  231. struct atiixp_dma dmas[NUM_ATI_DMAS];
  232. struct ac97_pcm *pcms[NUM_ATI_PCMS];
  233. struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
  234. int max_channels; /* max. channels for PCM out */
  235. unsigned int codec_not_ready_bits; /* for codec detection */
  236. int spdif_over_aclink; /* passed from the module option */
  237. struct mutex open_mutex; /* playback open mutex */
  238. };
  239. /*
  240. */
  241. static struct pci_device_id snd_atiixp_ids[] = {
  242. { 0x1002, 0x4341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB200 */
  243. { 0x1002, 0x4361, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB300 */
  244. { 0x1002, 0x4370, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB400 */
  245. { 0, }
  246. };
  247. MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
  248. /*
  249. * lowlevel functions
  250. */
  251. /*
  252. * update the bits of the given register.
  253. * return 1 if the bits changed.
  254. */
  255. static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg,
  256. unsigned int mask, unsigned int value)
  257. {
  258. void __iomem *addr = chip->remap_addr + reg;
  259. unsigned int data, old_data;
  260. old_data = data = readl(addr);
  261. data &= ~mask;
  262. data |= value;
  263. if (old_data == data)
  264. return 0;
  265. writel(data, addr);
  266. return 1;
  267. }
  268. /*
  269. * macros for easy use
  270. */
  271. #define atiixp_write(chip,reg,value) \
  272. writel(value, chip->remap_addr + ATI_REG_##reg)
  273. #define atiixp_read(chip,reg) \
  274. readl(chip->remap_addr + ATI_REG_##reg)
  275. #define atiixp_update(chip,reg,mask,val) \
  276. snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
  277. /*
  278. * handling DMA packets
  279. *
  280. * we allocate a linear buffer for the DMA, and split it to each packet.
  281. * in a future version, a scatter-gather buffer should be implemented.
  282. */
  283. #define ATI_DESC_LIST_SIZE \
  284. PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
  285. /*
  286. * build packets ring for the given buffer size.
  287. *
  288. * IXP handles the buffer descriptors, which are connected as a linked
  289. * list. although we can change the list dynamically, in this version,
  290. * a static RING of buffer descriptors is used.
  291. *
  292. * the ring is built in this function, and is set up to the hardware.
  293. */
  294. static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
  295. struct snd_pcm_substream *substream,
  296. unsigned int periods,
  297. unsigned int period_bytes)
  298. {
  299. unsigned int i;
  300. u32 addr, desc_addr;
  301. unsigned long flags;
  302. if (periods > ATI_MAX_DESCRIPTORS)
  303. return -ENOMEM;
  304. if (dma->desc_buf.area == NULL) {
  305. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
  306. snd_dma_pci_data(chip->pci),
  307. ATI_DESC_LIST_SIZE,
  308. &dma->desc_buf) < 0)
  309. return -ENOMEM;
  310. dma->period_bytes = dma->periods = 0; /* clear */
  311. }
  312. if (dma->periods == periods && dma->period_bytes == period_bytes)
  313. return 0;
  314. /* reset DMA before changing the descriptor table */
  315. spin_lock_irqsave(&chip->reg_lock, flags);
  316. writel(0, chip->remap_addr + dma->ops->llp_offset);
  317. dma->ops->enable_dma(chip, 0);
  318. dma->ops->enable_dma(chip, 1);
  319. spin_unlock_irqrestore(&chip->reg_lock, flags);
  320. /* fill the entries */
  321. addr = (u32)substream->runtime->dma_addr;
  322. desc_addr = (u32)dma->desc_buf.addr;
  323. for (i = 0; i < periods; i++) {
  324. struct atiixp_dma_desc *desc;
  325. desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
  326. desc->addr = cpu_to_le32(addr);
  327. desc->status = 0;
  328. desc->size = period_bytes >> 2; /* in dwords */
  329. desc_addr += sizeof(struct atiixp_dma_desc);
  330. if (i == periods - 1)
  331. desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
  332. else
  333. desc->next = cpu_to_le32(desc_addr);
  334. addr += period_bytes;
  335. }
  336. writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
  337. chip->remap_addr + dma->ops->llp_offset);
  338. dma->period_bytes = period_bytes;
  339. dma->periods = periods;
  340. return 0;
  341. }
  342. /*
  343. * remove the ring buffer and release it if assigned
  344. */
  345. static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
  346. struct snd_pcm_substream *substream)
  347. {
  348. if (dma->desc_buf.area) {
  349. writel(0, chip->remap_addr + dma->ops->llp_offset);
  350. snd_dma_free_pages(&dma->desc_buf);
  351. dma->desc_buf.area = NULL;
  352. }
  353. }
  354. /*
  355. * AC97 interface
  356. */
  357. static int snd_atiixp_acquire_codec(struct atiixp *chip)
  358. {
  359. int timeout = 1000;
  360. while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
  361. if (! timeout--) {
  362. snd_printk(KERN_WARNING "atiixp: codec acquire timeout\n");
  363. return -EBUSY;
  364. }
  365. udelay(1);
  366. }
  367. return 0;
  368. }
  369. static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg)
  370. {
  371. unsigned int data;
  372. int timeout;
  373. if (snd_atiixp_acquire_codec(chip) < 0)
  374. return 0xffff;
  375. data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
  376. ATI_REG_PHYS_OUT_ADDR_EN |
  377. ATI_REG_PHYS_OUT_RW |
  378. codec;
  379. atiixp_write(chip, PHYS_OUT_ADDR, data);
  380. if (snd_atiixp_acquire_codec(chip) < 0)
  381. return 0xffff;
  382. timeout = 1000;
  383. do {
  384. data = atiixp_read(chip, PHYS_IN_ADDR);
  385. if (data & ATI_REG_PHYS_IN_READ_FLAG)
  386. return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
  387. udelay(1);
  388. } while (--timeout);
  389. /* time out may happen during reset */
  390. if (reg < 0x7c)
  391. snd_printk(KERN_WARNING "atiixp: codec read timeout (reg %x)\n", reg);
  392. return 0xffff;
  393. }
  394. static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec,
  395. unsigned short reg, unsigned short val)
  396. {
  397. unsigned int data;
  398. if (snd_atiixp_acquire_codec(chip) < 0)
  399. return;
  400. data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
  401. ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
  402. ATI_REG_PHYS_OUT_ADDR_EN | codec;
  403. atiixp_write(chip, PHYS_OUT_ADDR, data);
  404. }
  405. static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
  406. unsigned short reg)
  407. {
  408. struct atiixp *chip = ac97->private_data;
  409. return snd_atiixp_codec_read(chip, ac97->num, reg);
  410. }
  411. static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  412. unsigned short val)
  413. {
  414. struct atiixp *chip = ac97->private_data;
  415. snd_atiixp_codec_write(chip, ac97->num, reg, val);
  416. }
  417. /*
  418. * reset AC link
  419. */
  420. static int snd_atiixp_aclink_reset(struct atiixp *chip)
  421. {
  422. int timeout;
  423. /* reset powerdoewn */
  424. if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
  425. udelay(10);
  426. /* perform a software reset */
  427. atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
  428. atiixp_read(chip, CMD);
  429. udelay(10);
  430. atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
  431. timeout = 10;
  432. while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
  433. /* do a hard reset */
  434. atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
  435. ATI_REG_CMD_AC_SYNC);
  436. atiixp_read(chip, CMD);
  437. mdelay(1);
  438. atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
  439. if (--timeout) {
  440. snd_printk(KERN_ERR "atiixp: codec reset timeout\n");
  441. break;
  442. }
  443. }
  444. /* deassert RESET and assert SYNC to make sure */
  445. atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
  446. ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
  447. return 0;
  448. }
  449. #ifdef CONFIG_PM
  450. static int snd_atiixp_aclink_down(struct atiixp *chip)
  451. {
  452. // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
  453. // return -EBUSY;
  454. atiixp_update(chip, CMD,
  455. ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
  456. ATI_REG_CMD_POWERDOWN);
  457. return 0;
  458. }
  459. #endif
  460. /*
  461. * auto-detection of codecs
  462. *
  463. * the IXP chip can generate interrupts for the non-existing codecs.
  464. * NEW_FRAME interrupt is used to make sure that the interrupt is generated
  465. * even if all three codecs are connected.
  466. */
  467. #define ALL_CODEC_NOT_READY \
  468. (ATI_REG_ISR_CODEC0_NOT_READY |\
  469. ATI_REG_ISR_CODEC1_NOT_READY |\
  470. ATI_REG_ISR_CODEC2_NOT_READY)
  471. #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
  472. static int snd_atiixp_codec_detect(struct atiixp *chip)
  473. {
  474. int timeout;
  475. chip->codec_not_ready_bits = 0;
  476. atiixp_write(chip, IER, CODEC_CHECK_BITS);
  477. /* wait for the interrupts */
  478. timeout = 50;
  479. while (timeout-- > 0) {
  480. mdelay(1);
  481. if (chip->codec_not_ready_bits)
  482. break;
  483. }
  484. atiixp_write(chip, IER, 0); /* disable irqs */
  485. if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
  486. snd_printk(KERN_ERR "atiixp: no codec detected!\n");
  487. return -ENXIO;
  488. }
  489. return 0;
  490. }
  491. /*
  492. * enable DMA and irqs
  493. */
  494. static int snd_atiixp_chip_start(struct atiixp *chip)
  495. {
  496. unsigned int reg;
  497. /* set up spdif, enable burst mode */
  498. reg = atiixp_read(chip, CMD);
  499. reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
  500. reg |= ATI_REG_CMD_BURST_EN;
  501. atiixp_write(chip, CMD, reg);
  502. reg = atiixp_read(chip, SPDF_CMD);
  503. reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH);
  504. atiixp_write(chip, SPDF_CMD, reg);
  505. /* clear all interrupt source */
  506. atiixp_write(chip, ISR, 0xffffffff);
  507. /* enable irqs */
  508. atiixp_write(chip, IER,
  509. ATI_REG_IER_IO_STATUS_EN |
  510. ATI_REG_IER_IN_XRUN_EN |
  511. ATI_REG_IER_OUT_XRUN_EN |
  512. ATI_REG_IER_SPDF_XRUN_EN |
  513. ATI_REG_IER_SPDF_STATUS_EN);
  514. return 0;
  515. }
  516. /*
  517. * disable DMA and IRQs
  518. */
  519. static int snd_atiixp_chip_stop(struct atiixp *chip)
  520. {
  521. /* clear interrupt source */
  522. atiixp_write(chip, ISR, atiixp_read(chip, ISR));
  523. /* disable irqs */
  524. atiixp_write(chip, IER, 0);
  525. return 0;
  526. }
  527. /*
  528. * PCM section
  529. */
  530. /*
  531. * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
  532. * position. when SG-buffer is implemented, the offset must be calculated
  533. * correctly...
  534. */
  535. static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
  536. {
  537. struct atiixp *chip = snd_pcm_substream_chip(substream);
  538. struct snd_pcm_runtime *runtime = substream->runtime;
  539. struct atiixp_dma *dma = runtime->private_data;
  540. unsigned int curptr;
  541. int timeout = 1000;
  542. while (timeout--) {
  543. curptr = readl(chip->remap_addr + dma->ops->dt_cur);
  544. if (curptr < dma->buf_addr)
  545. continue;
  546. curptr -= dma->buf_addr;
  547. if (curptr >= dma->buf_bytes)
  548. continue;
  549. return bytes_to_frames(runtime, curptr);
  550. }
  551. snd_printd("atiixp: invalid DMA pointer read 0x%x (buf=%x)\n",
  552. readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
  553. return 0;
  554. }
  555. /*
  556. * XRUN detected, and stop the PCM substream
  557. */
  558. static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma)
  559. {
  560. if (! dma->substream || ! dma->running)
  561. return;
  562. snd_printdd("atiixp: XRUN detected (DMA %d)\n", dma->ops->type);
  563. snd_pcm_stop(dma->substream, SNDRV_PCM_STATE_XRUN);
  564. }
  565. /*
  566. * the period ack. update the substream.
  567. */
  568. static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma)
  569. {
  570. if (! dma->substream || ! dma->running)
  571. return;
  572. snd_pcm_period_elapsed(dma->substream);
  573. }
  574. /* set BUS_BUSY interrupt bit if any DMA is running */
  575. /* call with spinlock held */
  576. static void snd_atiixp_check_bus_busy(struct atiixp *chip)
  577. {
  578. unsigned int bus_busy;
  579. if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN |
  580. ATI_REG_CMD_RECEIVE_EN |
  581. ATI_REG_CMD_SPDF_OUT_EN))
  582. bus_busy = ATI_REG_IER_SET_BUS_BUSY;
  583. else
  584. bus_busy = 0;
  585. atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
  586. }
  587. /* common trigger callback
  588. * calling the lowlevel callbacks in it
  589. */
  590. static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  591. {
  592. struct atiixp *chip = snd_pcm_substream_chip(substream);
  593. struct atiixp_dma *dma = substream->runtime->private_data;
  594. int err = 0;
  595. snd_assert(dma->ops->enable_transfer && dma->ops->flush_dma, return -EINVAL);
  596. spin_lock(&chip->reg_lock);
  597. switch (cmd) {
  598. case SNDRV_PCM_TRIGGER_START:
  599. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  600. case SNDRV_PCM_TRIGGER_RESUME:
  601. dma->ops->enable_transfer(chip, 1);
  602. dma->running = 1;
  603. dma->suspended = 0;
  604. break;
  605. case SNDRV_PCM_TRIGGER_STOP:
  606. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  607. case SNDRV_PCM_TRIGGER_SUSPEND:
  608. dma->ops->enable_transfer(chip, 0);
  609. dma->running = 0;
  610. dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND;
  611. break;
  612. default:
  613. err = -EINVAL;
  614. break;
  615. }
  616. if (! err) {
  617. snd_atiixp_check_bus_busy(chip);
  618. if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  619. dma->ops->flush_dma(chip);
  620. snd_atiixp_check_bus_busy(chip);
  621. }
  622. }
  623. spin_unlock(&chip->reg_lock);
  624. return err;
  625. }
  626. /*
  627. * lowlevel callbacks for each DMA type
  628. *
  629. * every callback is supposed to be called in chip->reg_lock spinlock
  630. */
  631. /* flush FIFO of analog OUT DMA */
  632. static void atiixp_out_flush_dma(struct atiixp *chip)
  633. {
  634. atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
  635. }
  636. /* enable/disable analog OUT DMA */
  637. static void atiixp_out_enable_dma(struct atiixp *chip, int on)
  638. {
  639. unsigned int data;
  640. data = atiixp_read(chip, CMD);
  641. if (on) {
  642. if (data & ATI_REG_CMD_OUT_DMA_EN)
  643. return;
  644. atiixp_out_flush_dma(chip);
  645. data |= ATI_REG_CMD_OUT_DMA_EN;
  646. } else
  647. data &= ~ATI_REG_CMD_OUT_DMA_EN;
  648. atiixp_write(chip, CMD, data);
  649. }
  650. /* start/stop transfer over OUT DMA */
  651. static void atiixp_out_enable_transfer(struct atiixp *chip, int on)
  652. {
  653. atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
  654. on ? ATI_REG_CMD_SEND_EN : 0);
  655. }
  656. /* enable/disable analog IN DMA */
  657. static void atiixp_in_enable_dma(struct atiixp *chip, int on)
  658. {
  659. atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
  660. on ? ATI_REG_CMD_IN_DMA_EN : 0);
  661. }
  662. /* start/stop analog IN DMA */
  663. static void atiixp_in_enable_transfer(struct atiixp *chip, int on)
  664. {
  665. if (on) {
  666. unsigned int data = atiixp_read(chip, CMD);
  667. if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
  668. data |= ATI_REG_CMD_RECEIVE_EN;
  669. #if 0 /* FIXME: this causes the endless loop */
  670. /* wait until slot 3/4 are finished */
  671. while ((atiixp_read(chip, COUNTER) &
  672. ATI_REG_COUNTER_SLOT) != 5)
  673. ;
  674. #endif
  675. atiixp_write(chip, CMD, data);
  676. }
  677. } else
  678. atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
  679. }
  680. /* flush FIFO of analog IN DMA */
  681. static void atiixp_in_flush_dma(struct atiixp *chip)
  682. {
  683. atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
  684. }
  685. /* enable/disable SPDIF OUT DMA */
  686. static void atiixp_spdif_enable_dma(struct atiixp *chip, int on)
  687. {
  688. atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
  689. on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
  690. }
  691. /* start/stop SPDIF OUT DMA */
  692. static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on)
  693. {
  694. unsigned int data;
  695. data = atiixp_read(chip, CMD);
  696. if (on)
  697. data |= ATI_REG_CMD_SPDF_OUT_EN;
  698. else
  699. data &= ~ATI_REG_CMD_SPDF_OUT_EN;
  700. atiixp_write(chip, CMD, data);
  701. }
  702. /* flush FIFO of SPDIF OUT DMA */
  703. static void atiixp_spdif_flush_dma(struct atiixp *chip)
  704. {
  705. int timeout;
  706. /* DMA off, transfer on */
  707. atiixp_spdif_enable_dma(chip, 0);
  708. atiixp_spdif_enable_transfer(chip, 1);
  709. timeout = 100;
  710. do {
  711. if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
  712. break;
  713. udelay(1);
  714. } while (timeout-- > 0);
  715. atiixp_spdif_enable_transfer(chip, 0);
  716. }
  717. /* set up slots and formats for SPDIF OUT */
  718. static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream)
  719. {
  720. struct atiixp *chip = snd_pcm_substream_chip(substream);
  721. spin_lock_irq(&chip->reg_lock);
  722. if (chip->spdif_over_aclink) {
  723. unsigned int data;
  724. /* enable slots 10/11 */
  725. atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
  726. ATI_REG_CMD_SPDF_CONFIG_01);
  727. data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
  728. data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
  729. ATI_REG_OUT_DMA_SLOT_BIT(11);
  730. data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
  731. atiixp_write(chip, OUT_DMA_SLOT, data);
  732. atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
  733. substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
  734. ATI_REG_CMD_INTERLEAVE_OUT : 0);
  735. } else {
  736. atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
  737. atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
  738. }
  739. spin_unlock_irq(&chip->reg_lock);
  740. return 0;
  741. }
  742. /* set up slots and formats for analog OUT */
  743. static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
  744. {
  745. struct atiixp *chip = snd_pcm_substream_chip(substream);
  746. unsigned int data;
  747. spin_lock_irq(&chip->reg_lock);
  748. data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
  749. switch (substream->runtime->channels) {
  750. case 8:
  751. data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
  752. ATI_REG_OUT_DMA_SLOT_BIT(11);
  753. /* fallthru */
  754. case 6:
  755. data |= ATI_REG_OUT_DMA_SLOT_BIT(7) |
  756. ATI_REG_OUT_DMA_SLOT_BIT(8);
  757. /* fallthru */
  758. case 4:
  759. data |= ATI_REG_OUT_DMA_SLOT_BIT(6) |
  760. ATI_REG_OUT_DMA_SLOT_BIT(9);
  761. /* fallthru */
  762. default:
  763. data |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
  764. ATI_REG_OUT_DMA_SLOT_BIT(4);
  765. break;
  766. }
  767. /* set output threshold */
  768. data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
  769. atiixp_write(chip, OUT_DMA_SLOT, data);
  770. atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
  771. substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
  772. ATI_REG_CMD_INTERLEAVE_OUT : 0);
  773. /*
  774. * enable 6 channel re-ordering bit if needed
  775. */
  776. atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
  777. substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
  778. spin_unlock_irq(&chip->reg_lock);
  779. return 0;
  780. }
  781. /* set up slots and formats for analog IN */
  782. static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
  783. {
  784. struct atiixp *chip = snd_pcm_substream_chip(substream);
  785. spin_lock_irq(&chip->reg_lock);
  786. atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
  787. substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
  788. ATI_REG_CMD_INTERLEAVE_IN : 0);
  789. spin_unlock_irq(&chip->reg_lock);
  790. return 0;
  791. }
  792. /*
  793. * hw_params - allocate the buffer and set up buffer descriptors
  794. */
  795. static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
  796. struct snd_pcm_hw_params *hw_params)
  797. {
  798. struct atiixp *chip = snd_pcm_substream_chip(substream);
  799. struct atiixp_dma *dma = substream->runtime->private_data;
  800. int err;
  801. err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  802. if (err < 0)
  803. return err;
  804. dma->buf_addr = substream->runtime->dma_addr;
  805. dma->buf_bytes = params_buffer_bytes(hw_params);
  806. err = atiixp_build_dma_packets(chip, dma, substream,
  807. params_periods(hw_params),
  808. params_period_bytes(hw_params));
  809. if (err < 0)
  810. return err;
  811. if (dma->ac97_pcm_type >= 0) {
  812. struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
  813. /* PCM is bound to AC97 codec(s)
  814. * set up the AC97 codecs
  815. */
  816. if (dma->pcm_open_flag) {
  817. snd_ac97_pcm_close(pcm);
  818. dma->pcm_open_flag = 0;
  819. }
  820. err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
  821. params_channels(hw_params),
  822. pcm->r[0].slots);
  823. if (err >= 0)
  824. dma->pcm_open_flag = 1;
  825. }
  826. return err;
  827. }
  828. static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
  829. {
  830. struct atiixp *chip = snd_pcm_substream_chip(substream);
  831. struct atiixp_dma *dma = substream->runtime->private_data;
  832. if (dma->pcm_open_flag) {
  833. struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
  834. snd_ac97_pcm_close(pcm);
  835. dma->pcm_open_flag = 0;
  836. }
  837. atiixp_clear_dma_packets(chip, dma, substream);
  838. snd_pcm_lib_free_pages(substream);
  839. return 0;
  840. }
  841. /*
  842. * pcm hardware definition, identical for all DMA types
  843. */
  844. static struct snd_pcm_hardware snd_atiixp_pcm_hw =
  845. {
  846. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  847. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  848. SNDRV_PCM_INFO_PAUSE |
  849. SNDRV_PCM_INFO_RESUME |
  850. SNDRV_PCM_INFO_MMAP_VALID),
  851. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
  852. .rates = SNDRV_PCM_RATE_48000,
  853. .rate_min = 48000,
  854. .rate_max = 48000,
  855. .channels_min = 2,
  856. .channels_max = 2,
  857. .buffer_bytes_max = 256 * 1024,
  858. .period_bytes_min = 32,
  859. .period_bytes_max = 128 * 1024,
  860. .periods_min = 2,
  861. .periods_max = ATI_MAX_DESCRIPTORS,
  862. };
  863. static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
  864. struct atiixp_dma *dma, int pcm_type)
  865. {
  866. struct atiixp *chip = snd_pcm_substream_chip(substream);
  867. struct snd_pcm_runtime *runtime = substream->runtime;
  868. int err;
  869. snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL);
  870. if (dma->opened)
  871. return -EBUSY;
  872. dma->substream = substream;
  873. runtime->hw = snd_atiixp_pcm_hw;
  874. dma->ac97_pcm_type = pcm_type;
  875. if (pcm_type >= 0) {
  876. runtime->hw.rates = chip->pcms[pcm_type]->rates;
  877. snd_pcm_limit_hw_rates(runtime);
  878. } else {
  879. /* direct SPDIF */
  880. runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
  881. }
  882. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  883. return err;
  884. runtime->private_data = dma;
  885. /* enable DMA bits */
  886. spin_lock_irq(&chip->reg_lock);
  887. dma->ops->enable_dma(chip, 1);
  888. spin_unlock_irq(&chip->reg_lock);
  889. dma->opened = 1;
  890. return 0;
  891. }
  892. static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
  893. struct atiixp_dma *dma)
  894. {
  895. struct atiixp *chip = snd_pcm_substream_chip(substream);
  896. /* disable DMA bits */
  897. snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL);
  898. spin_lock_irq(&chip->reg_lock);
  899. dma->ops->enable_dma(chip, 0);
  900. spin_unlock_irq(&chip->reg_lock);
  901. dma->substream = NULL;
  902. dma->opened = 0;
  903. return 0;
  904. }
  905. /*
  906. */
  907. static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
  908. {
  909. struct atiixp *chip = snd_pcm_substream_chip(substream);
  910. int err;
  911. mutex_lock(&chip->open_mutex);
  912. err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
  913. mutex_unlock(&chip->open_mutex);
  914. if (err < 0)
  915. return err;
  916. substream->runtime->hw.channels_max = chip->max_channels;
  917. if (chip->max_channels > 2)
  918. /* channels must be even */
  919. snd_pcm_hw_constraint_step(substream->runtime, 0,
  920. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  921. return 0;
  922. }
  923. static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
  924. {
  925. struct atiixp *chip = snd_pcm_substream_chip(substream);
  926. int err;
  927. mutex_lock(&chip->open_mutex);
  928. err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
  929. mutex_unlock(&chip->open_mutex);
  930. return err;
  931. }
  932. static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
  933. {
  934. struct atiixp *chip = snd_pcm_substream_chip(substream);
  935. return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
  936. }
  937. static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
  938. {
  939. struct atiixp *chip = snd_pcm_substream_chip(substream);
  940. return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
  941. }
  942. static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream)
  943. {
  944. struct atiixp *chip = snd_pcm_substream_chip(substream);
  945. int err;
  946. mutex_lock(&chip->open_mutex);
  947. if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
  948. err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
  949. else
  950. err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
  951. mutex_unlock(&chip->open_mutex);
  952. return err;
  953. }
  954. static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream)
  955. {
  956. struct atiixp *chip = snd_pcm_substream_chip(substream);
  957. int err;
  958. mutex_lock(&chip->open_mutex);
  959. if (chip->spdif_over_aclink)
  960. err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
  961. else
  962. err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
  963. mutex_unlock(&chip->open_mutex);
  964. return err;
  965. }
  966. /* AC97 playback */
  967. static struct snd_pcm_ops snd_atiixp_playback_ops = {
  968. .open = snd_atiixp_playback_open,
  969. .close = snd_atiixp_playback_close,
  970. .ioctl = snd_pcm_lib_ioctl,
  971. .hw_params = snd_atiixp_pcm_hw_params,
  972. .hw_free = snd_atiixp_pcm_hw_free,
  973. .prepare = snd_atiixp_playback_prepare,
  974. .trigger = snd_atiixp_pcm_trigger,
  975. .pointer = snd_atiixp_pcm_pointer,
  976. };
  977. /* AC97 capture */
  978. static struct snd_pcm_ops snd_atiixp_capture_ops = {
  979. .open = snd_atiixp_capture_open,
  980. .close = snd_atiixp_capture_close,
  981. .ioctl = snd_pcm_lib_ioctl,
  982. .hw_params = snd_atiixp_pcm_hw_params,
  983. .hw_free = snd_atiixp_pcm_hw_free,
  984. .prepare = snd_atiixp_capture_prepare,
  985. .trigger = snd_atiixp_pcm_trigger,
  986. .pointer = snd_atiixp_pcm_pointer,
  987. };
  988. /* SPDIF playback */
  989. static struct snd_pcm_ops snd_atiixp_spdif_ops = {
  990. .open = snd_atiixp_spdif_open,
  991. .close = snd_atiixp_spdif_close,
  992. .ioctl = snd_pcm_lib_ioctl,
  993. .hw_params = snd_atiixp_pcm_hw_params,
  994. .hw_free = snd_atiixp_pcm_hw_free,
  995. .prepare = snd_atiixp_spdif_prepare,
  996. .trigger = snd_atiixp_pcm_trigger,
  997. .pointer = snd_atiixp_pcm_pointer,
  998. };
  999. static struct ac97_pcm atiixp_pcm_defs[] __devinitdata = {
  1000. /* front PCM */
  1001. {
  1002. .exclusive = 1,
  1003. .r = { {
  1004. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1005. (1 << AC97_SLOT_PCM_RIGHT) |
  1006. (1 << AC97_SLOT_PCM_CENTER) |
  1007. (1 << AC97_SLOT_PCM_SLEFT) |
  1008. (1 << AC97_SLOT_PCM_SRIGHT) |
  1009. (1 << AC97_SLOT_LFE)
  1010. }
  1011. }
  1012. },
  1013. /* PCM IN #1 */
  1014. {
  1015. .stream = 1,
  1016. .exclusive = 1,
  1017. .r = { {
  1018. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1019. (1 << AC97_SLOT_PCM_RIGHT)
  1020. }
  1021. }
  1022. },
  1023. /* S/PDIF OUT (optional) */
  1024. {
  1025. .exclusive = 1,
  1026. .spdif = 1,
  1027. .r = { {
  1028. .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
  1029. (1 << AC97_SLOT_SPDIF_RIGHT2)
  1030. }
  1031. }
  1032. },
  1033. };
  1034. static struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
  1035. .type = ATI_DMA_PLAYBACK,
  1036. .llp_offset = ATI_REG_OUT_DMA_LINKPTR,
  1037. .dt_cur = ATI_REG_OUT_DMA_DT_CUR,
  1038. .enable_dma = atiixp_out_enable_dma,
  1039. .enable_transfer = atiixp_out_enable_transfer,
  1040. .flush_dma = atiixp_out_flush_dma,
  1041. };
  1042. static struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
  1043. .type = ATI_DMA_CAPTURE,
  1044. .llp_offset = ATI_REG_IN_DMA_LINKPTR,
  1045. .dt_cur = ATI_REG_IN_DMA_DT_CUR,
  1046. .enable_dma = atiixp_in_enable_dma,
  1047. .enable_transfer = atiixp_in_enable_transfer,
  1048. .flush_dma = atiixp_in_flush_dma,
  1049. };
  1050. static struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = {
  1051. .type = ATI_DMA_SPDIF,
  1052. .llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
  1053. .dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
  1054. .enable_dma = atiixp_spdif_enable_dma,
  1055. .enable_transfer = atiixp_spdif_enable_transfer,
  1056. .flush_dma = atiixp_spdif_flush_dma,
  1057. };
  1058. static int __devinit snd_atiixp_pcm_new(struct atiixp *chip)
  1059. {
  1060. struct snd_pcm *pcm;
  1061. struct snd_ac97_bus *pbus = chip->ac97_bus;
  1062. int err, i, num_pcms;
  1063. /* initialize constants */
  1064. chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
  1065. chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
  1066. if (! chip->spdif_over_aclink)
  1067. chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
  1068. /* assign AC97 pcm */
  1069. if (chip->spdif_over_aclink)
  1070. num_pcms = 3;
  1071. else
  1072. num_pcms = 2;
  1073. err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
  1074. if (err < 0)
  1075. return err;
  1076. for (i = 0; i < num_pcms; i++)
  1077. chip->pcms[i] = &pbus->pcms[i];
  1078. chip->max_channels = 2;
  1079. if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  1080. if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
  1081. chip->max_channels = 6;
  1082. else
  1083. chip->max_channels = 4;
  1084. }
  1085. /* PCM #0: analog I/O */
  1086. err = snd_pcm_new(chip->card, "ATI IXP AC97",
  1087. ATI_PCMDEV_ANALOG, 1, 1, &pcm);
  1088. if (err < 0)
  1089. return err;
  1090. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
  1091. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
  1092. pcm->private_data = chip;
  1093. strcpy(pcm->name, "ATI IXP AC97");
  1094. chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
  1095. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1096. snd_dma_pci_data(chip->pci),
  1097. 64*1024, 128*1024);
  1098. /* no SPDIF support on codec? */
  1099. if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
  1100. return 0;
  1101. /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
  1102. if (chip->pcms[ATI_PCM_SPDIF])
  1103. chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
  1104. /* PCM #1: spdif playback */
  1105. err = snd_pcm_new(chip->card, "ATI IXP IEC958",
  1106. ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
  1107. if (err < 0)
  1108. return err;
  1109. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
  1110. pcm->private_data = chip;
  1111. if (chip->spdif_over_aclink)
  1112. strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
  1113. else
  1114. strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
  1115. chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
  1116. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1117. snd_dma_pci_data(chip->pci),
  1118. 64*1024, 128*1024);
  1119. /* pre-select AC97 SPDIF slots 10/11 */
  1120. for (i = 0; i < NUM_ATI_CODECS; i++) {
  1121. if (chip->ac97[i])
  1122. snd_ac97_update_bits(chip->ac97[i],
  1123. AC97_EXTENDED_STATUS,
  1124. 0x03 << 4, 0x03 << 4);
  1125. }
  1126. return 0;
  1127. }
  1128. /*
  1129. * interrupt handler
  1130. */
  1131. static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  1132. {
  1133. struct atiixp *chip = dev_id;
  1134. unsigned int status;
  1135. status = atiixp_read(chip, ISR);
  1136. if (! status)
  1137. return IRQ_NONE;
  1138. /* process audio DMA */
  1139. if (status & ATI_REG_ISR_OUT_XRUN)
  1140. snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
  1141. else if (status & ATI_REG_ISR_OUT_STATUS)
  1142. snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
  1143. if (status & ATI_REG_ISR_IN_XRUN)
  1144. snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
  1145. else if (status & ATI_REG_ISR_IN_STATUS)
  1146. snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
  1147. if (! chip->spdif_over_aclink) {
  1148. if (status & ATI_REG_ISR_SPDF_XRUN)
  1149. snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
  1150. else if (status & ATI_REG_ISR_SPDF_STATUS)
  1151. snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
  1152. }
  1153. /* for codec detection */
  1154. if (status & CODEC_CHECK_BITS) {
  1155. unsigned int detected;
  1156. detected = status & CODEC_CHECK_BITS;
  1157. spin_lock(&chip->reg_lock);
  1158. chip->codec_not_ready_bits |= detected;
  1159. atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
  1160. spin_unlock(&chip->reg_lock);
  1161. }
  1162. /* ack */
  1163. atiixp_write(chip, ISR, status);
  1164. return IRQ_HANDLED;
  1165. }
  1166. /*
  1167. * ac97 mixer section
  1168. */
  1169. static struct ac97_quirk ac97_quirks[] __devinitdata = {
  1170. {
  1171. .subvendor = 0x103c,
  1172. .subdevice = 0x006b,
  1173. .name = "HP Pavilion ZV5030US",
  1174. .type = AC97_TUNE_MUTE_LED
  1175. },
  1176. {
  1177. .subvendor = 0x103c,
  1178. .subdevice = 0x308b,
  1179. .name = "HP nx6125",
  1180. .type = AC97_TUNE_MUTE_LED
  1181. },
  1182. { } /* terminator */
  1183. };
  1184. static int __devinit snd_atiixp_mixer_new(struct atiixp *chip, int clock,
  1185. const char *quirk_override)
  1186. {
  1187. struct snd_ac97_bus *pbus;
  1188. struct snd_ac97_template ac97;
  1189. int i, err;
  1190. int codec_count;
  1191. static struct snd_ac97_bus_ops ops = {
  1192. .write = snd_atiixp_ac97_write,
  1193. .read = snd_atiixp_ac97_read,
  1194. };
  1195. static unsigned int codec_skip[NUM_ATI_CODECS] = {
  1196. ATI_REG_ISR_CODEC0_NOT_READY,
  1197. ATI_REG_ISR_CODEC1_NOT_READY,
  1198. ATI_REG_ISR_CODEC2_NOT_READY,
  1199. };
  1200. if (snd_atiixp_codec_detect(chip) < 0)
  1201. return -ENXIO;
  1202. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
  1203. return err;
  1204. pbus->clock = clock;
  1205. chip->ac97_bus = pbus;
  1206. codec_count = 0;
  1207. for (i = 0; i < NUM_ATI_CODECS; i++) {
  1208. if (chip->codec_not_ready_bits & codec_skip[i])
  1209. continue;
  1210. memset(&ac97, 0, sizeof(ac97));
  1211. ac97.private_data = chip;
  1212. ac97.pci = chip->pci;
  1213. ac97.num = i;
  1214. ac97.scaps = AC97_SCAP_SKIP_MODEM;
  1215. if (! chip->spdif_over_aclink)
  1216. ac97.scaps |= AC97_SCAP_NO_SPDIF;
  1217. if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
  1218. chip->ac97[i] = NULL; /* to be sure */
  1219. snd_printdd("atiixp: codec %d not available for audio\n", i);
  1220. continue;
  1221. }
  1222. codec_count++;
  1223. }
  1224. if (! codec_count) {
  1225. snd_printk(KERN_ERR "atiixp: no codec available\n");
  1226. return -ENODEV;
  1227. }
  1228. snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
  1229. return 0;
  1230. }
  1231. #ifdef CONFIG_PM
  1232. /*
  1233. * power management
  1234. */
  1235. static int snd_atiixp_suspend(struct pci_dev *pci, pm_message_t state)
  1236. {
  1237. struct snd_card *card = pci_get_drvdata(pci);
  1238. struct atiixp *chip = card->private_data;
  1239. int i;
  1240. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1241. for (i = 0; i < NUM_ATI_PCMDEVS; i++)
  1242. if (chip->pcmdevs[i]) {
  1243. struct atiixp_dma *dma = &chip->dmas[i];
  1244. if (dma->substream && dma->running)
  1245. dma->saved_curptr = readl(chip->remap_addr +
  1246. dma->ops->dt_cur);
  1247. snd_pcm_suspend_all(chip->pcmdevs[i]);
  1248. }
  1249. for (i = 0; i < NUM_ATI_CODECS; i++)
  1250. snd_ac97_suspend(chip->ac97[i]);
  1251. snd_atiixp_aclink_down(chip);
  1252. snd_atiixp_chip_stop(chip);
  1253. pci_set_power_state(pci, PCI_D3hot);
  1254. pci_disable_device(pci);
  1255. pci_save_state(pci);
  1256. return 0;
  1257. }
  1258. static int snd_atiixp_resume(struct pci_dev *pci)
  1259. {
  1260. struct snd_card *card = pci_get_drvdata(pci);
  1261. struct atiixp *chip = card->private_data;
  1262. int i;
  1263. pci_restore_state(pci);
  1264. pci_enable_device(pci);
  1265. pci_set_power_state(pci, PCI_D0);
  1266. pci_set_master(pci);
  1267. snd_atiixp_aclink_reset(chip);
  1268. snd_atiixp_chip_start(chip);
  1269. for (i = 0; i < NUM_ATI_CODECS; i++)
  1270. snd_ac97_resume(chip->ac97[i]);
  1271. for (i = 0; i < NUM_ATI_PCMDEVS; i++)
  1272. if (chip->pcmdevs[i]) {
  1273. struct atiixp_dma *dma = &chip->dmas[i];
  1274. if (dma->substream && dma->suspended) {
  1275. dma->ops->enable_dma(chip, 1);
  1276. dma->substream->ops->prepare(dma->substream);
  1277. writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
  1278. chip->remap_addr + dma->ops->llp_offset);
  1279. writel(dma->saved_curptr, chip->remap_addr +
  1280. dma->ops->dt_cur);
  1281. }
  1282. }
  1283. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1284. return 0;
  1285. }
  1286. #endif /* CONFIG_PM */
  1287. #ifdef CONFIG_PROC_FS
  1288. /*
  1289. * proc interface for register dump
  1290. */
  1291. static void snd_atiixp_proc_read(struct snd_info_entry *entry,
  1292. struct snd_info_buffer *buffer)
  1293. {
  1294. struct atiixp *chip = entry->private_data;
  1295. int i;
  1296. for (i = 0; i < 256; i += 4)
  1297. snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
  1298. }
  1299. static void __devinit snd_atiixp_proc_init(struct atiixp *chip)
  1300. {
  1301. struct snd_info_entry *entry;
  1302. if (! snd_card_proc_new(chip->card, "atiixp", &entry))
  1303. snd_info_set_text_ops(entry, chip, snd_atiixp_proc_read);
  1304. }
  1305. #else /* !CONFIG_PROC_FS */
  1306. #define snd_atiixp_proc_init(chip)
  1307. #endif
  1308. /*
  1309. * destructor
  1310. */
  1311. static int snd_atiixp_free(struct atiixp *chip)
  1312. {
  1313. if (chip->irq < 0)
  1314. goto __hw_end;
  1315. snd_atiixp_chip_stop(chip);
  1316. synchronize_irq(chip->irq);
  1317. __hw_end:
  1318. if (chip->irq >= 0)
  1319. free_irq(chip->irq, chip);
  1320. if (chip->remap_addr)
  1321. iounmap(chip->remap_addr);
  1322. pci_release_regions(chip->pci);
  1323. pci_disable_device(chip->pci);
  1324. kfree(chip);
  1325. return 0;
  1326. }
  1327. static int snd_atiixp_dev_free(struct snd_device *device)
  1328. {
  1329. struct atiixp *chip = device->device_data;
  1330. return snd_atiixp_free(chip);
  1331. }
  1332. /*
  1333. * constructor for chip instance
  1334. */
  1335. static int __devinit snd_atiixp_create(struct snd_card *card,
  1336. struct pci_dev *pci,
  1337. struct atiixp **r_chip)
  1338. {
  1339. static struct snd_device_ops ops = {
  1340. .dev_free = snd_atiixp_dev_free,
  1341. };
  1342. struct atiixp *chip;
  1343. int err;
  1344. if ((err = pci_enable_device(pci)) < 0)
  1345. return err;
  1346. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1347. if (chip == NULL) {
  1348. pci_disable_device(pci);
  1349. return -ENOMEM;
  1350. }
  1351. spin_lock_init(&chip->reg_lock);
  1352. mutex_init(&chip->open_mutex);
  1353. chip->card = card;
  1354. chip->pci = pci;
  1355. chip->irq = -1;
  1356. if ((err = pci_request_regions(pci, "ATI IXP AC97")) < 0) {
  1357. pci_disable_device(pci);
  1358. kfree(chip);
  1359. return err;
  1360. }
  1361. chip->addr = pci_resource_start(pci, 0);
  1362. chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci, 0));
  1363. if (chip->remap_addr == NULL) {
  1364. snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
  1365. snd_atiixp_free(chip);
  1366. return -EIO;
  1367. }
  1368. if (request_irq(pci->irq, snd_atiixp_interrupt, IRQF_DISABLED|IRQF_SHARED,
  1369. card->shortname, chip)) {
  1370. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1371. snd_atiixp_free(chip);
  1372. return -EBUSY;
  1373. }
  1374. chip->irq = pci->irq;
  1375. pci_set_master(pci);
  1376. synchronize_irq(chip->irq);
  1377. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1378. snd_atiixp_free(chip);
  1379. return err;
  1380. }
  1381. snd_card_set_dev(card, &pci->dev);
  1382. *r_chip = chip;
  1383. return 0;
  1384. }
  1385. static int __devinit snd_atiixp_probe(struct pci_dev *pci,
  1386. const struct pci_device_id *pci_id)
  1387. {
  1388. struct snd_card *card;
  1389. struct atiixp *chip;
  1390. unsigned char revision;
  1391. int err;
  1392. card = snd_card_new(index, id, THIS_MODULE, 0);
  1393. if (card == NULL)
  1394. return -ENOMEM;
  1395. pci_read_config_byte(pci, PCI_REVISION_ID, &revision);
  1396. strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA");
  1397. strcpy(card->shortname, "ATI IXP");
  1398. if ((err = snd_atiixp_create(card, pci, &chip)) < 0)
  1399. goto __error;
  1400. card->private_data = chip;
  1401. if ((err = snd_atiixp_aclink_reset(chip)) < 0)
  1402. goto __error;
  1403. chip->spdif_over_aclink = spdif_aclink;
  1404. if ((err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk)) < 0)
  1405. goto __error;
  1406. if ((err = snd_atiixp_pcm_new(chip)) < 0)
  1407. goto __error;
  1408. snd_atiixp_proc_init(chip);
  1409. snd_atiixp_chip_start(chip);
  1410. snprintf(card->longname, sizeof(card->longname),
  1411. "%s rev %x with %s at %#lx, irq %i", card->shortname, revision,
  1412. chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?",
  1413. chip->addr, chip->irq);
  1414. if ((err = snd_card_register(card)) < 0)
  1415. goto __error;
  1416. pci_set_drvdata(pci, card);
  1417. return 0;
  1418. __error:
  1419. snd_card_free(card);
  1420. return err;
  1421. }
  1422. static void __devexit snd_atiixp_remove(struct pci_dev *pci)
  1423. {
  1424. snd_card_free(pci_get_drvdata(pci));
  1425. pci_set_drvdata(pci, NULL);
  1426. }
  1427. static struct pci_driver driver = {
  1428. .name = "ATI IXP AC97 controller",
  1429. .id_table = snd_atiixp_ids,
  1430. .probe = snd_atiixp_probe,
  1431. .remove = __devexit_p(snd_atiixp_remove),
  1432. #ifdef CONFIG_PM
  1433. .suspend = snd_atiixp_suspend,
  1434. .resume = snd_atiixp_resume,
  1435. #endif
  1436. };
  1437. static int __init alsa_card_atiixp_init(void)
  1438. {
  1439. return pci_register_driver(&driver);
  1440. }
  1441. static void __exit alsa_card_atiixp_exit(void)
  1442. {
  1443. pci_unregister_driver(&driver);
  1444. }
  1445. module_init(alsa_card_atiixp_init)
  1446. module_exit(alsa_card_atiixp_exit)