au1000.c 57 KB

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  1. /*
  2. * au1000.c -- Sound driver for Alchemy Au1000 MIPS Internet Edge
  3. * Processor.
  4. *
  5. * Copyright 2001 MontaVista Software Inc.
  6. * Author: MontaVista Software, Inc.
  7. * stevel@mvista.com or source@mvista.com
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. *
  14. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  15. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  16. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  17. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  20. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24. *
  25. * You should have received a copy of the GNU General Public License along
  26. * with this program; if not, write to the Free Software Foundation, Inc.,
  27. * 675 Mass Ave, Cambridge, MA 02139, USA.
  28. *
  29. *
  30. * Module command line parameters:
  31. *
  32. * Supported devices:
  33. * /dev/dsp standard OSS /dev/dsp device
  34. * /dev/mixer standard OSS /dev/mixer device
  35. *
  36. * Notes:
  37. *
  38. * 1. Much of the OSS buffer allocation, ioctl's, and mmap'ing are
  39. * taken, slightly modified or not at all, from the ES1371 driver,
  40. * so refer to the credits in es1371.c for those. The rest of the
  41. * code (probe, open, read, write, the ISR, etc.) is new.
  42. *
  43. * Revision history
  44. * 06.27.2001 Initial version
  45. * 03.20.2002 Added mutex locks around read/write methods, to prevent
  46. * simultaneous access on SMP or preemptible kernels. Also
  47. * removed the counter/pointer fragment aligning at the end
  48. * of read/write methods [stevel].
  49. * 03.21.2002 Add support for coherent DMA on the audio read/write DMA
  50. * channels [stevel].
  51. *
  52. */
  53. #include <linux/module.h>
  54. #include <linux/string.h>
  55. #include <linux/ioport.h>
  56. #include <linux/sched.h>
  57. #include <linux/delay.h>
  58. #include <linux/sound.h>
  59. #include <linux/slab.h>
  60. #include <linux/soundcard.h>
  61. #include <linux/init.h>
  62. #include <linux/page-flags.h>
  63. #include <linux/poll.h>
  64. #include <linux/pci.h>
  65. #include <linux/bitops.h>
  66. #include <linux/proc_fs.h>
  67. #include <linux/spinlock.h>
  68. #include <linux/smp_lock.h>
  69. #include <linux/ac97_codec.h>
  70. #include <linux/interrupt.h>
  71. #include <linux/mutex.h>
  72. #include <asm/io.h>
  73. #include <asm/uaccess.h>
  74. #include <asm/mach-au1x00/au1000.h>
  75. #include <asm/mach-au1x00/au1000_dma.h>
  76. /* --------------------------------------------------------------------- */
  77. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  78. #undef AU1000_DEBUG
  79. #undef AU1000_VERBOSE_DEBUG
  80. #define AU1000_MODULE_NAME "Au1000 audio"
  81. #define PFX AU1000_MODULE_NAME
  82. #ifdef AU1000_DEBUG
  83. #define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
  84. #else
  85. #define dbg(format, arg...) do {} while (0)
  86. #endif
  87. #define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
  88. #define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
  89. #define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
  90. /* misc stuff */
  91. #define POLL_COUNT 0x5000
  92. #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
  93. /* Boot options */
  94. static int vra = 0; // 0 = no VRA, 1 = use VRA if codec supports it
  95. module_param(vra, bool, 0);
  96. MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
  97. /* --------------------------------------------------------------------- */
  98. struct au1000_state {
  99. /* soundcore stuff */
  100. int dev_audio;
  101. #ifdef AU1000_DEBUG
  102. /* debug /proc entry */
  103. struct proc_dir_entry *ps;
  104. struct proc_dir_entry *ac97_ps;
  105. #endif /* AU1000_DEBUG */
  106. struct ac97_codec codec;
  107. unsigned codec_base_caps;// AC'97 reg 00h, "Reset Register"
  108. unsigned codec_ext_caps; // AC'97 reg 28h, "Extended Audio ID"
  109. int no_vra; // do not use VRA
  110. spinlock_t lock;
  111. struct mutex open_mutex;
  112. struct mutex sem;
  113. mode_t open_mode;
  114. wait_queue_head_t open_wait;
  115. struct dmabuf {
  116. unsigned int dmanr; // DMA Channel number
  117. unsigned sample_rate; // Hz
  118. unsigned src_factor; // SRC interp/decimation (no vra)
  119. unsigned sample_size; // 8 or 16
  120. int num_channels; // 1 = mono, 2 = stereo, 4, 6
  121. int dma_bytes_per_sample;// DMA bytes per audio sample frame
  122. int user_bytes_per_sample;// User bytes per audio sample frame
  123. int cnt_factor; // user-to-DMA bytes per audio
  124. // sample frame
  125. void *rawbuf;
  126. dma_addr_t dmaaddr;
  127. unsigned buforder;
  128. unsigned numfrag; // # of DMA fragments in DMA buffer
  129. unsigned fragshift;
  130. void *nextIn; // ptr to next-in to DMA buffer
  131. void *nextOut;// ptr to next-out from DMA buffer
  132. int count; // current byte count in DMA buffer
  133. unsigned total_bytes; // total bytes written or read
  134. unsigned error; // over/underrun
  135. wait_queue_head_t wait;
  136. /* redundant, but makes calculations easier */
  137. unsigned fragsize; // user perception of fragment size
  138. unsigned dma_fragsize; // DMA (real) fragment size
  139. unsigned dmasize; // Total DMA buffer size
  140. // (mult. of DMA fragsize)
  141. /* OSS stuff */
  142. unsigned mapped:1;
  143. unsigned ready:1;
  144. unsigned stopped:1;
  145. unsigned ossfragshift;
  146. int ossmaxfrags;
  147. unsigned subdivision;
  148. } dma_dac , dma_adc;
  149. } au1000_state;
  150. /* --------------------------------------------------------------------- */
  151. static inline unsigned ld2(unsigned int x)
  152. {
  153. unsigned r = 0;
  154. if (x >= 0x10000) {
  155. x >>= 16;
  156. r += 16;
  157. }
  158. if (x >= 0x100) {
  159. x >>= 8;
  160. r += 8;
  161. }
  162. if (x >= 0x10) {
  163. x >>= 4;
  164. r += 4;
  165. }
  166. if (x >= 4) {
  167. x >>= 2;
  168. r += 2;
  169. }
  170. if (x >= 2)
  171. r++;
  172. return r;
  173. }
  174. /* --------------------------------------------------------------------- */
  175. static void au1000_delay(int msec)
  176. {
  177. unsigned long tmo;
  178. signed long tmo2;
  179. if (in_interrupt())
  180. return;
  181. tmo = jiffies + (msec * HZ) / 1000;
  182. for (;;) {
  183. tmo2 = tmo - jiffies;
  184. if (tmo2 <= 0)
  185. break;
  186. schedule_timeout(tmo2);
  187. }
  188. }
  189. /* --------------------------------------------------------------------- */
  190. static u16 rdcodec(struct ac97_codec *codec, u8 addr)
  191. {
  192. struct au1000_state *s = (struct au1000_state *)codec->private_data;
  193. unsigned long flags;
  194. u32 cmd;
  195. u16 data;
  196. int i;
  197. spin_lock_irqsave(&s->lock, flags);
  198. for (i = 0; i < POLL_COUNT; i++)
  199. if (!(au_readl(AC97C_STATUS) & AC97C_CP))
  200. break;
  201. if (i == POLL_COUNT)
  202. err("rdcodec: codec cmd pending expired!");
  203. cmd = (u32) addr & AC97C_INDEX_MASK;
  204. cmd |= AC97C_READ; // read command
  205. au_writel(cmd, AC97C_CMD);
  206. /* now wait for the data */
  207. for (i = 0; i < POLL_COUNT; i++)
  208. if (!(au_readl(AC97C_STATUS) & AC97C_CP))
  209. break;
  210. if (i == POLL_COUNT) {
  211. err("rdcodec: read poll expired!");
  212. return 0;
  213. }
  214. data = au_readl(AC97C_CMD) & 0xffff;
  215. spin_unlock_irqrestore(&s->lock, flags);
  216. return data;
  217. }
  218. static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
  219. {
  220. struct au1000_state *s = (struct au1000_state *)codec->private_data;
  221. unsigned long flags;
  222. u32 cmd;
  223. int i;
  224. spin_lock_irqsave(&s->lock, flags);
  225. for (i = 0; i < POLL_COUNT; i++)
  226. if (!(au_readl(AC97C_STATUS) & AC97C_CP))
  227. break;
  228. if (i == POLL_COUNT)
  229. err("wrcodec: codec cmd pending expired!");
  230. cmd = (u32) addr & AC97C_INDEX_MASK;
  231. cmd &= ~AC97C_READ; // write command
  232. cmd |= ((u32) data << AC97C_WD_BIT); // OR in the data word
  233. au_writel(cmd, AC97C_CMD);
  234. spin_unlock_irqrestore(&s->lock, flags);
  235. }
  236. static void waitcodec(struct ac97_codec *codec)
  237. {
  238. u16 temp;
  239. int i;
  240. /* codec_wait is used to wait for a ready state after
  241. an AC97C_RESET. */
  242. au1000_delay(10);
  243. // first poll the CODEC_READY tag bit
  244. for (i = 0; i < POLL_COUNT; i++)
  245. if (au_readl(AC97C_STATUS) & AC97C_READY)
  246. break;
  247. if (i == POLL_COUNT) {
  248. err("waitcodec: CODEC_READY poll expired!");
  249. return;
  250. }
  251. // get AC'97 powerdown control/status register
  252. temp = rdcodec(codec, AC97_POWER_CONTROL);
  253. // If anything is powered down, power'em up
  254. if (temp & 0x7f00) {
  255. // Power on
  256. wrcodec(codec, AC97_POWER_CONTROL, 0);
  257. au1000_delay(100);
  258. // Reread
  259. temp = rdcodec(codec, AC97_POWER_CONTROL);
  260. }
  261. // Check if Codec REF,ANL,DAC,ADC ready
  262. if ((temp & 0x7f0f) != 0x000f)
  263. err("codec reg 26 status (0x%x) not ready!!", temp);
  264. }
  265. /* --------------------------------------------------------------------- */
  266. /* stop the ADC before calling */
  267. static void set_adc_rate(struct au1000_state *s, unsigned rate)
  268. {
  269. struct dmabuf *adc = &s->dma_adc;
  270. struct dmabuf *dac = &s->dma_dac;
  271. unsigned adc_rate, dac_rate;
  272. u16 ac97_extstat;
  273. if (s->no_vra) {
  274. // calc SRC factor
  275. adc->src_factor = ((96000 / rate) + 1) >> 1;
  276. adc->sample_rate = 48000 / adc->src_factor;
  277. return;
  278. }
  279. adc->src_factor = 1;
  280. ac97_extstat = rdcodec(&s->codec, AC97_EXTENDED_STATUS);
  281. rate = rate > 48000 ? 48000 : rate;
  282. // enable VRA
  283. wrcodec(&s->codec, AC97_EXTENDED_STATUS,
  284. ac97_extstat | AC97_EXTSTAT_VRA);
  285. // now write the sample rate
  286. wrcodec(&s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
  287. // read it back for actual supported rate
  288. adc_rate = rdcodec(&s->codec, AC97_PCM_LR_ADC_RATE);
  289. #ifdef AU1000_VERBOSE_DEBUG
  290. dbg("%s: set to %d Hz", __FUNCTION__, adc_rate);
  291. #endif
  292. // some codec's don't allow unequal DAC and ADC rates, in which case
  293. // writing one rate reg actually changes both.
  294. dac_rate = rdcodec(&s->codec, AC97_PCM_FRONT_DAC_RATE);
  295. if (dac->num_channels > 2)
  296. wrcodec(&s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
  297. if (dac->num_channels > 4)
  298. wrcodec(&s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
  299. adc->sample_rate = adc_rate;
  300. dac->sample_rate = dac_rate;
  301. }
  302. /* stop the DAC before calling */
  303. static void set_dac_rate(struct au1000_state *s, unsigned rate)
  304. {
  305. struct dmabuf *dac = &s->dma_dac;
  306. struct dmabuf *adc = &s->dma_adc;
  307. unsigned adc_rate, dac_rate;
  308. u16 ac97_extstat;
  309. if (s->no_vra) {
  310. // calc SRC factor
  311. dac->src_factor = ((96000 / rate) + 1) >> 1;
  312. dac->sample_rate = 48000 / dac->src_factor;
  313. return;
  314. }
  315. dac->src_factor = 1;
  316. ac97_extstat = rdcodec(&s->codec, AC97_EXTENDED_STATUS);
  317. rate = rate > 48000 ? 48000 : rate;
  318. // enable VRA
  319. wrcodec(&s->codec, AC97_EXTENDED_STATUS,
  320. ac97_extstat | AC97_EXTSTAT_VRA);
  321. // now write the sample rate
  322. wrcodec(&s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
  323. // I don't support different sample rates for multichannel,
  324. // so make these channels the same.
  325. if (dac->num_channels > 2)
  326. wrcodec(&s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
  327. if (dac->num_channels > 4)
  328. wrcodec(&s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
  329. // read it back for actual supported rate
  330. dac_rate = rdcodec(&s->codec, AC97_PCM_FRONT_DAC_RATE);
  331. #ifdef AU1000_VERBOSE_DEBUG
  332. dbg("%s: set to %d Hz", __FUNCTION__, dac_rate);
  333. #endif
  334. // some codec's don't allow unequal DAC and ADC rates, in which case
  335. // writing one rate reg actually changes both.
  336. adc_rate = rdcodec(&s->codec, AC97_PCM_LR_ADC_RATE);
  337. dac->sample_rate = dac_rate;
  338. adc->sample_rate = adc_rate;
  339. }
  340. static void stop_dac(struct au1000_state *s)
  341. {
  342. struct dmabuf *db = &s->dma_dac;
  343. unsigned long flags;
  344. if (db->stopped)
  345. return;
  346. spin_lock_irqsave(&s->lock, flags);
  347. disable_dma(db->dmanr);
  348. db->stopped = 1;
  349. spin_unlock_irqrestore(&s->lock, flags);
  350. }
  351. static void stop_adc(struct au1000_state *s)
  352. {
  353. struct dmabuf *db = &s->dma_adc;
  354. unsigned long flags;
  355. if (db->stopped)
  356. return;
  357. spin_lock_irqsave(&s->lock, flags);
  358. disable_dma(db->dmanr);
  359. db->stopped = 1;
  360. spin_unlock_irqrestore(&s->lock, flags);
  361. }
  362. static void set_xmit_slots(int num_channels)
  363. {
  364. u32 ac97_config = au_readl(AC97C_CONFIG) & ~AC97C_XMIT_SLOTS_MASK;
  365. switch (num_channels) {
  366. case 1: // mono
  367. case 2: // stereo, slots 3,4
  368. ac97_config |= (0x3 << AC97C_XMIT_SLOTS_BIT);
  369. break;
  370. case 4: // stereo with surround, slots 3,4,7,8
  371. ac97_config |= (0x33 << AC97C_XMIT_SLOTS_BIT);
  372. break;
  373. case 6: // stereo with surround and center/LFE, slots 3,4,6,7,8,9
  374. ac97_config |= (0x7b << AC97C_XMIT_SLOTS_BIT);
  375. break;
  376. }
  377. au_writel(ac97_config, AC97C_CONFIG);
  378. }
  379. static void set_recv_slots(int num_channels)
  380. {
  381. u32 ac97_config = au_readl(AC97C_CONFIG) & ~AC97C_RECV_SLOTS_MASK;
  382. /*
  383. * Always enable slots 3 and 4 (stereo). Slot 6 is
  384. * optional Mic ADC, which I don't support yet.
  385. */
  386. ac97_config |= (0x3 << AC97C_RECV_SLOTS_BIT);
  387. au_writel(ac97_config, AC97C_CONFIG);
  388. }
  389. static void start_dac(struct au1000_state *s)
  390. {
  391. struct dmabuf *db = &s->dma_dac;
  392. unsigned long flags;
  393. unsigned long buf1, buf2;
  394. if (!db->stopped)
  395. return;
  396. spin_lock_irqsave(&s->lock, flags);
  397. au_readl(AC97C_STATUS); // read status to clear sticky bits
  398. // reset Buffer 1 and 2 pointers to nextOut and nextOut+dma_fragsize
  399. buf1 = virt_to_phys(db->nextOut);
  400. buf2 = buf1 + db->dma_fragsize;
  401. if (buf2 >= db->dmaaddr + db->dmasize)
  402. buf2 -= db->dmasize;
  403. set_xmit_slots(db->num_channels);
  404. init_dma(db->dmanr);
  405. if (get_dma_active_buffer(db->dmanr) == 0) {
  406. clear_dma_done0(db->dmanr); // clear DMA done bit
  407. set_dma_addr0(db->dmanr, buf1);
  408. set_dma_addr1(db->dmanr, buf2);
  409. } else {
  410. clear_dma_done1(db->dmanr); // clear DMA done bit
  411. set_dma_addr1(db->dmanr, buf1);
  412. set_dma_addr0(db->dmanr, buf2);
  413. }
  414. set_dma_count(db->dmanr, db->dma_fragsize>>1);
  415. enable_dma_buffers(db->dmanr);
  416. start_dma(db->dmanr);
  417. #ifdef AU1000_VERBOSE_DEBUG
  418. dump_au1000_dma_channel(db->dmanr);
  419. #endif
  420. db->stopped = 0;
  421. spin_unlock_irqrestore(&s->lock, flags);
  422. }
  423. static void start_adc(struct au1000_state *s)
  424. {
  425. struct dmabuf *db = &s->dma_adc;
  426. unsigned long flags;
  427. unsigned long buf1, buf2;
  428. if (!db->stopped)
  429. return;
  430. spin_lock_irqsave(&s->lock, flags);
  431. au_readl(AC97C_STATUS); // read status to clear sticky bits
  432. // reset Buffer 1 and 2 pointers to nextIn and nextIn+dma_fragsize
  433. buf1 = virt_to_phys(db->nextIn);
  434. buf2 = buf1 + db->dma_fragsize;
  435. if (buf2 >= db->dmaaddr + db->dmasize)
  436. buf2 -= db->dmasize;
  437. set_recv_slots(db->num_channels);
  438. init_dma(db->dmanr);
  439. if (get_dma_active_buffer(db->dmanr) == 0) {
  440. clear_dma_done0(db->dmanr); // clear DMA done bit
  441. set_dma_addr0(db->dmanr, buf1);
  442. set_dma_addr1(db->dmanr, buf2);
  443. } else {
  444. clear_dma_done1(db->dmanr); // clear DMA done bit
  445. set_dma_addr1(db->dmanr, buf1);
  446. set_dma_addr0(db->dmanr, buf2);
  447. }
  448. set_dma_count(db->dmanr, db->dma_fragsize>>1);
  449. enable_dma_buffers(db->dmanr);
  450. start_dma(db->dmanr);
  451. #ifdef AU1000_VERBOSE_DEBUG
  452. dump_au1000_dma_channel(db->dmanr);
  453. #endif
  454. db->stopped = 0;
  455. spin_unlock_irqrestore(&s->lock, flags);
  456. }
  457. /* --------------------------------------------------------------------- */
  458. #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
  459. #define DMABUF_MINORDER 1
  460. static inline void dealloc_dmabuf(struct au1000_state *s, struct dmabuf *db)
  461. {
  462. struct page *page, *pend;
  463. if (db->rawbuf) {
  464. /* undo marking the pages as reserved */
  465. pend = virt_to_page(db->rawbuf +
  466. (PAGE_SIZE << db->buforder) - 1);
  467. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  468. ClearPageReserved(page);
  469. dma_free_noncoherent(NULL,
  470. PAGE_SIZE << db->buforder,
  471. db->rawbuf,
  472. db->dmaaddr);
  473. }
  474. db->rawbuf = db->nextIn = db->nextOut = NULL;
  475. db->mapped = db->ready = 0;
  476. }
  477. static int prog_dmabuf(struct au1000_state *s, struct dmabuf *db)
  478. {
  479. int order;
  480. unsigned user_bytes_per_sec;
  481. unsigned bufs;
  482. struct page *page, *pend;
  483. unsigned rate = db->sample_rate;
  484. if (!db->rawbuf) {
  485. db->ready = db->mapped = 0;
  486. for (order = DMABUF_DEFAULTORDER;
  487. order >= DMABUF_MINORDER; order--)
  488. if ((db->rawbuf = dma_alloc_noncoherent(NULL,
  489. PAGE_SIZE << order,
  490. &db->dmaaddr,
  491. 0)))
  492. break;
  493. if (!db->rawbuf)
  494. return -ENOMEM;
  495. db->buforder = order;
  496. /* now mark the pages as reserved;
  497. otherwise remap_pfn_range doesn't do what we want */
  498. pend = virt_to_page(db->rawbuf +
  499. (PAGE_SIZE << db->buforder) - 1);
  500. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  501. SetPageReserved(page);
  502. }
  503. db->cnt_factor = 1;
  504. if (db->sample_size == 8)
  505. db->cnt_factor *= 2;
  506. if (db->num_channels == 1)
  507. db->cnt_factor *= 2;
  508. db->cnt_factor *= db->src_factor;
  509. db->count = 0;
  510. db->nextIn = db->nextOut = db->rawbuf;
  511. db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
  512. db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
  513. 2 : db->num_channels);
  514. user_bytes_per_sec = rate * db->user_bytes_per_sample;
  515. bufs = PAGE_SIZE << db->buforder;
  516. if (db->ossfragshift) {
  517. if ((1000 << db->ossfragshift) < user_bytes_per_sec)
  518. db->fragshift = ld2(user_bytes_per_sec/1000);
  519. else
  520. db->fragshift = db->ossfragshift;
  521. } else {
  522. db->fragshift = ld2(user_bytes_per_sec / 100 /
  523. (db->subdivision ? db->subdivision : 1));
  524. if (db->fragshift < 3)
  525. db->fragshift = 3;
  526. }
  527. db->fragsize = 1 << db->fragshift;
  528. db->dma_fragsize = db->fragsize * db->cnt_factor;
  529. db->numfrag = bufs / db->dma_fragsize;
  530. while (db->numfrag < 4 && db->fragshift > 3) {
  531. db->fragshift--;
  532. db->fragsize = 1 << db->fragshift;
  533. db->dma_fragsize = db->fragsize * db->cnt_factor;
  534. db->numfrag = bufs / db->dma_fragsize;
  535. }
  536. if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
  537. db->numfrag = db->ossmaxfrags;
  538. db->dmasize = db->dma_fragsize * db->numfrag;
  539. memset(db->rawbuf, 0, bufs);
  540. #ifdef AU1000_VERBOSE_DEBUG
  541. dbg("rate=%d, samplesize=%d, channels=%d",
  542. rate, db->sample_size, db->num_channels);
  543. dbg("fragsize=%d, cnt_factor=%d, dma_fragsize=%d",
  544. db->fragsize, db->cnt_factor, db->dma_fragsize);
  545. dbg("numfrag=%d, dmasize=%d", db->numfrag, db->dmasize);
  546. #endif
  547. db->ready = 1;
  548. return 0;
  549. }
  550. static inline int prog_dmabuf_adc(struct au1000_state *s)
  551. {
  552. stop_adc(s);
  553. return prog_dmabuf(s, &s->dma_adc);
  554. }
  555. static inline int prog_dmabuf_dac(struct au1000_state *s)
  556. {
  557. stop_dac(s);
  558. return prog_dmabuf(s, &s->dma_dac);
  559. }
  560. /* hold spinlock for the following */
  561. static irqreturn_t dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  562. {
  563. struct au1000_state *s = (struct au1000_state *) dev_id;
  564. struct dmabuf *dac = &s->dma_dac;
  565. unsigned long newptr;
  566. u32 ac97c_stat, buff_done;
  567. ac97c_stat = au_readl(AC97C_STATUS);
  568. #ifdef AU1000_VERBOSE_DEBUG
  569. if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
  570. dbg("AC97C status = 0x%08x", ac97c_stat);
  571. #endif
  572. if ((buff_done = get_dma_buffer_done(dac->dmanr)) == 0) {
  573. /* fastpath out, to ease interrupt sharing */
  574. return IRQ_HANDLED;
  575. }
  576. spin_lock(&s->lock);
  577. if (buff_done != (DMA_D0 | DMA_D1)) {
  578. dac->nextOut += dac->dma_fragsize;
  579. if (dac->nextOut >= dac->rawbuf + dac->dmasize)
  580. dac->nextOut -= dac->dmasize;
  581. /* update playback pointers */
  582. newptr = virt_to_phys(dac->nextOut) + dac->dma_fragsize;
  583. if (newptr >= dac->dmaaddr + dac->dmasize)
  584. newptr -= dac->dmasize;
  585. dac->count -= dac->dma_fragsize;
  586. dac->total_bytes += dac->dma_fragsize;
  587. if (dac->count <= 0) {
  588. #ifdef AU1000_VERBOSE_DEBUG
  589. dbg("dac underrun");
  590. #endif
  591. spin_unlock(&s->lock);
  592. stop_dac(s);
  593. spin_lock(&s->lock);
  594. dac->count = 0;
  595. dac->nextIn = dac->nextOut;
  596. } else if (buff_done == DMA_D0) {
  597. clear_dma_done0(dac->dmanr); // clear DMA done bit
  598. set_dma_count0(dac->dmanr, dac->dma_fragsize>>1);
  599. set_dma_addr0(dac->dmanr, newptr);
  600. enable_dma_buffer0(dac->dmanr); // reenable
  601. } else {
  602. clear_dma_done1(dac->dmanr); // clear DMA done bit
  603. set_dma_count1(dac->dmanr, dac->dma_fragsize>>1);
  604. set_dma_addr1(dac->dmanr, newptr);
  605. enable_dma_buffer1(dac->dmanr); // reenable
  606. }
  607. } else {
  608. // both done bits set, we missed an interrupt
  609. spin_unlock(&s->lock);
  610. stop_dac(s);
  611. spin_lock(&s->lock);
  612. dac->nextOut += 2*dac->dma_fragsize;
  613. if (dac->nextOut >= dac->rawbuf + dac->dmasize)
  614. dac->nextOut -= dac->dmasize;
  615. dac->count -= 2*dac->dma_fragsize;
  616. dac->total_bytes += 2*dac->dma_fragsize;
  617. if (dac->count > 0) {
  618. spin_unlock(&s->lock);
  619. start_dac(s);
  620. spin_lock(&s->lock);
  621. }
  622. }
  623. /* wake up anybody listening */
  624. if (waitqueue_active(&dac->wait))
  625. wake_up(&dac->wait);
  626. spin_unlock(&s->lock);
  627. return IRQ_HANDLED;
  628. }
  629. static irqreturn_t adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  630. {
  631. struct au1000_state *s = (struct au1000_state *) dev_id;
  632. struct dmabuf *adc = &s->dma_adc;
  633. unsigned long newptr;
  634. u32 ac97c_stat, buff_done;
  635. ac97c_stat = au_readl(AC97C_STATUS);
  636. #ifdef AU1000_VERBOSE_DEBUG
  637. if (ac97c_stat & (AC97C_RU | AC97C_RO))
  638. dbg("AC97C status = 0x%08x", ac97c_stat);
  639. #endif
  640. if ((buff_done = get_dma_buffer_done(adc->dmanr)) == 0) {
  641. /* fastpath out, to ease interrupt sharing */
  642. return IRQ_HANDLED;
  643. }
  644. spin_lock(&s->lock);
  645. if (buff_done != (DMA_D0 | DMA_D1)) {
  646. if (adc->count + adc->dma_fragsize > adc->dmasize) {
  647. // Overrun. Stop ADC and log the error
  648. spin_unlock(&s->lock);
  649. stop_adc(s);
  650. adc->error++;
  651. err("adc overrun");
  652. return IRQ_NONE;
  653. }
  654. adc->nextIn += adc->dma_fragsize;
  655. if (adc->nextIn >= adc->rawbuf + adc->dmasize)
  656. adc->nextIn -= adc->dmasize;
  657. /* update capture pointers */
  658. newptr = virt_to_phys(adc->nextIn) + adc->dma_fragsize;
  659. if (newptr >= adc->dmaaddr + adc->dmasize)
  660. newptr -= adc->dmasize;
  661. adc->count += adc->dma_fragsize;
  662. adc->total_bytes += adc->dma_fragsize;
  663. if (buff_done == DMA_D0) {
  664. clear_dma_done0(adc->dmanr); // clear DMA done bit
  665. set_dma_count0(adc->dmanr, adc->dma_fragsize>>1);
  666. set_dma_addr0(adc->dmanr, newptr);
  667. enable_dma_buffer0(adc->dmanr); // reenable
  668. } else {
  669. clear_dma_done1(adc->dmanr); // clear DMA done bit
  670. set_dma_count1(adc->dmanr, adc->dma_fragsize>>1);
  671. set_dma_addr1(adc->dmanr, newptr);
  672. enable_dma_buffer1(adc->dmanr); // reenable
  673. }
  674. } else {
  675. // both done bits set, we missed an interrupt
  676. spin_unlock(&s->lock);
  677. stop_adc(s);
  678. spin_lock(&s->lock);
  679. if (adc->count + 2*adc->dma_fragsize > adc->dmasize) {
  680. // Overrun. Log the error
  681. adc->error++;
  682. err("adc overrun");
  683. spin_unlock(&s->lock);
  684. return IRQ_NONE;
  685. }
  686. adc->nextIn += 2*adc->dma_fragsize;
  687. if (adc->nextIn >= adc->rawbuf + adc->dmasize)
  688. adc->nextIn -= adc->dmasize;
  689. adc->count += 2*adc->dma_fragsize;
  690. adc->total_bytes += 2*adc->dma_fragsize;
  691. spin_unlock(&s->lock);
  692. start_adc(s);
  693. spin_lock(&s->lock);
  694. }
  695. /* wake up anybody listening */
  696. if (waitqueue_active(&adc->wait))
  697. wake_up(&adc->wait);
  698. spin_unlock(&s->lock);
  699. return IRQ_HANDLED;
  700. }
  701. /* --------------------------------------------------------------------- */
  702. static loff_t au1000_llseek(struct file *file, loff_t offset, int origin)
  703. {
  704. return -ESPIPE;
  705. }
  706. static int au1000_open_mixdev(struct inode *inode, struct file *file)
  707. {
  708. file->private_data = &au1000_state;
  709. return nonseekable_open(inode, file);
  710. }
  711. static int au1000_release_mixdev(struct inode *inode, struct file *file)
  712. {
  713. return 0;
  714. }
  715. static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
  716. unsigned long arg)
  717. {
  718. return codec->mixer_ioctl(codec, cmd, arg);
  719. }
  720. static int au1000_ioctl_mixdev(struct inode *inode, struct file *file,
  721. unsigned int cmd, unsigned long arg)
  722. {
  723. struct au1000_state *s = (struct au1000_state *)file->private_data;
  724. struct ac97_codec *codec = &s->codec;
  725. return mixdev_ioctl(codec, cmd, arg);
  726. }
  727. static /*const */ struct file_operations au1000_mixer_fops = {
  728. .owner = THIS_MODULE,
  729. .llseek = au1000_llseek,
  730. .ioctl = au1000_ioctl_mixdev,
  731. .open = au1000_open_mixdev,
  732. .release = au1000_release_mixdev,
  733. };
  734. /* --------------------------------------------------------------------- */
  735. static int drain_dac(struct au1000_state *s, int nonblock)
  736. {
  737. unsigned long flags;
  738. int count, tmo;
  739. if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
  740. return 0;
  741. for (;;) {
  742. spin_lock_irqsave(&s->lock, flags);
  743. count = s->dma_dac.count;
  744. spin_unlock_irqrestore(&s->lock, flags);
  745. if (count <= 0)
  746. break;
  747. if (signal_pending(current))
  748. break;
  749. if (nonblock)
  750. return -EBUSY;
  751. tmo = 1000 * count / (s->no_vra ?
  752. 48000 : s->dma_dac.sample_rate);
  753. tmo /= s->dma_dac.dma_bytes_per_sample;
  754. au1000_delay(tmo);
  755. }
  756. if (signal_pending(current))
  757. return -ERESTARTSYS;
  758. return 0;
  759. }
  760. /* --------------------------------------------------------------------- */
  761. static inline u8 S16_TO_U8(s16 ch)
  762. {
  763. return (u8) (ch >> 8) + 0x80;
  764. }
  765. static inline s16 U8_TO_S16(u8 ch)
  766. {
  767. return (s16) (ch - 0x80) << 8;
  768. }
  769. /*
  770. * Translates user samples to dma buffer suitable for AC'97 DAC data:
  771. * If mono, copy left channel to right channel in dma buffer.
  772. * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
  773. * If interpolating (no VRA), duplicate every audio frame src_factor times.
  774. */
  775. static int translate_from_user(struct dmabuf *db,
  776. char* dmabuf,
  777. char* userbuf,
  778. int dmacount)
  779. {
  780. int sample, i;
  781. int interp_bytes_per_sample;
  782. int num_samples;
  783. int mono = (db->num_channels == 1);
  784. char usersample[12];
  785. s16 ch, dmasample[6];
  786. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  787. // no translation necessary, just copy
  788. if (copy_from_user(dmabuf, userbuf, dmacount))
  789. return -EFAULT;
  790. return dmacount;
  791. }
  792. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  793. num_samples = dmacount / interp_bytes_per_sample;
  794. for (sample = 0; sample < num_samples; sample++) {
  795. if (copy_from_user(usersample, userbuf,
  796. db->user_bytes_per_sample)) {
  797. dbg("%s: fault", __FUNCTION__);
  798. return -EFAULT;
  799. }
  800. for (i = 0; i < db->num_channels; i++) {
  801. if (db->sample_size == 8)
  802. ch = U8_TO_S16(usersample[i]);
  803. else
  804. ch = *((s16 *) (&usersample[i * 2]));
  805. dmasample[i] = ch;
  806. if (mono)
  807. dmasample[i + 1] = ch; // right channel
  808. }
  809. // duplicate every audio frame src_factor times
  810. for (i = 0; i < db->src_factor; i++)
  811. memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
  812. userbuf += db->user_bytes_per_sample;
  813. dmabuf += interp_bytes_per_sample;
  814. }
  815. return num_samples * interp_bytes_per_sample;
  816. }
  817. /*
  818. * Translates AC'97 ADC samples to user buffer:
  819. * If mono, send only left channel to user buffer.
  820. * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
  821. * If decimating (no VRA), skip over src_factor audio frames.
  822. */
  823. static int translate_to_user(struct dmabuf *db,
  824. char* userbuf,
  825. char* dmabuf,
  826. int dmacount)
  827. {
  828. int sample, i;
  829. int interp_bytes_per_sample;
  830. int num_samples;
  831. int mono = (db->num_channels == 1);
  832. char usersample[12];
  833. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  834. // no translation necessary, just copy
  835. if (copy_to_user(userbuf, dmabuf, dmacount))
  836. return -EFAULT;
  837. return dmacount;
  838. }
  839. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  840. num_samples = dmacount / interp_bytes_per_sample;
  841. for (sample = 0; sample < num_samples; sample++) {
  842. for (i = 0; i < db->num_channels; i++) {
  843. if (db->sample_size == 8)
  844. usersample[i] =
  845. S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
  846. else
  847. *((s16 *) (&usersample[i * 2])) =
  848. *((s16 *) (&dmabuf[i * 2]));
  849. }
  850. if (copy_to_user(userbuf, usersample,
  851. db->user_bytes_per_sample)) {
  852. dbg("%s: fault", __FUNCTION__);
  853. return -EFAULT;
  854. }
  855. userbuf += db->user_bytes_per_sample;
  856. dmabuf += interp_bytes_per_sample;
  857. }
  858. return num_samples * interp_bytes_per_sample;
  859. }
  860. /*
  861. * Copy audio data to/from user buffer from/to dma buffer, taking care
  862. * that we wrap when reading/writing the dma buffer. Returns actual byte
  863. * count written to or read from the dma buffer.
  864. */
  865. static int copy_dmabuf_user(struct dmabuf *db, char* userbuf,
  866. int count, int to_user)
  867. {
  868. char *bufptr = to_user ? db->nextOut : db->nextIn;
  869. char *bufend = db->rawbuf + db->dmasize;
  870. int cnt, ret;
  871. if (bufptr + count > bufend) {
  872. int partial = (int) (bufend - bufptr);
  873. if (to_user) {
  874. if ((cnt = translate_to_user(db, userbuf,
  875. bufptr, partial)) < 0)
  876. return cnt;
  877. ret = cnt;
  878. if ((cnt = translate_to_user(db, userbuf + partial,
  879. db->rawbuf,
  880. count - partial)) < 0)
  881. return cnt;
  882. ret += cnt;
  883. } else {
  884. if ((cnt = translate_from_user(db, bufptr, userbuf,
  885. partial)) < 0)
  886. return cnt;
  887. ret = cnt;
  888. if ((cnt = translate_from_user(db, db->rawbuf,
  889. userbuf + partial,
  890. count - partial)) < 0)
  891. return cnt;
  892. ret += cnt;
  893. }
  894. } else {
  895. if (to_user)
  896. ret = translate_to_user(db, userbuf, bufptr, count);
  897. else
  898. ret = translate_from_user(db, bufptr, userbuf, count);
  899. }
  900. return ret;
  901. }
  902. static ssize_t au1000_read(struct file *file, char *buffer,
  903. size_t count, loff_t *ppos)
  904. {
  905. struct au1000_state *s = (struct au1000_state *)file->private_data;
  906. struct dmabuf *db = &s->dma_adc;
  907. DECLARE_WAITQUEUE(wait, current);
  908. ssize_t ret;
  909. unsigned long flags;
  910. int cnt, usercnt, avail;
  911. if (db->mapped)
  912. return -ENXIO;
  913. if (!access_ok(VERIFY_WRITE, buffer, count))
  914. return -EFAULT;
  915. ret = 0;
  916. count *= db->cnt_factor;
  917. mutex_lock(&s->sem);
  918. add_wait_queue(&db->wait, &wait);
  919. while (count > 0) {
  920. // wait for samples in ADC dma buffer
  921. do {
  922. if (db->stopped)
  923. start_adc(s);
  924. spin_lock_irqsave(&s->lock, flags);
  925. avail = db->count;
  926. if (avail <= 0)
  927. __set_current_state(TASK_INTERRUPTIBLE);
  928. spin_unlock_irqrestore(&s->lock, flags);
  929. if (avail <= 0) {
  930. if (file->f_flags & O_NONBLOCK) {
  931. if (!ret)
  932. ret = -EAGAIN;
  933. goto out;
  934. }
  935. mutex_unlock(&s->sem);
  936. schedule();
  937. if (signal_pending(current)) {
  938. if (!ret)
  939. ret = -ERESTARTSYS;
  940. goto out2;
  941. }
  942. mutex_lock(&s->sem);
  943. }
  944. } while (avail <= 0);
  945. // copy from nextOut to user
  946. if ((cnt = copy_dmabuf_user(db, buffer,
  947. count > avail ?
  948. avail : count, 1)) < 0) {
  949. if (!ret)
  950. ret = -EFAULT;
  951. goto out;
  952. }
  953. spin_lock_irqsave(&s->lock, flags);
  954. db->count -= cnt;
  955. db->nextOut += cnt;
  956. if (db->nextOut >= db->rawbuf + db->dmasize)
  957. db->nextOut -= db->dmasize;
  958. spin_unlock_irqrestore(&s->lock, flags);
  959. count -= cnt;
  960. usercnt = cnt / db->cnt_factor;
  961. buffer += usercnt;
  962. ret += usercnt;
  963. } // while (count > 0)
  964. out:
  965. mutex_unlock(&s->sem);
  966. out2:
  967. remove_wait_queue(&db->wait, &wait);
  968. set_current_state(TASK_RUNNING);
  969. return ret;
  970. }
  971. static ssize_t au1000_write(struct file *file, const char *buffer,
  972. size_t count, loff_t * ppos)
  973. {
  974. struct au1000_state *s = (struct au1000_state *)file->private_data;
  975. struct dmabuf *db = &s->dma_dac;
  976. DECLARE_WAITQUEUE(wait, current);
  977. ssize_t ret = 0;
  978. unsigned long flags;
  979. int cnt, usercnt, avail;
  980. #ifdef AU1000_VERBOSE_DEBUG
  981. dbg("write: count=%d", count);
  982. #endif
  983. if (db->mapped)
  984. return -ENXIO;
  985. if (!access_ok(VERIFY_READ, buffer, count))
  986. return -EFAULT;
  987. count *= db->cnt_factor;
  988. mutex_lock(&s->sem);
  989. add_wait_queue(&db->wait, &wait);
  990. while (count > 0) {
  991. // wait for space in playback buffer
  992. do {
  993. spin_lock_irqsave(&s->lock, flags);
  994. avail = (int) db->dmasize - db->count;
  995. if (avail <= 0)
  996. __set_current_state(TASK_INTERRUPTIBLE);
  997. spin_unlock_irqrestore(&s->lock, flags);
  998. if (avail <= 0) {
  999. if (file->f_flags & O_NONBLOCK) {
  1000. if (!ret)
  1001. ret = -EAGAIN;
  1002. goto out;
  1003. }
  1004. mutex_unlock(&s->sem);
  1005. schedule();
  1006. if (signal_pending(current)) {
  1007. if (!ret)
  1008. ret = -ERESTARTSYS;
  1009. goto out2;
  1010. }
  1011. mutex_lock(&s->sem);
  1012. }
  1013. } while (avail <= 0);
  1014. // copy from user to nextIn
  1015. if ((cnt = copy_dmabuf_user(db, (char *) buffer,
  1016. count > avail ?
  1017. avail : count, 0)) < 0) {
  1018. if (!ret)
  1019. ret = -EFAULT;
  1020. goto out;
  1021. }
  1022. spin_lock_irqsave(&s->lock, flags);
  1023. db->count += cnt;
  1024. db->nextIn += cnt;
  1025. if (db->nextIn >= db->rawbuf + db->dmasize)
  1026. db->nextIn -= db->dmasize;
  1027. spin_unlock_irqrestore(&s->lock, flags);
  1028. if (db->stopped)
  1029. start_dac(s);
  1030. count -= cnt;
  1031. usercnt = cnt / db->cnt_factor;
  1032. buffer += usercnt;
  1033. ret += usercnt;
  1034. } // while (count > 0)
  1035. out:
  1036. mutex_unlock(&s->sem);
  1037. out2:
  1038. remove_wait_queue(&db->wait, &wait);
  1039. set_current_state(TASK_RUNNING);
  1040. return ret;
  1041. }
  1042. /* No kernel lock - we have our own spinlock */
  1043. static unsigned int au1000_poll(struct file *file,
  1044. struct poll_table_struct *wait)
  1045. {
  1046. struct au1000_state *s = (struct au1000_state *)file->private_data;
  1047. unsigned long flags;
  1048. unsigned int mask = 0;
  1049. if (file->f_mode & FMODE_WRITE) {
  1050. if (!s->dma_dac.ready)
  1051. return 0;
  1052. poll_wait(file, &s->dma_dac.wait, wait);
  1053. }
  1054. if (file->f_mode & FMODE_READ) {
  1055. if (!s->dma_adc.ready)
  1056. return 0;
  1057. poll_wait(file, &s->dma_adc.wait, wait);
  1058. }
  1059. spin_lock_irqsave(&s->lock, flags);
  1060. if (file->f_mode & FMODE_READ) {
  1061. if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
  1062. mask |= POLLIN | POLLRDNORM;
  1063. }
  1064. if (file->f_mode & FMODE_WRITE) {
  1065. if (s->dma_dac.mapped) {
  1066. if (s->dma_dac.count >=
  1067. (signed)s->dma_dac.dma_fragsize)
  1068. mask |= POLLOUT | POLLWRNORM;
  1069. } else {
  1070. if ((signed) s->dma_dac.dmasize >=
  1071. s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
  1072. mask |= POLLOUT | POLLWRNORM;
  1073. }
  1074. }
  1075. spin_unlock_irqrestore(&s->lock, flags);
  1076. return mask;
  1077. }
  1078. static int au1000_mmap(struct file *file, struct vm_area_struct *vma)
  1079. {
  1080. struct au1000_state *s = (struct au1000_state *)file->private_data;
  1081. struct dmabuf *db;
  1082. unsigned long size;
  1083. int ret = 0;
  1084. dbg("%s", __FUNCTION__);
  1085. lock_kernel();
  1086. mutex_lock(&s->sem);
  1087. if (vma->vm_flags & VM_WRITE)
  1088. db = &s->dma_dac;
  1089. else if (vma->vm_flags & VM_READ)
  1090. db = &s->dma_adc;
  1091. else {
  1092. ret = -EINVAL;
  1093. goto out;
  1094. }
  1095. if (vma->vm_pgoff != 0) {
  1096. ret = -EINVAL;
  1097. goto out;
  1098. }
  1099. size = vma->vm_end - vma->vm_start;
  1100. if (size > (PAGE_SIZE << db->buforder)) {
  1101. ret = -EINVAL;
  1102. goto out;
  1103. }
  1104. if (remap_pfn_range(vma, vma->vm_start, virt_to_phys(db->rawbuf),
  1105. size, vma->vm_page_prot)) {
  1106. ret = -EAGAIN;
  1107. goto out;
  1108. }
  1109. vma->vm_flags &= ~VM_IO;
  1110. db->mapped = 1;
  1111. out:
  1112. mutex_unlock(&s->sem);
  1113. unlock_kernel();
  1114. return ret;
  1115. }
  1116. #ifdef AU1000_VERBOSE_DEBUG
  1117. static struct ioctl_str_t {
  1118. unsigned int cmd;
  1119. const char *str;
  1120. } ioctl_str[] = {
  1121. {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
  1122. {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
  1123. {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
  1124. {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
  1125. {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
  1126. {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
  1127. {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
  1128. {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
  1129. {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
  1130. {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
  1131. {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
  1132. {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
  1133. {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
  1134. {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
  1135. {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
  1136. {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
  1137. {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
  1138. {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
  1139. {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
  1140. {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
  1141. {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
  1142. {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
  1143. {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
  1144. {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
  1145. {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
  1146. {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
  1147. {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
  1148. {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
  1149. {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
  1150. {OSS_GETVERSION, "OSS_GETVERSION"},
  1151. {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
  1152. {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
  1153. {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
  1154. {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
  1155. };
  1156. #endif
  1157. // Need to hold a spin-lock before calling this!
  1158. static int dma_count_done(struct dmabuf *db)
  1159. {
  1160. if (db->stopped)
  1161. return 0;
  1162. return db->dma_fragsize - get_dma_residue(db->dmanr);
  1163. }
  1164. static int au1000_ioctl(struct inode *inode, struct file *file,
  1165. unsigned int cmd, unsigned long arg)
  1166. {
  1167. struct au1000_state *s = (struct au1000_state *)file->private_data;
  1168. unsigned long flags;
  1169. audio_buf_info abinfo;
  1170. count_info cinfo;
  1171. int count;
  1172. int val, mapped, ret, diff;
  1173. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
  1174. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1175. #ifdef AU1000_VERBOSE_DEBUG
  1176. for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
  1177. if (ioctl_str[count].cmd == cmd)
  1178. break;
  1179. }
  1180. if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
  1181. dbg("ioctl %s, arg=0x%lx", ioctl_str[count].str, arg);
  1182. else
  1183. dbg("ioctl 0x%x unknown, arg=0x%lx", cmd, arg);
  1184. #endif
  1185. switch (cmd) {
  1186. case OSS_GETVERSION:
  1187. return put_user(SOUND_VERSION, (int *) arg);
  1188. case SNDCTL_DSP_SYNC:
  1189. if (file->f_mode & FMODE_WRITE)
  1190. return drain_dac(s, file->f_flags & O_NONBLOCK);
  1191. return 0;
  1192. case SNDCTL_DSP_SETDUPLEX:
  1193. return 0;
  1194. case SNDCTL_DSP_GETCAPS:
  1195. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
  1196. DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
  1197. case SNDCTL_DSP_RESET:
  1198. if (file->f_mode & FMODE_WRITE) {
  1199. stop_dac(s);
  1200. synchronize_irq();
  1201. s->dma_dac.count = s->dma_dac.total_bytes = 0;
  1202. s->dma_dac.nextIn = s->dma_dac.nextOut =
  1203. s->dma_dac.rawbuf;
  1204. }
  1205. if (file->f_mode & FMODE_READ) {
  1206. stop_adc(s);
  1207. synchronize_irq();
  1208. s->dma_adc.count = s->dma_adc.total_bytes = 0;
  1209. s->dma_adc.nextIn = s->dma_adc.nextOut =
  1210. s->dma_adc.rawbuf;
  1211. }
  1212. return 0;
  1213. case SNDCTL_DSP_SPEED:
  1214. if (get_user(val, (int *) arg))
  1215. return -EFAULT;
  1216. if (val >= 0) {
  1217. if (file->f_mode & FMODE_READ) {
  1218. stop_adc(s);
  1219. set_adc_rate(s, val);
  1220. }
  1221. if (file->f_mode & FMODE_WRITE) {
  1222. stop_dac(s);
  1223. set_dac_rate(s, val);
  1224. }
  1225. if (s->open_mode & FMODE_READ)
  1226. if ((ret = prog_dmabuf_adc(s)))
  1227. return ret;
  1228. if (s->open_mode & FMODE_WRITE)
  1229. if ((ret = prog_dmabuf_dac(s)))
  1230. return ret;
  1231. }
  1232. return put_user((file->f_mode & FMODE_READ) ?
  1233. s->dma_adc.sample_rate :
  1234. s->dma_dac.sample_rate,
  1235. (int *)arg);
  1236. case SNDCTL_DSP_STEREO:
  1237. if (get_user(val, (int *) arg))
  1238. return -EFAULT;
  1239. if (file->f_mode & FMODE_READ) {
  1240. stop_adc(s);
  1241. s->dma_adc.num_channels = val ? 2 : 1;
  1242. if ((ret = prog_dmabuf_adc(s)))
  1243. return ret;
  1244. }
  1245. if (file->f_mode & FMODE_WRITE) {
  1246. stop_dac(s);
  1247. s->dma_dac.num_channels = val ? 2 : 1;
  1248. if (s->codec_ext_caps & AC97_EXT_DACS) {
  1249. // disable surround and center/lfe in AC'97
  1250. u16 ext_stat = rdcodec(&s->codec,
  1251. AC97_EXTENDED_STATUS);
  1252. wrcodec(&s->codec, AC97_EXTENDED_STATUS,
  1253. ext_stat | (AC97_EXTSTAT_PRI |
  1254. AC97_EXTSTAT_PRJ |
  1255. AC97_EXTSTAT_PRK));
  1256. }
  1257. if ((ret = prog_dmabuf_dac(s)))
  1258. return ret;
  1259. }
  1260. return 0;
  1261. case SNDCTL_DSP_CHANNELS:
  1262. if (get_user(val, (int *) arg))
  1263. return -EFAULT;
  1264. if (val != 0) {
  1265. if (file->f_mode & FMODE_READ) {
  1266. if (val < 0 || val > 2)
  1267. return -EINVAL;
  1268. stop_adc(s);
  1269. s->dma_adc.num_channels = val;
  1270. if ((ret = prog_dmabuf_adc(s)))
  1271. return ret;
  1272. }
  1273. if (file->f_mode & FMODE_WRITE) {
  1274. switch (val) {
  1275. case 1:
  1276. case 2:
  1277. break;
  1278. case 3:
  1279. case 5:
  1280. return -EINVAL;
  1281. case 4:
  1282. if (!(s->codec_ext_caps &
  1283. AC97_EXTID_SDAC))
  1284. return -EINVAL;
  1285. break;
  1286. case 6:
  1287. if ((s->codec_ext_caps &
  1288. AC97_EXT_DACS) != AC97_EXT_DACS)
  1289. return -EINVAL;
  1290. break;
  1291. default:
  1292. return -EINVAL;
  1293. }
  1294. stop_dac(s);
  1295. if (val <= 2 &&
  1296. (s->codec_ext_caps & AC97_EXT_DACS)) {
  1297. // disable surround and center/lfe
  1298. // channels in AC'97
  1299. u16 ext_stat =
  1300. rdcodec(&s->codec,
  1301. AC97_EXTENDED_STATUS);
  1302. wrcodec(&s->codec,
  1303. AC97_EXTENDED_STATUS,
  1304. ext_stat | (AC97_EXTSTAT_PRI |
  1305. AC97_EXTSTAT_PRJ |
  1306. AC97_EXTSTAT_PRK));
  1307. } else if (val >= 4) {
  1308. // enable surround, center/lfe
  1309. // channels in AC'97
  1310. u16 ext_stat =
  1311. rdcodec(&s->codec,
  1312. AC97_EXTENDED_STATUS);
  1313. ext_stat &= ~AC97_EXTSTAT_PRJ;
  1314. if (val == 6)
  1315. ext_stat &=
  1316. ~(AC97_EXTSTAT_PRI |
  1317. AC97_EXTSTAT_PRK);
  1318. wrcodec(&s->codec,
  1319. AC97_EXTENDED_STATUS,
  1320. ext_stat);
  1321. }
  1322. s->dma_dac.num_channels = val;
  1323. if ((ret = prog_dmabuf_dac(s)))
  1324. return ret;
  1325. }
  1326. }
  1327. return put_user(val, (int *) arg);
  1328. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1329. return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
  1330. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
  1331. if (get_user(val, (int *) arg))
  1332. return -EFAULT;
  1333. if (val != AFMT_QUERY) {
  1334. if (file->f_mode & FMODE_READ) {
  1335. stop_adc(s);
  1336. if (val == AFMT_S16_LE)
  1337. s->dma_adc.sample_size = 16;
  1338. else {
  1339. val = AFMT_U8;
  1340. s->dma_adc.sample_size = 8;
  1341. }
  1342. if ((ret = prog_dmabuf_adc(s)))
  1343. return ret;
  1344. }
  1345. if (file->f_mode & FMODE_WRITE) {
  1346. stop_dac(s);
  1347. if (val == AFMT_S16_LE)
  1348. s->dma_dac.sample_size = 16;
  1349. else {
  1350. val = AFMT_U8;
  1351. s->dma_dac.sample_size = 8;
  1352. }
  1353. if ((ret = prog_dmabuf_dac(s)))
  1354. return ret;
  1355. }
  1356. } else {
  1357. if (file->f_mode & FMODE_READ)
  1358. val = (s->dma_adc.sample_size == 16) ?
  1359. AFMT_S16_LE : AFMT_U8;
  1360. else
  1361. val = (s->dma_dac.sample_size == 16) ?
  1362. AFMT_S16_LE : AFMT_U8;
  1363. }
  1364. return put_user(val, (int *) arg);
  1365. case SNDCTL_DSP_POST:
  1366. return 0;
  1367. case SNDCTL_DSP_GETTRIGGER:
  1368. val = 0;
  1369. spin_lock_irqsave(&s->lock, flags);
  1370. if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
  1371. val |= PCM_ENABLE_INPUT;
  1372. if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
  1373. val |= PCM_ENABLE_OUTPUT;
  1374. spin_unlock_irqrestore(&s->lock, flags);
  1375. return put_user(val, (int *) arg);
  1376. case SNDCTL_DSP_SETTRIGGER:
  1377. if (get_user(val, (int *) arg))
  1378. return -EFAULT;
  1379. if (file->f_mode & FMODE_READ) {
  1380. if (val & PCM_ENABLE_INPUT)
  1381. start_adc(s);
  1382. else
  1383. stop_adc(s);
  1384. }
  1385. if (file->f_mode & FMODE_WRITE) {
  1386. if (val & PCM_ENABLE_OUTPUT)
  1387. start_dac(s);
  1388. else
  1389. stop_dac(s);
  1390. }
  1391. return 0;
  1392. case SNDCTL_DSP_GETOSPACE:
  1393. if (!(file->f_mode & FMODE_WRITE))
  1394. return -EINVAL;
  1395. abinfo.fragsize = s->dma_dac.fragsize;
  1396. spin_lock_irqsave(&s->lock, flags);
  1397. count = s->dma_dac.count;
  1398. count -= dma_count_done(&s->dma_dac);
  1399. spin_unlock_irqrestore(&s->lock, flags);
  1400. if (count < 0)
  1401. count = 0;
  1402. abinfo.bytes = (s->dma_dac.dmasize - count) /
  1403. s->dma_dac.cnt_factor;
  1404. abinfo.fragstotal = s->dma_dac.numfrag;
  1405. abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
  1406. #ifdef AU1000_VERBOSE_DEBUG
  1407. dbg("bytes=%d, fragments=%d", abinfo.bytes, abinfo.fragments);
  1408. #endif
  1409. return copy_to_user((void *) arg, &abinfo,
  1410. sizeof(abinfo)) ? -EFAULT : 0;
  1411. case SNDCTL_DSP_GETISPACE:
  1412. if (!(file->f_mode & FMODE_READ))
  1413. return -EINVAL;
  1414. abinfo.fragsize = s->dma_adc.fragsize;
  1415. spin_lock_irqsave(&s->lock, flags);
  1416. count = s->dma_adc.count;
  1417. count += dma_count_done(&s->dma_adc);
  1418. spin_unlock_irqrestore(&s->lock, flags);
  1419. if (count < 0)
  1420. count = 0;
  1421. abinfo.bytes = count / s->dma_adc.cnt_factor;
  1422. abinfo.fragstotal = s->dma_adc.numfrag;
  1423. abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
  1424. return copy_to_user((void *) arg, &abinfo,
  1425. sizeof(abinfo)) ? -EFAULT : 0;
  1426. case SNDCTL_DSP_NONBLOCK:
  1427. file->f_flags |= O_NONBLOCK;
  1428. return 0;
  1429. case SNDCTL_DSP_GETODELAY:
  1430. if (!(file->f_mode & FMODE_WRITE))
  1431. return -EINVAL;
  1432. spin_lock_irqsave(&s->lock, flags);
  1433. count = s->dma_dac.count;
  1434. count -= dma_count_done(&s->dma_dac);
  1435. spin_unlock_irqrestore(&s->lock, flags);
  1436. if (count < 0)
  1437. count = 0;
  1438. count /= s->dma_dac.cnt_factor;
  1439. return put_user(count, (int *) arg);
  1440. case SNDCTL_DSP_GETIPTR:
  1441. if (!(file->f_mode & FMODE_READ))
  1442. return -EINVAL;
  1443. spin_lock_irqsave(&s->lock, flags);
  1444. cinfo.bytes = s->dma_adc.total_bytes;
  1445. count = s->dma_adc.count;
  1446. if (!s->dma_adc.stopped) {
  1447. diff = dma_count_done(&s->dma_adc);
  1448. count += diff;
  1449. cinfo.bytes += diff;
  1450. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
  1451. s->dma_adc.dmaaddr;
  1452. } else
  1453. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
  1454. s->dma_adc.dmaaddr;
  1455. if (s->dma_adc.mapped)
  1456. s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
  1457. spin_unlock_irqrestore(&s->lock, flags);
  1458. if (count < 0)
  1459. count = 0;
  1460. cinfo.blocks = count >> s->dma_adc.fragshift;
  1461. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
  1462. case SNDCTL_DSP_GETOPTR:
  1463. if (!(file->f_mode & FMODE_READ))
  1464. return -EINVAL;
  1465. spin_lock_irqsave(&s->lock, flags);
  1466. cinfo.bytes = s->dma_dac.total_bytes;
  1467. count = s->dma_dac.count;
  1468. if (!s->dma_dac.stopped) {
  1469. diff = dma_count_done(&s->dma_dac);
  1470. count -= diff;
  1471. cinfo.bytes += diff;
  1472. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
  1473. s->dma_dac.dmaaddr;
  1474. } else
  1475. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
  1476. s->dma_dac.dmaaddr;
  1477. if (s->dma_dac.mapped)
  1478. s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
  1479. spin_unlock_irqrestore(&s->lock, flags);
  1480. if (count < 0)
  1481. count = 0;
  1482. cinfo.blocks = count >> s->dma_dac.fragshift;
  1483. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
  1484. case SNDCTL_DSP_GETBLKSIZE:
  1485. if (file->f_mode & FMODE_WRITE)
  1486. return put_user(s->dma_dac.fragsize, (int *) arg);
  1487. else
  1488. return put_user(s->dma_adc.fragsize, (int *) arg);
  1489. case SNDCTL_DSP_SETFRAGMENT:
  1490. if (get_user(val, (int *) arg))
  1491. return -EFAULT;
  1492. if (file->f_mode & FMODE_READ) {
  1493. stop_adc(s);
  1494. s->dma_adc.ossfragshift = val & 0xffff;
  1495. s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
  1496. if (s->dma_adc.ossfragshift < 4)
  1497. s->dma_adc.ossfragshift = 4;
  1498. if (s->dma_adc.ossfragshift > 15)
  1499. s->dma_adc.ossfragshift = 15;
  1500. if (s->dma_adc.ossmaxfrags < 4)
  1501. s->dma_adc.ossmaxfrags = 4;
  1502. if ((ret = prog_dmabuf_adc(s)))
  1503. return ret;
  1504. }
  1505. if (file->f_mode & FMODE_WRITE) {
  1506. stop_dac(s);
  1507. s->dma_dac.ossfragshift = val & 0xffff;
  1508. s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
  1509. if (s->dma_dac.ossfragshift < 4)
  1510. s->dma_dac.ossfragshift = 4;
  1511. if (s->dma_dac.ossfragshift > 15)
  1512. s->dma_dac.ossfragshift = 15;
  1513. if (s->dma_dac.ossmaxfrags < 4)
  1514. s->dma_dac.ossmaxfrags = 4;
  1515. if ((ret = prog_dmabuf_dac(s)))
  1516. return ret;
  1517. }
  1518. return 0;
  1519. case SNDCTL_DSP_SUBDIVIDE:
  1520. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
  1521. (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
  1522. return -EINVAL;
  1523. if (get_user(val, (int *) arg))
  1524. return -EFAULT;
  1525. if (val != 1 && val != 2 && val != 4)
  1526. return -EINVAL;
  1527. if (file->f_mode & FMODE_READ) {
  1528. stop_adc(s);
  1529. s->dma_adc.subdivision = val;
  1530. if ((ret = prog_dmabuf_adc(s)))
  1531. return ret;
  1532. }
  1533. if (file->f_mode & FMODE_WRITE) {
  1534. stop_dac(s);
  1535. s->dma_dac.subdivision = val;
  1536. if ((ret = prog_dmabuf_dac(s)))
  1537. return ret;
  1538. }
  1539. return 0;
  1540. case SOUND_PCM_READ_RATE:
  1541. return put_user((file->f_mode & FMODE_READ) ?
  1542. s->dma_adc.sample_rate :
  1543. s->dma_dac.sample_rate,
  1544. (int *)arg);
  1545. case SOUND_PCM_READ_CHANNELS:
  1546. if (file->f_mode & FMODE_READ)
  1547. return put_user(s->dma_adc.num_channels, (int *)arg);
  1548. else
  1549. return put_user(s->dma_dac.num_channels, (int *)arg);
  1550. case SOUND_PCM_READ_BITS:
  1551. if (file->f_mode & FMODE_READ)
  1552. return put_user(s->dma_adc.sample_size, (int *)arg);
  1553. else
  1554. return put_user(s->dma_dac.sample_size, (int *)arg);
  1555. case SOUND_PCM_WRITE_FILTER:
  1556. case SNDCTL_DSP_SETSYNCRO:
  1557. case SOUND_PCM_READ_FILTER:
  1558. return -EINVAL;
  1559. }
  1560. return mixdev_ioctl(&s->codec, cmd, arg);
  1561. }
  1562. static int au1000_open(struct inode *inode, struct file *file)
  1563. {
  1564. int minor = iminor(inode);
  1565. DECLARE_WAITQUEUE(wait, current);
  1566. struct au1000_state *s = &au1000_state;
  1567. int ret;
  1568. #ifdef AU1000_VERBOSE_DEBUG
  1569. if (file->f_flags & O_NONBLOCK)
  1570. dbg("%s: non-blocking", __FUNCTION__);
  1571. else
  1572. dbg("%s: blocking", __FUNCTION__);
  1573. #endif
  1574. file->private_data = s;
  1575. /* wait for device to become free */
  1576. mutex_lock(&s->open_mutex);
  1577. while (s->open_mode & file->f_mode) {
  1578. if (file->f_flags & O_NONBLOCK) {
  1579. mutex_unlock(&s->open_mutex);
  1580. return -EBUSY;
  1581. }
  1582. add_wait_queue(&s->open_wait, &wait);
  1583. __set_current_state(TASK_INTERRUPTIBLE);
  1584. mutex_unlock(&s->open_mutex);
  1585. schedule();
  1586. remove_wait_queue(&s->open_wait, &wait);
  1587. set_current_state(TASK_RUNNING);
  1588. if (signal_pending(current))
  1589. return -ERESTARTSYS;
  1590. mutex_lock(&s->open_mutex);
  1591. }
  1592. stop_dac(s);
  1593. stop_adc(s);
  1594. if (file->f_mode & FMODE_READ) {
  1595. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
  1596. s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
  1597. s->dma_adc.num_channels = 1;
  1598. s->dma_adc.sample_size = 8;
  1599. set_adc_rate(s, 8000);
  1600. if ((minor & 0xf) == SND_DEV_DSP16)
  1601. s->dma_adc.sample_size = 16;
  1602. }
  1603. if (file->f_mode & FMODE_WRITE) {
  1604. s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
  1605. s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
  1606. s->dma_dac.num_channels = 1;
  1607. s->dma_dac.sample_size = 8;
  1608. set_dac_rate(s, 8000);
  1609. if ((minor & 0xf) == SND_DEV_DSP16)
  1610. s->dma_dac.sample_size = 16;
  1611. }
  1612. if (file->f_mode & FMODE_READ) {
  1613. if ((ret = prog_dmabuf_adc(s)))
  1614. return ret;
  1615. }
  1616. if (file->f_mode & FMODE_WRITE) {
  1617. if ((ret = prog_dmabuf_dac(s)))
  1618. return ret;
  1619. }
  1620. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1621. mutex_unlock(&s->open_mutex);
  1622. mutex_init(&s->sem);
  1623. return nonseekable_open(inode, file);
  1624. }
  1625. static int au1000_release(struct inode *inode, struct file *file)
  1626. {
  1627. struct au1000_state *s = (struct au1000_state *)file->private_data;
  1628. lock_kernel();
  1629. if (file->f_mode & FMODE_WRITE) {
  1630. unlock_kernel();
  1631. drain_dac(s, file->f_flags & O_NONBLOCK);
  1632. lock_kernel();
  1633. }
  1634. mutex_lock(&s->open_mutex);
  1635. if (file->f_mode & FMODE_WRITE) {
  1636. stop_dac(s);
  1637. dealloc_dmabuf(s, &s->dma_dac);
  1638. }
  1639. if (file->f_mode & FMODE_READ) {
  1640. stop_adc(s);
  1641. dealloc_dmabuf(s, &s->dma_adc);
  1642. }
  1643. s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
  1644. mutex_unlock(&s->open_mutex);
  1645. wake_up(&s->open_wait);
  1646. unlock_kernel();
  1647. return 0;
  1648. }
  1649. static /*const */ struct file_operations au1000_audio_fops = {
  1650. .owner = THIS_MODULE,
  1651. .llseek = au1000_llseek,
  1652. .read = au1000_read,
  1653. .write = au1000_write,
  1654. .poll = au1000_poll,
  1655. .ioctl = au1000_ioctl,
  1656. .mmap = au1000_mmap,
  1657. .open = au1000_open,
  1658. .release = au1000_release,
  1659. };
  1660. /* --------------------------------------------------------------------- */
  1661. /* --------------------------------------------------------------------- */
  1662. /*
  1663. * for debugging purposes, we'll create a proc device that dumps the
  1664. * CODEC chipstate
  1665. */
  1666. #ifdef AU1000_DEBUG
  1667. static int proc_au1000_dump(char *buf, char **start, off_t fpos,
  1668. int length, int *eof, void *data)
  1669. {
  1670. struct au1000_state *s = &au1000_state;
  1671. int cnt, len = 0;
  1672. /* print out header */
  1673. len += sprintf(buf + len, "\n\t\tAU1000 Audio Debug\n\n");
  1674. // print out digital controller state
  1675. len += sprintf(buf + len, "AU1000 Audio Controller registers\n");
  1676. len += sprintf(buf + len, "---------------------------------\n");
  1677. len += sprintf (buf + len, "AC97C_CONFIG = %08x\n",
  1678. au_readl(AC97C_CONFIG));
  1679. len += sprintf (buf + len, "AC97C_STATUS = %08x\n",
  1680. au_readl(AC97C_STATUS));
  1681. len += sprintf (buf + len, "AC97C_CNTRL = %08x\n",
  1682. au_readl(AC97C_CNTRL));
  1683. /* print out CODEC state */
  1684. len += sprintf(buf + len, "\nAC97 CODEC registers\n");
  1685. len += sprintf(buf + len, "----------------------\n");
  1686. for (cnt = 0; cnt <= 0x7e; cnt += 2)
  1687. len += sprintf(buf + len, "reg %02x = %04x\n",
  1688. cnt, rdcodec(&s->codec, cnt));
  1689. if (fpos >= len) {
  1690. *start = buf;
  1691. *eof = 1;
  1692. return 0;
  1693. }
  1694. *start = buf + fpos;
  1695. if ((len -= fpos) > length)
  1696. return length;
  1697. *eof = 1;
  1698. return len;
  1699. }
  1700. #endif /* AU1000_DEBUG */
  1701. /* --------------------------------------------------------------------- */
  1702. MODULE_AUTHOR("Monta Vista Software, stevel@mvista.com");
  1703. MODULE_DESCRIPTION("Au1000 Audio Driver");
  1704. /* --------------------------------------------------------------------- */
  1705. static int __devinit au1000_probe(void)
  1706. {
  1707. struct au1000_state *s = &au1000_state;
  1708. int val;
  1709. #ifdef AU1000_DEBUG
  1710. char proc_str[80];
  1711. #endif
  1712. memset(s, 0, sizeof(struct au1000_state));
  1713. init_waitqueue_head(&s->dma_adc.wait);
  1714. init_waitqueue_head(&s->dma_dac.wait);
  1715. init_waitqueue_head(&s->open_wait);
  1716. mutex_init(&s->open_mutex);
  1717. spin_lock_init(&s->lock);
  1718. s->codec.private_data = s;
  1719. s->codec.id = 0;
  1720. s->codec.codec_read = rdcodec;
  1721. s->codec.codec_write = wrcodec;
  1722. s->codec.codec_wait = waitcodec;
  1723. if (!request_mem_region(CPHYSADDR(AC97C_CONFIG),
  1724. 0x14, AU1000_MODULE_NAME)) {
  1725. err("AC'97 ports in use");
  1726. return -1;
  1727. }
  1728. // Allocate the DMA Channels
  1729. if ((s->dma_dac.dmanr = request_au1000_dma(DMA_ID_AC97C_TX,
  1730. "audio DAC",
  1731. dac_dma_interrupt,
  1732. IRQF_DISABLED, s)) < 0) {
  1733. err("Can't get DAC DMA");
  1734. goto err_dma1;
  1735. }
  1736. if ((s->dma_adc.dmanr = request_au1000_dma(DMA_ID_AC97C_RX,
  1737. "audio ADC",
  1738. adc_dma_interrupt,
  1739. IRQF_DISABLED, s)) < 0) {
  1740. err("Can't get ADC DMA");
  1741. goto err_dma2;
  1742. }
  1743. info("DAC: DMA%d/IRQ%d, ADC: DMA%d/IRQ%d",
  1744. s->dma_dac.dmanr, get_dma_done_irq(s->dma_dac.dmanr),
  1745. s->dma_adc.dmanr, get_dma_done_irq(s->dma_adc.dmanr));
  1746. // enable DMA coherency in read/write DMA channels
  1747. set_dma_mode(s->dma_dac.dmanr,
  1748. get_dma_mode(s->dma_dac.dmanr) & ~DMA_NC);
  1749. set_dma_mode(s->dma_adc.dmanr,
  1750. get_dma_mode(s->dma_adc.dmanr) & ~DMA_NC);
  1751. /* register devices */
  1752. if ((s->dev_audio = register_sound_dsp(&au1000_audio_fops, -1)) < 0)
  1753. goto err_dev1;
  1754. if ((s->codec.dev_mixer =
  1755. register_sound_mixer(&au1000_mixer_fops, -1)) < 0)
  1756. goto err_dev2;
  1757. #ifdef AU1000_DEBUG
  1758. /* intialize the debug proc device */
  1759. s->ps = create_proc_read_entry(AU1000_MODULE_NAME, 0, NULL,
  1760. proc_au1000_dump, NULL);
  1761. #endif /* AU1000_DEBUG */
  1762. // configure pins for AC'97
  1763. au_writel(au_readl(SYS_PINFUNC) & ~0x02, SYS_PINFUNC);
  1764. // Assert reset for 10msec to the AC'97 controller, and enable clock
  1765. au_writel(AC97C_RS | AC97C_CE, AC97C_CNTRL);
  1766. au1000_delay(10);
  1767. au_writel(AC97C_CE, AC97C_CNTRL);
  1768. au1000_delay(10); // wait for clock to stabilize
  1769. /* cold reset the AC'97 */
  1770. au_writel(AC97C_RESET, AC97C_CONFIG);
  1771. au1000_delay(10);
  1772. au_writel(0, AC97C_CONFIG);
  1773. /* need to delay around 500msec(bleech) to give
  1774. some CODECs enough time to wakeup */
  1775. au1000_delay(500);
  1776. /* warm reset the AC'97 to start the bitclk */
  1777. au_writel(AC97C_SG | AC97C_SYNC, AC97C_CONFIG);
  1778. udelay(100);
  1779. au_writel(0, AC97C_CONFIG);
  1780. /* codec init */
  1781. if (!ac97_probe_codec(&s->codec))
  1782. goto err_dev3;
  1783. s->codec_base_caps = rdcodec(&s->codec, AC97_RESET);
  1784. s->codec_ext_caps = rdcodec(&s->codec, AC97_EXTENDED_ID);
  1785. info("AC'97 Base/Extended ID = %04x/%04x",
  1786. s->codec_base_caps, s->codec_ext_caps);
  1787. /*
  1788. * On the Pb1000, audio playback is on the AUX_OUT
  1789. * channel (which defaults to LNLVL_OUT in AC'97
  1790. * rev 2.2) so make sure this channel is listed
  1791. * as supported (soundcard.h calls this channel
  1792. * ALTPCM). ac97_codec.c does not handle detection
  1793. * of this channel correctly.
  1794. */
  1795. s->codec.supported_mixers |= SOUND_MASK_ALTPCM;
  1796. /*
  1797. * Now set AUX_OUT's default volume.
  1798. */
  1799. val = 0x4343;
  1800. mixdev_ioctl(&s->codec, SOUND_MIXER_WRITE_ALTPCM,
  1801. (unsigned long) &val);
  1802. if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
  1803. // codec does not support VRA
  1804. s->no_vra = 1;
  1805. } else if (!vra) {
  1806. // Boot option says disable VRA
  1807. u16 ac97_extstat = rdcodec(&s->codec, AC97_EXTENDED_STATUS);
  1808. wrcodec(&s->codec, AC97_EXTENDED_STATUS,
  1809. ac97_extstat & ~AC97_EXTSTAT_VRA);
  1810. s->no_vra = 1;
  1811. }
  1812. if (s->no_vra)
  1813. info("no VRA, interpolating and decimating");
  1814. /* set mic to be the recording source */
  1815. val = SOUND_MASK_MIC;
  1816. mixdev_ioctl(&s->codec, SOUND_MIXER_WRITE_RECSRC,
  1817. (unsigned long) &val);
  1818. #ifdef AU1000_DEBUG
  1819. sprintf(proc_str, "driver/%s/%d/ac97", AU1000_MODULE_NAME,
  1820. s->codec.id);
  1821. s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL,
  1822. ac97_read_proc, &s->codec);
  1823. #endif
  1824. #ifdef CONFIG_MIPS_XXS1500
  1825. /* deassert eapd */
  1826. wrcodec(&s->codec, AC97_POWER_CONTROL,
  1827. rdcodec(&s->codec, AC97_POWER_CONTROL) & ~0x8000);
  1828. /* mute a number of signals which seem to be causing problems
  1829. * if not muted.
  1830. */
  1831. wrcodec(&s->codec, AC97_PCBEEP_VOL, 0x8000);
  1832. wrcodec(&s->codec, AC97_PHONE_VOL, 0x8008);
  1833. wrcodec(&s->codec, AC97_MIC_VOL, 0x8008);
  1834. wrcodec(&s->codec, AC97_LINEIN_VOL, 0x8808);
  1835. wrcodec(&s->codec, AC97_CD_VOL, 0x8808);
  1836. wrcodec(&s->codec, AC97_VIDEO_VOL, 0x8808);
  1837. wrcodec(&s->codec, AC97_AUX_VOL, 0x8808);
  1838. wrcodec(&s->codec, AC97_PCMOUT_VOL, 0x0808);
  1839. wrcodec(&s->codec, AC97_GENERAL_PURPOSE, 0x2000);
  1840. #endif
  1841. return 0;
  1842. err_dev3:
  1843. unregister_sound_mixer(s->codec.dev_mixer);
  1844. err_dev2:
  1845. unregister_sound_dsp(s->dev_audio);
  1846. err_dev1:
  1847. free_au1000_dma(s->dma_adc.dmanr);
  1848. err_dma2:
  1849. free_au1000_dma(s->dma_dac.dmanr);
  1850. err_dma1:
  1851. release_mem_region(CPHYSADDR(AC97C_CONFIG), 0x14);
  1852. return -1;
  1853. }
  1854. static void au1000_remove(void)
  1855. {
  1856. struct au1000_state *s = &au1000_state;
  1857. if (!s)
  1858. return;
  1859. #ifdef AU1000_DEBUG
  1860. if (s->ps)
  1861. remove_proc_entry(AU1000_MODULE_NAME, NULL);
  1862. #endif /* AU1000_DEBUG */
  1863. synchronize_irq();
  1864. free_au1000_dma(s->dma_adc.dmanr);
  1865. free_au1000_dma(s->dma_dac.dmanr);
  1866. release_mem_region(CPHYSADDR(AC97C_CONFIG), 0x14);
  1867. unregister_sound_dsp(s->dev_audio);
  1868. unregister_sound_mixer(s->codec.dev_mixer);
  1869. }
  1870. static int __init init_au1000(void)
  1871. {
  1872. info("stevel@mvista.com, built " __TIME__ " on " __DATE__);
  1873. return au1000_probe();
  1874. }
  1875. static void __exit cleanup_au1000(void)
  1876. {
  1877. info("unloading");
  1878. au1000_remove();
  1879. }
  1880. module_init(init_au1000);
  1881. module_exit(cleanup_au1000);
  1882. /* --------------------------------------------------------------------- */
  1883. #ifndef MODULE
  1884. static int __init au1000_setup(char *options)
  1885. {
  1886. char *this_opt;
  1887. if (!options || !*options)
  1888. return 0;
  1889. while ((this_opt = strsep(&options, ","))) {
  1890. if (!*this_opt)
  1891. continue;
  1892. if (!strncmp(this_opt, "vra", 3)) {
  1893. vra = 1;
  1894. }
  1895. }
  1896. return 1;
  1897. }
  1898. __setup("au1000_audio=", au1000_setup);
  1899. #endif /* MODULE */