Home Explore Help
Register Sign In
phyus
/
linux-vybrid_public
8
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: d10be6d1bd
Branches Tags
linux-vybrid_pu...
/
include
/
asm-arm
/
hardware
/
iop3xx.h

iop3xx.h 14 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301 
  1. /*
    2. 

  2.  * include/asm-arm/hardware/iop3xx.h
    3. 

  3.  *
    4. 

  4.  * Intel IOP32X and IOP33X register definitions
    5. 

  5.  *
    6. 

  6.  * Author: Rory Bolt <rorybolt@pacbell.net>
    7. 

  7.  * Copyright (C) 2002 Rory Bolt
    8. 

  8.  * Copyright (C) 2004 Intel Corp.
    9. 

  9.  *
    10. 

  10.  * This program is free software; you can redistribute it and/or modify
    11. 

  11.  * it under the terms of the GNU General Public License version 2 as
    12. 

  12.  * published by the Free Software Foundation.
    13. 

  13.  */
    14. 

  14. 

  15. #ifndef __IOP3XX_H
    16. 

  16. #define __IOP3XX_H
    17. 

  17. 

  18. /*
    19. 

  19.  * IOP3XX GPIO handling
    20. 

  20.  */
    21. 

  21. #define GPIO_IN			0
    22. 

  22. #define GPIO_OUT		1
    23. 

  23. #define GPIO_LOW		0
    24. 

  24. #define GPIO_HIGH		1
    25. 

  25. #define IOP3XX_GPIO_LINE(x)	(x)
    26. 

  26. 

  27. #ifndef __ASSEMBLY__
    28. 

  28. extern void gpio_line_config(int line, int direction);
    29. 

  29. extern int  gpio_line_get(int line);
    30. 

  30. extern void gpio_line_set(int line, int value);
    31. 

  31. #endif
    32. 

  32. 

  33. 

  34. /*
    35. 

  35.  * IOP3XX processor registers
    36. 

  36.  */
    37. 

  37. #define IOP3XX_PERIPHERAL_PHYS_BASE	0xffffe000
    38. 

  38. #define IOP3XX_PERIPHERAL_VIRT_BASE	0xfeffe000
    39. 

  39. #define IOP3XX_PERIPHERAL_SIZE		0x00002000
    40. 

  40. #define IOP3XX_REG_ADDR(reg)		(IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
    41. 

  41. 

  42. /* Address Translation Unit  */
    43. 

  43. #define IOP3XX_ATUVID		(volatile u16 *)IOP3XX_REG_ADDR(0x0100)
    44. 

  44. #define IOP3XX_ATUDID		(volatile u16 *)IOP3XX_REG_ADDR(0x0102)
    45. 

  45. #define IOP3XX_ATUCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x0104)
    46. 

  46. #define IOP3XX_ATUSR		(volatile u16 *)IOP3XX_REG_ADDR(0x0106)
    47. 

  47. #define IOP3XX_ATURID		(volatile u8  *)IOP3XX_REG_ADDR(0x0108)
    48. 

  48. #define IOP3XX_ATUCCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0109)
    49. 

  49. #define IOP3XX_ATUCLSR		(volatile u8  *)IOP3XX_REG_ADDR(0x010c)
    50. 

  50. #define IOP3XX_ATULT		(volatile u8  *)IOP3XX_REG_ADDR(0x010d)
    51. 

  51. #define IOP3XX_ATUHTR		(volatile u8  *)IOP3XX_REG_ADDR(0x010e)
    52. 

  52. #define IOP3XX_ATUBIST		(volatile u8  *)IOP3XX_REG_ADDR(0x010f)
    53. 

  53. #define IOP3XX_IABAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0110)
    54. 

  54. #define IOP3XX_IAUBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0114)
    55. 

  55. #define IOP3XX_IABAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0118)
    56. 

  56. #define IOP3XX_IAUBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x011c)
    57. 

  57. #define IOP3XX_IABAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0120)
    58. 

  58. #define IOP3XX_IAUBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0124)
    59. 

  59. #define IOP3XX_ASVIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012c)
    60. 

  60. #define IOP3XX_ASIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012e)
    61. 

  61. #define IOP3XX_ERBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0130)
    62. 

  62. #define IOP3XX_ATUILR		(volatile u8  *)IOP3XX_REG_ADDR(0x013c)
    63. 

  63. #define IOP3XX_ATUIPR		(volatile u8  *)IOP3XX_REG_ADDR(0x013d)
    64. 

  64. #define IOP3XX_ATUMGNT		(volatile u8  *)IOP3XX_REG_ADDR(0x013e)
    65. 

  65. #define IOP3XX_ATUMLAT		(volatile u8  *)IOP3XX_REG_ADDR(0x013f)
    66. 

  66. #define IOP3XX_IALR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0140)
    67. 

  67. #define IOP3XX_IATVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0144)
    68. 

  68. #define IOP3XX_ERLR		(volatile u32 *)IOP3XX_REG_ADDR(0x0148)
    69. 

  69. #define IOP3XX_ERTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x014c)
    70. 

  70. #define IOP3XX_IALR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0150)
    71. 

  71. #define IOP3XX_IALR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0154)
    72. 

  72. #define IOP3XX_IATVR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0158)
    73. 

  73. #define IOP3XX_OIOWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x015c)
    74. 

  74. #define IOP3XX_OMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0160)
    75. 

  75. #define IOP3XX_OUMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0164)
    76. 

  76. #define IOP3XX_OMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0168)
    77. 

  77. #define IOP3XX_OUMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x016c)
    78. 

  78. #define IOP3XX_OUDWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x0178)
    79. 

  79. #define IOP3XX_ATUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0180)
    80. 

  80. #define IOP3XX_PCSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0184)
    81. 

  81. #define IOP3XX_ATUISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0188)
    82. 

  82. #define IOP3XX_ATUIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x018c)
    83. 

  83. #define IOP3XX_IABAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0190)
    84. 

  84. #define IOP3XX_IAUBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0194)
    85. 

  85. #define IOP3XX_IALR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0198)
    86. 

  86. #define IOP3XX_IATVR3		(volatile u32 *)IOP3XX_REG_ADDR(0x019c)
    87. 

  87. #define IOP3XX_OCCAR		(volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
    88. 

  88. #define IOP3XX_OCCDR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
    89. 

  89. #define IOP3XX_PDSCR		(volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
    90. 

  90. #define IOP3XX_PMCAPID		(volatile u8  *)IOP3XX_REG_ADDR(0x01c0)
    91. 

  91. #define IOP3XX_PMNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01c1)
    92. 

  92. #define IOP3XX_APMCR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
    93. 

  93. #define IOP3XX_APMCSR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
    94. 

  94. #define IOP3XX_PCIXCAPID	(volatile u8  *)IOP3XX_REG_ADDR(0x01e0)
    95. 

  95. #define IOP3XX_PCIXNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01e1)
    96. 

  96. #define IOP3XX_PCIXCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
    97. 

  97. #define IOP3XX_PCIXSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
    98. 

  98. #define IOP3XX_PCIIRSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
    99. 

  99. 

  100. /* Messaging Unit  */
    101. 

  101. #define IOP3XX_IMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0310)
    102. 

  102. #define IOP3XX_IMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0314)
    103. 

  103. #define IOP3XX_OMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0318)
    104. 

  104. #define IOP3XX_OMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x031c)
    105. 

  105. #define IOP3XX_IDR		(volatile u32 *)IOP3XX_REG_ADDR(0x0320)
    106. 

  106. #define IOP3XX_IISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0324)
    107. 

  107. #define IOP3XX_IIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0328)
    108. 

  108. #define IOP3XX_ODR		(volatile u32 *)IOP3XX_REG_ADDR(0x032c)
    109. 

  109. #define IOP3XX_OISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0330)
    110. 

  110. #define IOP3XX_OIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0334)
    111. 

  111. #define IOP3XX_MUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0350)
    112. 

  112. #define IOP3XX_QBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0354)
    113. 

  113. #define IOP3XX_IFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0360)
    114. 

  114. #define IOP3XX_IFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0364)
    115. 

  115. #define IOP3XX_IPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0368)
    116. 

  116. #define IOP3XX_IPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x036c)
    117. 

  117. #define IOP3XX_OFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0370)
    118. 

  118. #define IOP3XX_OFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0374)
    119. 

  119. #define IOP3XX_OPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0378)
    120. 

  120. #define IOP3XX_OPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x037c)
    121. 

  121. #define IOP3XX_IAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0380)
    122. 

  122. 

  123. /* DMA Controller  */
    124. 

  124. #define IOP3XX_DMA0_CCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0400)
    125. 

  125. #define IOP3XX_DMA0_CSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0404)
    126. 

  126. #define IOP3XX_DMA0_DAR		(volatile u32 *)IOP3XX_REG_ADDR(0x040c)
    127. 

  127. #define IOP3XX_DMA0_NDAR	(volatile u32 *)IOP3XX_REG_ADDR(0x0410)
    128. 

  128. #define IOP3XX_DMA0_PADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0414)
    129. 

  129. #define IOP3XX_DMA0_PUADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0418)
    130. 

  130. #define IOP3XX_DMA0_LADR	(volatile u32 *)IOP3XX_REG_ADDR(0x041c)
    131. 

  131. #define IOP3XX_DMA0_BCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0420)
    132. 

  132. #define IOP3XX_DMA0_DCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0424)
    133. 

  133. #define IOP3XX_DMA1_CCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0440)
    134. 

  134. #define IOP3XX_DMA1_CSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0444)
    135. 

  135. #define IOP3XX_DMA1_DAR		(volatile u32 *)IOP3XX_REG_ADDR(0x044c)
    136. 

  136. #define IOP3XX_DMA1_NDAR	(volatile u32 *)IOP3XX_REG_ADDR(0x0450)
    137. 

  137. #define IOP3XX_DMA1_PADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0454)
    138. 

  138. #define IOP3XX_DMA1_PUADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0458)
    139. 

  139. #define IOP3XX_DMA1_LADR	(volatile u32 *)IOP3XX_REG_ADDR(0x045c)
    140. 

  140. #define IOP3XX_DMA1_BCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0460)
    141. 

  141. #define IOP3XX_DMA1_DCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0464)
    142. 

  142. 

  143. /* Peripheral bus interface  */
    144. 

  144. #define IOP3XX_PBCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0680)
    145. 

  145. #define IOP3XX_PBISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0684)
    146. 

  146. #define IOP3XX_PBBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0688)
    147. 

  147. #define IOP3XX_PBLR0		(volatile u32 *)IOP3XX_REG_ADDR(0x068c)
    148. 

  148. #define IOP3XX_PBBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0690)
    149. 

  149. #define IOP3XX_PBLR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0694)
    150. 

  150. #define IOP3XX_PBBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0698)
    151. 

  151. #define IOP3XX_PBLR2		(volatile u32 *)IOP3XX_REG_ADDR(0x069c)
    152. 

  152. #define IOP3XX_PBBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
    153. 

  153. #define IOP3XX_PBLR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
    154. 

  154. #define IOP3XX_PBBAR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
    155. 

  155. #define IOP3XX_PBLR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
    156. 

  156. #define IOP3XX_PBBAR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
    157. 

  157. #define IOP3XX_PBLR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
    158. 

  158. #define IOP3XX_PMBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
    159. 

  159. #define IOP3XX_PMBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
    160. 

  160. #define IOP3XX_PMBR2		(volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
    161. 

  161. 

  162. /* Peripheral performance monitoring unit  */
    163. 

  163. #define IOP3XX_GTMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0700)
    164. 

  164. #define IOP3XX_ESR		(volatile u32 *)IOP3XX_REG_ADDR(0x0704)
    165. 

  165. #define IOP3XX_EMISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0708)
    166. 

  166. #define IOP3XX_GTSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)
    167. 

  167. /* PERCR0 DOESN'T EXIST - index from 1! */
    168. 

  168. #define IOP3XX_PERCR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)
    169. 

  169. 

  170. /* General Purpose I/O  */
    171. 

  171. #define IOP3XX_GPOE		(volatile u32 *)IOP3XX_GPIO_REG(0x0004)
    172. 

  172. #define IOP3XX_GPID		(volatile u32 *)IOP3XX_GPIO_REG(0x0008)
    173. 

  173. #define IOP3XX_GPOD		(volatile u32 *)IOP3XX_GPIO_REG(0x000c)
    174. 

  174. 

  175. /* Timers  */
    176. 

  176. #define IOP3XX_TU_TMR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0000)
    177. 

  177. #define IOP3XX_TU_TMR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0004)
    178. 

  178. #define IOP3XX_TU_TCR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0008)
    179. 

  179. #define IOP3XX_TU_TCR1		(volatile u32 *)IOP3XX_TIMER_REG(0x000c)
    180. 

  180. #define IOP3XX_TU_TRR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0010)
    181. 

  181. #define IOP3XX_TU_TRR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0014)
    182. 

  182. #define IOP3XX_TU_TISR		(volatile u32 *)IOP3XX_TIMER_REG(0x0018)
    183. 

  183. #define IOP3XX_TU_WDTCR		(volatile u32 *)IOP3XX_TIMER_REG(0x001c)
    184. 

  184. #define IOP3XX_TMR_TC		0x01
    185. 

  185. #define IOP3XX_TMR_EN		0x02
    186. 

  186. #define IOP3XX_TMR_RELOAD	0x04
    187. 

  187. #define IOP3XX_TMR_PRIVILEGED	0x09
    188. 

  188. #define IOP3XX_TMR_RATIO_1_1	0x00
    189. 

  189. #define IOP3XX_TMR_RATIO_4_1	0x10
    190. 

  190. #define IOP3XX_TMR_RATIO_8_1	0x20
    191. 

  191. #define IOP3XX_TMR_RATIO_16_1	0x30
    192. 

  192. 

  193. /* Application accelerator unit  */
    194. 

  194. #define IOP3XX_AAU_ACR		(volatile u32 *)IOP3XX_REG_ADDR(0x0800)
    195. 

  195. #define IOP3XX_AAU_ASR		(volatile u32 *)IOP3XX_REG_ADDR(0x0804)
    196. 

  196. #define IOP3XX_AAU_ADAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0808)
    197. 

  197. #define IOP3XX_AAU_ANDAR	(volatile u32 *)IOP3XX_REG_ADDR(0x080c)
    198. 

  198. #define IOP3XX_AAU_SAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0810)
    199. 

  199. #define IOP3XX_AAU_SAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0814)
    200. 

  200. #define IOP3XX_AAU_SAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0818)
    201. 

  201. #define IOP3XX_AAU_SAR4		(volatile u32 *)IOP3XX_REG_ADDR(0x081c)
    202. 

  202. #define IOP3XX_AAU_DAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0820)
    203. 

  203. #define IOP3XX_AAU_ABCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0824)
    204. 

  204. #define IOP3XX_AAU_ADCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0828)
    205. 

  205. #define IOP3XX_AAU_SAR5		(volatile u32 *)IOP3XX_REG_ADDR(0x082c)
    206. 

  206. #define IOP3XX_AAU_SAR6		(volatile u32 *)IOP3XX_REG_ADDR(0x0830)
    207. 

  207. #define IOP3XX_AAU_SAR7		(volatile u32 *)IOP3XX_REG_ADDR(0x0834)
    208. 

  208. #define IOP3XX_AAU_SAR8		(volatile u32 *)IOP3XX_REG_ADDR(0x0838)
    209. 

  209. #define IOP3XX_AAU_EDCR0	(volatile u32 *)IOP3XX_REG_ADDR(0x083c)
    210. 

  210. #define IOP3XX_AAU_SAR9		(volatile u32 *)IOP3XX_REG_ADDR(0x0840)
    211. 

  211. #define IOP3XX_AAU_SAR10	(volatile u32 *)IOP3XX_REG_ADDR(0x0844)
    212. 

  212. #define IOP3XX_AAU_SAR11	(volatile u32 *)IOP3XX_REG_ADDR(0x0848)
    213. 

  213. #define IOP3XX_AAU_SAR12	(volatile u32 *)IOP3XX_REG_ADDR(0x084c)
    214. 

  214. #define IOP3XX_AAU_SAR13	(volatile u32 *)IOP3XX_REG_ADDR(0x0850)
    215. 

  215. #define IOP3XX_AAU_SAR14	(volatile u32 *)IOP3XX_REG_ADDR(0x0854)
    216. 

  216. #define IOP3XX_AAU_SAR15	(volatile u32 *)IOP3XX_REG_ADDR(0x0858)
    217. 

  217. #define IOP3XX_AAU_SAR16	(volatile u32 *)IOP3XX_REG_ADDR(0x085c)
    218. 

  218. #define IOP3XX_AAU_EDCR1	(volatile u32 *)IOP3XX_REG_ADDR(0x0860)
    219. 

  219. #define IOP3XX_AAU_SAR17	(volatile u32 *)IOP3XX_REG_ADDR(0x0864)
    220. 

  220. #define IOP3XX_AAU_SAR18	(volatile u32 *)IOP3XX_REG_ADDR(0x0868)
    221. 

  221. #define IOP3XX_AAU_SAR19	(volatile u32 *)IOP3XX_REG_ADDR(0x086c)
    222. 

  222. #define IOP3XX_AAU_SAR20	(volatile u32 *)IOP3XX_REG_ADDR(0x0870)
    223. 

  223. #define IOP3XX_AAU_SAR21	(volatile u32 *)IOP3XX_REG_ADDR(0x0874)
    224. 

  224. #define IOP3XX_AAU_SAR22	(volatile u32 *)IOP3XX_REG_ADDR(0x0878)
    225. 

  225. #define IOP3XX_AAU_SAR23	(volatile u32 *)IOP3XX_REG_ADDR(0x087c)
    226. 

  226. #define IOP3XX_AAU_SAR24	(volatile u32 *)IOP3XX_REG_ADDR(0x0880)
    227. 

  227. #define IOP3XX_AAU_EDCR2	(volatile u32 *)IOP3XX_REG_ADDR(0x0884)
    228. 

  228. #define IOP3XX_AAU_SAR25	(volatile u32 *)IOP3XX_REG_ADDR(0x0888)
    229. 

  229. #define IOP3XX_AAU_SAR26	(volatile u32 *)IOP3XX_REG_ADDR(0x088c)
    230. 

  230. #define IOP3XX_AAU_SAR27	(volatile u32 *)IOP3XX_REG_ADDR(0x0890)
    231. 

  231. #define IOP3XX_AAU_SAR28	(volatile u32 *)IOP3XX_REG_ADDR(0x0894)
    232. 

  232. #define IOP3XX_AAU_SAR29	(volatile u32 *)IOP3XX_REG_ADDR(0x0898)
    233. 

  233. #define IOP3XX_AAU_SAR30	(volatile u32 *)IOP3XX_REG_ADDR(0x089c)
    234. 

  234. #define IOP3XX_AAU_SAR31	(volatile u32 *)IOP3XX_REG_ADDR(0x08a0)
    235. 

  235. #define IOP3XX_AAU_SAR32	(volatile u32 *)IOP3XX_REG_ADDR(0x08a4)
    236. 

  236. 

  237. /* I2C bus interface unit  */
    238. 

  238. #define IOP3XX_ICR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1680)
    239. 

  239. #define IOP3XX_ISR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1684)
    240. 

  240. #define IOP3XX_ISAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1688)
    241. 

  241. #define IOP3XX_IDBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x168c)
    242. 

  242. #define IOP3XX_IBMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1694)
    243. 

  243. #define IOP3XX_ICR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
    244. 

  244. #define IOP3XX_ISR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
    245. 

  245. #define IOP3XX_ISAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
    246. 

  246. #define IOP3XX_IDBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
    247. 

  247. #define IOP3XX_IBMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
    248. 

  248. 

  249. 

  250. /*
    251. 

  251.  * IOP3XX I/O and Mem space regions for PCI autoconfiguration
    252. 

  252.  */
    253. 

  253. #define IOP3XX_PCI_MEM_WINDOW_SIZE	0x04000000
    254. 

  254. #define IOP3XX_PCI_LOWER_MEM_PA		0x80000000
    255. 

  255. #define IOP3XX_PCI_LOWER_MEM_BA		(*IOP3XX_OMWTVR0)
    256. 

  256. 

  257. #define IOP3XX_PCI_IO_WINDOW_SIZE	0x00010000
    258. 

  258. #define IOP3XX_PCI_LOWER_IO_PA		0x90000000
    259. 

  259. #define IOP3XX_PCI_LOWER_IO_VA		0xfe000000
    260. 

  260. #define IOP3XX_PCI_LOWER_IO_BA		(*IOP3XX_OIOWTVR)
    261. 

  261. 

  262. 

  263. #ifndef __ASSEMBLY__
    264. 

  264. void iop3xx_map_io(void);
    265. 

  265. void iop3xx_init_time(unsigned long);
    266. 

  266. unsigned long iop3xx_gettimeoffset(void);
    267. 

  267. 

  268. extern struct platform_device iop3xx_i2c0_device;
    269. 

  269. extern struct platform_device iop3xx_i2c1_device;
    270. 

  270. 

  271. extern inline void iop3xx_cp6_enable(void)
    272. 

  272. {
    273. 

  273. 	u32 temp;
    274. 

  274. 

  275. 	asm volatile (
    276. 

  276. 		"mrc	p15, 0, %0, c15, c1, 0\n\t"
    277. 

  277. 		"orr	%0, %0, #(1 << 6)\n\t"
    278. 

  278. 		"mcr	p15, 0, %0, c15, c1, 0\n\t"
    279. 

  279. 		"mrc	p15, 0, %0, c15, c1, 0\n\t"
    280. 

  280. 		"mov	%0, %0\n\t"
    281. 

  281. 		"sub	pc, pc, #4\n\t"
    282. 

  282. 		: "=r" (temp) );
    283. 

  283. }
    284. 

  284. 

  285. extern inline void iop3xx_cp6_disable(void)
    286. 

  286. {
    287. 

  287. 	u32 temp;
    288. 

  288. 

  289. 	asm volatile (
    290. 

  290. 		"mrc	p15, 0, %0, c15, c1, 0\n\t"
    291. 

  291. 		"bic	%0, %0, #(1 << 6)\n\t"
    292. 

  292. 		"mcr	p15, 0, %0, c15, c1, 0\n\t"
    293. 

  293. 		"mrc	p15, 0, %0, c15, c1, 0\n\t"
    294. 

  294. 		"mov	%0, %0\n\t"
    295. 

  295. 		"sub	pc, pc, #4\n\t"
    296. 

  296. 		: "=r" (temp) );
    297. 

  297. }
    298. 

  298. #endif
    299. 

  299. 

  300. 

  301. #endif
    302.