spi_s3c24xx.c 9.5 KB

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  1. /* linux/drivers/spi/spi_s3c24xx.c
  2. *
  3. * Copyright (c) 2006 Ben Dooks
  4. * Copyright (c) 2006 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. */
  12. //#define DEBUG
  13. #include <linux/config.h>
  14. #include <linux/init.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/workqueue.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <linux/err.h>
  21. #include <linux/clk.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/spi/spi.h>
  24. #include <linux/spi/spi_bitbang.h>
  25. #include <asm/io.h>
  26. #include <asm/dma.h>
  27. #include <asm/hardware.h>
  28. #include <asm/arch/regs-gpio.h>
  29. #include <asm/arch/regs-spi.h>
  30. #include <asm/arch/spi.h>
  31. struct s3c24xx_spi {
  32. /* bitbang has to be first */
  33. struct spi_bitbang bitbang;
  34. struct completion done;
  35. void __iomem *regs;
  36. int irq;
  37. int len;
  38. int count;
  39. /* data buffers */
  40. const unsigned char *tx;
  41. unsigned char *rx;
  42. struct clk *clk;
  43. struct resource *ioarea;
  44. struct spi_master *master;
  45. struct spi_device *curdev;
  46. struct device *dev;
  47. struct s3c2410_spi_info *pdata;
  48. };
  49. #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
  50. #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
  51. static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
  52. {
  53. return spi_master_get_devdata(sdev->master);
  54. }
  55. static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
  56. {
  57. struct s3c24xx_spi *hw = to_hw(spi);
  58. unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
  59. unsigned int spcon;
  60. switch (value) {
  61. case BITBANG_CS_INACTIVE:
  62. if (hw->pdata->set_cs)
  63. hw->pdata->set_cs(hw->pdata, value, cspol);
  64. else
  65. s3c2410_gpio_setpin(hw->pdata->pin_cs, cspol ^ 1);
  66. break;
  67. case BITBANG_CS_ACTIVE:
  68. spcon = readb(hw->regs + S3C2410_SPCON);
  69. if (spi->mode & SPI_CPHA)
  70. spcon |= S3C2410_SPCON_CPHA_FMTB;
  71. else
  72. spcon &= ~S3C2410_SPCON_CPHA_FMTB;
  73. if (spi->mode & SPI_CPOL)
  74. spcon |= S3C2410_SPCON_CPOL_HIGH;
  75. else
  76. spcon &= ~S3C2410_SPCON_CPOL_HIGH;
  77. spcon |= S3C2410_SPCON_ENSCK;
  78. /* write new configration */
  79. writeb(spcon, hw->regs + S3C2410_SPCON);
  80. if (hw->pdata->set_cs)
  81. hw->pdata->set_cs(hw->pdata, value, cspol);
  82. else
  83. s3c2410_gpio_setpin(hw->pdata->pin_cs, cspol);
  84. break;
  85. }
  86. }
  87. static int s3c24xx_spi_setupxfer(struct spi_device *spi,
  88. struct spi_transfer *t)
  89. {
  90. struct s3c24xx_spi *hw = to_hw(spi);
  91. unsigned int bpw;
  92. unsigned int hz;
  93. unsigned int div;
  94. bpw = t ? t->bits_per_word : spi->bits_per_word;
  95. hz = t ? t->speed_hz : spi->max_speed_hz;
  96. if (bpw != 8) {
  97. dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
  98. return -EINVAL;
  99. }
  100. div = clk_get_rate(hw->clk) / hz;
  101. /* is clk = pclk / (2 * (pre+1)), or is it
  102. * clk = (pclk * 2) / ( pre + 1) */
  103. div = (div / 2) - 1;
  104. if (div < 0)
  105. div = 1;
  106. if (div > 255)
  107. div = 255;
  108. dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
  109. writeb(div, hw->regs + S3C2410_SPPRE);
  110. spin_lock(&hw->bitbang.lock);
  111. if (!hw->bitbang.busy) {
  112. hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
  113. /* need to ndelay for 0.5 clocktick ? */
  114. }
  115. spin_unlock(&hw->bitbang.lock);
  116. return 0;
  117. }
  118. static int s3c24xx_spi_setup(struct spi_device *spi)
  119. {
  120. int ret;
  121. if (!spi->bits_per_word)
  122. spi->bits_per_word = 8;
  123. if ((spi->mode & SPI_LSB_FIRST) != 0)
  124. return -EINVAL;
  125. ret = s3c24xx_spi_setupxfer(spi, NULL);
  126. if (ret < 0) {
  127. dev_err(&spi->dev, "setupxfer returned %d\n", ret);
  128. return ret;
  129. }
  130. dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
  131. __FUNCTION__, spi->mode, spi->bits_per_word,
  132. spi->max_speed_hz);
  133. return 0;
  134. }
  135. static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
  136. {
  137. return hw->tx ? hw->tx[count] : 0xff;
  138. }
  139. static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  140. {
  141. struct s3c24xx_spi *hw = to_hw(spi);
  142. dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
  143. t->tx_buf, t->rx_buf, t->len);
  144. hw->tx = t->tx_buf;
  145. hw->rx = t->rx_buf;
  146. hw->len = t->len;
  147. hw->count = 0;
  148. /* send the first byte */
  149. writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
  150. wait_for_completion(&hw->done);
  151. return hw->count;
  152. }
  153. static irqreturn_t s3c24xx_spi_irq(int irq, void *dev, struct pt_regs *regs)
  154. {
  155. struct s3c24xx_spi *hw = dev;
  156. unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
  157. unsigned int count = hw->count;
  158. if (spsta & S3C2410_SPSTA_DCOL) {
  159. dev_dbg(hw->dev, "data-collision\n");
  160. complete(&hw->done);
  161. goto irq_done;
  162. }
  163. if (!(spsta & S3C2410_SPSTA_READY)) {
  164. dev_dbg(hw->dev, "spi not ready for tx?\n");
  165. complete(&hw->done);
  166. goto irq_done;
  167. }
  168. hw->count++;
  169. if (hw->rx)
  170. hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
  171. count++;
  172. if (count < hw->len)
  173. writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
  174. else
  175. complete(&hw->done);
  176. irq_done:
  177. return IRQ_HANDLED;
  178. }
  179. static int s3c24xx_spi_probe(struct platform_device *pdev)
  180. {
  181. struct s3c24xx_spi *hw;
  182. struct spi_master *master;
  183. struct spi_board_info *bi;
  184. struct resource *res;
  185. int err = 0;
  186. int i;
  187. master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
  188. if (master == NULL) {
  189. dev_err(&pdev->dev, "No memory for spi_master\n");
  190. err = -ENOMEM;
  191. goto err_nomem;
  192. }
  193. hw = spi_master_get_devdata(master);
  194. memset(hw, 0, sizeof(struct s3c24xx_spi));
  195. hw->master = spi_master_get(master);
  196. hw->pdata = pdev->dev.platform_data;
  197. hw->dev = &pdev->dev;
  198. if (hw->pdata == NULL) {
  199. dev_err(&pdev->dev, "No platform data supplied\n");
  200. err = -ENOENT;
  201. goto err_no_pdata;
  202. }
  203. platform_set_drvdata(pdev, hw);
  204. init_completion(&hw->done);
  205. /* setup the state for the bitbang driver */
  206. hw->bitbang.master = hw->master;
  207. hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
  208. hw->bitbang.chipselect = s3c24xx_spi_chipsel;
  209. hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
  210. hw->bitbang.master->setup = s3c24xx_spi_setup;
  211. dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
  212. /* find and map our resources */
  213. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  214. if (res == NULL) {
  215. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  216. err = -ENOENT;
  217. goto err_no_iores;
  218. }
  219. hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
  220. pdev->name);
  221. if (hw->ioarea == NULL) {
  222. dev_err(&pdev->dev, "Cannot reserve region\n");
  223. err = -ENXIO;
  224. goto err_no_iores;
  225. }
  226. hw->regs = ioremap(res->start, (res->end - res->start)+1);
  227. if (hw->regs == NULL) {
  228. dev_err(&pdev->dev, "Cannot map IO\n");
  229. err = -ENXIO;
  230. goto err_no_iomap;
  231. }
  232. hw->irq = platform_get_irq(pdev, 0);
  233. if (hw->irq < 0) {
  234. dev_err(&pdev->dev, "No IRQ specified\n");
  235. err = -ENOENT;
  236. goto err_no_irq;
  237. }
  238. err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
  239. if (err) {
  240. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  241. goto err_no_irq;
  242. }
  243. hw->clk = clk_get(&pdev->dev, "spi");
  244. if (IS_ERR(hw->clk)) {
  245. dev_err(&pdev->dev, "No clock for device\n");
  246. err = PTR_ERR(hw->clk);
  247. goto err_no_clk;
  248. }
  249. /* for the moment, permanently enable the clock */
  250. clk_enable(hw->clk);
  251. /* program defaults into the registers */
  252. writeb(0xff, hw->regs + S3C2410_SPPRE);
  253. writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
  254. writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
  255. /* setup any gpio we can */
  256. if (!hw->pdata->set_cs) {
  257. s3c2410_gpio_setpin(hw->pdata->pin_cs, 1);
  258. s3c2410_gpio_cfgpin(hw->pdata->pin_cs, S3C2410_GPIO_OUTPUT);
  259. }
  260. /* register our spi controller */
  261. err = spi_bitbang_start(&hw->bitbang);
  262. if (err) {
  263. dev_err(&pdev->dev, "Failed to register SPI master\n");
  264. goto err_register;
  265. }
  266. dev_dbg(hw->dev, "shutdown=%d\n", hw->bitbang.shutdown);
  267. /* register all the devices associated */
  268. bi = &hw->pdata->board_info[0];
  269. for (i = 0; i < hw->pdata->board_size; i++, bi++) {
  270. dev_info(hw->dev, "registering %s\n", bi->modalias);
  271. bi->controller_data = hw;
  272. spi_new_device(master, bi);
  273. }
  274. return 0;
  275. err_register:
  276. clk_disable(hw->clk);
  277. clk_put(hw->clk);
  278. err_no_clk:
  279. free_irq(hw->irq, hw);
  280. err_no_irq:
  281. iounmap(hw->regs);
  282. err_no_iomap:
  283. release_resource(hw->ioarea);
  284. kfree(hw->ioarea);
  285. err_no_iores:
  286. err_no_pdata:
  287. spi_master_put(hw->master);;
  288. err_nomem:
  289. return err;
  290. }
  291. static int s3c24xx_spi_remove(struct platform_device *dev)
  292. {
  293. struct s3c24xx_spi *hw = platform_get_drvdata(dev);
  294. platform_set_drvdata(dev, NULL);
  295. spi_unregister_master(hw->master);
  296. clk_disable(hw->clk);
  297. clk_put(hw->clk);
  298. free_irq(hw->irq, hw);
  299. iounmap(hw->regs);
  300. release_resource(hw->ioarea);
  301. kfree(hw->ioarea);
  302. spi_master_put(hw->master);
  303. return 0;
  304. }
  305. #ifdef CONFIG_PM
  306. static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
  307. {
  308. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  309. clk_disable(hw->clk);
  310. return 0;
  311. }
  312. static int s3c24xx_spi_resume(struct platform_device *pdev)
  313. {
  314. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  315. clk_enable(hw->clk);
  316. return 0;
  317. }
  318. #else
  319. #define s3c24xx_spi_suspend NULL
  320. #define s3c24xx_spi_resume NULL
  321. #endif
  322. static struct platform_driver s3c24xx_spidrv = {
  323. .probe = s3c24xx_spi_probe,
  324. .remove = s3c24xx_spi_remove,
  325. .suspend = s3c24xx_spi_suspend,
  326. .resume = s3c24xx_spi_resume,
  327. .driver = {
  328. .name = "s3c2410-spi",
  329. .owner = THIS_MODULE,
  330. },
  331. };
  332. static int __init s3c24xx_spi_init(void)
  333. {
  334. return platform_driver_register(&s3c24xx_spidrv);
  335. }
  336. static void __exit s3c24xx_spi_exit(void)
  337. {
  338. platform_driver_unregister(&s3c24xx_spidrv);
  339. }
  340. module_init(s3c24xx_spi_init);
  341. module_exit(s3c24xx_spi_exit);
  342. MODULE_DESCRIPTION("S3C24XX SPI Driver");
  343. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  344. MODULE_LICENSE("GPL");