sdhci.c 36 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/highmem.h>
  12. #include <linux/pci.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/mmc/protocol.h>
  16. #include <asm/scatterlist.h>
  17. #include "sdhci.h"
  18. #define DRIVER_NAME "sdhci"
  19. #define DRIVER_VERSION "0.12"
  20. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  21. #define DBG(f, x...) \
  22. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  23. static unsigned int debug_nodma = 0;
  24. static unsigned int debug_forcedma = 0;
  25. static unsigned int debug_quirks = 0;
  26. #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
  27. #define SDHCI_QUIRK_FORCE_DMA (1<<1)
  28. static const struct pci_device_id pci_ids[] __devinitdata = {
  29. {
  30. .vendor = PCI_VENDOR_ID_RICOH,
  31. .device = PCI_DEVICE_ID_RICOH_R5C822,
  32. .subvendor = PCI_VENDOR_ID_IBM,
  33. .subdevice = PCI_ANY_ID,
  34. .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  35. SDHCI_QUIRK_FORCE_DMA,
  36. },
  37. {
  38. .vendor = PCI_VENDOR_ID_RICOH,
  39. .device = PCI_DEVICE_ID_RICOH_R5C822,
  40. .subvendor = PCI_ANY_ID,
  41. .subdevice = PCI_ANY_ID,
  42. .driver_data = SDHCI_QUIRK_FORCE_DMA,
  43. },
  44. {
  45. .vendor = PCI_VENDOR_ID_TI,
  46. .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
  47. .subvendor = PCI_ANY_ID,
  48. .subdevice = PCI_ANY_ID,
  49. .driver_data = SDHCI_QUIRK_FORCE_DMA,
  50. },
  51. { /* Generic SD host controller */
  52. PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
  53. },
  54. { /* end: all zeroes */ },
  55. };
  56. MODULE_DEVICE_TABLE(pci, pci_ids);
  57. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  58. static void sdhci_finish_data(struct sdhci_host *);
  59. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  60. static void sdhci_finish_command(struct sdhci_host *);
  61. static void sdhci_dumpregs(struct sdhci_host *host)
  62. {
  63. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  64. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  65. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  66. readw(host->ioaddr + SDHCI_HOST_VERSION));
  67. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  68. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  69. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  70. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  71. readl(host->ioaddr + SDHCI_ARGUMENT),
  72. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  73. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  74. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  75. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  76. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  77. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  78. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  79. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  80. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  81. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  82. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  83. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  84. readl(host->ioaddr + SDHCI_INT_STATUS));
  85. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  86. readl(host->ioaddr + SDHCI_INT_ENABLE),
  87. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  88. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  89. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  90. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  91. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  92. readl(host->ioaddr + SDHCI_CAPABILITIES),
  93. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  94. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  95. }
  96. /*****************************************************************************\
  97. * *
  98. * Low level functions *
  99. * *
  100. \*****************************************************************************/
  101. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  102. {
  103. unsigned long timeout;
  104. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  105. if (mask & SDHCI_RESET_ALL)
  106. host->clock = 0;
  107. /* Wait max 100 ms */
  108. timeout = 100;
  109. /* hw clears the bit when it's done */
  110. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  111. if (timeout == 0) {
  112. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  113. "Please report this to " BUGMAIL ".\n",
  114. mmc_hostname(host->mmc), (int)mask);
  115. sdhci_dumpregs(host);
  116. return;
  117. }
  118. timeout--;
  119. mdelay(1);
  120. }
  121. }
  122. static void sdhci_init(struct sdhci_host *host)
  123. {
  124. u32 intmask;
  125. sdhci_reset(host, SDHCI_RESET_ALL);
  126. intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
  127. SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
  128. SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
  129. SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
  130. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
  131. SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
  132. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  133. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  134. }
  135. static void sdhci_activate_led(struct sdhci_host *host)
  136. {
  137. u8 ctrl;
  138. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  139. ctrl |= SDHCI_CTRL_LED;
  140. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  141. }
  142. static void sdhci_deactivate_led(struct sdhci_host *host)
  143. {
  144. u8 ctrl;
  145. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  146. ctrl &= ~SDHCI_CTRL_LED;
  147. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  148. }
  149. /*****************************************************************************\
  150. * *
  151. * Core functions *
  152. * *
  153. \*****************************************************************************/
  154. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  155. {
  156. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  157. return host->mapped_sg + host->cur_sg->offset;
  158. }
  159. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  160. {
  161. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  162. }
  163. static inline int sdhci_next_sg(struct sdhci_host* host)
  164. {
  165. /*
  166. * Skip to next SG entry.
  167. */
  168. host->cur_sg++;
  169. host->num_sg--;
  170. /*
  171. * Any entries left?
  172. */
  173. if (host->num_sg > 0) {
  174. host->offset = 0;
  175. host->remain = host->cur_sg->length;
  176. }
  177. return host->num_sg;
  178. }
  179. static void sdhci_read_block_pio(struct sdhci_host *host)
  180. {
  181. int blksize, chunk_remain;
  182. u32 data;
  183. char *buffer;
  184. int size;
  185. DBG("PIO reading\n");
  186. blksize = host->data->blksz;
  187. chunk_remain = 0;
  188. data = 0;
  189. buffer = sdhci_kmap_sg(host) + host->offset;
  190. while (blksize) {
  191. if (chunk_remain == 0) {
  192. data = readl(host->ioaddr + SDHCI_BUFFER);
  193. chunk_remain = min(blksize, 4);
  194. }
  195. size = min(host->size, host->remain);
  196. size = min(size, chunk_remain);
  197. chunk_remain -= size;
  198. blksize -= size;
  199. host->offset += size;
  200. host->remain -= size;
  201. host->size -= size;
  202. while (size) {
  203. *buffer = data & 0xFF;
  204. buffer++;
  205. data >>= 8;
  206. size--;
  207. }
  208. if (host->remain == 0) {
  209. sdhci_kunmap_sg(host);
  210. if (sdhci_next_sg(host) == 0) {
  211. BUG_ON(blksize != 0);
  212. return;
  213. }
  214. buffer = sdhci_kmap_sg(host);
  215. }
  216. }
  217. sdhci_kunmap_sg(host);
  218. }
  219. static void sdhci_write_block_pio(struct sdhci_host *host)
  220. {
  221. int blksize, chunk_remain;
  222. u32 data;
  223. char *buffer;
  224. int bytes, size;
  225. DBG("PIO writing\n");
  226. blksize = host->data->blksz;
  227. chunk_remain = 4;
  228. data = 0;
  229. bytes = 0;
  230. buffer = sdhci_kmap_sg(host) + host->offset;
  231. while (blksize) {
  232. size = min(host->size, host->remain);
  233. size = min(size, chunk_remain);
  234. chunk_remain -= size;
  235. blksize -= size;
  236. host->offset += size;
  237. host->remain -= size;
  238. host->size -= size;
  239. while (size) {
  240. data >>= 8;
  241. data |= (u32)*buffer << 24;
  242. buffer++;
  243. size--;
  244. }
  245. if (chunk_remain == 0) {
  246. writel(data, host->ioaddr + SDHCI_BUFFER);
  247. chunk_remain = min(blksize, 4);
  248. }
  249. if (host->remain == 0) {
  250. sdhci_kunmap_sg(host);
  251. if (sdhci_next_sg(host) == 0) {
  252. BUG_ON(blksize != 0);
  253. return;
  254. }
  255. buffer = sdhci_kmap_sg(host);
  256. }
  257. }
  258. sdhci_kunmap_sg(host);
  259. }
  260. static void sdhci_transfer_pio(struct sdhci_host *host)
  261. {
  262. u32 mask;
  263. BUG_ON(!host->data);
  264. if (host->size == 0)
  265. return;
  266. if (host->data->flags & MMC_DATA_READ)
  267. mask = SDHCI_DATA_AVAILABLE;
  268. else
  269. mask = SDHCI_SPACE_AVAILABLE;
  270. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  271. if (host->data->flags & MMC_DATA_READ)
  272. sdhci_read_block_pio(host);
  273. else
  274. sdhci_write_block_pio(host);
  275. if (host->size == 0)
  276. break;
  277. BUG_ON(host->num_sg == 0);
  278. }
  279. DBG("PIO transfer complete.\n");
  280. }
  281. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  282. {
  283. u8 count;
  284. unsigned target_timeout, current_timeout;
  285. WARN_ON(host->data);
  286. if (data == NULL)
  287. return;
  288. DBG("blksz %04x blks %04x flags %08x\n",
  289. data->blksz, data->blocks, data->flags);
  290. DBG("tsac %d ms nsac %d clk\n",
  291. data->timeout_ns / 1000000, data->timeout_clks);
  292. /* Sanity checks */
  293. BUG_ON(data->blksz * data->blocks > 524288);
  294. BUG_ON(data->blksz > host->max_block);
  295. BUG_ON(data->blocks > 65535);
  296. /* timeout in us */
  297. target_timeout = data->timeout_ns / 1000 +
  298. data->timeout_clks / host->clock;
  299. /*
  300. * Figure out needed cycles.
  301. * We do this in steps in order to fit inside a 32 bit int.
  302. * The first step is the minimum timeout, which will have a
  303. * minimum resolution of 6 bits:
  304. * (1) 2^13*1000 > 2^22,
  305. * (2) host->timeout_clk < 2^16
  306. * =>
  307. * (1) / (2) > 2^6
  308. */
  309. count = 0;
  310. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  311. while (current_timeout < target_timeout) {
  312. count++;
  313. current_timeout <<= 1;
  314. if (count >= 0xF)
  315. break;
  316. }
  317. if (count >= 0xF) {
  318. printk(KERN_WARNING "%s: Too large timeout requested!\n",
  319. mmc_hostname(host->mmc));
  320. count = 0xE;
  321. }
  322. writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  323. if (host->flags & SDHCI_USE_DMA) {
  324. int count;
  325. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  326. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  327. BUG_ON(count != 1);
  328. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  329. } else {
  330. host->size = data->blksz * data->blocks;
  331. host->cur_sg = data->sg;
  332. host->num_sg = data->sg_len;
  333. host->offset = 0;
  334. host->remain = host->cur_sg->length;
  335. }
  336. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  337. writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
  338. host->ioaddr + SDHCI_BLOCK_SIZE);
  339. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  340. }
  341. static void sdhci_set_transfer_mode(struct sdhci_host *host,
  342. struct mmc_data *data)
  343. {
  344. u16 mode;
  345. WARN_ON(host->data);
  346. if (data == NULL)
  347. return;
  348. mode = SDHCI_TRNS_BLK_CNT_EN;
  349. if (data->blocks > 1)
  350. mode |= SDHCI_TRNS_MULTI;
  351. if (data->flags & MMC_DATA_READ)
  352. mode |= SDHCI_TRNS_READ;
  353. if (host->flags & SDHCI_USE_DMA)
  354. mode |= SDHCI_TRNS_DMA;
  355. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  356. }
  357. static void sdhci_finish_data(struct sdhci_host *host)
  358. {
  359. struct mmc_data *data;
  360. u16 blocks;
  361. BUG_ON(!host->data);
  362. data = host->data;
  363. host->data = NULL;
  364. if (host->flags & SDHCI_USE_DMA) {
  365. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  366. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  367. }
  368. /*
  369. * Controller doesn't count down when in single block mode.
  370. */
  371. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  372. blocks = 0;
  373. else
  374. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  375. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  376. if ((data->error == MMC_ERR_NONE) && blocks) {
  377. printk(KERN_ERR "%s: Controller signalled completion even "
  378. "though there were blocks left. Please report this "
  379. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  380. data->error = MMC_ERR_FAILED;
  381. } else if (host->size != 0) {
  382. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  383. "Please report this to " BUGMAIL ".\n",
  384. mmc_hostname(host->mmc), host->size);
  385. data->error = MMC_ERR_FAILED;
  386. }
  387. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  388. if (data->stop) {
  389. /*
  390. * The controller needs a reset of internal state machines
  391. * upon error conditions.
  392. */
  393. if (data->error != MMC_ERR_NONE) {
  394. sdhci_reset(host, SDHCI_RESET_CMD);
  395. sdhci_reset(host, SDHCI_RESET_DATA);
  396. }
  397. sdhci_send_command(host, data->stop);
  398. } else
  399. tasklet_schedule(&host->finish_tasklet);
  400. }
  401. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  402. {
  403. int flags;
  404. u32 mask;
  405. unsigned long timeout;
  406. WARN_ON(host->cmd);
  407. DBG("Sending cmd (%x)\n", cmd->opcode);
  408. /* Wait max 10 ms */
  409. timeout = 10;
  410. mask = SDHCI_CMD_INHIBIT;
  411. if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
  412. mask |= SDHCI_DATA_INHIBIT;
  413. /* We shouldn't wait for data inihibit for stop commands, even
  414. though they might use busy signaling */
  415. if (host->mrq->data && (cmd == host->mrq->data->stop))
  416. mask &= ~SDHCI_DATA_INHIBIT;
  417. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  418. if (timeout == 0) {
  419. printk(KERN_ERR "%s: Controller never released "
  420. "inhibit bit(s). Please report this to "
  421. BUGMAIL ".\n", mmc_hostname(host->mmc));
  422. sdhci_dumpregs(host);
  423. cmd->error = MMC_ERR_FAILED;
  424. tasklet_schedule(&host->finish_tasklet);
  425. return;
  426. }
  427. timeout--;
  428. mdelay(1);
  429. }
  430. mod_timer(&host->timer, jiffies + 10 * HZ);
  431. host->cmd = cmd;
  432. sdhci_prepare_data(host, cmd->data);
  433. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  434. sdhci_set_transfer_mode(host, cmd->data);
  435. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  436. printk(KERN_ERR "%s: Unsupported response type! "
  437. "Please report this to " BUGMAIL ".\n",
  438. mmc_hostname(host->mmc));
  439. cmd->error = MMC_ERR_INVALID;
  440. tasklet_schedule(&host->finish_tasklet);
  441. return;
  442. }
  443. if (!(cmd->flags & MMC_RSP_PRESENT))
  444. flags = SDHCI_CMD_RESP_NONE;
  445. else if (cmd->flags & MMC_RSP_136)
  446. flags = SDHCI_CMD_RESP_LONG;
  447. else if (cmd->flags & MMC_RSP_BUSY)
  448. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  449. else
  450. flags = SDHCI_CMD_RESP_SHORT;
  451. if (cmd->flags & MMC_RSP_CRC)
  452. flags |= SDHCI_CMD_CRC;
  453. if (cmd->flags & MMC_RSP_OPCODE)
  454. flags |= SDHCI_CMD_INDEX;
  455. if (cmd->data)
  456. flags |= SDHCI_CMD_DATA;
  457. writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
  458. host->ioaddr + SDHCI_COMMAND);
  459. }
  460. static void sdhci_finish_command(struct sdhci_host *host)
  461. {
  462. int i;
  463. BUG_ON(host->cmd == NULL);
  464. if (host->cmd->flags & MMC_RSP_PRESENT) {
  465. if (host->cmd->flags & MMC_RSP_136) {
  466. /* CRC is stripped so we need to do some shifting. */
  467. for (i = 0;i < 4;i++) {
  468. host->cmd->resp[i] = readl(host->ioaddr +
  469. SDHCI_RESPONSE + (3-i)*4) << 8;
  470. if (i != 3)
  471. host->cmd->resp[i] |=
  472. readb(host->ioaddr +
  473. SDHCI_RESPONSE + (3-i)*4-1);
  474. }
  475. } else {
  476. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  477. }
  478. }
  479. host->cmd->error = MMC_ERR_NONE;
  480. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  481. if (host->cmd->data)
  482. host->data = host->cmd->data;
  483. else
  484. tasklet_schedule(&host->finish_tasklet);
  485. host->cmd = NULL;
  486. }
  487. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  488. {
  489. int div;
  490. u16 clk;
  491. unsigned long timeout;
  492. if (clock == host->clock)
  493. return;
  494. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  495. if (clock == 0)
  496. goto out;
  497. for (div = 1;div < 256;div *= 2) {
  498. if ((host->max_clk / div) <= clock)
  499. break;
  500. }
  501. div >>= 1;
  502. clk = div << SDHCI_DIVIDER_SHIFT;
  503. clk |= SDHCI_CLOCK_INT_EN;
  504. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  505. /* Wait max 10 ms */
  506. timeout = 10;
  507. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  508. & SDHCI_CLOCK_INT_STABLE)) {
  509. if (timeout == 0) {
  510. printk(KERN_ERR "%s: Internal clock never stabilised. "
  511. "Please report this to " BUGMAIL ".\n",
  512. mmc_hostname(host->mmc));
  513. sdhci_dumpregs(host);
  514. return;
  515. }
  516. timeout--;
  517. mdelay(1);
  518. }
  519. clk |= SDHCI_CLOCK_CARD_EN;
  520. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  521. out:
  522. host->clock = clock;
  523. }
  524. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  525. {
  526. u8 pwr;
  527. if (host->power == power)
  528. return;
  529. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  530. if (power == (unsigned short)-1)
  531. goto out;
  532. pwr = SDHCI_POWER_ON;
  533. switch (power) {
  534. case MMC_VDD_170:
  535. case MMC_VDD_180:
  536. case MMC_VDD_190:
  537. pwr |= SDHCI_POWER_180;
  538. break;
  539. case MMC_VDD_290:
  540. case MMC_VDD_300:
  541. case MMC_VDD_310:
  542. pwr |= SDHCI_POWER_300;
  543. break;
  544. case MMC_VDD_320:
  545. case MMC_VDD_330:
  546. case MMC_VDD_340:
  547. pwr |= SDHCI_POWER_330;
  548. break;
  549. default:
  550. BUG();
  551. }
  552. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  553. out:
  554. host->power = power;
  555. }
  556. /*****************************************************************************\
  557. * *
  558. * MMC callbacks *
  559. * *
  560. \*****************************************************************************/
  561. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  562. {
  563. struct sdhci_host *host;
  564. unsigned long flags;
  565. host = mmc_priv(mmc);
  566. spin_lock_irqsave(&host->lock, flags);
  567. WARN_ON(host->mrq != NULL);
  568. sdhci_activate_led(host);
  569. host->mrq = mrq;
  570. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  571. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  572. tasklet_schedule(&host->finish_tasklet);
  573. } else
  574. sdhci_send_command(host, mrq->cmd);
  575. spin_unlock_irqrestore(&host->lock, flags);
  576. }
  577. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  578. {
  579. struct sdhci_host *host;
  580. unsigned long flags;
  581. u8 ctrl;
  582. host = mmc_priv(mmc);
  583. spin_lock_irqsave(&host->lock, flags);
  584. /*
  585. * Reset the chip on each power off.
  586. * Should clear out any weird states.
  587. */
  588. if (ios->power_mode == MMC_POWER_OFF) {
  589. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  590. sdhci_init(host);
  591. }
  592. sdhci_set_clock(host, ios->clock);
  593. if (ios->power_mode == MMC_POWER_OFF)
  594. sdhci_set_power(host, -1);
  595. else
  596. sdhci_set_power(host, ios->vdd);
  597. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  598. if (ios->bus_width == MMC_BUS_WIDTH_4)
  599. ctrl |= SDHCI_CTRL_4BITBUS;
  600. else
  601. ctrl &= ~SDHCI_CTRL_4BITBUS;
  602. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  603. spin_unlock_irqrestore(&host->lock, flags);
  604. }
  605. static int sdhci_get_ro(struct mmc_host *mmc)
  606. {
  607. struct sdhci_host *host;
  608. unsigned long flags;
  609. int present;
  610. host = mmc_priv(mmc);
  611. spin_lock_irqsave(&host->lock, flags);
  612. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  613. spin_unlock_irqrestore(&host->lock, flags);
  614. return !(present & SDHCI_WRITE_PROTECT);
  615. }
  616. static struct mmc_host_ops sdhci_ops = {
  617. .request = sdhci_request,
  618. .set_ios = sdhci_set_ios,
  619. .get_ro = sdhci_get_ro,
  620. };
  621. /*****************************************************************************\
  622. * *
  623. * Tasklets *
  624. * *
  625. \*****************************************************************************/
  626. static void sdhci_tasklet_card(unsigned long param)
  627. {
  628. struct sdhci_host *host;
  629. unsigned long flags;
  630. host = (struct sdhci_host*)param;
  631. spin_lock_irqsave(&host->lock, flags);
  632. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  633. if (host->mrq) {
  634. printk(KERN_ERR "%s: Card removed during transfer!\n",
  635. mmc_hostname(host->mmc));
  636. printk(KERN_ERR "%s: Resetting controller.\n",
  637. mmc_hostname(host->mmc));
  638. sdhci_reset(host, SDHCI_RESET_CMD);
  639. sdhci_reset(host, SDHCI_RESET_DATA);
  640. host->mrq->cmd->error = MMC_ERR_FAILED;
  641. tasklet_schedule(&host->finish_tasklet);
  642. }
  643. }
  644. spin_unlock_irqrestore(&host->lock, flags);
  645. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  646. }
  647. static void sdhci_tasklet_finish(unsigned long param)
  648. {
  649. struct sdhci_host *host;
  650. unsigned long flags;
  651. struct mmc_request *mrq;
  652. host = (struct sdhci_host*)param;
  653. spin_lock_irqsave(&host->lock, flags);
  654. del_timer(&host->timer);
  655. mrq = host->mrq;
  656. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  657. /*
  658. * The controller needs a reset of internal state machines
  659. * upon error conditions.
  660. */
  661. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  662. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  663. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  664. /* Some controllers need this kick or reset won't work here */
  665. if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
  666. unsigned int clock;
  667. /* This is to force an update */
  668. clock = host->clock;
  669. host->clock = 0;
  670. sdhci_set_clock(host, clock);
  671. }
  672. /* Spec says we should do both at the same time, but Ricoh
  673. controllers do not like that. */
  674. sdhci_reset(host, SDHCI_RESET_CMD);
  675. sdhci_reset(host, SDHCI_RESET_DATA);
  676. }
  677. host->mrq = NULL;
  678. host->cmd = NULL;
  679. host->data = NULL;
  680. sdhci_deactivate_led(host);
  681. spin_unlock_irqrestore(&host->lock, flags);
  682. mmc_request_done(host->mmc, mrq);
  683. }
  684. static void sdhci_timeout_timer(unsigned long data)
  685. {
  686. struct sdhci_host *host;
  687. unsigned long flags;
  688. host = (struct sdhci_host*)data;
  689. spin_lock_irqsave(&host->lock, flags);
  690. if (host->mrq) {
  691. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  692. "Please report this to " BUGMAIL ".\n",
  693. mmc_hostname(host->mmc));
  694. sdhci_dumpregs(host);
  695. if (host->data) {
  696. host->data->error = MMC_ERR_TIMEOUT;
  697. sdhci_finish_data(host);
  698. } else {
  699. if (host->cmd)
  700. host->cmd->error = MMC_ERR_TIMEOUT;
  701. else
  702. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  703. tasklet_schedule(&host->finish_tasklet);
  704. }
  705. }
  706. spin_unlock_irqrestore(&host->lock, flags);
  707. }
  708. /*****************************************************************************\
  709. * *
  710. * Interrupt handling *
  711. * *
  712. \*****************************************************************************/
  713. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  714. {
  715. BUG_ON(intmask == 0);
  716. if (!host->cmd) {
  717. printk(KERN_ERR "%s: Got command interrupt even though no "
  718. "command operation was in progress.\n",
  719. mmc_hostname(host->mmc));
  720. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  721. mmc_hostname(host->mmc));
  722. sdhci_dumpregs(host);
  723. return;
  724. }
  725. if (intmask & SDHCI_INT_RESPONSE)
  726. sdhci_finish_command(host);
  727. else {
  728. if (intmask & SDHCI_INT_TIMEOUT)
  729. host->cmd->error = MMC_ERR_TIMEOUT;
  730. else if (intmask & SDHCI_INT_CRC)
  731. host->cmd->error = MMC_ERR_BADCRC;
  732. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  733. host->cmd->error = MMC_ERR_FAILED;
  734. else
  735. host->cmd->error = MMC_ERR_INVALID;
  736. tasklet_schedule(&host->finish_tasklet);
  737. }
  738. }
  739. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  740. {
  741. BUG_ON(intmask == 0);
  742. if (!host->data) {
  743. /*
  744. * A data end interrupt is sent together with the response
  745. * for the stop command.
  746. */
  747. if (intmask & SDHCI_INT_DATA_END)
  748. return;
  749. printk(KERN_ERR "%s: Got data interrupt even though no "
  750. "data operation was in progress.\n",
  751. mmc_hostname(host->mmc));
  752. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  753. mmc_hostname(host->mmc));
  754. sdhci_dumpregs(host);
  755. return;
  756. }
  757. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  758. host->data->error = MMC_ERR_TIMEOUT;
  759. else if (intmask & SDHCI_INT_DATA_CRC)
  760. host->data->error = MMC_ERR_BADCRC;
  761. else if (intmask & SDHCI_INT_DATA_END_BIT)
  762. host->data->error = MMC_ERR_FAILED;
  763. if (host->data->error != MMC_ERR_NONE)
  764. sdhci_finish_data(host);
  765. else {
  766. if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
  767. sdhci_transfer_pio(host);
  768. if (intmask & SDHCI_INT_DATA_END)
  769. sdhci_finish_data(host);
  770. }
  771. }
  772. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  773. {
  774. irqreturn_t result;
  775. struct sdhci_host* host = dev_id;
  776. u32 intmask;
  777. spin_lock(&host->lock);
  778. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  779. if (!intmask) {
  780. result = IRQ_NONE;
  781. goto out;
  782. }
  783. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  784. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
  785. writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
  786. host->ioaddr + SDHCI_INT_STATUS);
  787. tasklet_schedule(&host->card_tasklet);
  788. }
  789. intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
  790. if (intmask & SDHCI_INT_CMD_MASK) {
  791. writel(intmask & SDHCI_INT_CMD_MASK,
  792. host->ioaddr + SDHCI_INT_STATUS);
  793. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  794. }
  795. if (intmask & SDHCI_INT_DATA_MASK) {
  796. writel(intmask & SDHCI_INT_DATA_MASK,
  797. host->ioaddr + SDHCI_INT_STATUS);
  798. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  799. }
  800. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  801. if (intmask & SDHCI_INT_BUS_POWER) {
  802. printk(KERN_ERR "%s: Card is consuming too much power!\n",
  803. mmc_hostname(host->mmc));
  804. writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
  805. }
  806. intmask &= SDHCI_INT_BUS_POWER;
  807. if (intmask) {
  808. printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
  809. "report this to " BUGMAIL ".\n",
  810. mmc_hostname(host->mmc), intmask);
  811. sdhci_dumpregs(host);
  812. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  813. }
  814. result = IRQ_HANDLED;
  815. out:
  816. spin_unlock(&host->lock);
  817. return result;
  818. }
  819. /*****************************************************************************\
  820. * *
  821. * Suspend/resume *
  822. * *
  823. \*****************************************************************************/
  824. #ifdef CONFIG_PM
  825. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  826. {
  827. struct sdhci_chip *chip;
  828. int i, ret;
  829. chip = pci_get_drvdata(pdev);
  830. if (!chip)
  831. return 0;
  832. DBG("Suspending...\n");
  833. for (i = 0;i < chip->num_slots;i++) {
  834. if (!chip->hosts[i])
  835. continue;
  836. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  837. if (ret) {
  838. for (i--;i >= 0;i--)
  839. mmc_resume_host(chip->hosts[i]->mmc);
  840. return ret;
  841. }
  842. }
  843. pci_save_state(pdev);
  844. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  845. pci_disable_device(pdev);
  846. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  847. return 0;
  848. }
  849. static int sdhci_resume (struct pci_dev *pdev)
  850. {
  851. struct sdhci_chip *chip;
  852. int i, ret;
  853. chip = pci_get_drvdata(pdev);
  854. if (!chip)
  855. return 0;
  856. DBG("Resuming...\n");
  857. pci_set_power_state(pdev, PCI_D0);
  858. pci_restore_state(pdev);
  859. pci_enable_device(pdev);
  860. for (i = 0;i < chip->num_slots;i++) {
  861. if (!chip->hosts[i])
  862. continue;
  863. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  864. pci_set_master(pdev);
  865. sdhci_init(chip->hosts[i]);
  866. ret = mmc_resume_host(chip->hosts[i]->mmc);
  867. if (ret)
  868. return ret;
  869. }
  870. return 0;
  871. }
  872. #else /* CONFIG_PM */
  873. #define sdhci_suspend NULL
  874. #define sdhci_resume NULL
  875. #endif /* CONFIG_PM */
  876. /*****************************************************************************\
  877. * *
  878. * Device probing/removal *
  879. * *
  880. \*****************************************************************************/
  881. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  882. {
  883. int ret;
  884. unsigned int version;
  885. struct sdhci_chip *chip;
  886. struct mmc_host *mmc;
  887. struct sdhci_host *host;
  888. u8 first_bar;
  889. unsigned int caps;
  890. chip = pci_get_drvdata(pdev);
  891. BUG_ON(!chip);
  892. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  893. if (ret)
  894. return ret;
  895. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  896. if (first_bar > 5) {
  897. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  898. return -ENODEV;
  899. }
  900. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  901. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  902. return -ENODEV;
  903. }
  904. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  905. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  906. return -ENODEV;
  907. }
  908. if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
  909. printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
  910. return -ENODEV;
  911. }
  912. if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
  913. printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
  914. return -ENODEV;
  915. }
  916. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  917. if (!mmc)
  918. return -ENOMEM;
  919. host = mmc_priv(mmc);
  920. host->mmc = mmc;
  921. host->bar = first_bar + slot;
  922. host->addr = pci_resource_start(pdev, host->bar);
  923. host->irq = pdev->irq;
  924. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  925. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  926. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  927. if (ret)
  928. goto free;
  929. host->ioaddr = ioremap_nocache(host->addr,
  930. pci_resource_len(pdev, host->bar));
  931. if (!host->ioaddr) {
  932. ret = -ENOMEM;
  933. goto release;
  934. }
  935. sdhci_reset(host, SDHCI_RESET_ALL);
  936. version = readw(host->ioaddr + SDHCI_HOST_VERSION);
  937. version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
  938. if (version != 0) {
  939. printk(KERN_ERR "%s: Unknown controller version (%d). "
  940. "You may experience problems.\n", host->slot_descr,
  941. version);
  942. }
  943. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  944. if (debug_nodma)
  945. DBG("DMA forced off\n");
  946. else if (debug_forcedma) {
  947. DBG("DMA forced on\n");
  948. host->flags |= SDHCI_USE_DMA;
  949. } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
  950. host->flags |= SDHCI_USE_DMA;
  951. else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
  952. DBG("Controller doesn't have DMA interface\n");
  953. else if (!(caps & SDHCI_CAN_DO_DMA))
  954. DBG("Controller doesn't have DMA capability\n");
  955. else
  956. host->flags |= SDHCI_USE_DMA;
  957. if (host->flags & SDHCI_USE_DMA) {
  958. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  959. printk(KERN_WARNING "%s: No suitable DMA available. "
  960. "Falling back to PIO.\n", host->slot_descr);
  961. host->flags &= ~SDHCI_USE_DMA;
  962. }
  963. }
  964. if (host->flags & SDHCI_USE_DMA)
  965. pci_set_master(pdev);
  966. else /* XXX: Hack to get MMC layer to avoid highmem */
  967. pdev->dma_mask = 0;
  968. host->max_clk =
  969. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  970. if (host->max_clk == 0) {
  971. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  972. "frequency.\n", host->slot_descr);
  973. ret = -ENODEV;
  974. goto unmap;
  975. }
  976. host->max_clk *= 1000000;
  977. host->timeout_clk =
  978. (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
  979. if (host->timeout_clk == 0) {
  980. printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
  981. "frequency.\n", host->slot_descr);
  982. ret = -ENODEV;
  983. goto unmap;
  984. }
  985. if (caps & SDHCI_TIMEOUT_CLK_UNIT)
  986. host->timeout_clk *= 1000;
  987. host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
  988. if (host->max_block >= 3) {
  989. printk(KERN_ERR "%s: Invalid maximum block size.\n",
  990. host->slot_descr);
  991. ret = -ENODEV;
  992. goto unmap;
  993. }
  994. host->max_block = 512 << host->max_block;
  995. /*
  996. * Set host parameters.
  997. */
  998. mmc->ops = &sdhci_ops;
  999. mmc->f_min = host->max_clk / 256;
  1000. mmc->f_max = host->max_clk;
  1001. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
  1002. mmc->ocr_avail = 0;
  1003. if (caps & SDHCI_CAN_VDD_330)
  1004. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  1005. else if (caps & SDHCI_CAN_VDD_300)
  1006. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  1007. else if (caps & SDHCI_CAN_VDD_180)
  1008. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  1009. if (mmc->ocr_avail == 0) {
  1010. printk(KERN_ERR "%s: Hardware doesn't report any "
  1011. "support voltages.\n", host->slot_descr);
  1012. ret = -ENODEV;
  1013. goto unmap;
  1014. }
  1015. spin_lock_init(&host->lock);
  1016. /*
  1017. * Maximum number of segments. Hardware cannot do scatter lists.
  1018. */
  1019. if (host->flags & SDHCI_USE_DMA)
  1020. mmc->max_hw_segs = 1;
  1021. else
  1022. mmc->max_hw_segs = 16;
  1023. mmc->max_phys_segs = 16;
  1024. /*
  1025. * Maximum number of sectors in one transfer. Limited by DMA boundary
  1026. * size (512KiB), which means (512 KiB/512=) 1024 entries.
  1027. */
  1028. mmc->max_sectors = 1024;
  1029. /*
  1030. * Maximum segment size. Could be one segment with the maximum number
  1031. * of sectors.
  1032. */
  1033. mmc->max_seg_size = mmc->max_sectors * 512;
  1034. /*
  1035. * Init tasklets.
  1036. */
  1037. tasklet_init(&host->card_tasklet,
  1038. sdhci_tasklet_card, (unsigned long)host);
  1039. tasklet_init(&host->finish_tasklet,
  1040. sdhci_tasklet_finish, (unsigned long)host);
  1041. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  1042. ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
  1043. host->slot_descr, host);
  1044. if (ret)
  1045. goto untasklet;
  1046. sdhci_init(host);
  1047. #ifdef CONFIG_MMC_DEBUG
  1048. sdhci_dumpregs(host);
  1049. #endif
  1050. host->chip = chip;
  1051. chip->hosts[slot] = host;
  1052. mmc_add_host(mmc);
  1053. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  1054. host->addr, host->irq,
  1055. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  1056. return 0;
  1057. untasklet:
  1058. tasklet_kill(&host->card_tasklet);
  1059. tasklet_kill(&host->finish_tasklet);
  1060. unmap:
  1061. iounmap(host->ioaddr);
  1062. release:
  1063. pci_release_region(pdev, host->bar);
  1064. free:
  1065. mmc_free_host(mmc);
  1066. return ret;
  1067. }
  1068. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  1069. {
  1070. struct sdhci_chip *chip;
  1071. struct mmc_host *mmc;
  1072. struct sdhci_host *host;
  1073. chip = pci_get_drvdata(pdev);
  1074. host = chip->hosts[slot];
  1075. mmc = host->mmc;
  1076. chip->hosts[slot] = NULL;
  1077. mmc_remove_host(mmc);
  1078. sdhci_reset(host, SDHCI_RESET_ALL);
  1079. free_irq(host->irq, host);
  1080. del_timer_sync(&host->timer);
  1081. tasklet_kill(&host->card_tasklet);
  1082. tasklet_kill(&host->finish_tasklet);
  1083. iounmap(host->ioaddr);
  1084. pci_release_region(pdev, host->bar);
  1085. mmc_free_host(mmc);
  1086. }
  1087. static int __devinit sdhci_probe(struct pci_dev *pdev,
  1088. const struct pci_device_id *ent)
  1089. {
  1090. int ret, i;
  1091. u8 slots, rev;
  1092. struct sdhci_chip *chip;
  1093. BUG_ON(pdev == NULL);
  1094. BUG_ON(ent == NULL);
  1095. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  1096. printk(KERN_INFO DRIVER_NAME
  1097. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  1098. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  1099. (int)rev);
  1100. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  1101. if (ret)
  1102. return ret;
  1103. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  1104. DBG("found %d slot(s)\n", slots);
  1105. if (slots == 0)
  1106. return -ENODEV;
  1107. ret = pci_enable_device(pdev);
  1108. if (ret)
  1109. return ret;
  1110. chip = kzalloc(sizeof(struct sdhci_chip) +
  1111. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  1112. if (!chip) {
  1113. ret = -ENOMEM;
  1114. goto err;
  1115. }
  1116. chip->pdev = pdev;
  1117. chip->quirks = ent->driver_data;
  1118. if (debug_quirks)
  1119. chip->quirks = debug_quirks;
  1120. chip->num_slots = slots;
  1121. pci_set_drvdata(pdev, chip);
  1122. for (i = 0;i < slots;i++) {
  1123. ret = sdhci_probe_slot(pdev, i);
  1124. if (ret) {
  1125. for (i--;i >= 0;i--)
  1126. sdhci_remove_slot(pdev, i);
  1127. goto free;
  1128. }
  1129. }
  1130. return 0;
  1131. free:
  1132. pci_set_drvdata(pdev, NULL);
  1133. kfree(chip);
  1134. err:
  1135. pci_disable_device(pdev);
  1136. return ret;
  1137. }
  1138. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1139. {
  1140. int i;
  1141. struct sdhci_chip *chip;
  1142. chip = pci_get_drvdata(pdev);
  1143. if (chip) {
  1144. for (i = 0;i < chip->num_slots;i++)
  1145. sdhci_remove_slot(pdev, i);
  1146. pci_set_drvdata(pdev, NULL);
  1147. kfree(chip);
  1148. }
  1149. pci_disable_device(pdev);
  1150. }
  1151. static struct pci_driver sdhci_driver = {
  1152. .name = DRIVER_NAME,
  1153. .id_table = pci_ids,
  1154. .probe = sdhci_probe,
  1155. .remove = __devexit_p(sdhci_remove),
  1156. .suspend = sdhci_suspend,
  1157. .resume = sdhci_resume,
  1158. };
  1159. /*****************************************************************************\
  1160. * *
  1161. * Driver init/exit *
  1162. * *
  1163. \*****************************************************************************/
  1164. static int __init sdhci_drv_init(void)
  1165. {
  1166. printk(KERN_INFO DRIVER_NAME
  1167. ": Secure Digital Host Controller Interface driver, "
  1168. DRIVER_VERSION "\n");
  1169. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1170. return pci_register_driver(&sdhci_driver);
  1171. }
  1172. static void __exit sdhci_drv_exit(void)
  1173. {
  1174. DBG("Exiting\n");
  1175. pci_unregister_driver(&sdhci_driver);
  1176. }
  1177. module_init(sdhci_drv_init);
  1178. module_exit(sdhci_drv_exit);
  1179. module_param(debug_nodma, uint, 0444);
  1180. module_param(debug_forcedma, uint, 0444);
  1181. module_param(debug_quirks, uint, 0444);
  1182. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1183. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1184. MODULE_VERSION(DRIVER_VERSION);
  1185. MODULE_LICENSE("GPL");
  1186. MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
  1187. MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
  1188. MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");