ipath_intr.c 28 KB

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  1. /*
  2. * Copyright (c) 2006 QLogic, Inc. All rights reserved.
  3. * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/pci.h>
  34. #include "ipath_kernel.h"
  35. #include "ipath_verbs.h"
  36. #include "ipath_common.h"
  37. /* These are all rcv-related errors which we want to count for stats */
  38. #define E_SUM_PKTERRS \
  39. (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \
  40. INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \
  41. INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \
  42. INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \
  43. INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \
  44. INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP)
  45. /* These are all send-related errors which we want to count for stats */
  46. #define E_SUM_ERRS \
  47. (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \
  48. INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
  49. INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \
  50. INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
  51. INFINIPATH_E_INVALIDADDR)
  52. /*
  53. * these are errors that can occur when the link changes state while
  54. * a packet is being sent or received. This doesn't cover things
  55. * like EBP or VCRC that can be the result of a sending having the
  56. * link change state, so we receive a "known bad" packet.
  57. */
  58. #define E_SUM_LINK_PKTERRS \
  59. (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
  60. INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
  61. INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \
  62. INFINIPATH_E_RUNEXPCHAR)
  63. static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
  64. {
  65. unsigned long sbuf[4];
  66. u64 ignore_this_time = 0;
  67. u32 piobcnt;
  68. /* if possible that sendbuffererror could be valid */
  69. piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
  70. /* read these before writing errorclear */
  71. sbuf[0] = ipath_read_kreg64(
  72. dd, dd->ipath_kregs->kr_sendbuffererror);
  73. sbuf[1] = ipath_read_kreg64(
  74. dd, dd->ipath_kregs->kr_sendbuffererror + 1);
  75. if (piobcnt > 128) {
  76. sbuf[2] = ipath_read_kreg64(
  77. dd, dd->ipath_kregs->kr_sendbuffererror + 2);
  78. sbuf[3] = ipath_read_kreg64(
  79. dd, dd->ipath_kregs->kr_sendbuffererror + 3);
  80. }
  81. if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) {
  82. int i;
  83. ipath_cdbg(PKT, "SendbufErrs %lx %lx ", sbuf[0], sbuf[1]);
  84. if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128)
  85. printk("%lx %lx ", sbuf[2], sbuf[3]);
  86. for (i = 0; i < piobcnt; i++) {
  87. if (test_bit(i, sbuf)) {
  88. u32 __iomem *piobuf;
  89. if (i < dd->ipath_piobcnt2k)
  90. piobuf = (u32 __iomem *)
  91. (dd->ipath_pio2kbase +
  92. i * dd->ipath_palign);
  93. else
  94. piobuf = (u32 __iomem *)
  95. (dd->ipath_pio4kbase +
  96. (i - dd->ipath_piobcnt2k) *
  97. dd->ipath_4kalign);
  98. ipath_cdbg(PKT,
  99. "PIObuf[%u] @%p pbc is %x; ",
  100. i, piobuf, readl(piobuf));
  101. ipath_disarm_piobufs(dd, i, 1);
  102. }
  103. }
  104. if (ipath_debug & __IPATH_PKTDBG)
  105. printk("\n");
  106. }
  107. if ((errs & E_SUM_LINK_PKTERRS) &&
  108. !(dd->ipath_flags & IPATH_LINKACTIVE)) {
  109. /*
  110. * This can happen when SMA is trying to bring the link
  111. * up, but the IB link changes state at the "wrong" time.
  112. * The IB logic then complains that the packet isn't
  113. * valid. We don't want to confuse people, so we just
  114. * don't print them, except at debug
  115. */
  116. ipath_dbg("Ignoring packet errors %llx, because link not "
  117. "ACTIVE\n", (unsigned long long) errs);
  118. ignore_this_time = errs & E_SUM_LINK_PKTERRS;
  119. }
  120. return ignore_this_time;
  121. }
  122. /* return the strings for the most common link states */
  123. static char *ib_linkstate(u32 linkstate)
  124. {
  125. char *ret;
  126. switch (linkstate) {
  127. case IPATH_IBSTATE_INIT:
  128. ret = "Init";
  129. break;
  130. case IPATH_IBSTATE_ARM:
  131. ret = "Arm";
  132. break;
  133. case IPATH_IBSTATE_ACTIVE:
  134. ret = "Active";
  135. break;
  136. default:
  137. ret = "Down";
  138. }
  139. return ret;
  140. }
  141. static void handle_e_ibstatuschanged(struct ipath_devdata *dd,
  142. ipath_err_t errs, int noprint)
  143. {
  144. u64 val;
  145. u32 ltstate, lstate;
  146. /*
  147. * even if diags are enabled, we want to notice LINKINIT, etc.
  148. * We just don't want to change the LED state, or
  149. * dd->ipath_kregs->kr_ibcctrl
  150. */
  151. val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
  152. lstate = val & IPATH_IBSTATE_MASK;
  153. /*
  154. * this is confusing enough when it happens that I want to always put it
  155. * on the console and in the logs. If it was a requested state change,
  156. * we'll have already cleared the flags, so we won't print this warning
  157. */
  158. if ((lstate != IPATH_IBSTATE_ARM && lstate != IPATH_IBSTATE_ACTIVE)
  159. && (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) {
  160. dev_info(&dd->pcidev->dev, "Link state changed from %s to %s\n",
  161. (dd->ipath_flags & IPATH_LINKARMED) ? "ARM" : "ACTIVE",
  162. ib_linkstate(lstate));
  163. /*
  164. * Flush all queued sends when link went to DOWN or INIT,
  165. * to be sure that they don't block SMA and other MAD packets
  166. */
  167. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  168. INFINIPATH_S_ABORT);
  169. ipath_disarm_piobufs(dd, dd->ipath_lastport_piobuf,
  170. (unsigned)(dd->ipath_piobcnt2k +
  171. dd->ipath_piobcnt4k) -
  172. dd->ipath_lastport_piobuf);
  173. }
  174. else if (lstate == IPATH_IBSTATE_INIT || lstate == IPATH_IBSTATE_ARM ||
  175. lstate == IPATH_IBSTATE_ACTIVE) {
  176. /*
  177. * only print at SMA if there is a change, debug if not
  178. * (sometimes we want to know that, usually not).
  179. */
  180. if (lstate == ((unsigned) dd->ipath_lastibcstat
  181. & IPATH_IBSTATE_MASK)) {
  182. ipath_dbg("Status change intr but no change (%s)\n",
  183. ib_linkstate(lstate));
  184. }
  185. else
  186. ipath_cdbg(VERBOSE, "Unit %u link state %s, last "
  187. "was %s\n", dd->ipath_unit,
  188. ib_linkstate(lstate),
  189. ib_linkstate((unsigned)
  190. dd->ipath_lastibcstat
  191. & IPATH_IBSTATE_MASK));
  192. }
  193. else {
  194. lstate = dd->ipath_lastibcstat & IPATH_IBSTATE_MASK;
  195. if (lstate == IPATH_IBSTATE_INIT ||
  196. lstate == IPATH_IBSTATE_ARM ||
  197. lstate == IPATH_IBSTATE_ACTIVE)
  198. ipath_cdbg(VERBOSE, "Unit %u link state down"
  199. " (state 0x%x), from %s\n",
  200. dd->ipath_unit,
  201. (u32)val & IPATH_IBSTATE_MASK,
  202. ib_linkstate(lstate));
  203. else
  204. ipath_cdbg(VERBOSE, "Unit %u link state changed "
  205. "to 0x%x from down (%x)\n",
  206. dd->ipath_unit, (u32) val, lstate);
  207. }
  208. ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
  209. INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
  210. lstate = (val >> INFINIPATH_IBCS_LINKSTATE_SHIFT) &
  211. INFINIPATH_IBCS_LINKSTATE_MASK;
  212. if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
  213. ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
  214. u32 last_ltstate;
  215. /*
  216. * Ignore cycling back and forth from Polling.Active
  217. * to Polling.Quiet while waiting for the other end of
  218. * the link to come up. We will cycle back and forth
  219. * between them if no cable is plugged in,
  220. * the other device is powered off or disabled, etc.
  221. */
  222. last_ltstate = (dd->ipath_lastibcstat >>
  223. INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT)
  224. & INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
  225. if (last_ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE
  226. || last_ltstate ==
  227. INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
  228. if (dd->ipath_ibpollcnt > 40) {
  229. dd->ipath_flags |= IPATH_NOCABLE;
  230. *dd->ipath_statusp |=
  231. IPATH_STATUS_IB_NOCABLE;
  232. } else
  233. dd->ipath_ibpollcnt++;
  234. goto skip_ibchange;
  235. }
  236. }
  237. dd->ipath_ibpollcnt = 0; /* some state other than 2 or 3 */
  238. ipath_stats.sps_iblink++;
  239. if (ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
  240. dd->ipath_flags |= IPATH_LINKDOWN;
  241. dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
  242. | IPATH_LINKACTIVE |
  243. IPATH_LINKARMED);
  244. *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
  245. dd->ipath_lli_counter = 0;
  246. if (!noprint) {
  247. if (((dd->ipath_lastibcstat >>
  248. INFINIPATH_IBCS_LINKSTATE_SHIFT) &
  249. INFINIPATH_IBCS_LINKSTATE_MASK)
  250. == INFINIPATH_IBCS_L_STATE_ACTIVE)
  251. /* if from up to down be more vocal */
  252. ipath_cdbg(VERBOSE,
  253. "Unit %u link now down (%s)\n",
  254. dd->ipath_unit,
  255. ipath_ibcstatus_str[ltstate]);
  256. else
  257. ipath_cdbg(VERBOSE, "Unit %u link is "
  258. "down (%s)\n", dd->ipath_unit,
  259. ipath_ibcstatus_str[ltstate]);
  260. }
  261. dd->ipath_f_setextled(dd, lstate, ltstate);
  262. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ACTIVE) {
  263. dd->ipath_flags |= IPATH_LINKACTIVE;
  264. dd->ipath_flags &=
  265. ~(IPATH_LINKUNK | IPATH_LINKINIT | IPATH_LINKDOWN |
  266. IPATH_LINKARMED | IPATH_NOCABLE);
  267. *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE;
  268. *dd->ipath_statusp |=
  269. IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF;
  270. dd->ipath_f_setextled(dd, lstate, ltstate);
  271. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_INIT) {
  272. /*
  273. * set INIT and DOWN. Down is checked by most of the other
  274. * code, but INIT is useful to know in a few places.
  275. */
  276. dd->ipath_flags |= IPATH_LINKINIT | IPATH_LINKDOWN;
  277. dd->ipath_flags &=
  278. ~(IPATH_LINKUNK | IPATH_LINKACTIVE | IPATH_LINKARMED
  279. | IPATH_NOCABLE);
  280. *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
  281. | IPATH_STATUS_IB_READY);
  282. dd->ipath_f_setextled(dd, lstate, ltstate);
  283. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ARM) {
  284. dd->ipath_flags |= IPATH_LINKARMED;
  285. dd->ipath_flags &=
  286. ~(IPATH_LINKUNK | IPATH_LINKDOWN | IPATH_LINKINIT |
  287. IPATH_LINKACTIVE | IPATH_NOCABLE);
  288. *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
  289. | IPATH_STATUS_IB_READY);
  290. dd->ipath_f_setextled(dd, lstate, ltstate);
  291. } else {
  292. if (!noprint)
  293. ipath_dbg("IBstatuschange unit %u: %s (%x)\n",
  294. dd->ipath_unit,
  295. ipath_ibcstatus_str[ltstate], ltstate);
  296. }
  297. skip_ibchange:
  298. dd->ipath_lastibcstat = val;
  299. }
  300. static void handle_supp_msgs(struct ipath_devdata *dd,
  301. unsigned supp_msgs, char msg[512])
  302. {
  303. /*
  304. * Print the message unless it's ibc status change only, which
  305. * happens so often we never want to count it.
  306. */
  307. if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) {
  308. ipath_decode_err(msg, sizeof msg, dd->ipath_lasterror &
  309. ~INFINIPATH_E_IBSTATUSCHANGED);
  310. if (dd->ipath_lasterror &
  311. ~(INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL))
  312. ipath_dev_err(dd, "Suppressed %u messages for "
  313. "fast-repeating errors (%s) (%llx)\n",
  314. supp_msgs, msg,
  315. (unsigned long long)
  316. dd->ipath_lasterror);
  317. else {
  318. /*
  319. * rcvegrfull and rcvhdrqfull are "normal", for some
  320. * types of processes (mostly benchmarks) that send
  321. * huge numbers of messages, while not processing
  322. * them. So only complain about these at debug
  323. * level.
  324. */
  325. ipath_dbg("Suppressed %u messages for %s\n",
  326. supp_msgs, msg);
  327. }
  328. }
  329. }
  330. static unsigned handle_frequent_errors(struct ipath_devdata *dd,
  331. ipath_err_t errs, char msg[512],
  332. int *noprint)
  333. {
  334. unsigned long nc;
  335. static unsigned long nextmsg_time;
  336. static unsigned nmsgs, supp_msgs;
  337. /*
  338. * Throttle back "fast" messages to no more than 10 per 5 seconds.
  339. * This isn't perfect, but it's a reasonable heuristic. If we get
  340. * more than 10, give a 6x longer delay.
  341. */
  342. nc = jiffies;
  343. if (nmsgs > 10) {
  344. if (time_before(nc, nextmsg_time)) {
  345. *noprint = 1;
  346. if (!supp_msgs++)
  347. nextmsg_time = nc + HZ * 3;
  348. }
  349. else if (supp_msgs) {
  350. handle_supp_msgs(dd, supp_msgs, msg);
  351. supp_msgs = 0;
  352. nmsgs = 0;
  353. }
  354. }
  355. else if (!nmsgs++ || time_after(nc, nextmsg_time))
  356. nextmsg_time = nc + HZ / 2;
  357. return supp_msgs;
  358. }
  359. static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
  360. {
  361. char msg[512];
  362. u64 ignore_this_time = 0;
  363. int i;
  364. int chkerrpkts = 0, noprint = 0;
  365. unsigned supp_msgs;
  366. supp_msgs = handle_frequent_errors(dd, errs, msg, &noprint);
  367. /*
  368. * don't report errors that are masked (includes those always
  369. * ignored)
  370. */
  371. errs &= ~dd->ipath_maskederrs;
  372. /* do these first, they are most important */
  373. if (errs & INFINIPATH_E_HARDWARE) {
  374. /* reuse same msg buf */
  375. dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg);
  376. }
  377. if (!noprint && (errs & ~infinipath_e_bitsextant))
  378. ipath_dev_err(dd, "error interrupt with unknown errors "
  379. "%llx set\n", (unsigned long long)
  380. (errs & ~infinipath_e_bitsextant));
  381. if (errs & E_SUM_ERRS)
  382. ignore_this_time = handle_e_sum_errs(dd, errs);
  383. else if ((errs & E_SUM_LINK_PKTERRS) &&
  384. !(dd->ipath_flags & IPATH_LINKACTIVE)) {
  385. /*
  386. * This can happen when SMA is trying to bring the link
  387. * up, but the IB link changes state at the "wrong" time.
  388. * The IB logic then complains that the packet isn't
  389. * valid. We don't want to confuse people, so we just
  390. * don't print them, except at debug
  391. */
  392. ipath_dbg("Ignoring packet errors %llx, because link not "
  393. "ACTIVE\n", (unsigned long long) errs);
  394. ignore_this_time = errs & E_SUM_LINK_PKTERRS;
  395. }
  396. if (supp_msgs == 250000) {
  397. /*
  398. * It's not entirely reasonable assuming that the errors set
  399. * in the last clear period are all responsible for the
  400. * problem, but the alternative is to assume it's the only
  401. * ones on this particular interrupt, which also isn't great
  402. */
  403. dd->ipath_maskederrs |= dd->ipath_lasterror | errs;
  404. ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
  405. ~dd->ipath_maskederrs);
  406. ipath_decode_err(msg, sizeof msg,
  407. (dd->ipath_maskederrs & ~dd->
  408. ipath_ignorederrs));
  409. if ((dd->ipath_maskederrs & ~dd->ipath_ignorederrs) &
  410. ~(INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL))
  411. ipath_dev_err(dd, "Disabling error(s) %llx because "
  412. "occurring too frequently (%s)\n",
  413. (unsigned long long)
  414. (dd->ipath_maskederrs &
  415. ~dd->ipath_ignorederrs), msg);
  416. else {
  417. /*
  418. * rcvegrfull and rcvhdrqfull are "normal",
  419. * for some types of processes (mostly benchmarks)
  420. * that send huge numbers of messages, while not
  421. * processing them. So only complain about
  422. * these at debug level.
  423. */
  424. ipath_dbg("Disabling frequent queue full errors "
  425. "(%s)\n", msg);
  426. }
  427. /*
  428. * Re-enable the masked errors after around 3 minutes. in
  429. * ipath_get_faststats(). If we have a series of fast
  430. * repeating but different errors, the interval will keep
  431. * stretching out, but that's OK, as that's pretty
  432. * catastrophic.
  433. */
  434. dd->ipath_unmasktime = jiffies + HZ * 180;
  435. }
  436. ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs);
  437. if (ignore_this_time)
  438. errs &= ~ignore_this_time;
  439. if (errs & ~dd->ipath_lasterror) {
  440. errs &= ~dd->ipath_lasterror;
  441. /* never suppress duplicate hwerrors or ibstatuschange */
  442. dd->ipath_lasterror |= errs &
  443. ~(INFINIPATH_E_HARDWARE |
  444. INFINIPATH_E_IBSTATUSCHANGED);
  445. }
  446. if (!errs)
  447. return 0;
  448. if (!noprint)
  449. /*
  450. * the ones we mask off are handled specially below or above
  451. */
  452. ipath_decode_err(msg, sizeof msg,
  453. errs & ~(INFINIPATH_E_IBSTATUSCHANGED |
  454. INFINIPATH_E_RRCVEGRFULL |
  455. INFINIPATH_E_RRCVHDRFULL |
  456. INFINIPATH_E_HARDWARE));
  457. else
  458. /* so we don't need if (!noprint) at strlcat's below */
  459. *msg = 0;
  460. if (errs & E_SUM_PKTERRS) {
  461. ipath_stats.sps_pkterrs++;
  462. chkerrpkts = 1;
  463. }
  464. if (errs & E_SUM_ERRS)
  465. ipath_stats.sps_errs++;
  466. if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) {
  467. ipath_stats.sps_crcerrs++;
  468. chkerrpkts = 1;
  469. }
  470. /*
  471. * We don't want to print these two as they happen, or we can make
  472. * the situation even worse, because it takes so long to print
  473. * messages to serial consoles. Kernel ports get printed from
  474. * fast_stats, no more than every 5 seconds, user ports get printed
  475. * on close
  476. */
  477. if (errs & INFINIPATH_E_RRCVHDRFULL) {
  478. int any;
  479. u32 hd, tl;
  480. ipath_stats.sps_hdrqfull++;
  481. for (any = i = 0; i < dd->ipath_cfgports; i++) {
  482. struct ipath_portdata *pd = dd->ipath_pd[i];
  483. if (i == 0) {
  484. hd = dd->ipath_port0head;
  485. tl = (u32) le64_to_cpu(
  486. *dd->ipath_hdrqtailptr);
  487. } else if (pd && pd->port_cnt &&
  488. pd->port_rcvhdrtail_kvaddr) {
  489. /*
  490. * don't report same point multiple times,
  491. * except kernel
  492. */
  493. tl = (u32) * pd->port_rcvhdrtail_kvaddr;
  494. if (tl == dd->ipath_lastrcvhdrqtails[i])
  495. continue;
  496. hd = ipath_read_ureg32(dd, ur_rcvhdrhead,
  497. i);
  498. } else
  499. continue;
  500. if (hd == (tl + 1) ||
  501. (!hd && tl == dd->ipath_hdrqlast)) {
  502. if (i == 0)
  503. chkerrpkts = 1;
  504. dd->ipath_lastrcvhdrqtails[i] = tl;
  505. pd->port_hdrqfull++;
  506. }
  507. }
  508. }
  509. if (errs & INFINIPATH_E_RRCVEGRFULL) {
  510. /*
  511. * since this is of less importance and not likely to
  512. * happen without also getting hdrfull, only count
  513. * occurrences; don't check each port (or even the kernel
  514. * vs user)
  515. */
  516. ipath_stats.sps_etidfull++;
  517. if (dd->ipath_port0head !=
  518. (u32) le64_to_cpu(*dd->ipath_hdrqtailptr))
  519. chkerrpkts = 1;
  520. }
  521. /*
  522. * do this before IBSTATUSCHANGED, in case both bits set in a single
  523. * interrupt; we want the STATUSCHANGE to "win", so we do our
  524. * internal copy of state machine correctly
  525. */
  526. if (errs & INFINIPATH_E_RIBLOSTLINK) {
  527. /*
  528. * force through block below
  529. */
  530. errs |= INFINIPATH_E_IBSTATUSCHANGED;
  531. ipath_stats.sps_iblink++;
  532. dd->ipath_flags |= IPATH_LINKDOWN;
  533. dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
  534. | IPATH_LINKARMED | IPATH_LINKACTIVE);
  535. *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
  536. if (!noprint) {
  537. u64 st = ipath_read_kreg64(
  538. dd, dd->ipath_kregs->kr_ibcstatus);
  539. ipath_dbg("Lost link, link now down (%s)\n",
  540. ipath_ibcstatus_str[st & 0xf]);
  541. }
  542. }
  543. if (errs & INFINIPATH_E_IBSTATUSCHANGED)
  544. handle_e_ibstatuschanged(dd, errs, noprint);
  545. if (errs & INFINIPATH_E_RESET) {
  546. if (!noprint)
  547. ipath_dev_err(dd, "Got reset, requires re-init "
  548. "(unload and reload driver)\n");
  549. dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */
  550. /* mark as having had error */
  551. *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
  552. *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF;
  553. }
  554. if (!noprint && *msg)
  555. ipath_dev_err(dd, "%s error\n", msg);
  556. if (dd->ipath_state_wanted & dd->ipath_flags) {
  557. ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, "
  558. "waking\n", dd->ipath_state_wanted,
  559. dd->ipath_flags);
  560. wake_up_interruptible(&ipath_state_wait);
  561. }
  562. return chkerrpkts;
  563. }
  564. /* this is separate to allow for better optimization of ipath_intr() */
  565. static void ipath_bad_intr(struct ipath_devdata *dd, u32 * unexpectp)
  566. {
  567. /*
  568. * sometimes happen during driver init and unload, don't want
  569. * to process any interrupts at that point
  570. */
  571. /* this is just a bandaid, not a fix, if something goes badly
  572. * wrong */
  573. if (++*unexpectp > 100) {
  574. if (++*unexpectp > 105) {
  575. /*
  576. * ok, we must be taking somebody else's interrupts,
  577. * due to a messed up mptable and/or PIRQ table, so
  578. * unregister the interrupt. We've seen this during
  579. * linuxbios development work, and it may happen in
  580. * the future again.
  581. */
  582. if (dd->pcidev && dd->pcidev->irq) {
  583. ipath_dev_err(dd, "Now %u unexpected "
  584. "interrupts, unregistering "
  585. "interrupt handler\n",
  586. *unexpectp);
  587. ipath_dbg("free_irq of irq %x\n",
  588. dd->pcidev->irq);
  589. free_irq(dd->pcidev->irq, dd);
  590. }
  591. }
  592. if (ipath_read_kreg32(dd, dd->ipath_kregs->kr_intmask)) {
  593. ipath_dev_err(dd, "%u unexpected interrupts, "
  594. "disabling interrupts completely\n",
  595. *unexpectp);
  596. /*
  597. * disable all interrupts, something is very wrong
  598. */
  599. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
  600. 0ULL);
  601. }
  602. } else if (*unexpectp > 1)
  603. ipath_dbg("Interrupt when not ready, should not happen, "
  604. "ignoring\n");
  605. }
  606. static void ipath_bad_regread(struct ipath_devdata *dd)
  607. {
  608. static int allbits;
  609. /* separate routine, for better optimization of ipath_intr() */
  610. /*
  611. * We print the message and disable interrupts, in hope of
  612. * having a better chance of debugging the problem.
  613. */
  614. ipath_dev_err(dd,
  615. "Read of interrupt status failed (all bits set)\n");
  616. if (allbits++) {
  617. /* disable all interrupts, something is very wrong */
  618. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
  619. if (allbits == 2) {
  620. ipath_dev_err(dd, "Still bad interrupt status, "
  621. "unregistering interrupt\n");
  622. free_irq(dd->pcidev->irq, dd);
  623. } else if (allbits > 2) {
  624. if ((allbits % 10000) == 0)
  625. printk(".");
  626. } else
  627. ipath_dev_err(dd, "Disabling interrupts, "
  628. "multiple errors\n");
  629. }
  630. }
  631. static void handle_port_pioavail(struct ipath_devdata *dd)
  632. {
  633. u32 i;
  634. /*
  635. * start from port 1, since for now port 0 is never using
  636. * wait_event for PIO
  637. */
  638. for (i = 1; dd->ipath_portpiowait && i < dd->ipath_cfgports; i++) {
  639. struct ipath_portdata *pd = dd->ipath_pd[i];
  640. if (pd && pd->port_cnt &&
  641. dd->ipath_portpiowait & (1U << i)) {
  642. clear_bit(i, &dd->ipath_portpiowait);
  643. if (test_bit(IPATH_PORT_WAITING_PIO,
  644. &pd->port_flag)) {
  645. clear_bit(IPATH_PORT_WAITING_PIO,
  646. &pd->port_flag);
  647. wake_up_interruptible(&pd->port_wait);
  648. }
  649. }
  650. }
  651. }
  652. static void handle_layer_pioavail(struct ipath_devdata *dd)
  653. {
  654. int ret;
  655. ret = ipath_ib_piobufavail(dd->verbs_dev);
  656. if (ret > 0)
  657. goto set;
  658. return;
  659. set:
  660. set_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
  661. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  662. dd->ipath_sendctrl);
  663. }
  664. /*
  665. * Handle receive interrupts for user ports; this means a user
  666. * process was waiting for a packet to arrive, and didn't want
  667. * to poll
  668. */
  669. static void handle_urcv(struct ipath_devdata *dd, u32 istat)
  670. {
  671. u64 portr;
  672. int i;
  673. int rcvdint = 0;
  674. portr = ((istat >> INFINIPATH_I_RCVAVAIL_SHIFT) &
  675. infinipath_i_rcvavail_mask)
  676. | ((istat >> INFINIPATH_I_RCVURG_SHIFT) &
  677. infinipath_i_rcvurg_mask);
  678. for (i = 1; i < dd->ipath_cfgports; i++) {
  679. struct ipath_portdata *pd = dd->ipath_pd[i];
  680. if (portr & (1 << i) && pd && pd->port_cnt &&
  681. test_bit(IPATH_PORT_WAITING_RCV, &pd->port_flag)) {
  682. int rcbit;
  683. clear_bit(IPATH_PORT_WAITING_RCV,
  684. &pd->port_flag);
  685. rcbit = i + INFINIPATH_R_INTRAVAIL_SHIFT;
  686. clear_bit(1UL << rcbit, &dd->ipath_rcvctrl);
  687. wake_up_interruptible(&pd->port_wait);
  688. rcvdint = 1;
  689. }
  690. }
  691. if (rcvdint) {
  692. /* only want to take one interrupt, so turn off the rcv
  693. * interrupt for all the ports that we did the wakeup on
  694. * (but never for kernel port)
  695. */
  696. ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
  697. dd->ipath_rcvctrl);
  698. }
  699. }
  700. irqreturn_t ipath_intr(int irq, void *data, struct pt_regs *regs)
  701. {
  702. struct ipath_devdata *dd = data;
  703. u32 istat, chk0rcv = 0;
  704. ipath_err_t estat = 0;
  705. irqreturn_t ret;
  706. u32 oldhead, curtail;
  707. static unsigned unexpected = 0;
  708. static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) |
  709. (1U<<INFINIPATH_I_RCVURG_SHIFT);
  710. ipath_stats.sps_ints++;
  711. if (!(dd->ipath_flags & IPATH_PRESENT)) {
  712. /*
  713. * This return value is not great, but we do not want the
  714. * interrupt core code to remove our interrupt handler
  715. * because we don't appear to be handling an interrupt
  716. * during a chip reset.
  717. */
  718. return IRQ_HANDLED;
  719. }
  720. /*
  721. * this needs to be flags&initted, not statusp, so we keep
  722. * taking interrupts even after link goes down, etc.
  723. * Also, we *must* clear the interrupt at some point, or we won't
  724. * take it again, which can be real bad for errors, etc...
  725. */
  726. if (!(dd->ipath_flags & IPATH_INITTED)) {
  727. ipath_bad_intr(dd, &unexpected);
  728. ret = IRQ_NONE;
  729. goto bail;
  730. }
  731. /*
  732. * We try to avoid reading the interrupt status register, since
  733. * that's a PIO read, and stalls the processor for up to about
  734. * ~0.25 usec. The idea is that if we processed a port0 packet,
  735. * we blindly clear the port 0 receive interrupt bits, and nothing
  736. * else, then return. If other interrupts are pending, the chip
  737. * will re-interrupt us as soon as we write the intclear register.
  738. * We then won't process any more kernel packets (if not the 2nd
  739. * time, then the 3rd or 4th) and we'll then handle the other
  740. * interrupts. We clear the interrupts first so that we don't
  741. * lose intr for later packets that arrive while we are processing.
  742. */
  743. oldhead = dd->ipath_port0head;
  744. curtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr);
  745. if (oldhead != curtail) {
  746. if (dd->ipath_flags & IPATH_GPIO_INTR) {
  747. ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
  748. (u64) (1 << 2));
  749. istat = port0rbits | INFINIPATH_I_GPIO;
  750. }
  751. else
  752. istat = port0rbits;
  753. ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
  754. ipath_kreceive(dd);
  755. if (oldhead != dd->ipath_port0head) {
  756. ipath_stats.sps_fastrcvint++;
  757. goto done;
  758. }
  759. }
  760. istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus);
  761. if (unlikely(!istat)) {
  762. ipath_stats.sps_nullintr++;
  763. ret = IRQ_NONE; /* not our interrupt, or already handled */
  764. goto bail;
  765. }
  766. if (unlikely(istat == -1)) {
  767. ipath_bad_regread(dd);
  768. /* don't know if it was our interrupt or not */
  769. ret = IRQ_NONE;
  770. goto bail;
  771. }
  772. if (unexpected)
  773. unexpected = 0;
  774. if (unlikely(istat & ~infinipath_i_bitsextant))
  775. ipath_dev_err(dd,
  776. "interrupt with unknown interrupts %x set\n",
  777. istat & (u32) ~ infinipath_i_bitsextant);
  778. else
  779. ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat);
  780. if (unlikely(istat & INFINIPATH_I_ERROR)) {
  781. ipath_stats.sps_errints++;
  782. estat = ipath_read_kreg64(dd,
  783. dd->ipath_kregs->kr_errorstatus);
  784. if (!estat)
  785. dev_info(&dd->pcidev->dev, "error interrupt (%x), "
  786. "but no error bits set!\n", istat);
  787. else if (estat == -1LL)
  788. /*
  789. * should we try clearing all, or hope next read
  790. * works?
  791. */
  792. ipath_dev_err(dd, "Read of error status failed "
  793. "(all bits set); ignoring\n");
  794. else
  795. if (handle_errors(dd, estat))
  796. /* force calling ipath_kreceive() */
  797. chk0rcv = 1;
  798. }
  799. if (istat & INFINIPATH_I_GPIO) {
  800. /*
  801. * Packets are available in the port 0 rcv queue.
  802. * Eventually this needs to be generalized to check
  803. * IPATH_GPIO_INTR, and the specific GPIO bit, if
  804. * GPIO interrupts are used for anything else.
  805. */
  806. if (unlikely(!(dd->ipath_flags & IPATH_GPIO_INTR))) {
  807. u32 gpiostatus;
  808. gpiostatus = ipath_read_kreg32(
  809. dd, dd->ipath_kregs->kr_gpio_status);
  810. ipath_dbg("Unexpected GPIO interrupt bits %x\n",
  811. gpiostatus);
  812. ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
  813. gpiostatus);
  814. }
  815. else {
  816. /* Clear GPIO status bit 2 */
  817. ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
  818. (u64) (1 << 2));
  819. chk0rcv = 1;
  820. }
  821. }
  822. chk0rcv |= istat & port0rbits;
  823. /*
  824. * Clear the interrupt bits we found set, unless they are receive
  825. * related, in which case we already cleared them above, and don't
  826. * want to clear them again, because we might lose an interrupt.
  827. * Clear it early, so we "know" know the chip will have seen this by
  828. * the time we process the queue, and will re-interrupt if necessary.
  829. * The processor itself won't take the interrupt again until we return.
  830. */
  831. ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
  832. /*
  833. * handle port0 receive before checking for pio buffers available,
  834. * since receives can overflow; piobuf waiters can afford a few
  835. * extra cycles, since they were waiting anyway, and user's waiting
  836. * for receive are at the bottom.
  837. */
  838. if (chk0rcv) {
  839. ipath_kreceive(dd);
  840. istat &= ~port0rbits;
  841. }
  842. if (istat & ((infinipath_i_rcvavail_mask <<
  843. INFINIPATH_I_RCVAVAIL_SHIFT)
  844. | (infinipath_i_rcvurg_mask <<
  845. INFINIPATH_I_RCVURG_SHIFT)))
  846. handle_urcv(dd, istat);
  847. if (istat & INFINIPATH_I_SPIOBUFAVAIL) {
  848. clear_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
  849. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  850. dd->ipath_sendctrl);
  851. if (dd->ipath_portpiowait)
  852. handle_port_pioavail(dd);
  853. handle_layer_pioavail(dd);
  854. }
  855. done:
  856. ret = IRQ_HANDLED;
  857. bail:
  858. return ret;
  859. }