omap_wdt.c 9.0 KB

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  1. /*
  2. * linux/drivers/char/watchdog/omap_wdt.c
  3. *
  4. * Watchdog driver for the TI OMAP 16xx & 24xx 32KHz (non-secure) watchdog
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * <gdavis@mvista.com> or <source@mvista.com>
  8. *
  9. * 2003 (c) MontaVista Software, Inc. This file is licensed under the
  10. * terms of the GNU General Public License version 2. This program is
  11. * licensed "as is" without any warranty of any kind, whether express
  12. * or implied.
  13. *
  14. * History:
  15. *
  16. * 20030527: George G. Davis <gdavis@mvista.com>
  17. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  18. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  19. * Based on SoftDog driver by Alan Cox <alan@redhat.com>
  20. *
  21. * Copyright (c) 2004 Texas Instruments.
  22. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  23. * 2. Ported to 2.6 kernel
  24. *
  25. * Copyright (c) 2005 David Brownell
  26. * Use the driver model and standard identifiers; handle bigger timeouts.
  27. */
  28. #include <linux/module.h>
  29. #include <linux/config.h>
  30. #include <linux/types.h>
  31. #include <linux/kernel.h>
  32. #include <linux/fs.h>
  33. #include <linux/mm.h>
  34. #include <linux/miscdevice.h>
  35. #include <linux/watchdog.h>
  36. #include <linux/reboot.h>
  37. #include <linux/smp_lock.h>
  38. #include <linux/init.h>
  39. #include <linux/err.h>
  40. #include <linux/platform_device.h>
  41. #include <linux/moduleparam.h>
  42. #include <linux/clk.h>
  43. #include <asm/io.h>
  44. #include <asm/uaccess.h>
  45. #include <asm/hardware.h>
  46. #include <asm/bitops.h>
  47. #include <asm/arch/prcm.h>
  48. #include "omap_wdt.h"
  49. static unsigned timer_margin;
  50. module_param(timer_margin, uint, 0);
  51. MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
  52. static int omap_wdt_users;
  53. static struct clk *armwdt_ck = NULL;
  54. static struct clk *mpu_wdt_ick = NULL;
  55. static struct clk *mpu_wdt_fck = NULL;
  56. static unsigned int wdt_trgr_pattern = 0x1234;
  57. static void omap_wdt_ping(void)
  58. {
  59. /* wait for posted write to complete */
  60. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
  61. cpu_relax();
  62. wdt_trgr_pattern = ~wdt_trgr_pattern;
  63. omap_writel(wdt_trgr_pattern, (OMAP_WATCHDOG_TGR));
  64. /* wait for posted write to complete */
  65. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
  66. cpu_relax();
  67. /* reloaded WCRR from WLDR */
  68. }
  69. static void omap_wdt_enable(void)
  70. {
  71. /* Sequence to enable the watchdog */
  72. omap_writel(0xBBBB, OMAP_WATCHDOG_SPR);
  73. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
  74. cpu_relax();
  75. omap_writel(0x4444, OMAP_WATCHDOG_SPR);
  76. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
  77. cpu_relax();
  78. }
  79. static void omap_wdt_disable(void)
  80. {
  81. /* sequence required to disable watchdog */
  82. omap_writel(0xAAAA, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  83. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
  84. cpu_relax();
  85. omap_writel(0x5555, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  86. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
  87. cpu_relax();
  88. }
  89. static void omap_wdt_adjust_timeout(unsigned new_timeout)
  90. {
  91. if (new_timeout < TIMER_MARGIN_MIN)
  92. new_timeout = TIMER_MARGIN_DEFAULT;
  93. if (new_timeout > TIMER_MARGIN_MAX)
  94. new_timeout = TIMER_MARGIN_MAX;
  95. timer_margin = new_timeout;
  96. }
  97. static void omap_wdt_set_timeout(void)
  98. {
  99. u32 pre_margin = GET_WLDR_VAL(timer_margin);
  100. /* just count up at 32 KHz */
  101. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
  102. cpu_relax();
  103. omap_writel(pre_margin, OMAP_WATCHDOG_LDR);
  104. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
  105. cpu_relax();
  106. }
  107. /*
  108. * Allow only one task to hold it open
  109. */
  110. static int omap_wdt_open(struct inode *inode, struct file *file)
  111. {
  112. if (test_and_set_bit(1, (unsigned long *)&omap_wdt_users))
  113. return -EBUSY;
  114. if (cpu_is_omap16xx())
  115. clk_enable(armwdt_ck); /* Enable the clock */
  116. if (cpu_is_omap24xx()) {
  117. clk_enable(mpu_wdt_ick); /* Enable the interface clock */
  118. clk_enable(mpu_wdt_fck); /* Enable the functional clock */
  119. }
  120. /* initialize prescaler */
  121. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
  122. cpu_relax();
  123. omap_writel((1 << 5) | (PTV << 2), OMAP_WATCHDOG_CNTRL);
  124. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
  125. cpu_relax();
  126. omap_wdt_set_timeout();
  127. omap_wdt_enable();
  128. return 0;
  129. }
  130. static int omap_wdt_release(struct inode *inode, struct file *file)
  131. {
  132. /*
  133. * Shut off the timer unless NOWAYOUT is defined.
  134. */
  135. #ifndef CONFIG_WATCHDOG_NOWAYOUT
  136. omap_wdt_disable();
  137. if (cpu_is_omap16xx()) {
  138. clk_disable(armwdt_ck); /* Disable the clock */
  139. clk_put(armwdt_ck);
  140. armwdt_ck = NULL;
  141. }
  142. if (cpu_is_omap24xx()) {
  143. clk_disable(mpu_wdt_ick); /* Disable the clock */
  144. clk_disable(mpu_wdt_fck); /* Disable the clock */
  145. clk_put(mpu_wdt_ick);
  146. clk_put(mpu_wdt_fck);
  147. mpu_wdt_ick = NULL;
  148. mpu_wdt_fck = NULL;
  149. }
  150. #else
  151. printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
  152. #endif
  153. omap_wdt_users = 0;
  154. return 0;
  155. }
  156. static ssize_t
  157. omap_wdt_write(struct file *file, const char __user *data,
  158. size_t len, loff_t *ppos)
  159. {
  160. /* Refresh LOAD_TIME. */
  161. if (len)
  162. omap_wdt_ping();
  163. return len;
  164. }
  165. static int
  166. omap_wdt_ioctl(struct inode *inode, struct file *file,
  167. unsigned int cmd, unsigned long arg)
  168. {
  169. int new_margin;
  170. static struct watchdog_info ident = {
  171. .identity = "OMAP Watchdog",
  172. .options = WDIOF_SETTIMEOUT,
  173. .firmware_version = 0,
  174. };
  175. switch (cmd) {
  176. default:
  177. return -ENOIOCTLCMD;
  178. case WDIOC_GETSUPPORT:
  179. return copy_to_user((struct watchdog_info __user *)arg, &ident,
  180. sizeof(ident));
  181. case WDIOC_GETSTATUS:
  182. return put_user(0, (int __user *)arg);
  183. case WDIOC_GETBOOTSTATUS:
  184. if (cpu_is_omap16xx())
  185. return put_user(omap_readw(ARM_SYSST),
  186. (int __user *)arg);
  187. if (cpu_is_omap24xx())
  188. return put_user(omap_prcm_get_reset_sources(),
  189. (int __user *)arg);
  190. case WDIOC_KEEPALIVE:
  191. omap_wdt_ping();
  192. return 0;
  193. case WDIOC_SETTIMEOUT:
  194. if (get_user(new_margin, (int __user *)arg))
  195. return -EFAULT;
  196. omap_wdt_adjust_timeout(new_margin);
  197. omap_wdt_disable();
  198. omap_wdt_set_timeout();
  199. omap_wdt_enable();
  200. omap_wdt_ping();
  201. /* Fall */
  202. case WDIOC_GETTIMEOUT:
  203. return put_user(timer_margin, (int __user *)arg);
  204. }
  205. }
  206. static struct file_operations omap_wdt_fops = {
  207. .owner = THIS_MODULE,
  208. .write = omap_wdt_write,
  209. .ioctl = omap_wdt_ioctl,
  210. .open = omap_wdt_open,
  211. .release = omap_wdt_release,
  212. };
  213. static struct miscdevice omap_wdt_miscdev = {
  214. .minor = WATCHDOG_MINOR,
  215. .name = "watchdog",
  216. .fops = &omap_wdt_fops
  217. };
  218. static int __init omap_wdt_probe(struct platform_device *pdev)
  219. {
  220. struct resource *res, *mem;
  221. int ret;
  222. /* reserve static register mappings */
  223. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  224. if (!res)
  225. return -ENOENT;
  226. mem = request_mem_region(res->start, res->end - res->start + 1,
  227. pdev->name);
  228. if (mem == NULL)
  229. return -EBUSY;
  230. platform_set_drvdata(pdev, mem);
  231. omap_wdt_users = 0;
  232. if (cpu_is_omap16xx()) {
  233. armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
  234. if (IS_ERR(armwdt_ck)) {
  235. ret = PTR_ERR(armwdt_ck);
  236. armwdt_ck = NULL;
  237. goto fail;
  238. }
  239. }
  240. if (cpu_is_omap24xx()) {
  241. mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
  242. if (IS_ERR(mpu_wdt_ick)) {
  243. ret = PTR_ERR(mpu_wdt_ick);
  244. mpu_wdt_ick = NULL;
  245. goto fail;
  246. }
  247. mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
  248. if (IS_ERR(mpu_wdt_fck)) {
  249. ret = PTR_ERR(mpu_wdt_fck);
  250. mpu_wdt_fck = NULL;
  251. goto fail;
  252. }
  253. }
  254. omap_wdt_disable();
  255. omap_wdt_adjust_timeout(timer_margin);
  256. omap_wdt_miscdev.dev = &pdev->dev;
  257. ret = misc_register(&omap_wdt_miscdev);
  258. if (ret)
  259. goto fail;
  260. pr_info("OMAP Watchdog Timer: initial timeout %d sec\n", timer_margin);
  261. /* autogate OCP interface clock */
  262. omap_writel(0x01, OMAP_WATCHDOG_SYS_CONFIG);
  263. return 0;
  264. fail:
  265. if (armwdt_ck)
  266. clk_put(armwdt_ck);
  267. if (mpu_wdt_ick)
  268. clk_put(mpu_wdt_ick);
  269. if (mpu_wdt_fck)
  270. clk_put(mpu_wdt_fck);
  271. release_resource(mem);
  272. return ret;
  273. }
  274. static void omap_wdt_shutdown(struct platform_device *pdev)
  275. {
  276. omap_wdt_disable();
  277. }
  278. static int omap_wdt_remove(struct platform_device *pdev)
  279. {
  280. struct resource *mem = platform_get_drvdata(pdev);
  281. misc_deregister(&omap_wdt_miscdev);
  282. release_resource(mem);
  283. if (armwdt_ck)
  284. clk_put(armwdt_ck);
  285. if (mpu_wdt_ick)
  286. clk_put(mpu_wdt_ick);
  287. if (mpu_wdt_fck)
  288. clk_put(mpu_wdt_fck);
  289. return 0;
  290. }
  291. #ifdef CONFIG_PM
  292. /* REVISIT ... not clear this is the best way to handle system suspend; and
  293. * it's very inappropriate for selective device suspend (e.g. suspending this
  294. * through sysfs rather than by stopping the watchdog daemon). Also, this
  295. * may not play well enough with NOWAYOUT...
  296. */
  297. static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
  298. {
  299. if (omap_wdt_users)
  300. omap_wdt_disable();
  301. return 0;
  302. }
  303. static int omap_wdt_resume(struct platform_device *pdev)
  304. {
  305. if (omap_wdt_users) {
  306. omap_wdt_enable();
  307. omap_wdt_ping();
  308. }
  309. return 0;
  310. }
  311. #else
  312. #define omap_wdt_suspend NULL
  313. #define omap_wdt_resume NULL
  314. #endif
  315. static struct platform_driver omap_wdt_driver = {
  316. .probe = omap_wdt_probe,
  317. .remove = omap_wdt_remove,
  318. .shutdown = omap_wdt_shutdown,
  319. .suspend = omap_wdt_suspend,
  320. .resume = omap_wdt_resume,
  321. .driver = {
  322. .owner = THIS_MODULE,
  323. .name = "omap_wdt",
  324. },
  325. };
  326. static int __init omap_wdt_init(void)
  327. {
  328. return platform_driver_register(&omap_wdt_driver);
  329. }
  330. static void __exit omap_wdt_exit(void)
  331. {
  332. platform_driver_unregister(&omap_wdt_driver);
  333. }
  334. module_init(omap_wdt_init);
  335. module_exit(omap_wdt_exit);
  336. MODULE_AUTHOR("George G. Davis");
  337. MODULE_LICENSE("GPL");
  338. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);