qeth_core_main.c 131 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include "qeth_core.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_MSG] = {"qeth_msg",
  31. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  32. [QETH_DBF_CTRL] = {"qeth_control",
  33. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  34. };
  35. EXPORT_SYMBOL_GPL(qeth_dbf);
  36. struct qeth_card_list_struct qeth_core_card_list;
  37. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  38. struct kmem_cache *qeth_core_header_cache;
  39. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  40. static struct device *qeth_core_root_dev;
  41. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  42. static struct lock_class_key qdio_out_skb_queue_key;
  43. static void qeth_send_control_data_cb(struct qeth_channel *,
  44. struct qeth_cmd_buffer *);
  45. static int qeth_issue_next_read(struct qeth_card *);
  46. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  47. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  48. static void qeth_free_buffer_pool(struct qeth_card *);
  49. static int qeth_qdio_establish(struct qeth_card *);
  50. static inline const char *qeth_get_cardname(struct qeth_card *card)
  51. {
  52. if (card->info.guestlan) {
  53. switch (card->info.type) {
  54. case QETH_CARD_TYPE_OSD:
  55. return " Guest LAN QDIO";
  56. case QETH_CARD_TYPE_IQD:
  57. return " Guest LAN Hiper";
  58. case QETH_CARD_TYPE_OSM:
  59. return " Guest LAN QDIO - OSM";
  60. case QETH_CARD_TYPE_OSX:
  61. return " Guest LAN QDIO - OSX";
  62. default:
  63. return " unknown";
  64. }
  65. } else {
  66. switch (card->info.type) {
  67. case QETH_CARD_TYPE_OSD:
  68. return " OSD Express";
  69. case QETH_CARD_TYPE_IQD:
  70. return " HiperSockets";
  71. case QETH_CARD_TYPE_OSN:
  72. return " OSN QDIO";
  73. case QETH_CARD_TYPE_OSM:
  74. return " OSM QDIO";
  75. case QETH_CARD_TYPE_OSX:
  76. return " OSX QDIO";
  77. default:
  78. return " unknown";
  79. }
  80. }
  81. return " n/a";
  82. }
  83. /* max length to be returned: 14 */
  84. const char *qeth_get_cardname_short(struct qeth_card *card)
  85. {
  86. if (card->info.guestlan) {
  87. switch (card->info.type) {
  88. case QETH_CARD_TYPE_OSD:
  89. return "GuestLAN QDIO";
  90. case QETH_CARD_TYPE_IQD:
  91. return "GuestLAN Hiper";
  92. case QETH_CARD_TYPE_OSM:
  93. return "GuestLAN OSM";
  94. case QETH_CARD_TYPE_OSX:
  95. return "GuestLAN OSX";
  96. default:
  97. return "unknown";
  98. }
  99. } else {
  100. switch (card->info.type) {
  101. case QETH_CARD_TYPE_OSD:
  102. switch (card->info.link_type) {
  103. case QETH_LINK_TYPE_FAST_ETH:
  104. return "OSD_100";
  105. case QETH_LINK_TYPE_HSTR:
  106. return "HSTR";
  107. case QETH_LINK_TYPE_GBIT_ETH:
  108. return "OSD_1000";
  109. case QETH_LINK_TYPE_10GBIT_ETH:
  110. return "OSD_10GIG";
  111. case QETH_LINK_TYPE_LANE_ETH100:
  112. return "OSD_FE_LANE";
  113. case QETH_LINK_TYPE_LANE_TR:
  114. return "OSD_TR_LANE";
  115. case QETH_LINK_TYPE_LANE_ETH1000:
  116. return "OSD_GbE_LANE";
  117. case QETH_LINK_TYPE_LANE:
  118. return "OSD_ATM_LANE";
  119. default:
  120. return "OSD_Express";
  121. }
  122. case QETH_CARD_TYPE_IQD:
  123. return "HiperSockets";
  124. case QETH_CARD_TYPE_OSN:
  125. return "OSN";
  126. case QETH_CARD_TYPE_OSM:
  127. return "OSM_1000";
  128. case QETH_CARD_TYPE_OSX:
  129. return "OSX_10GIG";
  130. default:
  131. return "unknown";
  132. }
  133. }
  134. return "n/a";
  135. }
  136. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  137. int clear_start_mask)
  138. {
  139. unsigned long flags;
  140. spin_lock_irqsave(&card->thread_mask_lock, flags);
  141. card->thread_allowed_mask = threads;
  142. if (clear_start_mask)
  143. card->thread_start_mask &= threads;
  144. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  145. wake_up(&card->wait_q);
  146. }
  147. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  148. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  149. {
  150. unsigned long flags;
  151. int rc = 0;
  152. spin_lock_irqsave(&card->thread_mask_lock, flags);
  153. rc = (card->thread_running_mask & threads);
  154. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  155. return rc;
  156. }
  157. EXPORT_SYMBOL_GPL(qeth_threads_running);
  158. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  159. {
  160. return wait_event_interruptible(card->wait_q,
  161. qeth_threads_running(card, threads) == 0);
  162. }
  163. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  164. void qeth_clear_working_pool_list(struct qeth_card *card)
  165. {
  166. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  167. QETH_CARD_TEXT(card, 5, "clwrklst");
  168. list_for_each_entry_safe(pool_entry, tmp,
  169. &card->qdio.in_buf_pool.entry_list, list){
  170. list_del(&pool_entry->list);
  171. }
  172. }
  173. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  174. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  175. {
  176. struct qeth_buffer_pool_entry *pool_entry;
  177. void *ptr;
  178. int i, j;
  179. QETH_CARD_TEXT(card, 5, "alocpool");
  180. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  181. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  182. if (!pool_entry) {
  183. qeth_free_buffer_pool(card);
  184. return -ENOMEM;
  185. }
  186. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  187. ptr = (void *) __get_free_page(GFP_KERNEL);
  188. if (!ptr) {
  189. while (j > 0)
  190. free_page((unsigned long)
  191. pool_entry->elements[--j]);
  192. kfree(pool_entry);
  193. qeth_free_buffer_pool(card);
  194. return -ENOMEM;
  195. }
  196. pool_entry->elements[j] = ptr;
  197. }
  198. list_add(&pool_entry->init_list,
  199. &card->qdio.init_pool.entry_list);
  200. }
  201. return 0;
  202. }
  203. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  204. {
  205. QETH_CARD_TEXT(card, 2, "realcbp");
  206. if ((card->state != CARD_STATE_DOWN) &&
  207. (card->state != CARD_STATE_RECOVER))
  208. return -EPERM;
  209. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  210. qeth_clear_working_pool_list(card);
  211. qeth_free_buffer_pool(card);
  212. card->qdio.in_buf_pool.buf_count = bufcnt;
  213. card->qdio.init_pool.buf_count = bufcnt;
  214. return qeth_alloc_buffer_pool(card);
  215. }
  216. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  217. static int qeth_issue_next_read(struct qeth_card *card)
  218. {
  219. int rc;
  220. struct qeth_cmd_buffer *iob;
  221. QETH_CARD_TEXT(card, 5, "issnxrd");
  222. if (card->read.state != CH_STATE_UP)
  223. return -EIO;
  224. iob = qeth_get_buffer(&card->read);
  225. if (!iob) {
  226. dev_warn(&card->gdev->dev, "The qeth device driver "
  227. "failed to recover an error on the device\n");
  228. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  229. "available\n", dev_name(&card->gdev->dev));
  230. return -ENOMEM;
  231. }
  232. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  233. QETH_CARD_TEXT(card, 6, "noirqpnd");
  234. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  235. (addr_t) iob, 0, 0);
  236. if (rc) {
  237. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  238. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  239. atomic_set(&card->read.irq_pending, 0);
  240. card->read_or_write_problem = 1;
  241. qeth_schedule_recovery(card);
  242. wake_up(&card->wait_q);
  243. }
  244. return rc;
  245. }
  246. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  247. {
  248. struct qeth_reply *reply;
  249. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  250. if (reply) {
  251. atomic_set(&reply->refcnt, 1);
  252. atomic_set(&reply->received, 0);
  253. reply->card = card;
  254. };
  255. return reply;
  256. }
  257. static void qeth_get_reply(struct qeth_reply *reply)
  258. {
  259. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  260. atomic_inc(&reply->refcnt);
  261. }
  262. static void qeth_put_reply(struct qeth_reply *reply)
  263. {
  264. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  265. if (atomic_dec_and_test(&reply->refcnt))
  266. kfree(reply);
  267. }
  268. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  269. struct qeth_card *card)
  270. {
  271. char *ipa_name;
  272. int com = cmd->hdr.command;
  273. ipa_name = qeth_get_ipa_cmd_name(com);
  274. if (rc)
  275. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  276. ipa_name, com, QETH_CARD_IFNAME(card),
  277. rc, qeth_get_ipa_msg(rc));
  278. else
  279. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  280. ipa_name, com, QETH_CARD_IFNAME(card));
  281. }
  282. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  283. struct qeth_cmd_buffer *iob)
  284. {
  285. struct qeth_ipa_cmd *cmd = NULL;
  286. QETH_CARD_TEXT(card, 5, "chkipad");
  287. if (IS_IPA(iob->data)) {
  288. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  289. if (IS_IPA_REPLY(cmd)) {
  290. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  291. cmd->hdr.command != IPA_CMD_DELCCID &&
  292. cmd->hdr.command != IPA_CMD_MODCCID &&
  293. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  294. qeth_issue_ipa_msg(cmd,
  295. cmd->hdr.return_code, card);
  296. return cmd;
  297. } else {
  298. switch (cmd->hdr.command) {
  299. case IPA_CMD_STOPLAN:
  300. dev_warn(&card->gdev->dev,
  301. "The link for interface %s on CHPID"
  302. " 0x%X failed\n",
  303. QETH_CARD_IFNAME(card),
  304. card->info.chpid);
  305. card->lan_online = 0;
  306. if (card->dev && netif_carrier_ok(card->dev))
  307. netif_carrier_off(card->dev);
  308. return NULL;
  309. case IPA_CMD_STARTLAN:
  310. dev_info(&card->gdev->dev,
  311. "The link for %s on CHPID 0x%X has"
  312. " been restored\n",
  313. QETH_CARD_IFNAME(card),
  314. card->info.chpid);
  315. netif_carrier_on(card->dev);
  316. card->lan_online = 1;
  317. qeth_schedule_recovery(card);
  318. return NULL;
  319. case IPA_CMD_MODCCID:
  320. return cmd;
  321. case IPA_CMD_REGISTER_LOCAL_ADDR:
  322. QETH_CARD_TEXT(card, 3, "irla");
  323. break;
  324. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  325. QETH_CARD_TEXT(card, 3, "urla");
  326. break;
  327. default:
  328. QETH_DBF_MESSAGE(2, "Received data is IPA "
  329. "but not a reply!\n");
  330. break;
  331. }
  332. }
  333. }
  334. return cmd;
  335. }
  336. void qeth_clear_ipacmd_list(struct qeth_card *card)
  337. {
  338. struct qeth_reply *reply, *r;
  339. unsigned long flags;
  340. QETH_CARD_TEXT(card, 4, "clipalst");
  341. spin_lock_irqsave(&card->lock, flags);
  342. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  343. qeth_get_reply(reply);
  344. reply->rc = -EIO;
  345. atomic_inc(&reply->received);
  346. list_del_init(&reply->list);
  347. wake_up(&reply->wait_q);
  348. qeth_put_reply(reply);
  349. }
  350. spin_unlock_irqrestore(&card->lock, flags);
  351. atomic_set(&card->write.irq_pending, 0);
  352. }
  353. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  354. static int qeth_check_idx_response(struct qeth_card *card,
  355. unsigned char *buffer)
  356. {
  357. if (!buffer)
  358. return 0;
  359. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  360. if ((buffer[2] & 0xc0) == 0xc0) {
  361. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  362. "with cause code 0x%02x%s\n",
  363. buffer[4],
  364. ((buffer[4] == 0x22) ?
  365. " -- try another portname" : ""));
  366. QETH_CARD_TEXT(card, 2, "ckidxres");
  367. QETH_CARD_TEXT(card, 2, " idxterm");
  368. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  369. if (buffer[4] == 0xf6) {
  370. dev_err(&card->gdev->dev,
  371. "The qeth device is not configured "
  372. "for the OSI layer required by z/VM\n");
  373. return -EPERM;
  374. }
  375. return -EIO;
  376. }
  377. return 0;
  378. }
  379. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  380. __u32 len)
  381. {
  382. struct qeth_card *card;
  383. card = CARD_FROM_CDEV(channel->ccwdev);
  384. QETH_CARD_TEXT(card, 4, "setupccw");
  385. if (channel == &card->read)
  386. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  387. else
  388. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  389. channel->ccw.count = len;
  390. channel->ccw.cda = (__u32) __pa(iob);
  391. }
  392. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  393. {
  394. __u8 index;
  395. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  396. index = channel->io_buf_no;
  397. do {
  398. if (channel->iob[index].state == BUF_STATE_FREE) {
  399. channel->iob[index].state = BUF_STATE_LOCKED;
  400. channel->io_buf_no = (channel->io_buf_no + 1) %
  401. QETH_CMD_BUFFER_NO;
  402. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  403. return channel->iob + index;
  404. }
  405. index = (index + 1) % QETH_CMD_BUFFER_NO;
  406. } while (index != channel->io_buf_no);
  407. return NULL;
  408. }
  409. void qeth_release_buffer(struct qeth_channel *channel,
  410. struct qeth_cmd_buffer *iob)
  411. {
  412. unsigned long flags;
  413. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  414. spin_lock_irqsave(&channel->iob_lock, flags);
  415. memset(iob->data, 0, QETH_BUFSIZE);
  416. iob->state = BUF_STATE_FREE;
  417. iob->callback = qeth_send_control_data_cb;
  418. iob->rc = 0;
  419. spin_unlock_irqrestore(&channel->iob_lock, flags);
  420. }
  421. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  422. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  423. {
  424. struct qeth_cmd_buffer *buffer = NULL;
  425. unsigned long flags;
  426. spin_lock_irqsave(&channel->iob_lock, flags);
  427. buffer = __qeth_get_buffer(channel);
  428. spin_unlock_irqrestore(&channel->iob_lock, flags);
  429. return buffer;
  430. }
  431. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  432. {
  433. struct qeth_cmd_buffer *buffer;
  434. wait_event(channel->wait_q,
  435. ((buffer = qeth_get_buffer(channel)) != NULL));
  436. return buffer;
  437. }
  438. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  439. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  440. {
  441. int cnt;
  442. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  443. qeth_release_buffer(channel, &channel->iob[cnt]);
  444. channel->buf_no = 0;
  445. channel->io_buf_no = 0;
  446. }
  447. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  448. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  449. struct qeth_cmd_buffer *iob)
  450. {
  451. struct qeth_card *card;
  452. struct qeth_reply *reply, *r;
  453. struct qeth_ipa_cmd *cmd;
  454. unsigned long flags;
  455. int keep_reply;
  456. int rc = 0;
  457. card = CARD_FROM_CDEV(channel->ccwdev);
  458. QETH_CARD_TEXT(card, 4, "sndctlcb");
  459. rc = qeth_check_idx_response(card, iob->data);
  460. switch (rc) {
  461. case 0:
  462. break;
  463. case -EIO:
  464. qeth_clear_ipacmd_list(card);
  465. qeth_schedule_recovery(card);
  466. /* fall through */
  467. default:
  468. goto out;
  469. }
  470. cmd = qeth_check_ipa_data(card, iob);
  471. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  472. goto out;
  473. /*in case of OSN : check if cmd is set */
  474. if (card->info.type == QETH_CARD_TYPE_OSN &&
  475. cmd &&
  476. cmd->hdr.command != IPA_CMD_STARTLAN &&
  477. card->osn_info.assist_cb != NULL) {
  478. card->osn_info.assist_cb(card->dev, cmd);
  479. goto out;
  480. }
  481. spin_lock_irqsave(&card->lock, flags);
  482. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  483. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  484. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  485. qeth_get_reply(reply);
  486. list_del_init(&reply->list);
  487. spin_unlock_irqrestore(&card->lock, flags);
  488. keep_reply = 0;
  489. if (reply->callback != NULL) {
  490. if (cmd) {
  491. reply->offset = (__u16)((char *)cmd -
  492. (char *)iob->data);
  493. keep_reply = reply->callback(card,
  494. reply,
  495. (unsigned long)cmd);
  496. } else
  497. keep_reply = reply->callback(card,
  498. reply,
  499. (unsigned long)iob);
  500. }
  501. if (cmd)
  502. reply->rc = (u16) cmd->hdr.return_code;
  503. else if (iob->rc)
  504. reply->rc = iob->rc;
  505. if (keep_reply) {
  506. spin_lock_irqsave(&card->lock, flags);
  507. list_add_tail(&reply->list,
  508. &card->cmd_waiter_list);
  509. spin_unlock_irqrestore(&card->lock, flags);
  510. } else {
  511. atomic_inc(&reply->received);
  512. wake_up(&reply->wait_q);
  513. }
  514. qeth_put_reply(reply);
  515. goto out;
  516. }
  517. }
  518. spin_unlock_irqrestore(&card->lock, flags);
  519. out:
  520. memcpy(&card->seqno.pdu_hdr_ack,
  521. QETH_PDU_HEADER_SEQ_NO(iob->data),
  522. QETH_SEQ_NO_LENGTH);
  523. qeth_release_buffer(channel, iob);
  524. }
  525. static int qeth_setup_channel(struct qeth_channel *channel)
  526. {
  527. int cnt;
  528. QETH_DBF_TEXT(SETUP, 2, "setupch");
  529. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  530. channel->iob[cnt].data =
  531. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  532. if (channel->iob[cnt].data == NULL)
  533. break;
  534. channel->iob[cnt].state = BUF_STATE_FREE;
  535. channel->iob[cnt].channel = channel;
  536. channel->iob[cnt].callback = qeth_send_control_data_cb;
  537. channel->iob[cnt].rc = 0;
  538. }
  539. if (cnt < QETH_CMD_BUFFER_NO) {
  540. while (cnt-- > 0)
  541. kfree(channel->iob[cnt].data);
  542. return -ENOMEM;
  543. }
  544. channel->buf_no = 0;
  545. channel->io_buf_no = 0;
  546. atomic_set(&channel->irq_pending, 0);
  547. spin_lock_init(&channel->iob_lock);
  548. init_waitqueue_head(&channel->wait_q);
  549. return 0;
  550. }
  551. static int qeth_set_thread_start_bit(struct qeth_card *card,
  552. unsigned long thread)
  553. {
  554. unsigned long flags;
  555. spin_lock_irqsave(&card->thread_mask_lock, flags);
  556. if (!(card->thread_allowed_mask & thread) ||
  557. (card->thread_start_mask & thread)) {
  558. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  559. return -EPERM;
  560. }
  561. card->thread_start_mask |= thread;
  562. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  563. return 0;
  564. }
  565. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  566. {
  567. unsigned long flags;
  568. spin_lock_irqsave(&card->thread_mask_lock, flags);
  569. card->thread_start_mask &= ~thread;
  570. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  571. wake_up(&card->wait_q);
  572. }
  573. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  574. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  575. {
  576. unsigned long flags;
  577. spin_lock_irqsave(&card->thread_mask_lock, flags);
  578. card->thread_running_mask &= ~thread;
  579. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  580. wake_up(&card->wait_q);
  581. }
  582. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  583. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  584. {
  585. unsigned long flags;
  586. int rc = 0;
  587. spin_lock_irqsave(&card->thread_mask_lock, flags);
  588. if (card->thread_start_mask & thread) {
  589. if ((card->thread_allowed_mask & thread) &&
  590. !(card->thread_running_mask & thread)) {
  591. rc = 1;
  592. card->thread_start_mask &= ~thread;
  593. card->thread_running_mask |= thread;
  594. } else
  595. rc = -EPERM;
  596. }
  597. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  598. return rc;
  599. }
  600. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  601. {
  602. int rc = 0;
  603. wait_event(card->wait_q,
  604. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  605. return rc;
  606. }
  607. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  608. void qeth_schedule_recovery(struct qeth_card *card)
  609. {
  610. QETH_CARD_TEXT(card, 2, "startrec");
  611. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  612. schedule_work(&card->kernel_thread_starter);
  613. }
  614. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  615. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  616. {
  617. int dstat, cstat;
  618. char *sense;
  619. struct qeth_card *card;
  620. sense = (char *) irb->ecw;
  621. cstat = irb->scsw.cmd.cstat;
  622. dstat = irb->scsw.cmd.dstat;
  623. card = CARD_FROM_CDEV(cdev);
  624. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  625. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  626. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  627. QETH_CARD_TEXT(card, 2, "CGENCHK");
  628. dev_warn(&cdev->dev, "The qeth device driver "
  629. "failed to recover an error on the device\n");
  630. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  631. dev_name(&cdev->dev), dstat, cstat);
  632. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  633. 16, 1, irb, 64, 1);
  634. return 1;
  635. }
  636. if (dstat & DEV_STAT_UNIT_CHECK) {
  637. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  638. SENSE_RESETTING_EVENT_FLAG) {
  639. QETH_CARD_TEXT(card, 2, "REVIND");
  640. return 1;
  641. }
  642. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  643. SENSE_COMMAND_REJECT_FLAG) {
  644. QETH_CARD_TEXT(card, 2, "CMDREJi");
  645. return 1;
  646. }
  647. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  648. QETH_CARD_TEXT(card, 2, "AFFE");
  649. return 1;
  650. }
  651. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  652. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  653. return 0;
  654. }
  655. QETH_CARD_TEXT(card, 2, "DGENCHK");
  656. return 1;
  657. }
  658. return 0;
  659. }
  660. static long __qeth_check_irb_error(struct ccw_device *cdev,
  661. unsigned long intparm, struct irb *irb)
  662. {
  663. struct qeth_card *card;
  664. card = CARD_FROM_CDEV(cdev);
  665. if (!IS_ERR(irb))
  666. return 0;
  667. switch (PTR_ERR(irb)) {
  668. case -EIO:
  669. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  670. dev_name(&cdev->dev));
  671. QETH_CARD_TEXT(card, 2, "ckirberr");
  672. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  673. break;
  674. case -ETIMEDOUT:
  675. dev_warn(&cdev->dev, "A hardware operation timed out"
  676. " on the device\n");
  677. QETH_CARD_TEXT(card, 2, "ckirberr");
  678. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  679. if (intparm == QETH_RCD_PARM) {
  680. if (card && (card->data.ccwdev == cdev)) {
  681. card->data.state = CH_STATE_DOWN;
  682. wake_up(&card->wait_q);
  683. }
  684. }
  685. break;
  686. default:
  687. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  688. dev_name(&cdev->dev), PTR_ERR(irb));
  689. QETH_CARD_TEXT(card, 2, "ckirberr");
  690. QETH_CARD_TEXT(card, 2, " rc???");
  691. }
  692. return PTR_ERR(irb);
  693. }
  694. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  695. struct irb *irb)
  696. {
  697. int rc;
  698. int cstat, dstat;
  699. struct qeth_cmd_buffer *buffer;
  700. struct qeth_channel *channel;
  701. struct qeth_card *card;
  702. struct qeth_cmd_buffer *iob;
  703. __u8 index;
  704. if (__qeth_check_irb_error(cdev, intparm, irb))
  705. return;
  706. cstat = irb->scsw.cmd.cstat;
  707. dstat = irb->scsw.cmd.dstat;
  708. card = CARD_FROM_CDEV(cdev);
  709. if (!card)
  710. return;
  711. QETH_CARD_TEXT(card, 5, "irq");
  712. if (card->read.ccwdev == cdev) {
  713. channel = &card->read;
  714. QETH_CARD_TEXT(card, 5, "read");
  715. } else if (card->write.ccwdev == cdev) {
  716. channel = &card->write;
  717. QETH_CARD_TEXT(card, 5, "write");
  718. } else {
  719. channel = &card->data;
  720. QETH_CARD_TEXT(card, 5, "data");
  721. }
  722. atomic_set(&channel->irq_pending, 0);
  723. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  724. channel->state = CH_STATE_STOPPED;
  725. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  726. channel->state = CH_STATE_HALTED;
  727. /*let's wake up immediately on data channel*/
  728. if ((channel == &card->data) && (intparm != 0) &&
  729. (intparm != QETH_RCD_PARM))
  730. goto out;
  731. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  732. QETH_CARD_TEXT(card, 6, "clrchpar");
  733. /* we don't have to handle this further */
  734. intparm = 0;
  735. }
  736. if (intparm == QETH_HALT_CHANNEL_PARM) {
  737. QETH_CARD_TEXT(card, 6, "hltchpar");
  738. /* we don't have to handle this further */
  739. intparm = 0;
  740. }
  741. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  742. (dstat & DEV_STAT_UNIT_CHECK) ||
  743. (cstat)) {
  744. if (irb->esw.esw0.erw.cons) {
  745. dev_warn(&channel->ccwdev->dev,
  746. "The qeth device driver failed to recover "
  747. "an error on the device\n");
  748. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  749. "0x%X dstat 0x%X\n",
  750. dev_name(&channel->ccwdev->dev), cstat, dstat);
  751. print_hex_dump(KERN_WARNING, "qeth: irb ",
  752. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  753. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  754. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  755. }
  756. if (intparm == QETH_RCD_PARM) {
  757. channel->state = CH_STATE_DOWN;
  758. goto out;
  759. }
  760. rc = qeth_get_problem(cdev, irb);
  761. if (rc) {
  762. qeth_clear_ipacmd_list(card);
  763. qeth_schedule_recovery(card);
  764. goto out;
  765. }
  766. }
  767. if (intparm == QETH_RCD_PARM) {
  768. channel->state = CH_STATE_RCD_DONE;
  769. goto out;
  770. }
  771. if (intparm) {
  772. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  773. buffer->state = BUF_STATE_PROCESSED;
  774. }
  775. if (channel == &card->data)
  776. return;
  777. if (channel == &card->read &&
  778. channel->state == CH_STATE_UP)
  779. qeth_issue_next_read(card);
  780. iob = channel->iob;
  781. index = channel->buf_no;
  782. while (iob[index].state == BUF_STATE_PROCESSED) {
  783. if (iob[index].callback != NULL)
  784. iob[index].callback(channel, iob + index);
  785. index = (index + 1) % QETH_CMD_BUFFER_NO;
  786. }
  787. channel->buf_no = index;
  788. out:
  789. wake_up(&card->wait_q);
  790. return;
  791. }
  792. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  793. struct qeth_qdio_out_buffer *buf)
  794. {
  795. int i;
  796. struct sk_buff *skb;
  797. /* is PCI flag set on buffer? */
  798. if (buf->buffer->element[0].flags & 0x40)
  799. atomic_dec(&queue->set_pci_flags_count);
  800. skb = skb_dequeue(&buf->skb_list);
  801. while (skb) {
  802. atomic_dec(&skb->users);
  803. dev_kfree_skb_any(skb);
  804. skb = skb_dequeue(&buf->skb_list);
  805. }
  806. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  807. if (buf->buffer->element[i].addr && buf->is_header[i])
  808. kmem_cache_free(qeth_core_header_cache,
  809. buf->buffer->element[i].addr);
  810. buf->is_header[i] = 0;
  811. buf->buffer->element[i].length = 0;
  812. buf->buffer->element[i].addr = NULL;
  813. buf->buffer->element[i].flags = 0;
  814. }
  815. buf->buffer->element[15].flags = 0;
  816. buf->next_element_to_fill = 0;
  817. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  818. }
  819. void qeth_clear_qdio_buffers(struct qeth_card *card)
  820. {
  821. int i, j;
  822. QETH_CARD_TEXT(card, 2, "clearqdbf");
  823. /* clear outbound buffers to free skbs */
  824. for (i = 0; i < card->qdio.no_out_queues; ++i)
  825. if (card->qdio.out_qs[i]) {
  826. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  827. qeth_clear_output_buffer(card->qdio.out_qs[i],
  828. &card->qdio.out_qs[i]->bufs[j]);
  829. }
  830. }
  831. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  832. static void qeth_free_buffer_pool(struct qeth_card *card)
  833. {
  834. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  835. int i = 0;
  836. list_for_each_entry_safe(pool_entry, tmp,
  837. &card->qdio.init_pool.entry_list, init_list){
  838. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  839. free_page((unsigned long)pool_entry->elements[i]);
  840. list_del(&pool_entry->init_list);
  841. kfree(pool_entry);
  842. }
  843. }
  844. static void qeth_free_qdio_buffers(struct qeth_card *card)
  845. {
  846. int i, j;
  847. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  848. QETH_QDIO_UNINITIALIZED)
  849. return;
  850. kfree(card->qdio.in_q);
  851. card->qdio.in_q = NULL;
  852. /* inbound buffer pool */
  853. qeth_free_buffer_pool(card);
  854. /* free outbound qdio_qs */
  855. if (card->qdio.out_qs) {
  856. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  857. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  858. qeth_clear_output_buffer(card->qdio.out_qs[i],
  859. &card->qdio.out_qs[i]->bufs[j]);
  860. kfree(card->qdio.out_qs[i]);
  861. }
  862. kfree(card->qdio.out_qs);
  863. card->qdio.out_qs = NULL;
  864. }
  865. }
  866. static void qeth_clean_channel(struct qeth_channel *channel)
  867. {
  868. int cnt;
  869. QETH_DBF_TEXT(SETUP, 2, "freech");
  870. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  871. kfree(channel->iob[cnt].data);
  872. }
  873. static void qeth_get_channel_path_desc(struct qeth_card *card)
  874. {
  875. struct ccw_device *ccwdev;
  876. struct channelPath_dsc {
  877. u8 flags;
  878. u8 lsn;
  879. u8 desc;
  880. u8 chpid;
  881. u8 swla;
  882. u8 zeroes;
  883. u8 chla;
  884. u8 chpp;
  885. } *chp_dsc;
  886. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  887. ccwdev = card->data.ccwdev;
  888. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  889. if (chp_dsc != NULL) {
  890. /* CHPP field bit 6 == 1 -> single queue */
  891. if ((chp_dsc->chpp & 0x02) == 0x02) {
  892. if ((atomic_read(&card->qdio.state) !=
  893. QETH_QDIO_UNINITIALIZED) &&
  894. (card->qdio.no_out_queues == 4))
  895. /* change from 4 to 1 outbound queues */
  896. qeth_free_qdio_buffers(card);
  897. card->qdio.no_out_queues = 1;
  898. if (card->qdio.default_out_queue != 0)
  899. dev_info(&card->gdev->dev,
  900. "Priority Queueing not supported\n");
  901. card->qdio.default_out_queue = 0;
  902. } else {
  903. if ((atomic_read(&card->qdio.state) !=
  904. QETH_QDIO_UNINITIALIZED) &&
  905. (card->qdio.no_out_queues == 1)) {
  906. /* change from 1 to 4 outbound queues */
  907. qeth_free_qdio_buffers(card);
  908. card->qdio.default_out_queue = 2;
  909. }
  910. card->qdio.no_out_queues = 4;
  911. }
  912. card->info.func_level = 0x4100 + chp_dsc->desc;
  913. kfree(chp_dsc);
  914. }
  915. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  916. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  917. return;
  918. }
  919. static void qeth_init_qdio_info(struct qeth_card *card)
  920. {
  921. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  922. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  923. /* inbound */
  924. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  925. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  926. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  927. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  928. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  929. }
  930. static void qeth_set_intial_options(struct qeth_card *card)
  931. {
  932. card->options.route4.type = NO_ROUTER;
  933. card->options.route6.type = NO_ROUTER;
  934. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  935. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  936. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  937. card->options.fake_broadcast = 0;
  938. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  939. card->options.performance_stats = 0;
  940. card->options.rx_sg_cb = QETH_RX_SG_CB;
  941. card->options.isolation = ISOLATION_MODE_NONE;
  942. }
  943. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  944. {
  945. unsigned long flags;
  946. int rc = 0;
  947. spin_lock_irqsave(&card->thread_mask_lock, flags);
  948. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  949. (u8) card->thread_start_mask,
  950. (u8) card->thread_allowed_mask,
  951. (u8) card->thread_running_mask);
  952. rc = (card->thread_start_mask & thread);
  953. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  954. return rc;
  955. }
  956. static void qeth_start_kernel_thread(struct work_struct *work)
  957. {
  958. struct qeth_card *card = container_of(work, struct qeth_card,
  959. kernel_thread_starter);
  960. QETH_CARD_TEXT(card , 2, "strthrd");
  961. if (card->read.state != CH_STATE_UP &&
  962. card->write.state != CH_STATE_UP)
  963. return;
  964. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  965. kthread_run(card->discipline.recover, (void *) card,
  966. "qeth_recover");
  967. }
  968. static int qeth_setup_card(struct qeth_card *card)
  969. {
  970. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  971. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  972. card->read.state = CH_STATE_DOWN;
  973. card->write.state = CH_STATE_DOWN;
  974. card->data.state = CH_STATE_DOWN;
  975. card->state = CARD_STATE_DOWN;
  976. card->lan_online = 0;
  977. card->use_hard_stop = 0;
  978. card->read_or_write_problem = 0;
  979. card->dev = NULL;
  980. spin_lock_init(&card->vlanlock);
  981. spin_lock_init(&card->mclock);
  982. card->vlangrp = NULL;
  983. spin_lock_init(&card->lock);
  984. spin_lock_init(&card->ip_lock);
  985. spin_lock_init(&card->thread_mask_lock);
  986. mutex_init(&card->conf_mutex);
  987. mutex_init(&card->discipline_mutex);
  988. card->thread_start_mask = 0;
  989. card->thread_allowed_mask = 0;
  990. card->thread_running_mask = 0;
  991. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  992. INIT_LIST_HEAD(&card->ip_list);
  993. INIT_LIST_HEAD(card->ip_tbd_list);
  994. INIT_LIST_HEAD(&card->cmd_waiter_list);
  995. init_waitqueue_head(&card->wait_q);
  996. /* intial options */
  997. qeth_set_intial_options(card);
  998. /* IP address takeover */
  999. INIT_LIST_HEAD(&card->ipato.entries);
  1000. card->ipato.enabled = 0;
  1001. card->ipato.invert4 = 0;
  1002. card->ipato.invert6 = 0;
  1003. /* init QDIO stuff */
  1004. qeth_init_qdio_info(card);
  1005. return 0;
  1006. }
  1007. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1008. {
  1009. struct qeth_card *card = container_of(slr, struct qeth_card,
  1010. qeth_service_level);
  1011. if (card->info.mcl_level[0])
  1012. seq_printf(m, "qeth: %s firmware level %s\n",
  1013. CARD_BUS_ID(card), card->info.mcl_level);
  1014. }
  1015. static struct qeth_card *qeth_alloc_card(void)
  1016. {
  1017. struct qeth_card *card;
  1018. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1019. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1020. if (!card)
  1021. goto out;
  1022. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1023. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1024. if (!card->ip_tbd_list) {
  1025. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1026. goto out_card;
  1027. }
  1028. if (qeth_setup_channel(&card->read))
  1029. goto out_ip;
  1030. if (qeth_setup_channel(&card->write))
  1031. goto out_channel;
  1032. card->options.layer2 = -1;
  1033. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1034. register_service_level(&card->qeth_service_level);
  1035. return card;
  1036. out_channel:
  1037. qeth_clean_channel(&card->read);
  1038. out_ip:
  1039. kfree(card->ip_tbd_list);
  1040. out_card:
  1041. kfree(card);
  1042. out:
  1043. return NULL;
  1044. }
  1045. static int qeth_determine_card_type(struct qeth_card *card)
  1046. {
  1047. int i = 0;
  1048. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1049. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1050. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1051. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1052. if ((CARD_RDEV(card)->id.dev_type ==
  1053. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1054. (CARD_RDEV(card)->id.dev_model ==
  1055. known_devices[i][QETH_DEV_MODEL_IND])) {
  1056. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1057. card->qdio.no_out_queues =
  1058. known_devices[i][QETH_QUEUE_NO_IND];
  1059. card->info.is_multicast_different =
  1060. known_devices[i][QETH_MULTICAST_IND];
  1061. qeth_get_channel_path_desc(card);
  1062. return 0;
  1063. }
  1064. i++;
  1065. }
  1066. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1067. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1068. "unknown type\n");
  1069. return -ENOENT;
  1070. }
  1071. static int qeth_clear_channel(struct qeth_channel *channel)
  1072. {
  1073. unsigned long flags;
  1074. struct qeth_card *card;
  1075. int rc;
  1076. card = CARD_FROM_CDEV(channel->ccwdev);
  1077. QETH_CARD_TEXT(card, 3, "clearch");
  1078. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1079. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1080. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1081. if (rc)
  1082. return rc;
  1083. rc = wait_event_interruptible_timeout(card->wait_q,
  1084. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1085. if (rc == -ERESTARTSYS)
  1086. return rc;
  1087. if (channel->state != CH_STATE_STOPPED)
  1088. return -ETIME;
  1089. channel->state = CH_STATE_DOWN;
  1090. return 0;
  1091. }
  1092. static int qeth_halt_channel(struct qeth_channel *channel)
  1093. {
  1094. unsigned long flags;
  1095. struct qeth_card *card;
  1096. int rc;
  1097. card = CARD_FROM_CDEV(channel->ccwdev);
  1098. QETH_CARD_TEXT(card, 3, "haltch");
  1099. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1100. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1101. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1102. if (rc)
  1103. return rc;
  1104. rc = wait_event_interruptible_timeout(card->wait_q,
  1105. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1106. if (rc == -ERESTARTSYS)
  1107. return rc;
  1108. if (channel->state != CH_STATE_HALTED)
  1109. return -ETIME;
  1110. return 0;
  1111. }
  1112. static int qeth_halt_channels(struct qeth_card *card)
  1113. {
  1114. int rc1 = 0, rc2 = 0, rc3 = 0;
  1115. QETH_CARD_TEXT(card, 3, "haltchs");
  1116. rc1 = qeth_halt_channel(&card->read);
  1117. rc2 = qeth_halt_channel(&card->write);
  1118. rc3 = qeth_halt_channel(&card->data);
  1119. if (rc1)
  1120. return rc1;
  1121. if (rc2)
  1122. return rc2;
  1123. return rc3;
  1124. }
  1125. static int qeth_clear_channels(struct qeth_card *card)
  1126. {
  1127. int rc1 = 0, rc2 = 0, rc3 = 0;
  1128. QETH_CARD_TEXT(card, 3, "clearchs");
  1129. rc1 = qeth_clear_channel(&card->read);
  1130. rc2 = qeth_clear_channel(&card->write);
  1131. rc3 = qeth_clear_channel(&card->data);
  1132. if (rc1)
  1133. return rc1;
  1134. if (rc2)
  1135. return rc2;
  1136. return rc3;
  1137. }
  1138. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1139. {
  1140. int rc = 0;
  1141. QETH_CARD_TEXT(card, 3, "clhacrd");
  1142. if (halt)
  1143. rc = qeth_halt_channels(card);
  1144. if (rc)
  1145. return rc;
  1146. return qeth_clear_channels(card);
  1147. }
  1148. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1149. {
  1150. int rc = 0;
  1151. QETH_CARD_TEXT(card, 3, "qdioclr");
  1152. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1153. QETH_QDIO_CLEANING)) {
  1154. case QETH_QDIO_ESTABLISHED:
  1155. if (card->info.type == QETH_CARD_TYPE_IQD)
  1156. rc = qdio_shutdown(CARD_DDEV(card),
  1157. QDIO_FLAG_CLEANUP_USING_HALT);
  1158. else
  1159. rc = qdio_shutdown(CARD_DDEV(card),
  1160. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1161. if (rc)
  1162. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1163. qdio_free(CARD_DDEV(card));
  1164. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1165. break;
  1166. case QETH_QDIO_CLEANING:
  1167. return rc;
  1168. default:
  1169. break;
  1170. }
  1171. rc = qeth_clear_halt_card(card, use_halt);
  1172. if (rc)
  1173. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1174. card->state = CARD_STATE_DOWN;
  1175. return rc;
  1176. }
  1177. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1178. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1179. int *length)
  1180. {
  1181. struct ciw *ciw;
  1182. char *rcd_buf;
  1183. int ret;
  1184. struct qeth_channel *channel = &card->data;
  1185. unsigned long flags;
  1186. /*
  1187. * scan for RCD command in extended SenseID data
  1188. */
  1189. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1190. if (!ciw || ciw->cmd == 0)
  1191. return -EOPNOTSUPP;
  1192. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1193. if (!rcd_buf)
  1194. return -ENOMEM;
  1195. channel->ccw.cmd_code = ciw->cmd;
  1196. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1197. channel->ccw.count = ciw->count;
  1198. channel->ccw.flags = CCW_FLAG_SLI;
  1199. channel->state = CH_STATE_RCD;
  1200. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1201. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1202. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1203. QETH_RCD_TIMEOUT);
  1204. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1205. if (!ret)
  1206. wait_event(card->wait_q,
  1207. (channel->state == CH_STATE_RCD_DONE ||
  1208. channel->state == CH_STATE_DOWN));
  1209. if (channel->state == CH_STATE_DOWN)
  1210. ret = -EIO;
  1211. else
  1212. channel->state = CH_STATE_DOWN;
  1213. if (ret) {
  1214. kfree(rcd_buf);
  1215. *buffer = NULL;
  1216. *length = 0;
  1217. } else {
  1218. *length = ciw->count;
  1219. *buffer = rcd_buf;
  1220. }
  1221. return ret;
  1222. }
  1223. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1224. {
  1225. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1226. card->info.chpid = prcd[30];
  1227. card->info.unit_addr2 = prcd[31];
  1228. card->info.cula = prcd[63];
  1229. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1230. (prcd[0x11] == _ascebc['M']));
  1231. }
  1232. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1233. {
  1234. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1235. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1236. card->info.blkt.time_total = 250;
  1237. card->info.blkt.inter_packet = 5;
  1238. card->info.blkt.inter_packet_jumbo = 15;
  1239. } else {
  1240. card->info.blkt.time_total = 0;
  1241. card->info.blkt.inter_packet = 0;
  1242. card->info.blkt.inter_packet_jumbo = 0;
  1243. }
  1244. }
  1245. static void qeth_init_tokens(struct qeth_card *card)
  1246. {
  1247. card->token.issuer_rm_w = 0x00010103UL;
  1248. card->token.cm_filter_w = 0x00010108UL;
  1249. card->token.cm_connection_w = 0x0001010aUL;
  1250. card->token.ulp_filter_w = 0x0001010bUL;
  1251. card->token.ulp_connection_w = 0x0001010dUL;
  1252. }
  1253. static void qeth_init_func_level(struct qeth_card *card)
  1254. {
  1255. switch (card->info.type) {
  1256. case QETH_CARD_TYPE_IQD:
  1257. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1258. break;
  1259. case QETH_CARD_TYPE_OSD:
  1260. case QETH_CARD_TYPE_OSN:
  1261. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1262. break;
  1263. default:
  1264. break;
  1265. }
  1266. }
  1267. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1268. void (*idx_reply_cb)(struct qeth_channel *,
  1269. struct qeth_cmd_buffer *))
  1270. {
  1271. struct qeth_cmd_buffer *iob;
  1272. unsigned long flags;
  1273. int rc;
  1274. struct qeth_card *card;
  1275. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1276. card = CARD_FROM_CDEV(channel->ccwdev);
  1277. iob = qeth_get_buffer(channel);
  1278. iob->callback = idx_reply_cb;
  1279. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1280. channel->ccw.count = QETH_BUFSIZE;
  1281. channel->ccw.cda = (__u32) __pa(iob->data);
  1282. wait_event(card->wait_q,
  1283. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1284. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1285. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1286. rc = ccw_device_start(channel->ccwdev,
  1287. &channel->ccw, (addr_t) iob, 0, 0);
  1288. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1289. if (rc) {
  1290. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1291. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1292. atomic_set(&channel->irq_pending, 0);
  1293. wake_up(&card->wait_q);
  1294. return rc;
  1295. }
  1296. rc = wait_event_interruptible_timeout(card->wait_q,
  1297. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1298. if (rc == -ERESTARTSYS)
  1299. return rc;
  1300. if (channel->state != CH_STATE_UP) {
  1301. rc = -ETIME;
  1302. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1303. qeth_clear_cmd_buffers(channel);
  1304. } else
  1305. rc = 0;
  1306. return rc;
  1307. }
  1308. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1309. void (*idx_reply_cb)(struct qeth_channel *,
  1310. struct qeth_cmd_buffer *))
  1311. {
  1312. struct qeth_card *card;
  1313. struct qeth_cmd_buffer *iob;
  1314. unsigned long flags;
  1315. __u16 temp;
  1316. __u8 tmp;
  1317. int rc;
  1318. struct ccw_dev_id temp_devid;
  1319. card = CARD_FROM_CDEV(channel->ccwdev);
  1320. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1321. iob = qeth_get_buffer(channel);
  1322. iob->callback = idx_reply_cb;
  1323. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1324. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1325. channel->ccw.cda = (__u32) __pa(iob->data);
  1326. if (channel == &card->write) {
  1327. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1328. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1329. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1330. card->seqno.trans_hdr++;
  1331. } else {
  1332. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1333. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1334. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1335. }
  1336. tmp = ((__u8)card->info.portno) | 0x80;
  1337. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1338. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1339. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1340. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1341. &card->info.func_level, sizeof(__u16));
  1342. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1343. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1344. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1345. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1346. wait_event(card->wait_q,
  1347. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1348. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1349. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1350. rc = ccw_device_start(channel->ccwdev,
  1351. &channel->ccw, (addr_t) iob, 0, 0);
  1352. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1353. if (rc) {
  1354. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1355. rc);
  1356. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1357. atomic_set(&channel->irq_pending, 0);
  1358. wake_up(&card->wait_q);
  1359. return rc;
  1360. }
  1361. rc = wait_event_interruptible_timeout(card->wait_q,
  1362. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1363. if (rc == -ERESTARTSYS)
  1364. return rc;
  1365. if (channel->state != CH_STATE_ACTIVATING) {
  1366. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1367. " failed to recover an error on the device\n");
  1368. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1369. dev_name(&channel->ccwdev->dev));
  1370. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1371. qeth_clear_cmd_buffers(channel);
  1372. return -ETIME;
  1373. }
  1374. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1375. }
  1376. static int qeth_peer_func_level(int level)
  1377. {
  1378. if ((level & 0xff) == 8)
  1379. return (level & 0xff) + 0x400;
  1380. if (((level >> 8) & 3) == 1)
  1381. return (level & 0xff) + 0x200;
  1382. return level;
  1383. }
  1384. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1385. struct qeth_cmd_buffer *iob)
  1386. {
  1387. struct qeth_card *card;
  1388. __u16 temp;
  1389. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1390. if (channel->state == CH_STATE_DOWN) {
  1391. channel->state = CH_STATE_ACTIVATING;
  1392. goto out;
  1393. }
  1394. card = CARD_FROM_CDEV(channel->ccwdev);
  1395. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1396. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1397. dev_err(&card->write.ccwdev->dev,
  1398. "The adapter is used exclusively by another "
  1399. "host\n");
  1400. else
  1401. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1402. " negative reply\n",
  1403. dev_name(&card->write.ccwdev->dev));
  1404. goto out;
  1405. }
  1406. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1407. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1408. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1409. "function level mismatch (sent: 0x%x, received: "
  1410. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1411. card->info.func_level, temp);
  1412. goto out;
  1413. }
  1414. channel->state = CH_STATE_UP;
  1415. out:
  1416. qeth_release_buffer(channel, iob);
  1417. }
  1418. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1419. struct qeth_cmd_buffer *iob)
  1420. {
  1421. struct qeth_card *card;
  1422. __u16 temp;
  1423. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1424. if (channel->state == CH_STATE_DOWN) {
  1425. channel->state = CH_STATE_ACTIVATING;
  1426. goto out;
  1427. }
  1428. card = CARD_FROM_CDEV(channel->ccwdev);
  1429. if (qeth_check_idx_response(card, iob->data))
  1430. goto out;
  1431. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1432. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1433. case QETH_IDX_ACT_ERR_EXCL:
  1434. dev_err(&card->write.ccwdev->dev,
  1435. "The adapter is used exclusively by another "
  1436. "host\n");
  1437. break;
  1438. case QETH_IDX_ACT_ERR_AUTH:
  1439. case QETH_IDX_ACT_ERR_AUTH_USER:
  1440. dev_err(&card->read.ccwdev->dev,
  1441. "Setting the device online failed because of "
  1442. "insufficient authorization\n");
  1443. break;
  1444. default:
  1445. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1446. " negative reply\n",
  1447. dev_name(&card->read.ccwdev->dev));
  1448. }
  1449. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1450. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1451. goto out;
  1452. }
  1453. /**
  1454. * * temporary fix for microcode bug
  1455. * * to revert it,replace OR by AND
  1456. * */
  1457. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1458. (card->info.type == QETH_CARD_TYPE_OSD))
  1459. card->info.portname_required = 1;
  1460. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1461. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1462. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1463. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1464. dev_name(&card->read.ccwdev->dev),
  1465. card->info.func_level, temp);
  1466. goto out;
  1467. }
  1468. memcpy(&card->token.issuer_rm_r,
  1469. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1470. QETH_MPC_TOKEN_LENGTH);
  1471. memcpy(&card->info.mcl_level[0],
  1472. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1473. channel->state = CH_STATE_UP;
  1474. out:
  1475. qeth_release_buffer(channel, iob);
  1476. }
  1477. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1478. struct qeth_cmd_buffer *iob)
  1479. {
  1480. qeth_setup_ccw(&card->write, iob->data, len);
  1481. iob->callback = qeth_release_buffer;
  1482. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1483. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1484. card->seqno.trans_hdr++;
  1485. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1486. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1487. card->seqno.pdu_hdr++;
  1488. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1489. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1490. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1491. }
  1492. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1493. int qeth_send_control_data(struct qeth_card *card, int len,
  1494. struct qeth_cmd_buffer *iob,
  1495. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1496. unsigned long),
  1497. void *reply_param)
  1498. {
  1499. int rc;
  1500. unsigned long flags;
  1501. struct qeth_reply *reply = NULL;
  1502. unsigned long timeout, event_timeout;
  1503. struct qeth_ipa_cmd *cmd;
  1504. QETH_CARD_TEXT(card, 2, "sendctl");
  1505. if (card->read_or_write_problem) {
  1506. qeth_release_buffer(iob->channel, iob);
  1507. return -EIO;
  1508. }
  1509. reply = qeth_alloc_reply(card);
  1510. if (!reply) {
  1511. return -ENOMEM;
  1512. }
  1513. reply->callback = reply_cb;
  1514. reply->param = reply_param;
  1515. if (card->state == CARD_STATE_DOWN)
  1516. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1517. else
  1518. reply->seqno = card->seqno.ipa++;
  1519. init_waitqueue_head(&reply->wait_q);
  1520. spin_lock_irqsave(&card->lock, flags);
  1521. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1522. spin_unlock_irqrestore(&card->lock, flags);
  1523. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1524. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1525. qeth_prepare_control_data(card, len, iob);
  1526. if (IS_IPA(iob->data))
  1527. event_timeout = QETH_IPA_TIMEOUT;
  1528. else
  1529. event_timeout = QETH_TIMEOUT;
  1530. timeout = jiffies + event_timeout;
  1531. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1532. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1533. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1534. (addr_t) iob, 0, 0);
  1535. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1536. if (rc) {
  1537. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1538. "ccw_device_start rc = %i\n",
  1539. dev_name(&card->write.ccwdev->dev), rc);
  1540. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1541. spin_lock_irqsave(&card->lock, flags);
  1542. list_del_init(&reply->list);
  1543. qeth_put_reply(reply);
  1544. spin_unlock_irqrestore(&card->lock, flags);
  1545. qeth_release_buffer(iob->channel, iob);
  1546. atomic_set(&card->write.irq_pending, 0);
  1547. wake_up(&card->wait_q);
  1548. return rc;
  1549. }
  1550. /* we have only one long running ipassist, since we can ensure
  1551. process context of this command we can sleep */
  1552. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1553. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1554. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1555. if (!wait_event_timeout(reply->wait_q,
  1556. atomic_read(&reply->received), event_timeout))
  1557. goto time_err;
  1558. } else {
  1559. while (!atomic_read(&reply->received)) {
  1560. if (time_after(jiffies, timeout))
  1561. goto time_err;
  1562. cpu_relax();
  1563. };
  1564. }
  1565. rc = reply->rc;
  1566. qeth_put_reply(reply);
  1567. return rc;
  1568. time_err:
  1569. spin_lock_irqsave(&reply->card->lock, flags);
  1570. list_del_init(&reply->list);
  1571. spin_unlock_irqrestore(&reply->card->lock, flags);
  1572. reply->rc = -ETIME;
  1573. atomic_inc(&reply->received);
  1574. atomic_set(&card->write.irq_pending, 0);
  1575. qeth_release_buffer(iob->channel, iob);
  1576. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1577. wake_up(&reply->wait_q);
  1578. rc = reply->rc;
  1579. qeth_put_reply(reply);
  1580. return rc;
  1581. }
  1582. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1583. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1584. unsigned long data)
  1585. {
  1586. struct qeth_cmd_buffer *iob;
  1587. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1588. iob = (struct qeth_cmd_buffer *) data;
  1589. memcpy(&card->token.cm_filter_r,
  1590. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1591. QETH_MPC_TOKEN_LENGTH);
  1592. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1593. return 0;
  1594. }
  1595. static int qeth_cm_enable(struct qeth_card *card)
  1596. {
  1597. int rc;
  1598. struct qeth_cmd_buffer *iob;
  1599. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1600. iob = qeth_wait_for_buffer(&card->write);
  1601. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1602. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1603. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1604. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1605. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1606. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1607. qeth_cm_enable_cb, NULL);
  1608. return rc;
  1609. }
  1610. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1611. unsigned long data)
  1612. {
  1613. struct qeth_cmd_buffer *iob;
  1614. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1615. iob = (struct qeth_cmd_buffer *) data;
  1616. memcpy(&card->token.cm_connection_r,
  1617. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1618. QETH_MPC_TOKEN_LENGTH);
  1619. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1620. return 0;
  1621. }
  1622. static int qeth_cm_setup(struct qeth_card *card)
  1623. {
  1624. int rc;
  1625. struct qeth_cmd_buffer *iob;
  1626. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1627. iob = qeth_wait_for_buffer(&card->write);
  1628. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1629. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1630. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1631. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1632. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1633. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1634. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1635. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1636. qeth_cm_setup_cb, NULL);
  1637. return rc;
  1638. }
  1639. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1640. {
  1641. switch (card->info.type) {
  1642. case QETH_CARD_TYPE_UNKNOWN:
  1643. return 1500;
  1644. case QETH_CARD_TYPE_IQD:
  1645. return card->info.max_mtu;
  1646. case QETH_CARD_TYPE_OSD:
  1647. switch (card->info.link_type) {
  1648. case QETH_LINK_TYPE_HSTR:
  1649. case QETH_LINK_TYPE_LANE_TR:
  1650. return 2000;
  1651. default:
  1652. return 1492;
  1653. }
  1654. case QETH_CARD_TYPE_OSM:
  1655. case QETH_CARD_TYPE_OSX:
  1656. return 1492;
  1657. default:
  1658. return 1500;
  1659. }
  1660. }
  1661. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1662. {
  1663. switch (framesize) {
  1664. case 0x4000:
  1665. return 8192;
  1666. case 0x6000:
  1667. return 16384;
  1668. case 0xa000:
  1669. return 32768;
  1670. case 0xffff:
  1671. return 57344;
  1672. default:
  1673. return 0;
  1674. }
  1675. }
  1676. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1677. {
  1678. switch (card->info.type) {
  1679. case QETH_CARD_TYPE_OSD:
  1680. case QETH_CARD_TYPE_OSM:
  1681. case QETH_CARD_TYPE_OSX:
  1682. case QETH_CARD_TYPE_IQD:
  1683. return ((mtu >= 576) &&
  1684. (mtu <= card->info.max_mtu));
  1685. case QETH_CARD_TYPE_OSN:
  1686. case QETH_CARD_TYPE_UNKNOWN:
  1687. default:
  1688. return 1;
  1689. }
  1690. }
  1691. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1692. unsigned long data)
  1693. {
  1694. __u16 mtu, framesize;
  1695. __u16 len;
  1696. __u8 link_type;
  1697. struct qeth_cmd_buffer *iob;
  1698. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1699. iob = (struct qeth_cmd_buffer *) data;
  1700. memcpy(&card->token.ulp_filter_r,
  1701. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1702. QETH_MPC_TOKEN_LENGTH);
  1703. if (card->info.type == QETH_CARD_TYPE_IQD) {
  1704. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1705. mtu = qeth_get_mtu_outof_framesize(framesize);
  1706. if (!mtu) {
  1707. iob->rc = -EINVAL;
  1708. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1709. return 0;
  1710. }
  1711. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  1712. /* frame size has changed */
  1713. if (card->dev &&
  1714. ((card->dev->mtu == card->info.initial_mtu) ||
  1715. (card->dev->mtu > mtu)))
  1716. card->dev->mtu = mtu;
  1717. qeth_free_qdio_buffers(card);
  1718. }
  1719. card->info.initial_mtu = mtu;
  1720. card->info.max_mtu = mtu;
  1721. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1722. } else {
  1723. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1724. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  1725. iob->data);
  1726. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1727. }
  1728. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1729. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1730. memcpy(&link_type,
  1731. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1732. card->info.link_type = link_type;
  1733. } else
  1734. card->info.link_type = 0;
  1735. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  1736. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1737. return 0;
  1738. }
  1739. static int qeth_ulp_enable(struct qeth_card *card)
  1740. {
  1741. int rc;
  1742. char prot_type;
  1743. struct qeth_cmd_buffer *iob;
  1744. /*FIXME: trace view callbacks*/
  1745. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1746. iob = qeth_wait_for_buffer(&card->write);
  1747. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1748. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1749. (__u8) card->info.portno;
  1750. if (card->options.layer2)
  1751. if (card->info.type == QETH_CARD_TYPE_OSN)
  1752. prot_type = QETH_PROT_OSN2;
  1753. else
  1754. prot_type = QETH_PROT_LAYER2;
  1755. else
  1756. prot_type = QETH_PROT_TCPIP;
  1757. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1758. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1759. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1760. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1761. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1762. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1763. card->info.portname, 9);
  1764. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1765. qeth_ulp_enable_cb, NULL);
  1766. return rc;
  1767. }
  1768. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1769. unsigned long data)
  1770. {
  1771. struct qeth_cmd_buffer *iob;
  1772. int rc = 0;
  1773. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1774. iob = (struct qeth_cmd_buffer *) data;
  1775. memcpy(&card->token.ulp_connection_r,
  1776. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1777. QETH_MPC_TOKEN_LENGTH);
  1778. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1779. 3)) {
  1780. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  1781. dev_err(&card->gdev->dev, "A connection could not be "
  1782. "established because of an OLM limit\n");
  1783. iob->rc = -EMLINK;
  1784. }
  1785. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1786. return rc;
  1787. }
  1788. static int qeth_ulp_setup(struct qeth_card *card)
  1789. {
  1790. int rc;
  1791. __u16 temp;
  1792. struct qeth_cmd_buffer *iob;
  1793. struct ccw_dev_id dev_id;
  1794. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1795. iob = qeth_wait_for_buffer(&card->write);
  1796. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1797. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1798. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1799. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1800. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1801. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1802. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1803. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1804. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1805. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1806. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1807. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1808. qeth_ulp_setup_cb, NULL);
  1809. return rc;
  1810. }
  1811. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1812. {
  1813. int i, j;
  1814. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1815. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1816. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1817. return 0;
  1818. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1819. GFP_KERNEL);
  1820. if (!card->qdio.in_q)
  1821. goto out_nomem;
  1822. QETH_DBF_TEXT(SETUP, 2, "inq");
  1823. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1824. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1825. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1826. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1827. card->qdio.in_q->bufs[i].buffer =
  1828. &card->qdio.in_q->qdio_bufs[i];
  1829. /* inbound buffer pool */
  1830. if (qeth_alloc_buffer_pool(card))
  1831. goto out_freeinq;
  1832. /* outbound */
  1833. card->qdio.out_qs =
  1834. kmalloc(card->qdio.no_out_queues *
  1835. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1836. if (!card->qdio.out_qs)
  1837. goto out_freepool;
  1838. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1839. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1840. GFP_KERNEL);
  1841. if (!card->qdio.out_qs[i])
  1842. goto out_freeoutq;
  1843. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1844. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1845. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1846. card->qdio.out_qs[i]->queue_no = i;
  1847. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1848. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1849. card->qdio.out_qs[i]->bufs[j].buffer =
  1850. &card->qdio.out_qs[i]->qdio_bufs[j];
  1851. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1852. skb_list);
  1853. lockdep_set_class(
  1854. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1855. &qdio_out_skb_queue_key);
  1856. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1857. }
  1858. }
  1859. return 0;
  1860. out_freeoutq:
  1861. while (i > 0)
  1862. kfree(card->qdio.out_qs[--i]);
  1863. kfree(card->qdio.out_qs);
  1864. card->qdio.out_qs = NULL;
  1865. out_freepool:
  1866. qeth_free_buffer_pool(card);
  1867. out_freeinq:
  1868. kfree(card->qdio.in_q);
  1869. card->qdio.in_q = NULL;
  1870. out_nomem:
  1871. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1872. return -ENOMEM;
  1873. }
  1874. static void qeth_create_qib_param_field(struct qeth_card *card,
  1875. char *param_field)
  1876. {
  1877. param_field[0] = _ascebc['P'];
  1878. param_field[1] = _ascebc['C'];
  1879. param_field[2] = _ascebc['I'];
  1880. param_field[3] = _ascebc['T'];
  1881. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1882. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1883. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1884. }
  1885. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1886. char *param_field)
  1887. {
  1888. param_field[16] = _ascebc['B'];
  1889. param_field[17] = _ascebc['L'];
  1890. param_field[18] = _ascebc['K'];
  1891. param_field[19] = _ascebc['T'];
  1892. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1893. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1894. *((unsigned int *) (&param_field[28])) =
  1895. card->info.blkt.inter_packet_jumbo;
  1896. }
  1897. static int qeth_qdio_activate(struct qeth_card *card)
  1898. {
  1899. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1900. return qdio_activate(CARD_DDEV(card));
  1901. }
  1902. static int qeth_dm_act(struct qeth_card *card)
  1903. {
  1904. int rc;
  1905. struct qeth_cmd_buffer *iob;
  1906. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1907. iob = qeth_wait_for_buffer(&card->write);
  1908. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1909. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1910. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1911. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1912. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1913. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1914. return rc;
  1915. }
  1916. static int qeth_mpc_initialize(struct qeth_card *card)
  1917. {
  1918. int rc;
  1919. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1920. rc = qeth_issue_next_read(card);
  1921. if (rc) {
  1922. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1923. return rc;
  1924. }
  1925. rc = qeth_cm_enable(card);
  1926. if (rc) {
  1927. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1928. goto out_qdio;
  1929. }
  1930. rc = qeth_cm_setup(card);
  1931. if (rc) {
  1932. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1933. goto out_qdio;
  1934. }
  1935. rc = qeth_ulp_enable(card);
  1936. if (rc) {
  1937. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1938. goto out_qdio;
  1939. }
  1940. rc = qeth_ulp_setup(card);
  1941. if (rc) {
  1942. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1943. goto out_qdio;
  1944. }
  1945. rc = qeth_alloc_qdio_buffers(card);
  1946. if (rc) {
  1947. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1948. goto out_qdio;
  1949. }
  1950. rc = qeth_qdio_establish(card);
  1951. if (rc) {
  1952. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1953. qeth_free_qdio_buffers(card);
  1954. goto out_qdio;
  1955. }
  1956. rc = qeth_qdio_activate(card);
  1957. if (rc) {
  1958. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1959. goto out_qdio;
  1960. }
  1961. rc = qeth_dm_act(card);
  1962. if (rc) {
  1963. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1964. goto out_qdio;
  1965. }
  1966. return 0;
  1967. out_qdio:
  1968. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1969. return rc;
  1970. }
  1971. static void qeth_print_status_with_portname(struct qeth_card *card)
  1972. {
  1973. char dbf_text[15];
  1974. int i;
  1975. sprintf(dbf_text, "%s", card->info.portname + 1);
  1976. for (i = 0; i < 8; i++)
  1977. dbf_text[i] =
  1978. (char) _ebcasc[(__u8) dbf_text[i]];
  1979. dbf_text[8] = 0;
  1980. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1981. "with link type %s (portname: %s)\n",
  1982. qeth_get_cardname(card),
  1983. (card->info.mcl_level[0]) ? " (level: " : "",
  1984. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1985. (card->info.mcl_level[0]) ? ")" : "",
  1986. qeth_get_cardname_short(card),
  1987. dbf_text);
  1988. }
  1989. static void qeth_print_status_no_portname(struct qeth_card *card)
  1990. {
  1991. if (card->info.portname[0])
  1992. dev_info(&card->gdev->dev, "Device is a%s "
  1993. "card%s%s%s\nwith link type %s "
  1994. "(no portname needed by interface).\n",
  1995. qeth_get_cardname(card),
  1996. (card->info.mcl_level[0]) ? " (level: " : "",
  1997. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1998. (card->info.mcl_level[0]) ? ")" : "",
  1999. qeth_get_cardname_short(card));
  2000. else
  2001. dev_info(&card->gdev->dev, "Device is a%s "
  2002. "card%s%s%s\nwith link type %s.\n",
  2003. qeth_get_cardname(card),
  2004. (card->info.mcl_level[0]) ? " (level: " : "",
  2005. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2006. (card->info.mcl_level[0]) ? ")" : "",
  2007. qeth_get_cardname_short(card));
  2008. }
  2009. void qeth_print_status_message(struct qeth_card *card)
  2010. {
  2011. switch (card->info.type) {
  2012. case QETH_CARD_TYPE_OSD:
  2013. case QETH_CARD_TYPE_OSM:
  2014. case QETH_CARD_TYPE_OSX:
  2015. /* VM will use a non-zero first character
  2016. * to indicate a HiperSockets like reporting
  2017. * of the level OSA sets the first character to zero
  2018. * */
  2019. if (!card->info.mcl_level[0]) {
  2020. sprintf(card->info.mcl_level, "%02x%02x",
  2021. card->info.mcl_level[2],
  2022. card->info.mcl_level[3]);
  2023. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2024. break;
  2025. }
  2026. /* fallthrough */
  2027. case QETH_CARD_TYPE_IQD:
  2028. if ((card->info.guestlan) ||
  2029. (card->info.mcl_level[0] & 0x80)) {
  2030. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2031. card->info.mcl_level[0]];
  2032. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2033. card->info.mcl_level[1]];
  2034. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2035. card->info.mcl_level[2]];
  2036. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2037. card->info.mcl_level[3]];
  2038. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2039. }
  2040. break;
  2041. default:
  2042. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2043. }
  2044. if (card->info.portname_required)
  2045. qeth_print_status_with_portname(card);
  2046. else
  2047. qeth_print_status_no_portname(card);
  2048. }
  2049. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2050. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2051. {
  2052. struct qeth_buffer_pool_entry *entry;
  2053. QETH_CARD_TEXT(card, 5, "inwrklst");
  2054. list_for_each_entry(entry,
  2055. &card->qdio.init_pool.entry_list, init_list) {
  2056. qeth_put_buffer_pool_entry(card, entry);
  2057. }
  2058. }
  2059. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2060. struct qeth_card *card)
  2061. {
  2062. struct list_head *plh;
  2063. struct qeth_buffer_pool_entry *entry;
  2064. int i, free;
  2065. struct page *page;
  2066. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2067. return NULL;
  2068. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2069. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2070. free = 1;
  2071. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2072. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2073. free = 0;
  2074. break;
  2075. }
  2076. }
  2077. if (free) {
  2078. list_del_init(&entry->list);
  2079. return entry;
  2080. }
  2081. }
  2082. /* no free buffer in pool so take first one and swap pages */
  2083. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2084. struct qeth_buffer_pool_entry, list);
  2085. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2086. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2087. page = alloc_page(GFP_ATOMIC);
  2088. if (!page) {
  2089. return NULL;
  2090. } else {
  2091. free_page((unsigned long)entry->elements[i]);
  2092. entry->elements[i] = page_address(page);
  2093. if (card->options.performance_stats)
  2094. card->perf_stats.sg_alloc_page_rx++;
  2095. }
  2096. }
  2097. }
  2098. list_del_init(&entry->list);
  2099. return entry;
  2100. }
  2101. static int qeth_init_input_buffer(struct qeth_card *card,
  2102. struct qeth_qdio_buffer *buf)
  2103. {
  2104. struct qeth_buffer_pool_entry *pool_entry;
  2105. int i;
  2106. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2107. if (!pool_entry)
  2108. return 1;
  2109. /*
  2110. * since the buffer is accessed only from the input_tasklet
  2111. * there shouldn't be a need to synchronize; also, since we use
  2112. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2113. * buffers
  2114. */
  2115. buf->pool_entry = pool_entry;
  2116. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2117. buf->buffer->element[i].length = PAGE_SIZE;
  2118. buf->buffer->element[i].addr = pool_entry->elements[i];
  2119. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2120. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2121. else
  2122. buf->buffer->element[i].flags = 0;
  2123. }
  2124. return 0;
  2125. }
  2126. int qeth_init_qdio_queues(struct qeth_card *card)
  2127. {
  2128. int i, j;
  2129. int rc;
  2130. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2131. /* inbound queue */
  2132. memset(card->qdio.in_q->qdio_bufs, 0,
  2133. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2134. qeth_initialize_working_pool_list(card);
  2135. /*give only as many buffers to hardware as we have buffer pool entries*/
  2136. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2137. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2138. card->qdio.in_q->next_buf_to_init =
  2139. card->qdio.in_buf_pool.buf_count - 1;
  2140. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2141. card->qdio.in_buf_pool.buf_count - 1);
  2142. if (rc) {
  2143. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2144. return rc;
  2145. }
  2146. /* outbound queue */
  2147. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2148. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2149. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2150. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2151. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2152. &card->qdio.out_qs[i]->bufs[j]);
  2153. }
  2154. card->qdio.out_qs[i]->card = card;
  2155. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2156. card->qdio.out_qs[i]->do_pack = 0;
  2157. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2158. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2159. atomic_set(&card->qdio.out_qs[i]->state,
  2160. QETH_OUT_Q_UNLOCKED);
  2161. }
  2162. return 0;
  2163. }
  2164. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2165. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2166. {
  2167. switch (link_type) {
  2168. case QETH_LINK_TYPE_HSTR:
  2169. return 2;
  2170. default:
  2171. return 1;
  2172. }
  2173. }
  2174. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2175. struct qeth_ipa_cmd *cmd, __u8 command,
  2176. enum qeth_prot_versions prot)
  2177. {
  2178. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2179. cmd->hdr.command = command;
  2180. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2181. cmd->hdr.seqno = card->seqno.ipa;
  2182. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2183. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2184. if (card->options.layer2)
  2185. cmd->hdr.prim_version_no = 2;
  2186. else
  2187. cmd->hdr.prim_version_no = 1;
  2188. cmd->hdr.param_count = 1;
  2189. cmd->hdr.prot_version = prot;
  2190. cmd->hdr.ipa_supported = 0;
  2191. cmd->hdr.ipa_enabled = 0;
  2192. }
  2193. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2194. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2195. {
  2196. struct qeth_cmd_buffer *iob;
  2197. struct qeth_ipa_cmd *cmd;
  2198. iob = qeth_wait_for_buffer(&card->write);
  2199. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2200. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2201. return iob;
  2202. }
  2203. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2204. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2205. char prot_type)
  2206. {
  2207. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2208. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2209. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2210. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2211. }
  2212. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2213. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2214. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2215. unsigned long),
  2216. void *reply_param)
  2217. {
  2218. int rc;
  2219. char prot_type;
  2220. QETH_CARD_TEXT(card, 4, "sendipa");
  2221. if (card->options.layer2)
  2222. if (card->info.type == QETH_CARD_TYPE_OSN)
  2223. prot_type = QETH_PROT_OSN2;
  2224. else
  2225. prot_type = QETH_PROT_LAYER2;
  2226. else
  2227. prot_type = QETH_PROT_TCPIP;
  2228. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2229. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2230. iob, reply_cb, reply_param);
  2231. if (rc == -ETIME) {
  2232. qeth_clear_ipacmd_list(card);
  2233. qeth_schedule_recovery(card);
  2234. }
  2235. return rc;
  2236. }
  2237. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2238. static int qeth_send_startstoplan(struct qeth_card *card,
  2239. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2240. {
  2241. int rc;
  2242. struct qeth_cmd_buffer *iob;
  2243. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2244. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2245. return rc;
  2246. }
  2247. int qeth_send_startlan(struct qeth_card *card)
  2248. {
  2249. int rc;
  2250. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2251. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2252. return rc;
  2253. }
  2254. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2255. int qeth_send_stoplan(struct qeth_card *card)
  2256. {
  2257. int rc = 0;
  2258. /*
  2259. * TODO: according to the IPA format document page 14,
  2260. * TCP/IP (we!) never issue a STOPLAN
  2261. * is this right ?!?
  2262. */
  2263. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2264. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2265. return rc;
  2266. }
  2267. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2268. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2269. struct qeth_reply *reply, unsigned long data)
  2270. {
  2271. struct qeth_ipa_cmd *cmd;
  2272. QETH_CARD_TEXT(card, 4, "defadpcb");
  2273. cmd = (struct qeth_ipa_cmd *) data;
  2274. if (cmd->hdr.return_code == 0)
  2275. cmd->hdr.return_code =
  2276. cmd->data.setadapterparms.hdr.return_code;
  2277. return 0;
  2278. }
  2279. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2280. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2281. struct qeth_reply *reply, unsigned long data)
  2282. {
  2283. struct qeth_ipa_cmd *cmd;
  2284. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2285. cmd = (struct qeth_ipa_cmd *) data;
  2286. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2287. card->info.link_type =
  2288. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2289. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2290. }
  2291. card->options.adp.supported_funcs =
  2292. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2293. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2294. }
  2295. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2296. __u32 command, __u32 cmdlen)
  2297. {
  2298. struct qeth_cmd_buffer *iob;
  2299. struct qeth_ipa_cmd *cmd;
  2300. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2301. QETH_PROT_IPV4);
  2302. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2303. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2304. cmd->data.setadapterparms.hdr.command_code = command;
  2305. cmd->data.setadapterparms.hdr.used_total = 1;
  2306. cmd->data.setadapterparms.hdr.seq_no = 1;
  2307. return iob;
  2308. }
  2309. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2310. int qeth_query_setadapterparms(struct qeth_card *card)
  2311. {
  2312. int rc;
  2313. struct qeth_cmd_buffer *iob;
  2314. QETH_CARD_TEXT(card, 3, "queryadp");
  2315. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2316. sizeof(struct qeth_ipacmd_setadpparms));
  2317. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2318. return rc;
  2319. }
  2320. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2321. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2322. unsigned int qdio_error, const char *dbftext)
  2323. {
  2324. if (qdio_error) {
  2325. QETH_CARD_TEXT(card, 2, dbftext);
  2326. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2327. buf->element[15].flags & 0xff);
  2328. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2329. buf->element[14].flags & 0xff);
  2330. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2331. if ((buf->element[15].flags & 0xff) == 0x12) {
  2332. card->stats.rx_dropped++;
  2333. return 0;
  2334. } else
  2335. return 1;
  2336. }
  2337. return 0;
  2338. }
  2339. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2340. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2341. {
  2342. struct qeth_qdio_q *queue = card->qdio.in_q;
  2343. int count;
  2344. int i;
  2345. int rc;
  2346. int newcount = 0;
  2347. count = (index < queue->next_buf_to_init)?
  2348. card->qdio.in_buf_pool.buf_count -
  2349. (queue->next_buf_to_init - index) :
  2350. card->qdio.in_buf_pool.buf_count -
  2351. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2352. /* only requeue at a certain threshold to avoid SIGAs */
  2353. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2354. for (i = queue->next_buf_to_init;
  2355. i < queue->next_buf_to_init + count; ++i) {
  2356. if (qeth_init_input_buffer(card,
  2357. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2358. break;
  2359. } else {
  2360. newcount++;
  2361. }
  2362. }
  2363. if (newcount < count) {
  2364. /* we are in memory shortage so we switch back to
  2365. traditional skb allocation and drop packages */
  2366. atomic_set(&card->force_alloc_skb, 3);
  2367. count = newcount;
  2368. } else {
  2369. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2370. }
  2371. /*
  2372. * according to old code it should be avoided to requeue all
  2373. * 128 buffers in order to benefit from PCI avoidance.
  2374. * this function keeps at least one buffer (the buffer at
  2375. * 'index') un-requeued -> this buffer is the first buffer that
  2376. * will be requeued the next time
  2377. */
  2378. if (card->options.performance_stats) {
  2379. card->perf_stats.inbound_do_qdio_cnt++;
  2380. card->perf_stats.inbound_do_qdio_start_time =
  2381. qeth_get_micros();
  2382. }
  2383. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2384. queue->next_buf_to_init, count);
  2385. if (card->options.performance_stats)
  2386. card->perf_stats.inbound_do_qdio_time +=
  2387. qeth_get_micros() -
  2388. card->perf_stats.inbound_do_qdio_start_time;
  2389. if (rc) {
  2390. dev_warn(&card->gdev->dev,
  2391. "QDIO reported an error, rc=%i\n", rc);
  2392. QETH_CARD_TEXT(card, 2, "qinberr");
  2393. }
  2394. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2395. QDIO_MAX_BUFFERS_PER_Q;
  2396. }
  2397. }
  2398. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2399. static int qeth_handle_send_error(struct qeth_card *card,
  2400. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2401. {
  2402. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2403. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2404. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2405. if (sbalf15 == 0) {
  2406. qdio_err = 0;
  2407. } else {
  2408. qdio_err = 1;
  2409. }
  2410. }
  2411. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2412. if (!qdio_err)
  2413. return QETH_SEND_ERROR_NONE;
  2414. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2415. return QETH_SEND_ERROR_RETRY;
  2416. QETH_CARD_TEXT(card, 1, "lnkfail");
  2417. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2418. (u16)qdio_err, (u8)sbalf15);
  2419. return QETH_SEND_ERROR_LINK_FAILURE;
  2420. }
  2421. /*
  2422. * Switched to packing state if the number of used buffers on a queue
  2423. * reaches a certain limit.
  2424. */
  2425. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2426. {
  2427. if (!queue->do_pack) {
  2428. if (atomic_read(&queue->used_buffers)
  2429. >= QETH_HIGH_WATERMARK_PACK){
  2430. /* switch non-PACKING -> PACKING */
  2431. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2432. if (queue->card->options.performance_stats)
  2433. queue->card->perf_stats.sc_dp_p++;
  2434. queue->do_pack = 1;
  2435. }
  2436. }
  2437. }
  2438. /*
  2439. * Switches from packing to non-packing mode. If there is a packing
  2440. * buffer on the queue this buffer will be prepared to be flushed.
  2441. * In that case 1 is returned to inform the caller. If no buffer
  2442. * has to be flushed, zero is returned.
  2443. */
  2444. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2445. {
  2446. struct qeth_qdio_out_buffer *buffer;
  2447. int flush_count = 0;
  2448. if (queue->do_pack) {
  2449. if (atomic_read(&queue->used_buffers)
  2450. <= QETH_LOW_WATERMARK_PACK) {
  2451. /* switch PACKING -> non-PACKING */
  2452. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2453. if (queue->card->options.performance_stats)
  2454. queue->card->perf_stats.sc_p_dp++;
  2455. queue->do_pack = 0;
  2456. /* flush packing buffers */
  2457. buffer = &queue->bufs[queue->next_buf_to_fill];
  2458. if ((atomic_read(&buffer->state) ==
  2459. QETH_QDIO_BUF_EMPTY) &&
  2460. (buffer->next_element_to_fill > 0)) {
  2461. atomic_set(&buffer->state,
  2462. QETH_QDIO_BUF_PRIMED);
  2463. flush_count++;
  2464. queue->next_buf_to_fill =
  2465. (queue->next_buf_to_fill + 1) %
  2466. QDIO_MAX_BUFFERS_PER_Q;
  2467. }
  2468. }
  2469. }
  2470. return flush_count;
  2471. }
  2472. /*
  2473. * Called to flush a packing buffer if no more pci flags are on the queue.
  2474. * Checks if there is a packing buffer and prepares it to be flushed.
  2475. * In that case returns 1, otherwise zero.
  2476. */
  2477. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2478. {
  2479. struct qeth_qdio_out_buffer *buffer;
  2480. buffer = &queue->bufs[queue->next_buf_to_fill];
  2481. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2482. (buffer->next_element_to_fill > 0)) {
  2483. /* it's a packing buffer */
  2484. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2485. queue->next_buf_to_fill =
  2486. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2487. return 1;
  2488. }
  2489. return 0;
  2490. }
  2491. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2492. int count)
  2493. {
  2494. struct qeth_qdio_out_buffer *buf;
  2495. int rc;
  2496. int i;
  2497. unsigned int qdio_flags;
  2498. for (i = index; i < index + count; ++i) {
  2499. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2500. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2501. SBAL_FLAGS_LAST_ENTRY;
  2502. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2503. continue;
  2504. if (!queue->do_pack) {
  2505. if ((atomic_read(&queue->used_buffers) >=
  2506. (QETH_HIGH_WATERMARK_PACK -
  2507. QETH_WATERMARK_PACK_FUZZ)) &&
  2508. !atomic_read(&queue->set_pci_flags_count)) {
  2509. /* it's likely that we'll go to packing
  2510. * mode soon */
  2511. atomic_inc(&queue->set_pci_flags_count);
  2512. buf->buffer->element[0].flags |= 0x40;
  2513. }
  2514. } else {
  2515. if (!atomic_read(&queue->set_pci_flags_count)) {
  2516. /*
  2517. * there's no outstanding PCI any more, so we
  2518. * have to request a PCI to be sure the the PCI
  2519. * will wake at some time in the future then we
  2520. * can flush packed buffers that might still be
  2521. * hanging around, which can happen if no
  2522. * further send was requested by the stack
  2523. */
  2524. atomic_inc(&queue->set_pci_flags_count);
  2525. buf->buffer->element[0].flags |= 0x40;
  2526. }
  2527. }
  2528. }
  2529. queue->card->dev->trans_start = jiffies;
  2530. if (queue->card->options.performance_stats) {
  2531. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2532. queue->card->perf_stats.outbound_do_qdio_start_time =
  2533. qeth_get_micros();
  2534. }
  2535. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2536. if (atomic_read(&queue->set_pci_flags_count))
  2537. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2538. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2539. queue->queue_no, index, count);
  2540. if (queue->card->options.performance_stats)
  2541. queue->card->perf_stats.outbound_do_qdio_time +=
  2542. qeth_get_micros() -
  2543. queue->card->perf_stats.outbound_do_qdio_start_time;
  2544. atomic_add(count, &queue->used_buffers);
  2545. if (rc) {
  2546. queue->card->stats.tx_errors += count;
  2547. /* ignore temporary SIGA errors without busy condition */
  2548. if (rc == QDIO_ERROR_SIGA_TARGET)
  2549. return;
  2550. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2551. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2552. /* this must not happen under normal circumstances. if it
  2553. * happens something is really wrong -> recover */
  2554. qeth_schedule_recovery(queue->card);
  2555. return;
  2556. }
  2557. if (queue->card->options.performance_stats)
  2558. queue->card->perf_stats.bufs_sent += count;
  2559. }
  2560. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2561. {
  2562. int index;
  2563. int flush_cnt = 0;
  2564. int q_was_packing = 0;
  2565. /*
  2566. * check if weed have to switch to non-packing mode or if
  2567. * we have to get a pci flag out on the queue
  2568. */
  2569. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2570. !atomic_read(&queue->set_pci_flags_count)) {
  2571. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2572. QETH_OUT_Q_UNLOCKED) {
  2573. /*
  2574. * If we get in here, there was no action in
  2575. * do_send_packet. So, we check if there is a
  2576. * packing buffer to be flushed here.
  2577. */
  2578. netif_stop_queue(queue->card->dev);
  2579. index = queue->next_buf_to_fill;
  2580. q_was_packing = queue->do_pack;
  2581. /* queue->do_pack may change */
  2582. barrier();
  2583. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2584. if (!flush_cnt &&
  2585. !atomic_read(&queue->set_pci_flags_count))
  2586. flush_cnt +=
  2587. qeth_flush_buffers_on_no_pci(queue);
  2588. if (queue->card->options.performance_stats &&
  2589. q_was_packing)
  2590. queue->card->perf_stats.bufs_sent_pack +=
  2591. flush_cnt;
  2592. if (flush_cnt)
  2593. qeth_flush_buffers(queue, index, flush_cnt);
  2594. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2595. }
  2596. }
  2597. }
  2598. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  2599. unsigned long card_ptr)
  2600. {
  2601. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2602. if (card->dev && (card->dev->flags & IFF_UP))
  2603. napi_schedule(&card->napi);
  2604. }
  2605. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  2606. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  2607. unsigned int queue, int first_element, int count,
  2608. unsigned long card_ptr)
  2609. {
  2610. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2611. if (qdio_err)
  2612. qeth_schedule_recovery(card);
  2613. }
  2614. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  2615. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2616. unsigned int qdio_error, int __queue, int first_element,
  2617. int count, unsigned long card_ptr)
  2618. {
  2619. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2620. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2621. struct qeth_qdio_out_buffer *buffer;
  2622. int i;
  2623. QETH_CARD_TEXT(card, 6, "qdouhdl");
  2624. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2625. QETH_CARD_TEXT(card, 2, "achkcond");
  2626. netif_stop_queue(card->dev);
  2627. qeth_schedule_recovery(card);
  2628. return;
  2629. }
  2630. if (card->options.performance_stats) {
  2631. card->perf_stats.outbound_handler_cnt++;
  2632. card->perf_stats.outbound_handler_start_time =
  2633. qeth_get_micros();
  2634. }
  2635. for (i = first_element; i < (first_element + count); ++i) {
  2636. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2637. qeth_handle_send_error(card, buffer, qdio_error);
  2638. qeth_clear_output_buffer(queue, buffer);
  2639. }
  2640. atomic_sub(count, &queue->used_buffers);
  2641. /* check if we need to do something on this outbound queue */
  2642. if (card->info.type != QETH_CARD_TYPE_IQD)
  2643. qeth_check_outbound_queue(queue);
  2644. netif_wake_queue(queue->card->dev);
  2645. if (card->options.performance_stats)
  2646. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2647. card->perf_stats.outbound_handler_start_time;
  2648. }
  2649. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2650. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2651. int ipv, int cast_type)
  2652. {
  2653. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  2654. card->info.type == QETH_CARD_TYPE_OSX))
  2655. return card->qdio.default_out_queue;
  2656. switch (card->qdio.no_out_queues) {
  2657. case 4:
  2658. if (cast_type && card->info.is_multicast_different)
  2659. return card->info.is_multicast_different &
  2660. (card->qdio.no_out_queues - 1);
  2661. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2662. const u8 tos = ip_hdr(skb)->tos;
  2663. if (card->qdio.do_prio_queueing ==
  2664. QETH_PRIO_Q_ING_TOS) {
  2665. if (tos & IP_TOS_NOTIMPORTANT)
  2666. return 3;
  2667. if (tos & IP_TOS_HIGHRELIABILITY)
  2668. return 2;
  2669. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2670. return 1;
  2671. if (tos & IP_TOS_LOWDELAY)
  2672. return 0;
  2673. }
  2674. if (card->qdio.do_prio_queueing ==
  2675. QETH_PRIO_Q_ING_PREC)
  2676. return 3 - (tos >> 6);
  2677. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2678. /* TODO: IPv6!!! */
  2679. }
  2680. return card->qdio.default_out_queue;
  2681. case 1: /* fallthrough for single-out-queue 1920-device */
  2682. default:
  2683. return card->qdio.default_out_queue;
  2684. }
  2685. }
  2686. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2687. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2688. struct sk_buff *skb, int elems)
  2689. {
  2690. int dlen = skb->len - skb->data_len;
  2691. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  2692. PFN_DOWN((unsigned long)skb->data);
  2693. elements_needed += skb_shinfo(skb)->nr_frags;
  2694. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2695. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2696. "(Number=%d / Length=%d). Discarded.\n",
  2697. (elements_needed+elems), skb->len);
  2698. return 0;
  2699. }
  2700. return elements_needed;
  2701. }
  2702. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2703. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  2704. {
  2705. int hroom, inpage, rest;
  2706. if (((unsigned long)skb->data & PAGE_MASK) !=
  2707. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  2708. hroom = skb_headroom(skb);
  2709. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  2710. rest = len - inpage;
  2711. if (rest > hroom)
  2712. return 1;
  2713. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  2714. skb->data -= rest;
  2715. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  2716. }
  2717. return 0;
  2718. }
  2719. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  2720. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2721. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2722. int offset)
  2723. {
  2724. int length = skb->len - skb->data_len;
  2725. int length_here;
  2726. int element;
  2727. char *data;
  2728. int first_lap, cnt;
  2729. struct skb_frag_struct *frag;
  2730. element = *next_element_to_fill;
  2731. data = skb->data;
  2732. first_lap = (is_tso == 0 ? 1 : 0);
  2733. if (offset >= 0) {
  2734. data = skb->data + offset;
  2735. length -= offset;
  2736. first_lap = 0;
  2737. }
  2738. while (length > 0) {
  2739. /* length_here is the remaining amount of data in this page */
  2740. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2741. if (length < length_here)
  2742. length_here = length;
  2743. buffer->element[element].addr = data;
  2744. buffer->element[element].length = length_here;
  2745. length -= length_here;
  2746. if (!length) {
  2747. if (first_lap)
  2748. if (skb_shinfo(skb)->nr_frags)
  2749. buffer->element[element].flags =
  2750. SBAL_FLAGS_FIRST_FRAG;
  2751. else
  2752. buffer->element[element].flags = 0;
  2753. else
  2754. buffer->element[element].flags =
  2755. SBAL_FLAGS_MIDDLE_FRAG;
  2756. } else {
  2757. if (first_lap)
  2758. buffer->element[element].flags =
  2759. SBAL_FLAGS_FIRST_FRAG;
  2760. else
  2761. buffer->element[element].flags =
  2762. SBAL_FLAGS_MIDDLE_FRAG;
  2763. }
  2764. data += length_here;
  2765. element++;
  2766. first_lap = 0;
  2767. }
  2768. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  2769. frag = &skb_shinfo(skb)->frags[cnt];
  2770. buffer->element[element].addr = (char *)page_to_phys(frag->page)
  2771. + frag->page_offset;
  2772. buffer->element[element].length = frag->size;
  2773. buffer->element[element].flags = SBAL_FLAGS_MIDDLE_FRAG;
  2774. element++;
  2775. }
  2776. if (buffer->element[element - 1].flags)
  2777. buffer->element[element - 1].flags = SBAL_FLAGS_LAST_FRAG;
  2778. *next_element_to_fill = element;
  2779. }
  2780. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2781. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2782. struct qeth_hdr *hdr, int offset, int hd_len)
  2783. {
  2784. struct qdio_buffer *buffer;
  2785. int flush_cnt = 0, hdr_len, large_send = 0;
  2786. buffer = buf->buffer;
  2787. atomic_inc(&skb->users);
  2788. skb_queue_tail(&buf->skb_list, skb);
  2789. /*check first on TSO ....*/
  2790. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2791. int element = buf->next_element_to_fill;
  2792. hdr_len = sizeof(struct qeth_hdr_tso) +
  2793. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2794. /*fill first buffer entry only with header information */
  2795. buffer->element[element].addr = skb->data;
  2796. buffer->element[element].length = hdr_len;
  2797. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2798. buf->next_element_to_fill++;
  2799. skb->data += hdr_len;
  2800. skb->len -= hdr_len;
  2801. large_send = 1;
  2802. }
  2803. if (offset >= 0) {
  2804. int element = buf->next_element_to_fill;
  2805. buffer->element[element].addr = hdr;
  2806. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2807. hd_len;
  2808. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2809. buf->is_header[element] = 1;
  2810. buf->next_element_to_fill++;
  2811. }
  2812. __qeth_fill_buffer(skb, buffer, large_send,
  2813. (int *)&buf->next_element_to_fill, offset);
  2814. if (!queue->do_pack) {
  2815. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  2816. /* set state to PRIMED -> will be flushed */
  2817. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2818. flush_cnt = 1;
  2819. } else {
  2820. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  2821. if (queue->card->options.performance_stats)
  2822. queue->card->perf_stats.skbs_sent_pack++;
  2823. if (buf->next_element_to_fill >=
  2824. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2825. /*
  2826. * packed buffer if full -> set state PRIMED
  2827. * -> will be flushed
  2828. */
  2829. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2830. flush_cnt = 1;
  2831. }
  2832. }
  2833. return flush_cnt;
  2834. }
  2835. int qeth_do_send_packet_fast(struct qeth_card *card,
  2836. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2837. struct qeth_hdr *hdr, int elements_needed,
  2838. int offset, int hd_len)
  2839. {
  2840. struct qeth_qdio_out_buffer *buffer;
  2841. int index;
  2842. /* spin until we get the queue ... */
  2843. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2844. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2845. /* ... now we've got the queue */
  2846. index = queue->next_buf_to_fill;
  2847. buffer = &queue->bufs[queue->next_buf_to_fill];
  2848. /*
  2849. * check if buffer is empty to make sure that we do not 'overtake'
  2850. * ourselves and try to fill a buffer that is already primed
  2851. */
  2852. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2853. goto out;
  2854. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2855. QDIO_MAX_BUFFERS_PER_Q;
  2856. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2857. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2858. qeth_flush_buffers(queue, index, 1);
  2859. return 0;
  2860. out:
  2861. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2862. return -EBUSY;
  2863. }
  2864. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2865. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2866. struct sk_buff *skb, struct qeth_hdr *hdr,
  2867. int elements_needed)
  2868. {
  2869. struct qeth_qdio_out_buffer *buffer;
  2870. int start_index;
  2871. int flush_count = 0;
  2872. int do_pack = 0;
  2873. int tmp;
  2874. int rc = 0;
  2875. /* spin until we get the queue ... */
  2876. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2877. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2878. start_index = queue->next_buf_to_fill;
  2879. buffer = &queue->bufs[queue->next_buf_to_fill];
  2880. /*
  2881. * check if buffer is empty to make sure that we do not 'overtake'
  2882. * ourselves and try to fill a buffer that is already primed
  2883. */
  2884. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2885. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2886. return -EBUSY;
  2887. }
  2888. /* check if we need to switch packing state of this queue */
  2889. qeth_switch_to_packing_if_needed(queue);
  2890. if (queue->do_pack) {
  2891. do_pack = 1;
  2892. /* does packet fit in current buffer? */
  2893. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2894. buffer->next_element_to_fill) < elements_needed) {
  2895. /* ... no -> set state PRIMED */
  2896. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2897. flush_count++;
  2898. queue->next_buf_to_fill =
  2899. (queue->next_buf_to_fill + 1) %
  2900. QDIO_MAX_BUFFERS_PER_Q;
  2901. buffer = &queue->bufs[queue->next_buf_to_fill];
  2902. /* we did a step forward, so check buffer state
  2903. * again */
  2904. if (atomic_read(&buffer->state) !=
  2905. QETH_QDIO_BUF_EMPTY) {
  2906. qeth_flush_buffers(queue, start_index,
  2907. flush_count);
  2908. atomic_set(&queue->state,
  2909. QETH_OUT_Q_UNLOCKED);
  2910. return -EBUSY;
  2911. }
  2912. }
  2913. }
  2914. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2915. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2916. QDIO_MAX_BUFFERS_PER_Q;
  2917. flush_count += tmp;
  2918. if (flush_count)
  2919. qeth_flush_buffers(queue, start_index, flush_count);
  2920. else if (!atomic_read(&queue->set_pci_flags_count))
  2921. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2922. /*
  2923. * queue->state will go from LOCKED -> UNLOCKED or from
  2924. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2925. * (switch packing state or flush buffer to get another pci flag out).
  2926. * In that case we will enter this loop
  2927. */
  2928. while (atomic_dec_return(&queue->state)) {
  2929. flush_count = 0;
  2930. start_index = queue->next_buf_to_fill;
  2931. /* check if we can go back to non-packing state */
  2932. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2933. /*
  2934. * check if we need to flush a packing buffer to get a pci
  2935. * flag out on the queue
  2936. */
  2937. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2938. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2939. if (flush_count)
  2940. qeth_flush_buffers(queue, start_index, flush_count);
  2941. }
  2942. /* at this point the queue is UNLOCKED again */
  2943. if (queue->card->options.performance_stats && do_pack)
  2944. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2945. return rc;
  2946. }
  2947. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2948. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2949. struct qeth_reply *reply, unsigned long data)
  2950. {
  2951. struct qeth_ipa_cmd *cmd;
  2952. struct qeth_ipacmd_setadpparms *setparms;
  2953. QETH_CARD_TEXT(card, 4, "prmadpcb");
  2954. cmd = (struct qeth_ipa_cmd *) data;
  2955. setparms = &(cmd->data.setadapterparms);
  2956. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2957. if (cmd->hdr.return_code) {
  2958. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2959. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2960. }
  2961. card->info.promisc_mode = setparms->data.mode;
  2962. return 0;
  2963. }
  2964. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2965. {
  2966. enum qeth_ipa_promisc_modes mode;
  2967. struct net_device *dev = card->dev;
  2968. struct qeth_cmd_buffer *iob;
  2969. struct qeth_ipa_cmd *cmd;
  2970. QETH_CARD_TEXT(card, 4, "setprom");
  2971. if (((dev->flags & IFF_PROMISC) &&
  2972. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2973. (!(dev->flags & IFF_PROMISC) &&
  2974. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2975. return;
  2976. mode = SET_PROMISC_MODE_OFF;
  2977. if (dev->flags & IFF_PROMISC)
  2978. mode = SET_PROMISC_MODE_ON;
  2979. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  2980. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2981. sizeof(struct qeth_ipacmd_setadpparms));
  2982. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2983. cmd->data.setadapterparms.data.mode = mode;
  2984. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2985. }
  2986. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2987. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2988. {
  2989. struct qeth_card *card;
  2990. char dbf_text[15];
  2991. card = dev->ml_priv;
  2992. QETH_CARD_TEXT(card, 4, "chgmtu");
  2993. sprintf(dbf_text, "%8x", new_mtu);
  2994. QETH_CARD_TEXT(card, 4, dbf_text);
  2995. if (new_mtu < 64)
  2996. return -EINVAL;
  2997. if (new_mtu > 65535)
  2998. return -EINVAL;
  2999. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3000. (!qeth_mtu_is_valid(card, new_mtu)))
  3001. return -EINVAL;
  3002. dev->mtu = new_mtu;
  3003. return 0;
  3004. }
  3005. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3006. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3007. {
  3008. struct qeth_card *card;
  3009. card = dev->ml_priv;
  3010. QETH_CARD_TEXT(card, 5, "getstat");
  3011. return &card->stats;
  3012. }
  3013. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3014. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3015. struct qeth_reply *reply, unsigned long data)
  3016. {
  3017. struct qeth_ipa_cmd *cmd;
  3018. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3019. cmd = (struct qeth_ipa_cmd *) data;
  3020. if (!card->options.layer2 ||
  3021. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3022. memcpy(card->dev->dev_addr,
  3023. &cmd->data.setadapterparms.data.change_addr.addr,
  3024. OSA_ADDR_LEN);
  3025. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3026. }
  3027. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3028. return 0;
  3029. }
  3030. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3031. {
  3032. int rc;
  3033. struct qeth_cmd_buffer *iob;
  3034. struct qeth_ipa_cmd *cmd;
  3035. QETH_CARD_TEXT(card, 4, "chgmac");
  3036. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3037. sizeof(struct qeth_ipacmd_setadpparms));
  3038. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3039. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3040. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3041. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3042. card->dev->dev_addr, OSA_ADDR_LEN);
  3043. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3044. NULL);
  3045. return rc;
  3046. }
  3047. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3048. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3049. struct qeth_reply *reply, unsigned long data)
  3050. {
  3051. struct qeth_ipa_cmd *cmd;
  3052. struct qeth_set_access_ctrl *access_ctrl_req;
  3053. QETH_CARD_TEXT(card, 4, "setaccb");
  3054. cmd = (struct qeth_ipa_cmd *) data;
  3055. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3056. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3057. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3058. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3059. cmd->data.setadapterparms.hdr.return_code);
  3060. switch (cmd->data.setadapterparms.hdr.return_code) {
  3061. case SET_ACCESS_CTRL_RC_SUCCESS:
  3062. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3063. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3064. {
  3065. card->options.isolation = access_ctrl_req->subcmd_code;
  3066. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3067. dev_info(&card->gdev->dev,
  3068. "QDIO data connection isolation is deactivated\n");
  3069. } else {
  3070. dev_info(&card->gdev->dev,
  3071. "QDIO data connection isolation is activated\n");
  3072. }
  3073. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3074. card->gdev->dev.kobj.name,
  3075. access_ctrl_req->subcmd_code,
  3076. cmd->data.setadapterparms.hdr.return_code);
  3077. break;
  3078. }
  3079. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3080. {
  3081. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3082. card->gdev->dev.kobj.name,
  3083. access_ctrl_req->subcmd_code,
  3084. cmd->data.setadapterparms.hdr.return_code);
  3085. dev_err(&card->gdev->dev, "Adapter does not "
  3086. "support QDIO data connection isolation\n");
  3087. /* ensure isolation mode is "none" */
  3088. card->options.isolation = ISOLATION_MODE_NONE;
  3089. break;
  3090. }
  3091. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3092. {
  3093. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3094. card->gdev->dev.kobj.name,
  3095. access_ctrl_req->subcmd_code,
  3096. cmd->data.setadapterparms.hdr.return_code);
  3097. dev_err(&card->gdev->dev,
  3098. "Adapter is dedicated. "
  3099. "QDIO data connection isolation not supported\n");
  3100. /* ensure isolation mode is "none" */
  3101. card->options.isolation = ISOLATION_MODE_NONE;
  3102. break;
  3103. }
  3104. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3105. {
  3106. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3107. card->gdev->dev.kobj.name,
  3108. access_ctrl_req->subcmd_code,
  3109. cmd->data.setadapterparms.hdr.return_code);
  3110. dev_err(&card->gdev->dev,
  3111. "TSO does not permit QDIO data connection isolation\n");
  3112. /* ensure isolation mode is "none" */
  3113. card->options.isolation = ISOLATION_MODE_NONE;
  3114. break;
  3115. }
  3116. default:
  3117. {
  3118. /* this should never happen */
  3119. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3120. "==UNKNOWN\n",
  3121. card->gdev->dev.kobj.name,
  3122. access_ctrl_req->subcmd_code,
  3123. cmd->data.setadapterparms.hdr.return_code);
  3124. /* ensure isolation mode is "none" */
  3125. card->options.isolation = ISOLATION_MODE_NONE;
  3126. break;
  3127. }
  3128. }
  3129. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3130. return 0;
  3131. }
  3132. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3133. enum qeth_ipa_isolation_modes isolation)
  3134. {
  3135. int rc;
  3136. struct qeth_cmd_buffer *iob;
  3137. struct qeth_ipa_cmd *cmd;
  3138. struct qeth_set_access_ctrl *access_ctrl_req;
  3139. QETH_CARD_TEXT(card, 4, "setacctl");
  3140. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3141. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3142. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3143. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3144. sizeof(struct qeth_set_access_ctrl));
  3145. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3146. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3147. access_ctrl_req->subcmd_code = isolation;
  3148. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3149. NULL);
  3150. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3151. return rc;
  3152. }
  3153. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3154. {
  3155. int rc = 0;
  3156. QETH_CARD_TEXT(card, 4, "setactlo");
  3157. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3158. card->info.type == QETH_CARD_TYPE_OSX) &&
  3159. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3160. rc = qeth_setadpparms_set_access_ctrl(card,
  3161. card->options.isolation);
  3162. if (rc) {
  3163. QETH_DBF_MESSAGE(3,
  3164. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3165. card->gdev->dev.kobj.name,
  3166. rc);
  3167. }
  3168. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3169. card->options.isolation = ISOLATION_MODE_NONE;
  3170. dev_err(&card->gdev->dev, "Adapter does not "
  3171. "support QDIO data connection isolation\n");
  3172. rc = -EOPNOTSUPP;
  3173. }
  3174. return rc;
  3175. }
  3176. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3177. void qeth_tx_timeout(struct net_device *dev)
  3178. {
  3179. struct qeth_card *card;
  3180. card = dev->ml_priv;
  3181. QETH_CARD_TEXT(card, 4, "txtimeo");
  3182. card->stats.tx_errors++;
  3183. qeth_schedule_recovery(card);
  3184. }
  3185. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3186. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3187. {
  3188. struct qeth_card *card = dev->ml_priv;
  3189. int rc = 0;
  3190. switch (regnum) {
  3191. case MII_BMCR: /* Basic mode control register */
  3192. rc = BMCR_FULLDPLX;
  3193. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3194. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3195. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3196. rc |= BMCR_SPEED100;
  3197. break;
  3198. case MII_BMSR: /* Basic mode status register */
  3199. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3200. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3201. BMSR_100BASE4;
  3202. break;
  3203. case MII_PHYSID1: /* PHYS ID 1 */
  3204. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3205. dev->dev_addr[2];
  3206. rc = (rc >> 5) & 0xFFFF;
  3207. break;
  3208. case MII_PHYSID2: /* PHYS ID 2 */
  3209. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3210. break;
  3211. case MII_ADVERTISE: /* Advertisement control reg */
  3212. rc = ADVERTISE_ALL;
  3213. break;
  3214. case MII_LPA: /* Link partner ability reg */
  3215. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3216. LPA_100BASE4 | LPA_LPACK;
  3217. break;
  3218. case MII_EXPANSION: /* Expansion register */
  3219. break;
  3220. case MII_DCOUNTER: /* disconnect counter */
  3221. break;
  3222. case MII_FCSCOUNTER: /* false carrier counter */
  3223. break;
  3224. case MII_NWAYTEST: /* N-way auto-neg test register */
  3225. break;
  3226. case MII_RERRCOUNTER: /* rx error counter */
  3227. rc = card->stats.rx_errors;
  3228. break;
  3229. case MII_SREVISION: /* silicon revision */
  3230. break;
  3231. case MII_RESV1: /* reserved 1 */
  3232. break;
  3233. case MII_LBRERROR: /* loopback, rx, bypass error */
  3234. break;
  3235. case MII_PHYADDR: /* physical address */
  3236. break;
  3237. case MII_RESV2: /* reserved 2 */
  3238. break;
  3239. case MII_TPISTATUS: /* TPI status for 10mbps */
  3240. break;
  3241. case MII_NCONFIG: /* network interface config */
  3242. break;
  3243. default:
  3244. break;
  3245. }
  3246. return rc;
  3247. }
  3248. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3249. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3250. struct qeth_cmd_buffer *iob, int len,
  3251. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3252. unsigned long),
  3253. void *reply_param)
  3254. {
  3255. u16 s1, s2;
  3256. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3257. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3258. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3259. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3260. /* adjust PDU length fields in IPA_PDU_HEADER */
  3261. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3262. s2 = (u32) len;
  3263. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3264. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3265. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3266. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3267. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3268. reply_cb, reply_param);
  3269. }
  3270. static int qeth_snmp_command_cb(struct qeth_card *card,
  3271. struct qeth_reply *reply, unsigned long sdata)
  3272. {
  3273. struct qeth_ipa_cmd *cmd;
  3274. struct qeth_arp_query_info *qinfo;
  3275. struct qeth_snmp_cmd *snmp;
  3276. unsigned char *data;
  3277. __u16 data_len;
  3278. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3279. cmd = (struct qeth_ipa_cmd *) sdata;
  3280. data = (unsigned char *)((char *)cmd - reply->offset);
  3281. qinfo = (struct qeth_arp_query_info *) reply->param;
  3282. snmp = &cmd->data.setadapterparms.data.snmp;
  3283. if (cmd->hdr.return_code) {
  3284. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3285. return 0;
  3286. }
  3287. if (cmd->data.setadapterparms.hdr.return_code) {
  3288. cmd->hdr.return_code =
  3289. cmd->data.setadapterparms.hdr.return_code;
  3290. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3291. return 0;
  3292. }
  3293. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3294. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3295. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3296. else
  3297. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3298. /* check if there is enough room in userspace */
  3299. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3300. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3301. cmd->hdr.return_code = -ENOMEM;
  3302. return 0;
  3303. }
  3304. QETH_CARD_TEXT_(card, 4, "snore%i",
  3305. cmd->data.setadapterparms.hdr.used_total);
  3306. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3307. cmd->data.setadapterparms.hdr.seq_no);
  3308. /*copy entries to user buffer*/
  3309. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3310. memcpy(qinfo->udata + qinfo->udata_offset,
  3311. (char *)snmp,
  3312. data_len + offsetof(struct qeth_snmp_cmd, data));
  3313. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3314. } else {
  3315. memcpy(qinfo->udata + qinfo->udata_offset,
  3316. (char *)&snmp->request, data_len);
  3317. }
  3318. qinfo->udata_offset += data_len;
  3319. /* check if all replies received ... */
  3320. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3321. cmd->data.setadapterparms.hdr.used_total);
  3322. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3323. cmd->data.setadapterparms.hdr.seq_no);
  3324. if (cmd->data.setadapterparms.hdr.seq_no <
  3325. cmd->data.setadapterparms.hdr.used_total)
  3326. return 1;
  3327. return 0;
  3328. }
  3329. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3330. {
  3331. struct qeth_cmd_buffer *iob;
  3332. struct qeth_ipa_cmd *cmd;
  3333. struct qeth_snmp_ureq *ureq;
  3334. int req_len;
  3335. struct qeth_arp_query_info qinfo = {0, };
  3336. int rc = 0;
  3337. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3338. if (card->info.guestlan)
  3339. return -EOPNOTSUPP;
  3340. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3341. (!card->options.layer2)) {
  3342. return -EOPNOTSUPP;
  3343. }
  3344. /* skip 4 bytes (data_len struct member) to get req_len */
  3345. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3346. return -EFAULT;
  3347. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3348. if (IS_ERR(ureq)) {
  3349. QETH_CARD_TEXT(card, 2, "snmpnome");
  3350. return PTR_ERR(ureq);
  3351. }
  3352. qinfo.udata_len = ureq->hdr.data_len;
  3353. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3354. if (!qinfo.udata) {
  3355. kfree(ureq);
  3356. return -ENOMEM;
  3357. }
  3358. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3359. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3360. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3361. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3362. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3363. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3364. qeth_snmp_command_cb, (void *)&qinfo);
  3365. if (rc)
  3366. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3367. QETH_CARD_IFNAME(card), rc);
  3368. else {
  3369. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3370. rc = -EFAULT;
  3371. }
  3372. kfree(ureq);
  3373. kfree(qinfo.udata);
  3374. return rc;
  3375. }
  3376. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3377. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3378. {
  3379. switch (card->info.type) {
  3380. case QETH_CARD_TYPE_IQD:
  3381. return 2;
  3382. default:
  3383. return 0;
  3384. }
  3385. }
  3386. static void qeth_determine_capabilities(struct qeth_card *card)
  3387. {
  3388. int rc;
  3389. int length;
  3390. char *prcd;
  3391. struct ccw_device *ddev;
  3392. int ddev_offline = 0;
  3393. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3394. ddev = CARD_DDEV(card);
  3395. if (!ddev->online) {
  3396. ddev_offline = 1;
  3397. rc = ccw_device_set_online(ddev);
  3398. if (rc) {
  3399. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3400. goto out;
  3401. }
  3402. }
  3403. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3404. if (rc) {
  3405. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3406. dev_name(&card->gdev->dev), rc);
  3407. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3408. goto out_offline;
  3409. }
  3410. qeth_configure_unitaddr(card, prcd);
  3411. qeth_configure_blkt_default(card, prcd);
  3412. kfree(prcd);
  3413. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  3414. if (rc)
  3415. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3416. out_offline:
  3417. if (ddev_offline == 1)
  3418. ccw_device_set_offline(ddev);
  3419. out:
  3420. return;
  3421. }
  3422. static int qeth_qdio_establish(struct qeth_card *card)
  3423. {
  3424. struct qdio_initialize init_data;
  3425. char *qib_param_field;
  3426. struct qdio_buffer **in_sbal_ptrs;
  3427. struct qdio_buffer **out_sbal_ptrs;
  3428. int i, j, k;
  3429. int rc = 0;
  3430. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3431. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3432. GFP_KERNEL);
  3433. if (!qib_param_field)
  3434. return -ENOMEM;
  3435. qeth_create_qib_param_field(card, qib_param_field);
  3436. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3437. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3438. GFP_KERNEL);
  3439. if (!in_sbal_ptrs) {
  3440. kfree(qib_param_field);
  3441. return -ENOMEM;
  3442. }
  3443. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3444. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3445. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3446. out_sbal_ptrs =
  3447. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3448. sizeof(void *), GFP_KERNEL);
  3449. if (!out_sbal_ptrs) {
  3450. kfree(in_sbal_ptrs);
  3451. kfree(qib_param_field);
  3452. return -ENOMEM;
  3453. }
  3454. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3455. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3456. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3457. card->qdio.out_qs[i]->bufs[j].buffer);
  3458. }
  3459. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3460. init_data.cdev = CARD_DDEV(card);
  3461. init_data.q_format = qeth_get_qdio_q_format(card);
  3462. init_data.qib_param_field_format = 0;
  3463. init_data.qib_param_field = qib_param_field;
  3464. init_data.no_input_qs = 1;
  3465. init_data.no_output_qs = card->qdio.no_out_queues;
  3466. init_data.input_handler = card->discipline.input_handler;
  3467. init_data.output_handler = card->discipline.output_handler;
  3468. init_data.queue_start_poll = card->discipline.start_poll;
  3469. init_data.int_parm = (unsigned long) card;
  3470. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3471. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3472. init_data.scan_threshold =
  3473. (card->info.type == QETH_CARD_TYPE_IQD) ? 8 : 32;
  3474. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3475. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3476. rc = qdio_allocate(&init_data);
  3477. if (rc) {
  3478. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3479. goto out;
  3480. }
  3481. rc = qdio_establish(&init_data);
  3482. if (rc) {
  3483. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3484. qdio_free(CARD_DDEV(card));
  3485. }
  3486. }
  3487. out:
  3488. kfree(out_sbal_ptrs);
  3489. kfree(in_sbal_ptrs);
  3490. kfree(qib_param_field);
  3491. return rc;
  3492. }
  3493. static void qeth_core_free_card(struct qeth_card *card)
  3494. {
  3495. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3496. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3497. qeth_clean_channel(&card->read);
  3498. qeth_clean_channel(&card->write);
  3499. if (card->dev)
  3500. free_netdev(card->dev);
  3501. kfree(card->ip_tbd_list);
  3502. qeth_free_qdio_buffers(card);
  3503. unregister_service_level(&card->qeth_service_level);
  3504. kfree(card);
  3505. }
  3506. static struct ccw_device_id qeth_ids[] = {
  3507. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  3508. .driver_info = QETH_CARD_TYPE_OSD},
  3509. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  3510. .driver_info = QETH_CARD_TYPE_IQD},
  3511. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  3512. .driver_info = QETH_CARD_TYPE_OSN},
  3513. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  3514. .driver_info = QETH_CARD_TYPE_OSM},
  3515. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  3516. .driver_info = QETH_CARD_TYPE_OSX},
  3517. {},
  3518. };
  3519. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3520. static struct ccw_driver qeth_ccw_driver = {
  3521. .name = "qeth",
  3522. .ids = qeth_ids,
  3523. .probe = ccwgroup_probe_ccwdev,
  3524. .remove = ccwgroup_remove_ccwdev,
  3525. };
  3526. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3527. unsigned long driver_id)
  3528. {
  3529. return ccwgroup_create_from_string(root_dev, driver_id,
  3530. &qeth_ccw_driver, 3, buf);
  3531. }
  3532. int qeth_core_hardsetup_card(struct qeth_card *card)
  3533. {
  3534. int retries = 0;
  3535. int rc;
  3536. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3537. atomic_set(&card->force_alloc_skb, 0);
  3538. qeth_get_channel_path_desc(card);
  3539. retry:
  3540. if (retries)
  3541. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3542. dev_name(&card->gdev->dev));
  3543. ccw_device_set_offline(CARD_DDEV(card));
  3544. ccw_device_set_offline(CARD_WDEV(card));
  3545. ccw_device_set_offline(CARD_RDEV(card));
  3546. rc = ccw_device_set_online(CARD_RDEV(card));
  3547. if (rc)
  3548. goto retriable;
  3549. rc = ccw_device_set_online(CARD_WDEV(card));
  3550. if (rc)
  3551. goto retriable;
  3552. rc = ccw_device_set_online(CARD_DDEV(card));
  3553. if (rc)
  3554. goto retriable;
  3555. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3556. retriable:
  3557. if (rc == -ERESTARTSYS) {
  3558. QETH_DBF_TEXT(SETUP, 2, "break1");
  3559. return rc;
  3560. } else if (rc) {
  3561. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3562. if (++retries > 3)
  3563. goto out;
  3564. else
  3565. goto retry;
  3566. }
  3567. qeth_determine_capabilities(card);
  3568. qeth_init_tokens(card);
  3569. qeth_init_func_level(card);
  3570. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3571. if (rc == -ERESTARTSYS) {
  3572. QETH_DBF_TEXT(SETUP, 2, "break2");
  3573. return rc;
  3574. } else if (rc) {
  3575. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3576. if (--retries < 0)
  3577. goto out;
  3578. else
  3579. goto retry;
  3580. }
  3581. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3582. if (rc == -ERESTARTSYS) {
  3583. QETH_DBF_TEXT(SETUP, 2, "break3");
  3584. return rc;
  3585. } else if (rc) {
  3586. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3587. if (--retries < 0)
  3588. goto out;
  3589. else
  3590. goto retry;
  3591. }
  3592. card->read_or_write_problem = 0;
  3593. rc = qeth_mpc_initialize(card);
  3594. if (rc) {
  3595. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3596. goto out;
  3597. }
  3598. return 0;
  3599. out:
  3600. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3601. "an error on the device\n");
  3602. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3603. dev_name(&card->gdev->dev), rc);
  3604. return rc;
  3605. }
  3606. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3607. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3608. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3609. {
  3610. struct page *page = virt_to_page(element->addr);
  3611. if (*pskb == NULL) {
  3612. /* the upper protocol layers assume that there is data in the
  3613. * skb itself. Copy a small amount (64 bytes) to make them
  3614. * happy. */
  3615. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3616. if (!(*pskb))
  3617. return -ENOMEM;
  3618. skb_reserve(*pskb, ETH_HLEN);
  3619. if (data_len <= 64) {
  3620. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3621. data_len);
  3622. } else {
  3623. get_page(page);
  3624. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3625. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3626. data_len - 64);
  3627. (*pskb)->data_len += data_len - 64;
  3628. (*pskb)->len += data_len - 64;
  3629. (*pskb)->truesize += data_len - 64;
  3630. (*pfrag)++;
  3631. }
  3632. } else {
  3633. get_page(page);
  3634. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3635. (*pskb)->data_len += data_len;
  3636. (*pskb)->len += data_len;
  3637. (*pskb)->truesize += data_len;
  3638. (*pfrag)++;
  3639. }
  3640. return 0;
  3641. }
  3642. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3643. struct qdio_buffer *buffer,
  3644. struct qdio_buffer_element **__element, int *__offset,
  3645. struct qeth_hdr **hdr)
  3646. {
  3647. struct qdio_buffer_element *element = *__element;
  3648. int offset = *__offset;
  3649. struct sk_buff *skb = NULL;
  3650. int skb_len = 0;
  3651. void *data_ptr;
  3652. int data_len;
  3653. int headroom = 0;
  3654. int use_rx_sg = 0;
  3655. int frag = 0;
  3656. /* qeth_hdr must not cross element boundaries */
  3657. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3658. if (qeth_is_last_sbale(element))
  3659. return NULL;
  3660. element++;
  3661. offset = 0;
  3662. if (element->length < sizeof(struct qeth_hdr))
  3663. return NULL;
  3664. }
  3665. *hdr = element->addr + offset;
  3666. offset += sizeof(struct qeth_hdr);
  3667. switch ((*hdr)->hdr.l2.id) {
  3668. case QETH_HEADER_TYPE_LAYER2:
  3669. skb_len = (*hdr)->hdr.l2.pkt_length;
  3670. break;
  3671. case QETH_HEADER_TYPE_LAYER3:
  3672. skb_len = (*hdr)->hdr.l3.length;
  3673. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3674. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3675. headroom = TR_HLEN;
  3676. else
  3677. headroom = ETH_HLEN;
  3678. break;
  3679. case QETH_HEADER_TYPE_OSN:
  3680. skb_len = (*hdr)->hdr.osn.pdu_length;
  3681. headroom = sizeof(struct qeth_hdr);
  3682. break;
  3683. default:
  3684. break;
  3685. }
  3686. if (!skb_len)
  3687. return NULL;
  3688. if ((skb_len >= card->options.rx_sg_cb) &&
  3689. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3690. (!atomic_read(&card->force_alloc_skb))) {
  3691. use_rx_sg = 1;
  3692. } else {
  3693. skb = dev_alloc_skb(skb_len + headroom);
  3694. if (!skb)
  3695. goto no_mem;
  3696. if (headroom)
  3697. skb_reserve(skb, headroom);
  3698. }
  3699. data_ptr = element->addr + offset;
  3700. while (skb_len) {
  3701. data_len = min(skb_len, (int)(element->length - offset));
  3702. if (data_len) {
  3703. if (use_rx_sg) {
  3704. if (qeth_create_skb_frag(element, &skb, offset,
  3705. &frag, data_len))
  3706. goto no_mem;
  3707. } else {
  3708. memcpy(skb_put(skb, data_len), data_ptr,
  3709. data_len);
  3710. }
  3711. }
  3712. skb_len -= data_len;
  3713. if (skb_len) {
  3714. if (qeth_is_last_sbale(element)) {
  3715. QETH_CARD_TEXT(card, 4, "unexeob");
  3716. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  3717. dev_kfree_skb_any(skb);
  3718. card->stats.rx_errors++;
  3719. return NULL;
  3720. }
  3721. element++;
  3722. offset = 0;
  3723. data_ptr = element->addr;
  3724. } else {
  3725. offset += data_len;
  3726. }
  3727. }
  3728. *__element = element;
  3729. *__offset = offset;
  3730. if (use_rx_sg && card->options.performance_stats) {
  3731. card->perf_stats.sg_skbs_rx++;
  3732. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3733. }
  3734. return skb;
  3735. no_mem:
  3736. if (net_ratelimit()) {
  3737. QETH_CARD_TEXT(card, 2, "noskbmem");
  3738. }
  3739. card->stats.rx_dropped++;
  3740. return NULL;
  3741. }
  3742. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3743. static void qeth_unregister_dbf_views(void)
  3744. {
  3745. int x;
  3746. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3747. debug_unregister(qeth_dbf[x].id);
  3748. qeth_dbf[x].id = NULL;
  3749. }
  3750. }
  3751. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  3752. {
  3753. char dbf_txt_buf[32];
  3754. va_list args;
  3755. if (level > id->level)
  3756. return;
  3757. va_start(args, fmt);
  3758. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3759. va_end(args);
  3760. debug_text_event(id, level, dbf_txt_buf);
  3761. }
  3762. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3763. static int qeth_register_dbf_views(void)
  3764. {
  3765. int ret;
  3766. int x;
  3767. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3768. /* register the areas */
  3769. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3770. qeth_dbf[x].pages,
  3771. qeth_dbf[x].areas,
  3772. qeth_dbf[x].len);
  3773. if (qeth_dbf[x].id == NULL) {
  3774. qeth_unregister_dbf_views();
  3775. return -ENOMEM;
  3776. }
  3777. /* register a view */
  3778. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3779. if (ret) {
  3780. qeth_unregister_dbf_views();
  3781. return ret;
  3782. }
  3783. /* set a passing level */
  3784. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3785. }
  3786. return 0;
  3787. }
  3788. int qeth_core_load_discipline(struct qeth_card *card,
  3789. enum qeth_discipline_id discipline)
  3790. {
  3791. int rc = 0;
  3792. switch (discipline) {
  3793. case QETH_DISCIPLINE_LAYER3:
  3794. card->discipline.ccwgdriver = try_then_request_module(
  3795. symbol_get(qeth_l3_ccwgroup_driver),
  3796. "qeth_l3");
  3797. break;
  3798. case QETH_DISCIPLINE_LAYER2:
  3799. card->discipline.ccwgdriver = try_then_request_module(
  3800. symbol_get(qeth_l2_ccwgroup_driver),
  3801. "qeth_l2");
  3802. break;
  3803. }
  3804. if (!card->discipline.ccwgdriver) {
  3805. dev_err(&card->gdev->dev, "There is no kernel module to "
  3806. "support discipline %d\n", discipline);
  3807. rc = -EINVAL;
  3808. }
  3809. return rc;
  3810. }
  3811. void qeth_core_free_discipline(struct qeth_card *card)
  3812. {
  3813. if (card->options.layer2)
  3814. symbol_put(qeth_l2_ccwgroup_driver);
  3815. else
  3816. symbol_put(qeth_l3_ccwgroup_driver);
  3817. card->discipline.ccwgdriver = NULL;
  3818. }
  3819. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3820. {
  3821. struct qeth_card *card;
  3822. struct device *dev;
  3823. int rc;
  3824. unsigned long flags;
  3825. char dbf_name[20];
  3826. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3827. dev = &gdev->dev;
  3828. if (!get_device(dev))
  3829. return -ENODEV;
  3830. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3831. card = qeth_alloc_card();
  3832. if (!card) {
  3833. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3834. rc = -ENOMEM;
  3835. goto err_dev;
  3836. }
  3837. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  3838. dev_name(&gdev->dev));
  3839. card->debug = debug_register(dbf_name, 2, 1, 8);
  3840. if (!card->debug) {
  3841. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  3842. rc = -ENOMEM;
  3843. goto err_card;
  3844. }
  3845. debug_register_view(card->debug, &debug_hex_ascii_view);
  3846. card->read.ccwdev = gdev->cdev[0];
  3847. card->write.ccwdev = gdev->cdev[1];
  3848. card->data.ccwdev = gdev->cdev[2];
  3849. dev_set_drvdata(&gdev->dev, card);
  3850. card->gdev = gdev;
  3851. gdev->cdev[0]->handler = qeth_irq;
  3852. gdev->cdev[1]->handler = qeth_irq;
  3853. gdev->cdev[2]->handler = qeth_irq;
  3854. rc = qeth_determine_card_type(card);
  3855. if (rc) {
  3856. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3857. goto err_dbf;
  3858. }
  3859. rc = qeth_setup_card(card);
  3860. if (rc) {
  3861. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3862. goto err_dbf;
  3863. }
  3864. if (card->info.type == QETH_CARD_TYPE_OSN)
  3865. rc = qeth_core_create_osn_attributes(dev);
  3866. else
  3867. rc = qeth_core_create_device_attributes(dev);
  3868. if (rc)
  3869. goto err_dbf;
  3870. switch (card->info.type) {
  3871. case QETH_CARD_TYPE_OSN:
  3872. case QETH_CARD_TYPE_OSM:
  3873. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3874. if (rc)
  3875. goto err_attr;
  3876. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3877. if (rc)
  3878. goto err_disc;
  3879. case QETH_CARD_TYPE_OSD:
  3880. case QETH_CARD_TYPE_OSX:
  3881. default:
  3882. break;
  3883. }
  3884. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3885. list_add_tail(&card->list, &qeth_core_card_list.list);
  3886. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3887. qeth_determine_capabilities(card);
  3888. return 0;
  3889. err_disc:
  3890. qeth_core_free_discipline(card);
  3891. err_attr:
  3892. if (card->info.type == QETH_CARD_TYPE_OSN)
  3893. qeth_core_remove_osn_attributes(dev);
  3894. else
  3895. qeth_core_remove_device_attributes(dev);
  3896. err_dbf:
  3897. debug_unregister(card->debug);
  3898. err_card:
  3899. qeth_core_free_card(card);
  3900. err_dev:
  3901. put_device(dev);
  3902. return rc;
  3903. }
  3904. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3905. {
  3906. unsigned long flags;
  3907. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3908. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3909. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3910. qeth_core_remove_osn_attributes(&gdev->dev);
  3911. } else {
  3912. qeth_core_remove_device_attributes(&gdev->dev);
  3913. }
  3914. if (card->discipline.ccwgdriver) {
  3915. card->discipline.ccwgdriver->remove(gdev);
  3916. qeth_core_free_discipline(card);
  3917. }
  3918. debug_unregister(card->debug);
  3919. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3920. list_del(&card->list);
  3921. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3922. qeth_core_free_card(card);
  3923. dev_set_drvdata(&gdev->dev, NULL);
  3924. put_device(&gdev->dev);
  3925. return;
  3926. }
  3927. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3928. {
  3929. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3930. int rc = 0;
  3931. int def_discipline;
  3932. if (!card->discipline.ccwgdriver) {
  3933. if (card->info.type == QETH_CARD_TYPE_IQD)
  3934. def_discipline = QETH_DISCIPLINE_LAYER3;
  3935. else
  3936. def_discipline = QETH_DISCIPLINE_LAYER2;
  3937. rc = qeth_core_load_discipline(card, def_discipline);
  3938. if (rc)
  3939. goto err;
  3940. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3941. if (rc)
  3942. goto err;
  3943. }
  3944. rc = card->discipline.ccwgdriver->set_online(gdev);
  3945. err:
  3946. return rc;
  3947. }
  3948. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3949. {
  3950. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3951. return card->discipline.ccwgdriver->set_offline(gdev);
  3952. }
  3953. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3954. {
  3955. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3956. if (card->discipline.ccwgdriver &&
  3957. card->discipline.ccwgdriver->shutdown)
  3958. card->discipline.ccwgdriver->shutdown(gdev);
  3959. }
  3960. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3961. {
  3962. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3963. if (card->discipline.ccwgdriver &&
  3964. card->discipline.ccwgdriver->prepare)
  3965. return card->discipline.ccwgdriver->prepare(gdev);
  3966. return 0;
  3967. }
  3968. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3969. {
  3970. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3971. if (card->discipline.ccwgdriver &&
  3972. card->discipline.ccwgdriver->complete)
  3973. card->discipline.ccwgdriver->complete(gdev);
  3974. }
  3975. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3976. {
  3977. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3978. if (card->discipline.ccwgdriver &&
  3979. card->discipline.ccwgdriver->freeze)
  3980. return card->discipline.ccwgdriver->freeze(gdev);
  3981. return 0;
  3982. }
  3983. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3984. {
  3985. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3986. if (card->discipline.ccwgdriver &&
  3987. card->discipline.ccwgdriver->thaw)
  3988. return card->discipline.ccwgdriver->thaw(gdev);
  3989. return 0;
  3990. }
  3991. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3992. {
  3993. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3994. if (card->discipline.ccwgdriver &&
  3995. card->discipline.ccwgdriver->restore)
  3996. return card->discipline.ccwgdriver->restore(gdev);
  3997. return 0;
  3998. }
  3999. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4000. .owner = THIS_MODULE,
  4001. .name = "qeth",
  4002. .driver_id = 0xD8C5E3C8,
  4003. .probe = qeth_core_probe_device,
  4004. .remove = qeth_core_remove_device,
  4005. .set_online = qeth_core_set_online,
  4006. .set_offline = qeth_core_set_offline,
  4007. .shutdown = qeth_core_shutdown,
  4008. .prepare = qeth_core_prepare,
  4009. .complete = qeth_core_complete,
  4010. .freeze = qeth_core_freeze,
  4011. .thaw = qeth_core_thaw,
  4012. .restore = qeth_core_restore,
  4013. };
  4014. static ssize_t
  4015. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4016. size_t count)
  4017. {
  4018. int err;
  4019. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4020. qeth_core_ccwgroup_driver.driver_id);
  4021. if (err)
  4022. return err;
  4023. else
  4024. return count;
  4025. }
  4026. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4027. static struct {
  4028. const char str[ETH_GSTRING_LEN];
  4029. } qeth_ethtool_stats_keys[] = {
  4030. /* 0 */{"rx skbs"},
  4031. {"rx buffers"},
  4032. {"tx skbs"},
  4033. {"tx buffers"},
  4034. {"tx skbs no packing"},
  4035. {"tx buffers no packing"},
  4036. {"tx skbs packing"},
  4037. {"tx buffers packing"},
  4038. {"tx sg skbs"},
  4039. {"tx sg frags"},
  4040. /* 10 */{"rx sg skbs"},
  4041. {"rx sg frags"},
  4042. {"rx sg page allocs"},
  4043. {"tx large kbytes"},
  4044. {"tx large count"},
  4045. {"tx pk state ch n->p"},
  4046. {"tx pk state ch p->n"},
  4047. {"tx pk watermark low"},
  4048. {"tx pk watermark high"},
  4049. {"queue 0 buffer usage"},
  4050. /* 20 */{"queue 1 buffer usage"},
  4051. {"queue 2 buffer usage"},
  4052. {"queue 3 buffer usage"},
  4053. {"rx poll time"},
  4054. {"rx poll count"},
  4055. {"rx do_QDIO time"},
  4056. {"rx do_QDIO count"},
  4057. {"tx handler time"},
  4058. {"tx handler count"},
  4059. {"tx time"},
  4060. /* 30 */{"tx count"},
  4061. {"tx do_QDIO time"},
  4062. {"tx do_QDIO count"},
  4063. {"tx csum"},
  4064. {"tx lin"},
  4065. };
  4066. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4067. {
  4068. switch (stringset) {
  4069. case ETH_SS_STATS:
  4070. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4071. default:
  4072. return -EINVAL;
  4073. }
  4074. }
  4075. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4076. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4077. struct ethtool_stats *stats, u64 *data)
  4078. {
  4079. struct qeth_card *card = dev->ml_priv;
  4080. data[0] = card->stats.rx_packets -
  4081. card->perf_stats.initial_rx_packets;
  4082. data[1] = card->perf_stats.bufs_rec;
  4083. data[2] = card->stats.tx_packets -
  4084. card->perf_stats.initial_tx_packets;
  4085. data[3] = card->perf_stats.bufs_sent;
  4086. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4087. - card->perf_stats.skbs_sent_pack;
  4088. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4089. data[6] = card->perf_stats.skbs_sent_pack;
  4090. data[7] = card->perf_stats.bufs_sent_pack;
  4091. data[8] = card->perf_stats.sg_skbs_sent;
  4092. data[9] = card->perf_stats.sg_frags_sent;
  4093. data[10] = card->perf_stats.sg_skbs_rx;
  4094. data[11] = card->perf_stats.sg_frags_rx;
  4095. data[12] = card->perf_stats.sg_alloc_page_rx;
  4096. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4097. data[14] = card->perf_stats.large_send_cnt;
  4098. data[15] = card->perf_stats.sc_dp_p;
  4099. data[16] = card->perf_stats.sc_p_dp;
  4100. data[17] = QETH_LOW_WATERMARK_PACK;
  4101. data[18] = QETH_HIGH_WATERMARK_PACK;
  4102. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4103. data[20] = (card->qdio.no_out_queues > 1) ?
  4104. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4105. data[21] = (card->qdio.no_out_queues > 2) ?
  4106. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4107. data[22] = (card->qdio.no_out_queues > 3) ?
  4108. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4109. data[23] = card->perf_stats.inbound_time;
  4110. data[24] = card->perf_stats.inbound_cnt;
  4111. data[25] = card->perf_stats.inbound_do_qdio_time;
  4112. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4113. data[27] = card->perf_stats.outbound_handler_time;
  4114. data[28] = card->perf_stats.outbound_handler_cnt;
  4115. data[29] = card->perf_stats.outbound_time;
  4116. data[30] = card->perf_stats.outbound_cnt;
  4117. data[31] = card->perf_stats.outbound_do_qdio_time;
  4118. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4119. data[33] = card->perf_stats.tx_csum;
  4120. data[34] = card->perf_stats.tx_lin;
  4121. }
  4122. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4123. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4124. {
  4125. switch (stringset) {
  4126. case ETH_SS_STATS:
  4127. memcpy(data, &qeth_ethtool_stats_keys,
  4128. sizeof(qeth_ethtool_stats_keys));
  4129. break;
  4130. default:
  4131. WARN_ON(1);
  4132. break;
  4133. }
  4134. }
  4135. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4136. void qeth_core_get_drvinfo(struct net_device *dev,
  4137. struct ethtool_drvinfo *info)
  4138. {
  4139. struct qeth_card *card = dev->ml_priv;
  4140. if (card->options.layer2)
  4141. strcpy(info->driver, "qeth_l2");
  4142. else
  4143. strcpy(info->driver, "qeth_l3");
  4144. strcpy(info->version, "1.0");
  4145. strcpy(info->fw_version, card->info.mcl_level);
  4146. sprintf(info->bus_info, "%s/%s/%s",
  4147. CARD_RDEV_ID(card),
  4148. CARD_WDEV_ID(card),
  4149. CARD_DDEV_ID(card));
  4150. }
  4151. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4152. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4153. struct ethtool_cmd *ecmd)
  4154. {
  4155. struct qeth_card *card = netdev->ml_priv;
  4156. enum qeth_link_types link_type;
  4157. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4158. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4159. else
  4160. link_type = card->info.link_type;
  4161. ecmd->transceiver = XCVR_INTERNAL;
  4162. ecmd->supported = SUPPORTED_Autoneg;
  4163. ecmd->advertising = ADVERTISED_Autoneg;
  4164. ecmd->duplex = DUPLEX_FULL;
  4165. ecmd->autoneg = AUTONEG_ENABLE;
  4166. switch (link_type) {
  4167. case QETH_LINK_TYPE_FAST_ETH:
  4168. case QETH_LINK_TYPE_LANE_ETH100:
  4169. ecmd->supported |= SUPPORTED_10baseT_Half |
  4170. SUPPORTED_10baseT_Full |
  4171. SUPPORTED_100baseT_Half |
  4172. SUPPORTED_100baseT_Full |
  4173. SUPPORTED_TP;
  4174. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4175. ADVERTISED_10baseT_Full |
  4176. ADVERTISED_100baseT_Half |
  4177. ADVERTISED_100baseT_Full |
  4178. ADVERTISED_TP;
  4179. ecmd->speed = SPEED_100;
  4180. ecmd->port = PORT_TP;
  4181. break;
  4182. case QETH_LINK_TYPE_GBIT_ETH:
  4183. case QETH_LINK_TYPE_LANE_ETH1000:
  4184. ecmd->supported |= SUPPORTED_10baseT_Half |
  4185. SUPPORTED_10baseT_Full |
  4186. SUPPORTED_100baseT_Half |
  4187. SUPPORTED_100baseT_Full |
  4188. SUPPORTED_1000baseT_Half |
  4189. SUPPORTED_1000baseT_Full |
  4190. SUPPORTED_FIBRE;
  4191. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4192. ADVERTISED_10baseT_Full |
  4193. ADVERTISED_100baseT_Half |
  4194. ADVERTISED_100baseT_Full |
  4195. ADVERTISED_1000baseT_Half |
  4196. ADVERTISED_1000baseT_Full |
  4197. ADVERTISED_FIBRE;
  4198. ecmd->speed = SPEED_1000;
  4199. ecmd->port = PORT_FIBRE;
  4200. break;
  4201. case QETH_LINK_TYPE_10GBIT_ETH:
  4202. ecmd->supported |= SUPPORTED_10baseT_Half |
  4203. SUPPORTED_10baseT_Full |
  4204. SUPPORTED_100baseT_Half |
  4205. SUPPORTED_100baseT_Full |
  4206. SUPPORTED_1000baseT_Half |
  4207. SUPPORTED_1000baseT_Full |
  4208. SUPPORTED_10000baseT_Full |
  4209. SUPPORTED_FIBRE;
  4210. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4211. ADVERTISED_10baseT_Full |
  4212. ADVERTISED_100baseT_Half |
  4213. ADVERTISED_100baseT_Full |
  4214. ADVERTISED_1000baseT_Half |
  4215. ADVERTISED_1000baseT_Full |
  4216. ADVERTISED_10000baseT_Full |
  4217. ADVERTISED_FIBRE;
  4218. ecmd->speed = SPEED_10000;
  4219. ecmd->port = PORT_FIBRE;
  4220. break;
  4221. default:
  4222. ecmd->supported |= SUPPORTED_10baseT_Half |
  4223. SUPPORTED_10baseT_Full |
  4224. SUPPORTED_TP;
  4225. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4226. ADVERTISED_10baseT_Full |
  4227. ADVERTISED_TP;
  4228. ecmd->speed = SPEED_10;
  4229. ecmd->port = PORT_TP;
  4230. }
  4231. return 0;
  4232. }
  4233. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4234. static int __init qeth_core_init(void)
  4235. {
  4236. int rc;
  4237. pr_info("loading core functions\n");
  4238. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4239. rwlock_init(&qeth_core_card_list.rwlock);
  4240. rc = qeth_register_dbf_views();
  4241. if (rc)
  4242. goto out_err;
  4243. rc = ccw_driver_register(&qeth_ccw_driver);
  4244. if (rc)
  4245. goto ccw_err;
  4246. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4247. if (rc)
  4248. goto ccwgroup_err;
  4249. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4250. &driver_attr_group);
  4251. if (rc)
  4252. goto driver_err;
  4253. qeth_core_root_dev = root_device_register("qeth");
  4254. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4255. if (rc)
  4256. goto register_err;
  4257. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4258. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4259. if (!qeth_core_header_cache) {
  4260. rc = -ENOMEM;
  4261. goto slab_err;
  4262. }
  4263. return 0;
  4264. slab_err:
  4265. root_device_unregister(qeth_core_root_dev);
  4266. register_err:
  4267. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4268. &driver_attr_group);
  4269. driver_err:
  4270. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4271. ccwgroup_err:
  4272. ccw_driver_unregister(&qeth_ccw_driver);
  4273. ccw_err:
  4274. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4275. qeth_unregister_dbf_views();
  4276. out_err:
  4277. pr_err("Initializing the qeth device driver failed\n");
  4278. return rc;
  4279. }
  4280. static void __exit qeth_core_exit(void)
  4281. {
  4282. root_device_unregister(qeth_core_root_dev);
  4283. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4284. &driver_attr_group);
  4285. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4286. ccw_driver_unregister(&qeth_ccw_driver);
  4287. kmem_cache_destroy(qeth_core_header_cache);
  4288. qeth_unregister_dbf_views();
  4289. pr_info("core functions removed\n");
  4290. }
  4291. module_init(qeth_core_init);
  4292. module_exit(qeth_core_exit);
  4293. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4294. MODULE_DESCRIPTION("qeth core functions");
  4295. MODULE_LICENSE("GPL");