devices.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020
  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <asm/pmu.h>
  7. #include <mach/udc.h>
  8. #include <mach/pxafb.h>
  9. #include <mach/mmc.h>
  10. #include <mach/irda.h>
  11. #include <mach/ohci.h>
  12. #include <mach/pxa27x_keypad.h>
  13. #include <mach/pxa2xx_spi.h>
  14. #include <mach/camera.h>
  15. #include <mach/audio.h>
  16. #include <mach/hardware.h>
  17. #include <plat/i2c.h>
  18. #include <plat/pxa3xx_nand.h>
  19. #include "devices.h"
  20. #include "generic.h"
  21. void __init pxa_register_device(struct platform_device *dev, void *data)
  22. {
  23. int ret;
  24. dev->dev.platform_data = data;
  25. ret = platform_device_register(dev);
  26. if (ret)
  27. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  28. }
  29. static struct resource pxa_resource_pmu = {
  30. .start = IRQ_PMU,
  31. .end = IRQ_PMU,
  32. .flags = IORESOURCE_IRQ,
  33. };
  34. struct platform_device pxa_device_pmu = {
  35. .name = "arm-pmu",
  36. .id = ARM_PMU_DEVICE_CPU,
  37. .resource = &pxa_resource_pmu,
  38. .num_resources = 1,
  39. };
  40. static struct resource pxamci_resources[] = {
  41. [0] = {
  42. .start = 0x41100000,
  43. .end = 0x41100fff,
  44. .flags = IORESOURCE_MEM,
  45. },
  46. [1] = {
  47. .start = IRQ_MMC,
  48. .end = IRQ_MMC,
  49. .flags = IORESOURCE_IRQ,
  50. },
  51. [2] = {
  52. .start = 21,
  53. .end = 21,
  54. .flags = IORESOURCE_DMA,
  55. },
  56. [3] = {
  57. .start = 22,
  58. .end = 22,
  59. .flags = IORESOURCE_DMA,
  60. },
  61. };
  62. static u64 pxamci_dmamask = 0xffffffffUL;
  63. struct platform_device pxa_device_mci = {
  64. .name = "pxa2xx-mci",
  65. .id = 0,
  66. .dev = {
  67. .dma_mask = &pxamci_dmamask,
  68. .coherent_dma_mask = 0xffffffff,
  69. },
  70. .num_resources = ARRAY_SIZE(pxamci_resources),
  71. .resource = pxamci_resources,
  72. };
  73. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  74. {
  75. pxa_register_device(&pxa_device_mci, info);
  76. }
  77. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  78. .gpio_pullup = -1,
  79. .gpio_vbus = -1,
  80. };
  81. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  82. {
  83. memcpy(&pxa_udc_info, info, sizeof *info);
  84. }
  85. static struct resource pxa2xx_udc_resources[] = {
  86. [0] = {
  87. .start = 0x40600000,
  88. .end = 0x4060ffff,
  89. .flags = IORESOURCE_MEM,
  90. },
  91. [1] = {
  92. .start = IRQ_USB,
  93. .end = IRQ_USB,
  94. .flags = IORESOURCE_IRQ,
  95. },
  96. };
  97. static u64 udc_dma_mask = ~(u32)0;
  98. struct platform_device pxa25x_device_udc = {
  99. .name = "pxa25x-udc",
  100. .id = -1,
  101. .resource = pxa2xx_udc_resources,
  102. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  103. .dev = {
  104. .platform_data = &pxa_udc_info,
  105. .dma_mask = &udc_dma_mask,
  106. }
  107. };
  108. struct platform_device pxa27x_device_udc = {
  109. .name = "pxa27x-udc",
  110. .id = -1,
  111. .resource = pxa2xx_udc_resources,
  112. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  113. .dev = {
  114. .platform_data = &pxa_udc_info,
  115. .dma_mask = &udc_dma_mask,
  116. }
  117. };
  118. static struct resource pxafb_resources[] = {
  119. [0] = {
  120. .start = 0x44000000,
  121. .end = 0x4400ffff,
  122. .flags = IORESOURCE_MEM,
  123. },
  124. [1] = {
  125. .start = IRQ_LCD,
  126. .end = IRQ_LCD,
  127. .flags = IORESOURCE_IRQ,
  128. },
  129. };
  130. static u64 fb_dma_mask = ~(u64)0;
  131. struct platform_device pxa_device_fb = {
  132. .name = "pxa2xx-fb",
  133. .id = -1,
  134. .dev = {
  135. .dma_mask = &fb_dma_mask,
  136. .coherent_dma_mask = 0xffffffff,
  137. },
  138. .num_resources = ARRAY_SIZE(pxafb_resources),
  139. .resource = pxafb_resources,
  140. };
  141. void __init set_pxa_fb_info(struct pxafb_mach_info *info)
  142. {
  143. pxa_register_device(&pxa_device_fb, info);
  144. }
  145. void __init set_pxa_fb_parent(struct device *parent_dev)
  146. {
  147. pxa_device_fb.dev.parent = parent_dev;
  148. }
  149. static struct resource pxa_resource_ffuart[] = {
  150. {
  151. .start = 0x40100000,
  152. .end = 0x40100023,
  153. .flags = IORESOURCE_MEM,
  154. }, {
  155. .start = IRQ_FFUART,
  156. .end = IRQ_FFUART,
  157. .flags = IORESOURCE_IRQ,
  158. }
  159. };
  160. struct platform_device pxa_device_ffuart = {
  161. .name = "pxa2xx-uart",
  162. .id = 0,
  163. .resource = pxa_resource_ffuart,
  164. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  165. };
  166. void __init pxa_set_ffuart_info(void *info)
  167. {
  168. pxa_register_device(&pxa_device_ffuart, info);
  169. }
  170. static struct resource pxa_resource_btuart[] = {
  171. {
  172. .start = 0x40200000,
  173. .end = 0x40200023,
  174. .flags = IORESOURCE_MEM,
  175. }, {
  176. .start = IRQ_BTUART,
  177. .end = IRQ_BTUART,
  178. .flags = IORESOURCE_IRQ,
  179. }
  180. };
  181. struct platform_device pxa_device_btuart = {
  182. .name = "pxa2xx-uart",
  183. .id = 1,
  184. .resource = pxa_resource_btuart,
  185. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  186. };
  187. void __init pxa_set_btuart_info(void *info)
  188. {
  189. pxa_register_device(&pxa_device_btuart, info);
  190. }
  191. static struct resource pxa_resource_stuart[] = {
  192. {
  193. .start = 0x40700000,
  194. .end = 0x40700023,
  195. .flags = IORESOURCE_MEM,
  196. }, {
  197. .start = IRQ_STUART,
  198. .end = IRQ_STUART,
  199. .flags = IORESOURCE_IRQ,
  200. }
  201. };
  202. struct platform_device pxa_device_stuart = {
  203. .name = "pxa2xx-uart",
  204. .id = 2,
  205. .resource = pxa_resource_stuart,
  206. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  207. };
  208. void __init pxa_set_stuart_info(void *info)
  209. {
  210. pxa_register_device(&pxa_device_stuart, info);
  211. }
  212. static struct resource pxa_resource_hwuart[] = {
  213. {
  214. .start = 0x41600000,
  215. .end = 0x4160002F,
  216. .flags = IORESOURCE_MEM,
  217. }, {
  218. .start = IRQ_HWUART,
  219. .end = IRQ_HWUART,
  220. .flags = IORESOURCE_IRQ,
  221. }
  222. };
  223. struct platform_device pxa_device_hwuart = {
  224. .name = "pxa2xx-uart",
  225. .id = 3,
  226. .resource = pxa_resource_hwuart,
  227. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  228. };
  229. void __init pxa_set_hwuart_info(void *info)
  230. {
  231. if (cpu_is_pxa255())
  232. pxa_register_device(&pxa_device_hwuart, info);
  233. else
  234. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  235. }
  236. static struct resource pxai2c_resources[] = {
  237. {
  238. .start = 0x40301680,
  239. .end = 0x403016a3,
  240. .flags = IORESOURCE_MEM,
  241. }, {
  242. .start = IRQ_I2C,
  243. .end = IRQ_I2C,
  244. .flags = IORESOURCE_IRQ,
  245. },
  246. };
  247. struct platform_device pxa_device_i2c = {
  248. .name = "pxa2xx-i2c",
  249. .id = 0,
  250. .resource = pxai2c_resources,
  251. .num_resources = ARRAY_SIZE(pxai2c_resources),
  252. };
  253. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  254. {
  255. pxa_register_device(&pxa_device_i2c, info);
  256. }
  257. #ifdef CONFIG_PXA27x
  258. static struct resource pxa27x_resources_i2c_power[] = {
  259. {
  260. .start = 0x40f00180,
  261. .end = 0x40f001a3,
  262. .flags = IORESOURCE_MEM,
  263. }, {
  264. .start = IRQ_PWRI2C,
  265. .end = IRQ_PWRI2C,
  266. .flags = IORESOURCE_IRQ,
  267. },
  268. };
  269. struct platform_device pxa27x_device_i2c_power = {
  270. .name = "pxa2xx-i2c",
  271. .id = 1,
  272. .resource = pxa27x_resources_i2c_power,
  273. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  274. };
  275. #endif
  276. #ifdef CONFIG_PXA3xx
  277. static struct resource pxa3xx_resources_i2c_power[] = {
  278. {
  279. .start = 0x40f500c0,
  280. .end = 0x40f500d3,
  281. .flags = IORESOURCE_MEM,
  282. }, {
  283. .start = IRQ_PWRI2C,
  284. .end = IRQ_PWRI2C,
  285. .flags = IORESOURCE_IRQ,
  286. },
  287. };
  288. struct platform_device pxa3xx_device_i2c_power = {
  289. .name = "pxa3xx-pwri2c",
  290. .id = 1,
  291. .resource = pxa3xx_resources_i2c_power,
  292. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  293. };
  294. #endif
  295. static struct resource pxai2s_resources[] = {
  296. {
  297. .start = 0x40400000,
  298. .end = 0x40400083,
  299. .flags = IORESOURCE_MEM,
  300. }, {
  301. .start = IRQ_I2S,
  302. .end = IRQ_I2S,
  303. .flags = IORESOURCE_IRQ,
  304. },
  305. };
  306. struct platform_device pxa_device_i2s = {
  307. .name = "pxa2xx-i2s",
  308. .id = -1,
  309. .resource = pxai2s_resources,
  310. .num_resources = ARRAY_SIZE(pxai2s_resources),
  311. };
  312. static u64 pxaficp_dmamask = ~(u32)0;
  313. struct platform_device pxa_device_ficp = {
  314. .name = "pxa2xx-ir",
  315. .id = -1,
  316. .dev = {
  317. .dma_mask = &pxaficp_dmamask,
  318. .coherent_dma_mask = 0xffffffff,
  319. },
  320. };
  321. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  322. {
  323. pxa_register_device(&pxa_device_ficp, info);
  324. }
  325. static struct resource pxa_rtc_resources[] = {
  326. [0] = {
  327. .start = 0x40900000,
  328. .end = 0x40900000 + 0x3b,
  329. .flags = IORESOURCE_MEM,
  330. },
  331. [1] = {
  332. .start = IRQ_RTC1Hz,
  333. .end = IRQ_RTC1Hz,
  334. .flags = IORESOURCE_IRQ,
  335. },
  336. [2] = {
  337. .start = IRQ_RTCAlrm,
  338. .end = IRQ_RTCAlrm,
  339. .flags = IORESOURCE_IRQ,
  340. },
  341. };
  342. struct platform_device sa1100_device_rtc = {
  343. .name = "sa1100-rtc",
  344. .id = -1,
  345. };
  346. struct platform_device pxa_device_rtc = {
  347. .name = "pxa-rtc",
  348. .id = -1,
  349. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  350. .resource = pxa_rtc_resources,
  351. };
  352. static struct resource pxa_ac97_resources[] = {
  353. [0] = {
  354. .start = 0x40500000,
  355. .end = 0x40500000 + 0xfff,
  356. .flags = IORESOURCE_MEM,
  357. },
  358. [1] = {
  359. .start = IRQ_AC97,
  360. .end = IRQ_AC97,
  361. .flags = IORESOURCE_IRQ,
  362. },
  363. };
  364. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  365. struct platform_device pxa_device_ac97 = {
  366. .name = "pxa2xx-ac97",
  367. .id = -1,
  368. .dev = {
  369. .dma_mask = &pxa_ac97_dmamask,
  370. .coherent_dma_mask = 0xffffffff,
  371. },
  372. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  373. .resource = pxa_ac97_resources,
  374. };
  375. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  376. {
  377. pxa_register_device(&pxa_device_ac97, ops);
  378. }
  379. #ifdef CONFIG_PXA25x
  380. static struct resource pxa25x_resource_pwm0[] = {
  381. [0] = {
  382. .start = 0x40b00000,
  383. .end = 0x40b0000f,
  384. .flags = IORESOURCE_MEM,
  385. },
  386. };
  387. struct platform_device pxa25x_device_pwm0 = {
  388. .name = "pxa25x-pwm",
  389. .id = 0,
  390. .resource = pxa25x_resource_pwm0,
  391. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  392. };
  393. static struct resource pxa25x_resource_pwm1[] = {
  394. [0] = {
  395. .start = 0x40c00000,
  396. .end = 0x40c0000f,
  397. .flags = IORESOURCE_MEM,
  398. },
  399. };
  400. struct platform_device pxa25x_device_pwm1 = {
  401. .name = "pxa25x-pwm",
  402. .id = 1,
  403. .resource = pxa25x_resource_pwm1,
  404. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  405. };
  406. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  407. static struct resource pxa25x_resource_ssp[] = {
  408. [0] = {
  409. .start = 0x41000000,
  410. .end = 0x4100001f,
  411. .flags = IORESOURCE_MEM,
  412. },
  413. [1] = {
  414. .start = IRQ_SSP,
  415. .end = IRQ_SSP,
  416. .flags = IORESOURCE_IRQ,
  417. },
  418. [2] = {
  419. /* DRCMR for RX */
  420. .start = 13,
  421. .end = 13,
  422. .flags = IORESOURCE_DMA,
  423. },
  424. [3] = {
  425. /* DRCMR for TX */
  426. .start = 14,
  427. .end = 14,
  428. .flags = IORESOURCE_DMA,
  429. },
  430. };
  431. struct platform_device pxa25x_device_ssp = {
  432. .name = "pxa25x-ssp",
  433. .id = 0,
  434. .dev = {
  435. .dma_mask = &pxa25x_ssp_dma_mask,
  436. .coherent_dma_mask = DMA_BIT_MASK(32),
  437. },
  438. .resource = pxa25x_resource_ssp,
  439. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  440. };
  441. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  442. static struct resource pxa25x_resource_nssp[] = {
  443. [0] = {
  444. .start = 0x41400000,
  445. .end = 0x4140002f,
  446. .flags = IORESOURCE_MEM,
  447. },
  448. [1] = {
  449. .start = IRQ_NSSP,
  450. .end = IRQ_NSSP,
  451. .flags = IORESOURCE_IRQ,
  452. },
  453. [2] = {
  454. /* DRCMR for RX */
  455. .start = 15,
  456. .end = 15,
  457. .flags = IORESOURCE_DMA,
  458. },
  459. [3] = {
  460. /* DRCMR for TX */
  461. .start = 16,
  462. .end = 16,
  463. .flags = IORESOURCE_DMA,
  464. },
  465. };
  466. struct platform_device pxa25x_device_nssp = {
  467. .name = "pxa25x-nssp",
  468. .id = 1,
  469. .dev = {
  470. .dma_mask = &pxa25x_nssp_dma_mask,
  471. .coherent_dma_mask = DMA_BIT_MASK(32),
  472. },
  473. .resource = pxa25x_resource_nssp,
  474. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  475. };
  476. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  477. static struct resource pxa25x_resource_assp[] = {
  478. [0] = {
  479. .start = 0x41500000,
  480. .end = 0x4150002f,
  481. .flags = IORESOURCE_MEM,
  482. },
  483. [1] = {
  484. .start = IRQ_ASSP,
  485. .end = IRQ_ASSP,
  486. .flags = IORESOURCE_IRQ,
  487. },
  488. [2] = {
  489. /* DRCMR for RX */
  490. .start = 23,
  491. .end = 23,
  492. .flags = IORESOURCE_DMA,
  493. },
  494. [3] = {
  495. /* DRCMR for TX */
  496. .start = 24,
  497. .end = 24,
  498. .flags = IORESOURCE_DMA,
  499. },
  500. };
  501. struct platform_device pxa25x_device_assp = {
  502. /* ASSP is basically equivalent to NSSP */
  503. .name = "pxa25x-nssp",
  504. .id = 2,
  505. .dev = {
  506. .dma_mask = &pxa25x_assp_dma_mask,
  507. .coherent_dma_mask = DMA_BIT_MASK(32),
  508. },
  509. .resource = pxa25x_resource_assp,
  510. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  511. };
  512. #endif /* CONFIG_PXA25x */
  513. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  514. static struct resource pxa27x_resource_keypad[] = {
  515. [0] = {
  516. .start = 0x41500000,
  517. .end = 0x4150004c,
  518. .flags = IORESOURCE_MEM,
  519. },
  520. [1] = {
  521. .start = IRQ_KEYPAD,
  522. .end = IRQ_KEYPAD,
  523. .flags = IORESOURCE_IRQ,
  524. },
  525. };
  526. struct platform_device pxa27x_device_keypad = {
  527. .name = "pxa27x-keypad",
  528. .id = -1,
  529. .resource = pxa27x_resource_keypad,
  530. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  531. };
  532. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  533. {
  534. pxa_register_device(&pxa27x_device_keypad, info);
  535. }
  536. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  537. static struct resource pxa27x_resource_ohci[] = {
  538. [0] = {
  539. .start = 0x4C000000,
  540. .end = 0x4C00ff6f,
  541. .flags = IORESOURCE_MEM,
  542. },
  543. [1] = {
  544. .start = IRQ_USBH1,
  545. .end = IRQ_USBH1,
  546. .flags = IORESOURCE_IRQ,
  547. },
  548. };
  549. struct platform_device pxa27x_device_ohci = {
  550. .name = "pxa27x-ohci",
  551. .id = -1,
  552. .dev = {
  553. .dma_mask = &pxa27x_ohci_dma_mask,
  554. .coherent_dma_mask = DMA_BIT_MASK(32),
  555. },
  556. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  557. .resource = pxa27x_resource_ohci,
  558. };
  559. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  560. {
  561. pxa_register_device(&pxa27x_device_ohci, info);
  562. }
  563. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  564. static struct resource pxa27x_resource_ssp1[] = {
  565. [0] = {
  566. .start = 0x41000000,
  567. .end = 0x4100003f,
  568. .flags = IORESOURCE_MEM,
  569. },
  570. [1] = {
  571. .start = IRQ_SSP,
  572. .end = IRQ_SSP,
  573. .flags = IORESOURCE_IRQ,
  574. },
  575. [2] = {
  576. /* DRCMR for RX */
  577. .start = 13,
  578. .end = 13,
  579. .flags = IORESOURCE_DMA,
  580. },
  581. [3] = {
  582. /* DRCMR for TX */
  583. .start = 14,
  584. .end = 14,
  585. .flags = IORESOURCE_DMA,
  586. },
  587. };
  588. struct platform_device pxa27x_device_ssp1 = {
  589. .name = "pxa27x-ssp",
  590. .id = 0,
  591. .dev = {
  592. .dma_mask = &pxa27x_ssp1_dma_mask,
  593. .coherent_dma_mask = DMA_BIT_MASK(32),
  594. },
  595. .resource = pxa27x_resource_ssp1,
  596. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  597. };
  598. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  599. static struct resource pxa27x_resource_ssp2[] = {
  600. [0] = {
  601. .start = 0x41700000,
  602. .end = 0x4170003f,
  603. .flags = IORESOURCE_MEM,
  604. },
  605. [1] = {
  606. .start = IRQ_SSP2,
  607. .end = IRQ_SSP2,
  608. .flags = IORESOURCE_IRQ,
  609. },
  610. [2] = {
  611. /* DRCMR for RX */
  612. .start = 15,
  613. .end = 15,
  614. .flags = IORESOURCE_DMA,
  615. },
  616. [3] = {
  617. /* DRCMR for TX */
  618. .start = 16,
  619. .end = 16,
  620. .flags = IORESOURCE_DMA,
  621. },
  622. };
  623. struct platform_device pxa27x_device_ssp2 = {
  624. .name = "pxa27x-ssp",
  625. .id = 1,
  626. .dev = {
  627. .dma_mask = &pxa27x_ssp2_dma_mask,
  628. .coherent_dma_mask = DMA_BIT_MASK(32),
  629. },
  630. .resource = pxa27x_resource_ssp2,
  631. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  632. };
  633. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  634. static struct resource pxa27x_resource_ssp3[] = {
  635. [0] = {
  636. .start = 0x41900000,
  637. .end = 0x4190003f,
  638. .flags = IORESOURCE_MEM,
  639. },
  640. [1] = {
  641. .start = IRQ_SSP3,
  642. .end = IRQ_SSP3,
  643. .flags = IORESOURCE_IRQ,
  644. },
  645. [2] = {
  646. /* DRCMR for RX */
  647. .start = 66,
  648. .end = 66,
  649. .flags = IORESOURCE_DMA,
  650. },
  651. [3] = {
  652. /* DRCMR for TX */
  653. .start = 67,
  654. .end = 67,
  655. .flags = IORESOURCE_DMA,
  656. },
  657. };
  658. struct platform_device pxa27x_device_ssp3 = {
  659. .name = "pxa27x-ssp",
  660. .id = 2,
  661. .dev = {
  662. .dma_mask = &pxa27x_ssp3_dma_mask,
  663. .coherent_dma_mask = DMA_BIT_MASK(32),
  664. },
  665. .resource = pxa27x_resource_ssp3,
  666. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  667. };
  668. static struct resource pxa27x_resource_pwm0[] = {
  669. [0] = {
  670. .start = 0x40b00000,
  671. .end = 0x40b0001f,
  672. .flags = IORESOURCE_MEM,
  673. },
  674. };
  675. struct platform_device pxa27x_device_pwm0 = {
  676. .name = "pxa27x-pwm",
  677. .id = 0,
  678. .resource = pxa27x_resource_pwm0,
  679. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  680. };
  681. static struct resource pxa27x_resource_pwm1[] = {
  682. [0] = {
  683. .start = 0x40c00000,
  684. .end = 0x40c0001f,
  685. .flags = IORESOURCE_MEM,
  686. },
  687. };
  688. struct platform_device pxa27x_device_pwm1 = {
  689. .name = "pxa27x-pwm",
  690. .id = 1,
  691. .resource = pxa27x_resource_pwm1,
  692. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  693. };
  694. static struct resource pxa27x_resource_camera[] = {
  695. [0] = {
  696. .start = 0x50000000,
  697. .end = 0x50000fff,
  698. .flags = IORESOURCE_MEM,
  699. },
  700. [1] = {
  701. .start = IRQ_CAMERA,
  702. .end = IRQ_CAMERA,
  703. .flags = IORESOURCE_IRQ,
  704. },
  705. };
  706. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  707. static struct platform_device pxa27x_device_camera = {
  708. .name = "pxa27x-camera",
  709. .id = 0, /* This is used to put cameras on this interface */
  710. .dev = {
  711. .dma_mask = &pxa27x_dma_mask_camera,
  712. .coherent_dma_mask = 0xffffffff,
  713. },
  714. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  715. .resource = pxa27x_resource_camera,
  716. };
  717. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  718. {
  719. pxa_register_device(&pxa27x_device_camera, info);
  720. }
  721. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  722. #ifdef CONFIG_PXA3xx
  723. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  724. static struct resource pxa3xx_resource_ssp4[] = {
  725. [0] = {
  726. .start = 0x41a00000,
  727. .end = 0x41a0003f,
  728. .flags = IORESOURCE_MEM,
  729. },
  730. [1] = {
  731. .start = IRQ_SSP4,
  732. .end = IRQ_SSP4,
  733. .flags = IORESOURCE_IRQ,
  734. },
  735. [2] = {
  736. /* DRCMR for RX */
  737. .start = 2,
  738. .end = 2,
  739. .flags = IORESOURCE_DMA,
  740. },
  741. [3] = {
  742. /* DRCMR for TX */
  743. .start = 3,
  744. .end = 3,
  745. .flags = IORESOURCE_DMA,
  746. },
  747. };
  748. struct platform_device pxa3xx_device_ssp4 = {
  749. /* PXA3xx SSP is basically equivalent to PXA27x */
  750. .name = "pxa27x-ssp",
  751. .id = 3,
  752. .dev = {
  753. .dma_mask = &pxa3xx_ssp4_dma_mask,
  754. .coherent_dma_mask = DMA_BIT_MASK(32),
  755. },
  756. .resource = pxa3xx_resource_ssp4,
  757. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  758. };
  759. static struct resource pxa3xx_resources_mci2[] = {
  760. [0] = {
  761. .start = 0x42000000,
  762. .end = 0x42000fff,
  763. .flags = IORESOURCE_MEM,
  764. },
  765. [1] = {
  766. .start = IRQ_MMC2,
  767. .end = IRQ_MMC2,
  768. .flags = IORESOURCE_IRQ,
  769. },
  770. [2] = {
  771. .start = 93,
  772. .end = 93,
  773. .flags = IORESOURCE_DMA,
  774. },
  775. [3] = {
  776. .start = 94,
  777. .end = 94,
  778. .flags = IORESOURCE_DMA,
  779. },
  780. };
  781. struct platform_device pxa3xx_device_mci2 = {
  782. .name = "pxa2xx-mci",
  783. .id = 1,
  784. .dev = {
  785. .dma_mask = &pxamci_dmamask,
  786. .coherent_dma_mask = 0xffffffff,
  787. },
  788. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  789. .resource = pxa3xx_resources_mci2,
  790. };
  791. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  792. {
  793. pxa_register_device(&pxa3xx_device_mci2, info);
  794. }
  795. static struct resource pxa3xx_resources_mci3[] = {
  796. [0] = {
  797. .start = 0x42500000,
  798. .end = 0x42500fff,
  799. .flags = IORESOURCE_MEM,
  800. },
  801. [1] = {
  802. .start = IRQ_MMC3,
  803. .end = IRQ_MMC3,
  804. .flags = IORESOURCE_IRQ,
  805. },
  806. [2] = {
  807. .start = 100,
  808. .end = 100,
  809. .flags = IORESOURCE_DMA,
  810. },
  811. [3] = {
  812. .start = 101,
  813. .end = 101,
  814. .flags = IORESOURCE_DMA,
  815. },
  816. };
  817. struct platform_device pxa3xx_device_mci3 = {
  818. .name = "pxa2xx-mci",
  819. .id = 2,
  820. .dev = {
  821. .dma_mask = &pxamci_dmamask,
  822. .coherent_dma_mask = 0xffffffff,
  823. },
  824. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  825. .resource = pxa3xx_resources_mci3,
  826. };
  827. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  828. {
  829. pxa_register_device(&pxa3xx_device_mci3, info);
  830. }
  831. static struct resource pxa3xx_resources_nand[] = {
  832. [0] = {
  833. .start = 0x43100000,
  834. .end = 0x43100053,
  835. .flags = IORESOURCE_MEM,
  836. },
  837. [1] = {
  838. .start = IRQ_NAND,
  839. .end = IRQ_NAND,
  840. .flags = IORESOURCE_IRQ,
  841. },
  842. [2] = {
  843. /* DRCMR for Data DMA */
  844. .start = 97,
  845. .end = 97,
  846. .flags = IORESOURCE_DMA,
  847. },
  848. [3] = {
  849. /* DRCMR for Command DMA */
  850. .start = 99,
  851. .end = 99,
  852. .flags = IORESOURCE_DMA,
  853. },
  854. };
  855. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  856. struct platform_device pxa3xx_device_nand = {
  857. .name = "pxa3xx-nand",
  858. .id = -1,
  859. .dev = {
  860. .dma_mask = &pxa3xx_nand_dma_mask,
  861. .coherent_dma_mask = DMA_BIT_MASK(32),
  862. },
  863. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  864. .resource = pxa3xx_resources_nand,
  865. };
  866. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  867. {
  868. pxa_register_device(&pxa3xx_device_nand, info);
  869. }
  870. static struct resource pxa3xx_resources_gcu[] = {
  871. {
  872. .start = 0x54000000,
  873. .end = 0x54000fff,
  874. .flags = IORESOURCE_MEM,
  875. },
  876. {
  877. .start = IRQ_GCU,
  878. .end = IRQ_GCU,
  879. .flags = IORESOURCE_IRQ,
  880. },
  881. };
  882. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  883. struct platform_device pxa3xx_device_gcu = {
  884. .name = "pxa3xx-gcu",
  885. .id = -1,
  886. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  887. .resource = pxa3xx_resources_gcu,
  888. .dev = {
  889. .dma_mask = &pxa3xx_gcu_dmamask,
  890. .coherent_dma_mask = 0xffffffff,
  891. },
  892. };
  893. #endif /* CONFIG_PXA3xx */
  894. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  895. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  896. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  897. {
  898. struct platform_device *pd;
  899. pd = platform_device_alloc("pxa2xx-spi", id);
  900. if (pd == NULL) {
  901. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  902. id);
  903. return;
  904. }
  905. pd->dev.platform_data = info;
  906. platform_device_add(pd);
  907. }