main.c 50 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. #include "btcoex.h"
  19. static void ath_cache_conf_rate(struct ath_softc *sc,
  20. struct ieee80211_conf *conf)
  21. {
  22. switch (conf->channel->band) {
  23. case IEEE80211_BAND_2GHZ:
  24. if (conf_is_ht20(conf))
  25. sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
  26. else if (conf_is_ht40_minus(conf))
  27. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
  28. else if (conf_is_ht40_plus(conf))
  29. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
  30. else
  31. sc->cur_rate_mode = ATH9K_MODE_11G;
  32. break;
  33. case IEEE80211_BAND_5GHZ:
  34. if (conf_is_ht20(conf))
  35. sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
  36. else if (conf_is_ht40_minus(conf))
  37. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
  38. else if (conf_is_ht40_plus(conf))
  39. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
  40. else
  41. sc->cur_rate_mode = ATH9K_MODE_11A;
  42. break;
  43. default:
  44. BUG_ON(1);
  45. break;
  46. }
  47. }
  48. static void ath_update_txpow(struct ath_softc *sc)
  49. {
  50. struct ath_hw *ah = sc->sc_ah;
  51. if (sc->curtxpow != sc->config.txpowlimit) {
  52. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
  53. /* read back in case value is clamped */
  54. sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
  55. }
  56. }
  57. static u8 parse_mpdudensity(u8 mpdudensity)
  58. {
  59. /*
  60. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  61. * 0 for no restriction
  62. * 1 for 1/4 us
  63. * 2 for 1/2 us
  64. * 3 for 1 us
  65. * 4 for 2 us
  66. * 5 for 4 us
  67. * 6 for 8 us
  68. * 7 for 16 us
  69. */
  70. switch (mpdudensity) {
  71. case 0:
  72. return 0;
  73. case 1:
  74. case 2:
  75. case 3:
  76. /* Our lower layer calculations limit our precision to
  77. 1 microsecond */
  78. return 1;
  79. case 4:
  80. return 2;
  81. case 5:
  82. return 4;
  83. case 6:
  84. return 8;
  85. case 7:
  86. return 16;
  87. default:
  88. return 0;
  89. }
  90. }
  91. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  92. struct ieee80211_hw *hw)
  93. {
  94. struct ieee80211_channel *curchan = hw->conf.channel;
  95. struct ath9k_channel *channel;
  96. u8 chan_idx;
  97. chan_idx = curchan->hw_value;
  98. channel = &sc->sc_ah->channels[chan_idx];
  99. ath9k_update_ichannel(sc, hw, channel);
  100. return channel;
  101. }
  102. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  103. {
  104. unsigned long flags;
  105. bool ret;
  106. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  107. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  108. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  109. return ret;
  110. }
  111. void ath9k_ps_wakeup(struct ath_softc *sc)
  112. {
  113. unsigned long flags;
  114. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  115. if (++sc->ps_usecount != 1)
  116. goto unlock;
  117. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  118. unlock:
  119. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  120. }
  121. void ath9k_ps_restore(struct ath_softc *sc)
  122. {
  123. unsigned long flags;
  124. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  125. if (--sc->ps_usecount != 0)
  126. goto unlock;
  127. if (sc->ps_idle)
  128. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  129. else if (sc->ps_enabled &&
  130. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  131. PS_WAIT_FOR_CAB |
  132. PS_WAIT_FOR_PSPOLL_DATA |
  133. PS_WAIT_FOR_TX_ACK)))
  134. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  135. unlock:
  136. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  137. }
  138. /*
  139. * Set/change channels. If the channel is really being changed, it's done
  140. * by reseting the chip. To accomplish this we must first cleanup any pending
  141. * DMA, then restart stuff.
  142. */
  143. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  144. struct ath9k_channel *hchan)
  145. {
  146. struct ath_hw *ah = sc->sc_ah;
  147. struct ath_common *common = ath9k_hw_common(ah);
  148. struct ieee80211_conf *conf = &common->hw->conf;
  149. bool fastcc = true, stopped;
  150. struct ieee80211_channel *channel = hw->conf.channel;
  151. int r;
  152. if (sc->sc_flags & SC_OP_INVALID)
  153. return -EIO;
  154. ath9k_ps_wakeup(sc);
  155. /*
  156. * This is only performed if the channel settings have
  157. * actually changed.
  158. *
  159. * To switch channels clear any pending DMA operations;
  160. * wait long enough for the RX fifo to drain, reset the
  161. * hardware at the new frequency, and then re-enable
  162. * the relevant bits of the h/w.
  163. */
  164. ath9k_hw_set_interrupts(ah, 0);
  165. ath_drain_all_txq(sc, false);
  166. stopped = ath_stoprecv(sc);
  167. /* XXX: do not flush receive queue here. We don't want
  168. * to flush data frames already in queue because of
  169. * changing channel. */
  170. if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
  171. fastcc = false;
  172. ath_print(common, ATH_DBG_CONFIG,
  173. "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
  174. sc->sc_ah->curchan->channel,
  175. channel->center_freq, conf_is_ht40(conf));
  176. spin_lock_bh(&sc->sc_resetlock);
  177. r = ath9k_hw_reset(ah, hchan, fastcc);
  178. if (r) {
  179. ath_print(common, ATH_DBG_FATAL,
  180. "Unable to reset channel (%u MHz), "
  181. "reset status %d\n",
  182. channel->center_freq, r);
  183. spin_unlock_bh(&sc->sc_resetlock);
  184. goto ps_restore;
  185. }
  186. spin_unlock_bh(&sc->sc_resetlock);
  187. sc->sc_flags &= ~SC_OP_FULL_RESET;
  188. if (ath_startrecv(sc) != 0) {
  189. ath_print(common, ATH_DBG_FATAL,
  190. "Unable to restart recv logic\n");
  191. r = -EIO;
  192. goto ps_restore;
  193. }
  194. ath_cache_conf_rate(sc, &hw->conf);
  195. ath_update_txpow(sc);
  196. ath9k_hw_set_interrupts(ah, ah->imask);
  197. ps_restore:
  198. ath9k_ps_restore(sc);
  199. return r;
  200. }
  201. static void ath_paprd_activate(struct ath_softc *sc)
  202. {
  203. struct ath_hw *ah = sc->sc_ah;
  204. int chain;
  205. if (!ah->curchan->paprd_done)
  206. return;
  207. ath9k_ps_wakeup(sc);
  208. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  209. if (!(ah->caps.tx_chainmask & BIT(chain)))
  210. continue;
  211. ar9003_paprd_populate_single_table(ah, ah->curchan, chain);
  212. }
  213. ar9003_paprd_enable(ah, true);
  214. ath9k_ps_restore(sc);
  215. }
  216. void ath_paprd_calibrate(struct work_struct *work)
  217. {
  218. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  219. struct ieee80211_hw *hw = sc->hw;
  220. struct ath_hw *ah = sc->sc_ah;
  221. struct ieee80211_hdr *hdr;
  222. struct sk_buff *skb = NULL;
  223. struct ieee80211_tx_info *tx_info;
  224. int band = hw->conf.channel->band;
  225. struct ieee80211_supported_band *sband = &sc->sbands[band];
  226. struct ath_tx_control txctl;
  227. int qnum, ftype;
  228. int chain_ok = 0;
  229. int chain;
  230. int len = 1800;
  231. int time_left;
  232. int i;
  233. ath9k_ps_wakeup(sc);
  234. skb = alloc_skb(len, GFP_KERNEL);
  235. if (!skb)
  236. return;
  237. tx_info = IEEE80211_SKB_CB(skb);
  238. skb_put(skb, len);
  239. memset(skb->data, 0, len);
  240. hdr = (struct ieee80211_hdr *)skb->data;
  241. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  242. hdr->frame_control = cpu_to_le16(ftype);
  243. hdr->duration_id = 10;
  244. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  245. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  246. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  247. memset(&txctl, 0, sizeof(txctl));
  248. qnum = sc->tx.hwq_map[WME_AC_BE];
  249. txctl.txq = &sc->tx.txq[qnum];
  250. ar9003_paprd_init_table(ah);
  251. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  252. if (!(ah->caps.tx_chainmask & BIT(chain)))
  253. continue;
  254. chain_ok = 0;
  255. memset(tx_info, 0, sizeof(*tx_info));
  256. tx_info->band = band;
  257. for (i = 0; i < 4; i++) {
  258. tx_info->control.rates[i].idx = sband->n_bitrates - 1;
  259. tx_info->control.rates[i].count = 6;
  260. }
  261. init_completion(&sc->paprd_complete);
  262. ar9003_paprd_setup_gain_table(ah, chain);
  263. txctl.paprd = BIT(chain);
  264. if (ath_tx_start(hw, skb, &txctl) != 0)
  265. break;
  266. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  267. 100);
  268. if (!time_left) {
  269. ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
  270. "Timeout waiting for paprd training on "
  271. "TX chain %d\n",
  272. chain);
  273. break;
  274. }
  275. if (!ar9003_paprd_is_done(ah))
  276. break;
  277. if (ar9003_paprd_create_curve(ah, ah->curchan, chain) != 0)
  278. break;
  279. chain_ok = 1;
  280. }
  281. kfree_skb(skb);
  282. if (chain_ok) {
  283. ah->curchan->paprd_done = true;
  284. ath_paprd_activate(sc);
  285. }
  286. ath9k_ps_restore(sc);
  287. }
  288. /*
  289. * This routine performs the periodic noise floor calibration function
  290. * that is used to adjust and optimize the chip performance. This
  291. * takes environmental changes (location, temperature) into account.
  292. * When the task is complete, it reschedules itself depending on the
  293. * appropriate interval that was calculated.
  294. */
  295. void ath_ani_calibrate(unsigned long data)
  296. {
  297. struct ath_softc *sc = (struct ath_softc *)data;
  298. struct ath_hw *ah = sc->sc_ah;
  299. struct ath_common *common = ath9k_hw_common(ah);
  300. bool longcal = false;
  301. bool shortcal = false;
  302. bool aniflag = false;
  303. unsigned int timestamp = jiffies_to_msecs(jiffies);
  304. u32 cal_interval, short_cal_interval;
  305. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  306. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  307. /* Only calibrate if awake */
  308. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  309. goto set_timer;
  310. ath9k_ps_wakeup(sc);
  311. /* Long calibration runs independently of short calibration. */
  312. if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
  313. longcal = true;
  314. ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  315. common->ani.longcal_timer = timestamp;
  316. }
  317. /* Short calibration applies only while caldone is false */
  318. if (!common->ani.caldone) {
  319. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  320. shortcal = true;
  321. ath_print(common, ATH_DBG_ANI,
  322. "shortcal @%lu\n", jiffies);
  323. common->ani.shortcal_timer = timestamp;
  324. common->ani.resetcal_timer = timestamp;
  325. }
  326. } else {
  327. if ((timestamp - common->ani.resetcal_timer) >=
  328. ATH_RESTART_CALINTERVAL) {
  329. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  330. if (common->ani.caldone)
  331. common->ani.resetcal_timer = timestamp;
  332. }
  333. }
  334. /* Verify whether we must check ANI */
  335. if ((timestamp - common->ani.checkani_timer) >=
  336. ah->config.ani_poll_interval) {
  337. aniflag = true;
  338. common->ani.checkani_timer = timestamp;
  339. }
  340. /* Skip all processing if there's nothing to do. */
  341. if (longcal || shortcal || aniflag) {
  342. /* Call ANI routine if necessary */
  343. if (aniflag)
  344. ath9k_hw_ani_monitor(ah, ah->curchan);
  345. /* Perform calibration if necessary */
  346. if (longcal || shortcal) {
  347. common->ani.caldone =
  348. ath9k_hw_calibrate(ah,
  349. ah->curchan,
  350. common->rx_chainmask,
  351. longcal);
  352. if (longcal)
  353. common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
  354. ah->curchan);
  355. ath_print(common, ATH_DBG_ANI,
  356. " calibrate chan %u/%x nf: %d\n",
  357. ah->curchan->channel,
  358. ah->curchan->channelFlags,
  359. common->ani.noise_floor);
  360. }
  361. }
  362. ath9k_ps_restore(sc);
  363. set_timer:
  364. /*
  365. * Set timer interval based on previous results.
  366. * The interval must be the shortest necessary to satisfy ANI,
  367. * short calibration and long calibration.
  368. */
  369. cal_interval = ATH_LONG_CALINTERVAL;
  370. if (sc->sc_ah->config.enable_ani)
  371. cal_interval = min(cal_interval,
  372. (u32)ah->config.ani_poll_interval);
  373. if (!common->ani.caldone)
  374. cal_interval = min(cal_interval, (u32)short_cal_interval);
  375. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  376. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) &&
  377. !(sc->sc_flags & SC_OP_SCANNING)) {
  378. if (!sc->sc_ah->curchan->paprd_done)
  379. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  380. else
  381. ath_paprd_activate(sc);
  382. }
  383. }
  384. static void ath_start_ani(struct ath_common *common)
  385. {
  386. struct ath_hw *ah = common->ah;
  387. unsigned long timestamp = jiffies_to_msecs(jiffies);
  388. common->ani.longcal_timer = timestamp;
  389. common->ani.shortcal_timer = timestamp;
  390. common->ani.checkani_timer = timestamp;
  391. mod_timer(&common->ani.timer,
  392. jiffies +
  393. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  394. }
  395. /*
  396. * Update tx/rx chainmask. For legacy association,
  397. * hard code chainmask to 1x1, for 11n association, use
  398. * the chainmask configuration, for bt coexistence, use
  399. * the chainmask configuration even in legacy mode.
  400. */
  401. void ath_update_chainmask(struct ath_softc *sc, int is_ht)
  402. {
  403. struct ath_hw *ah = sc->sc_ah;
  404. struct ath_common *common = ath9k_hw_common(ah);
  405. if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
  406. (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
  407. common->tx_chainmask = ah->caps.tx_chainmask;
  408. common->rx_chainmask = ah->caps.rx_chainmask;
  409. } else {
  410. common->tx_chainmask = 1;
  411. common->rx_chainmask = 1;
  412. }
  413. ath_print(common, ATH_DBG_CONFIG,
  414. "tx chmask: %d, rx chmask: %d\n",
  415. common->tx_chainmask,
  416. common->rx_chainmask);
  417. }
  418. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  419. {
  420. struct ath_node *an;
  421. an = (struct ath_node *)sta->drv_priv;
  422. if (sc->sc_flags & SC_OP_TXAGGR) {
  423. ath_tx_node_init(sc, an);
  424. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  425. sta->ht_cap.ampdu_factor);
  426. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  427. an->last_rssi = ATH_RSSI_DUMMY_MARKER;
  428. }
  429. }
  430. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  431. {
  432. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  433. if (sc->sc_flags & SC_OP_TXAGGR)
  434. ath_tx_node_cleanup(sc, an);
  435. }
  436. void ath9k_tasklet(unsigned long data)
  437. {
  438. struct ath_softc *sc = (struct ath_softc *)data;
  439. struct ath_hw *ah = sc->sc_ah;
  440. struct ath_common *common = ath9k_hw_common(ah);
  441. u32 status = sc->intrstatus;
  442. u32 rxmask;
  443. ath9k_ps_wakeup(sc);
  444. if ((status & ATH9K_INT_FATAL) ||
  445. !ath9k_hw_check_alive(ah)) {
  446. ath_reset(sc, false);
  447. ath9k_ps_restore(sc);
  448. return;
  449. }
  450. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  451. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  452. ATH9K_INT_RXORN);
  453. else
  454. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  455. if (status & rxmask) {
  456. spin_lock_bh(&sc->rx.rxflushlock);
  457. /* Check for high priority Rx first */
  458. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  459. (status & ATH9K_INT_RXHP))
  460. ath_rx_tasklet(sc, 0, true);
  461. ath_rx_tasklet(sc, 0, false);
  462. spin_unlock_bh(&sc->rx.rxflushlock);
  463. }
  464. if (status & ATH9K_INT_TX) {
  465. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  466. ath_tx_edma_tasklet(sc);
  467. else
  468. ath_tx_tasklet(sc);
  469. }
  470. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  471. /*
  472. * TSF sync does not look correct; remain awake to sync with
  473. * the next Beacon.
  474. */
  475. ath_print(common, ATH_DBG_PS,
  476. "TSFOOR - Sync with next Beacon\n");
  477. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  478. }
  479. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  480. if (status & ATH9K_INT_GENTIMER)
  481. ath_gen_timer_isr(sc->sc_ah);
  482. /* re-enable hardware interrupt */
  483. ath9k_hw_set_interrupts(ah, ah->imask);
  484. ath9k_ps_restore(sc);
  485. }
  486. irqreturn_t ath_isr(int irq, void *dev)
  487. {
  488. #define SCHED_INTR ( \
  489. ATH9K_INT_FATAL | \
  490. ATH9K_INT_RXORN | \
  491. ATH9K_INT_RXEOL | \
  492. ATH9K_INT_RX | \
  493. ATH9K_INT_RXLP | \
  494. ATH9K_INT_RXHP | \
  495. ATH9K_INT_TX | \
  496. ATH9K_INT_BMISS | \
  497. ATH9K_INT_CST | \
  498. ATH9K_INT_TSFOOR | \
  499. ATH9K_INT_GENTIMER)
  500. struct ath_softc *sc = dev;
  501. struct ath_hw *ah = sc->sc_ah;
  502. enum ath9k_int status;
  503. bool sched = false;
  504. /*
  505. * The hardware is not ready/present, don't
  506. * touch anything. Note this can happen early
  507. * on if the IRQ is shared.
  508. */
  509. if (sc->sc_flags & SC_OP_INVALID)
  510. return IRQ_NONE;
  511. /* shared irq, not for us */
  512. if (!ath9k_hw_intrpend(ah))
  513. return IRQ_NONE;
  514. /*
  515. * Figure out the reason(s) for the interrupt. Note
  516. * that the hal returns a pseudo-ISR that may include
  517. * bits we haven't explicitly enabled so we mask the
  518. * value to insure we only process bits we requested.
  519. */
  520. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  521. status &= ah->imask; /* discard unasked-for bits */
  522. /*
  523. * If there are no status bits set, then this interrupt was not
  524. * for me (should have been caught above).
  525. */
  526. if (!status)
  527. return IRQ_NONE;
  528. /* Cache the status */
  529. sc->intrstatus = status;
  530. if (status & SCHED_INTR)
  531. sched = true;
  532. /*
  533. * If a FATAL or RXORN interrupt is received, we have to reset the
  534. * chip immediately.
  535. */
  536. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  537. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  538. goto chip_reset;
  539. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  540. (status & ATH9K_INT_BB_WATCHDOG)) {
  541. ar9003_hw_bb_watchdog_dbg_info(ah);
  542. goto chip_reset;
  543. }
  544. if (status & ATH9K_INT_SWBA)
  545. tasklet_schedule(&sc->bcon_tasklet);
  546. if (status & ATH9K_INT_TXURN)
  547. ath9k_hw_updatetxtriglevel(ah, true);
  548. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  549. if (status & ATH9K_INT_RXEOL) {
  550. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  551. ath9k_hw_set_interrupts(ah, ah->imask);
  552. }
  553. }
  554. if (status & ATH9K_INT_MIB) {
  555. /*
  556. * Disable interrupts until we service the MIB
  557. * interrupt; otherwise it will continue to
  558. * fire.
  559. */
  560. ath9k_hw_set_interrupts(ah, 0);
  561. /*
  562. * Let the hal handle the event. We assume
  563. * it will clear whatever condition caused
  564. * the interrupt.
  565. */
  566. ath9k_hw_procmibevent(ah);
  567. ath9k_hw_set_interrupts(ah, ah->imask);
  568. }
  569. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  570. if (status & ATH9K_INT_TIM_TIMER) {
  571. /* Clear RxAbort bit so that we can
  572. * receive frames */
  573. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  574. ath9k_hw_setrxabort(sc->sc_ah, 0);
  575. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  576. }
  577. chip_reset:
  578. ath_debug_stat_interrupt(sc, status);
  579. if (sched) {
  580. /* turn off every interrupt except SWBA */
  581. ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
  582. tasklet_schedule(&sc->intr_tq);
  583. }
  584. return IRQ_HANDLED;
  585. #undef SCHED_INTR
  586. }
  587. static u32 ath_get_extchanmode(struct ath_softc *sc,
  588. struct ieee80211_channel *chan,
  589. enum nl80211_channel_type channel_type)
  590. {
  591. u32 chanmode = 0;
  592. switch (chan->band) {
  593. case IEEE80211_BAND_2GHZ:
  594. switch(channel_type) {
  595. case NL80211_CHAN_NO_HT:
  596. case NL80211_CHAN_HT20:
  597. chanmode = CHANNEL_G_HT20;
  598. break;
  599. case NL80211_CHAN_HT40PLUS:
  600. chanmode = CHANNEL_G_HT40PLUS;
  601. break;
  602. case NL80211_CHAN_HT40MINUS:
  603. chanmode = CHANNEL_G_HT40MINUS;
  604. break;
  605. }
  606. break;
  607. case IEEE80211_BAND_5GHZ:
  608. switch(channel_type) {
  609. case NL80211_CHAN_NO_HT:
  610. case NL80211_CHAN_HT20:
  611. chanmode = CHANNEL_A_HT20;
  612. break;
  613. case NL80211_CHAN_HT40PLUS:
  614. chanmode = CHANNEL_A_HT40PLUS;
  615. break;
  616. case NL80211_CHAN_HT40MINUS:
  617. chanmode = CHANNEL_A_HT40MINUS;
  618. break;
  619. }
  620. break;
  621. default:
  622. break;
  623. }
  624. return chanmode;
  625. }
  626. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  627. struct ieee80211_vif *vif,
  628. struct ieee80211_bss_conf *bss_conf)
  629. {
  630. struct ath_hw *ah = sc->sc_ah;
  631. struct ath_common *common = ath9k_hw_common(ah);
  632. if (bss_conf->assoc) {
  633. ath_print(common, ATH_DBG_CONFIG,
  634. "Bss Info ASSOC %d, bssid: %pM\n",
  635. bss_conf->aid, common->curbssid);
  636. /* New association, store aid */
  637. common->curaid = bss_conf->aid;
  638. ath9k_hw_write_associd(ah);
  639. /*
  640. * Request a re-configuration of Beacon related timers
  641. * on the receipt of the first Beacon frame (i.e.,
  642. * after time sync with the AP).
  643. */
  644. sc->ps_flags |= PS_BEACON_SYNC;
  645. /* Configure the beacon */
  646. ath_beacon_config(sc, vif);
  647. /* Reset rssi stats */
  648. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  649. ath_start_ani(common);
  650. } else {
  651. ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  652. common->curaid = 0;
  653. /* Stop ANI */
  654. del_timer_sync(&common->ani.timer);
  655. }
  656. }
  657. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  658. {
  659. struct ath_hw *ah = sc->sc_ah;
  660. struct ath_common *common = ath9k_hw_common(ah);
  661. struct ieee80211_channel *channel = hw->conf.channel;
  662. int r;
  663. ath9k_ps_wakeup(sc);
  664. ath9k_hw_configpcipowersave(ah, 0, 0);
  665. if (!ah->curchan)
  666. ah->curchan = ath_get_curchannel(sc, sc->hw);
  667. spin_lock_bh(&sc->sc_resetlock);
  668. r = ath9k_hw_reset(ah, ah->curchan, false);
  669. if (r) {
  670. ath_print(common, ATH_DBG_FATAL,
  671. "Unable to reset channel (%u MHz), "
  672. "reset status %d\n",
  673. channel->center_freq, r);
  674. }
  675. spin_unlock_bh(&sc->sc_resetlock);
  676. ath_update_txpow(sc);
  677. if (ath_startrecv(sc) != 0) {
  678. ath_print(common, ATH_DBG_FATAL,
  679. "Unable to restart recv logic\n");
  680. return;
  681. }
  682. if (sc->sc_flags & SC_OP_BEACONS)
  683. ath_beacon_config(sc, NULL); /* restart beacons */
  684. /* Re-Enable interrupts */
  685. ath9k_hw_set_interrupts(ah, ah->imask);
  686. /* Enable LED */
  687. ath9k_hw_cfg_output(ah, ah->led_pin,
  688. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  689. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  690. ieee80211_wake_queues(hw);
  691. ath9k_ps_restore(sc);
  692. }
  693. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  694. {
  695. struct ath_hw *ah = sc->sc_ah;
  696. struct ieee80211_channel *channel = hw->conf.channel;
  697. int r;
  698. ath9k_ps_wakeup(sc);
  699. ieee80211_stop_queues(hw);
  700. /* Disable LED */
  701. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  702. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  703. /* Disable interrupts */
  704. ath9k_hw_set_interrupts(ah, 0);
  705. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  706. ath_stoprecv(sc); /* turn off frame recv */
  707. ath_flushrecv(sc); /* flush recv queue */
  708. if (!ah->curchan)
  709. ah->curchan = ath_get_curchannel(sc, hw);
  710. spin_lock_bh(&sc->sc_resetlock);
  711. r = ath9k_hw_reset(ah, ah->curchan, false);
  712. if (r) {
  713. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  714. "Unable to reset channel (%u MHz), "
  715. "reset status %d\n",
  716. channel->center_freq, r);
  717. }
  718. spin_unlock_bh(&sc->sc_resetlock);
  719. ath9k_hw_phy_disable(ah);
  720. ath9k_hw_configpcipowersave(ah, 1, 1);
  721. ath9k_ps_restore(sc);
  722. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  723. }
  724. int ath_reset(struct ath_softc *sc, bool retry_tx)
  725. {
  726. struct ath_hw *ah = sc->sc_ah;
  727. struct ath_common *common = ath9k_hw_common(ah);
  728. struct ieee80211_hw *hw = sc->hw;
  729. int r;
  730. /* Stop ANI */
  731. del_timer_sync(&common->ani.timer);
  732. ieee80211_stop_queues(hw);
  733. ath9k_hw_set_interrupts(ah, 0);
  734. ath_drain_all_txq(sc, retry_tx);
  735. ath_stoprecv(sc);
  736. ath_flushrecv(sc);
  737. spin_lock_bh(&sc->sc_resetlock);
  738. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
  739. if (r)
  740. ath_print(common, ATH_DBG_FATAL,
  741. "Unable to reset hardware; reset status %d\n", r);
  742. spin_unlock_bh(&sc->sc_resetlock);
  743. if (ath_startrecv(sc) != 0)
  744. ath_print(common, ATH_DBG_FATAL,
  745. "Unable to start recv logic\n");
  746. /*
  747. * We may be doing a reset in response to a request
  748. * that changes the channel so update any state that
  749. * might change as a result.
  750. */
  751. ath_cache_conf_rate(sc, &hw->conf);
  752. ath_update_txpow(sc);
  753. if (sc->sc_flags & SC_OP_BEACONS)
  754. ath_beacon_config(sc, NULL); /* restart beacons */
  755. ath9k_hw_set_interrupts(ah, ah->imask);
  756. if (retry_tx) {
  757. int i;
  758. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  759. if (ATH_TXQ_SETUP(sc, i)) {
  760. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  761. ath_txq_schedule(sc, &sc->tx.txq[i]);
  762. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  763. }
  764. }
  765. }
  766. ieee80211_wake_queues(hw);
  767. /* Start ANI */
  768. ath_start_ani(common);
  769. return r;
  770. }
  771. static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
  772. {
  773. int qnum;
  774. switch (queue) {
  775. case 0:
  776. qnum = sc->tx.hwq_map[WME_AC_VO];
  777. break;
  778. case 1:
  779. qnum = sc->tx.hwq_map[WME_AC_VI];
  780. break;
  781. case 2:
  782. qnum = sc->tx.hwq_map[WME_AC_BE];
  783. break;
  784. case 3:
  785. qnum = sc->tx.hwq_map[WME_AC_BK];
  786. break;
  787. default:
  788. qnum = sc->tx.hwq_map[WME_AC_BE];
  789. break;
  790. }
  791. return qnum;
  792. }
  793. int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
  794. {
  795. int qnum;
  796. switch (queue) {
  797. case WME_AC_VO:
  798. qnum = 0;
  799. break;
  800. case WME_AC_VI:
  801. qnum = 1;
  802. break;
  803. case WME_AC_BE:
  804. qnum = 2;
  805. break;
  806. case WME_AC_BK:
  807. qnum = 3;
  808. break;
  809. default:
  810. qnum = -1;
  811. break;
  812. }
  813. return qnum;
  814. }
  815. /* XXX: Remove me once we don't depend on ath9k_channel for all
  816. * this redundant data */
  817. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  818. struct ath9k_channel *ichan)
  819. {
  820. struct ieee80211_channel *chan = hw->conf.channel;
  821. struct ieee80211_conf *conf = &hw->conf;
  822. ichan->channel = chan->center_freq;
  823. ichan->chan = chan;
  824. if (chan->band == IEEE80211_BAND_2GHZ) {
  825. ichan->chanmode = CHANNEL_G;
  826. ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
  827. } else {
  828. ichan->chanmode = CHANNEL_A;
  829. ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
  830. }
  831. if (conf_is_ht(conf))
  832. ichan->chanmode = ath_get_extchanmode(sc, chan,
  833. conf->channel_type);
  834. }
  835. /**********************/
  836. /* mac80211 callbacks */
  837. /**********************/
  838. static int ath9k_start(struct ieee80211_hw *hw)
  839. {
  840. struct ath_wiphy *aphy = hw->priv;
  841. struct ath_softc *sc = aphy->sc;
  842. struct ath_hw *ah = sc->sc_ah;
  843. struct ath_common *common = ath9k_hw_common(ah);
  844. struct ieee80211_channel *curchan = hw->conf.channel;
  845. struct ath9k_channel *init_channel;
  846. int r;
  847. ath_print(common, ATH_DBG_CONFIG,
  848. "Starting driver with initial channel: %d MHz\n",
  849. curchan->center_freq);
  850. mutex_lock(&sc->mutex);
  851. if (ath9k_wiphy_started(sc)) {
  852. if (sc->chan_idx == curchan->hw_value) {
  853. /*
  854. * Already on the operational channel, the new wiphy
  855. * can be marked active.
  856. */
  857. aphy->state = ATH_WIPHY_ACTIVE;
  858. ieee80211_wake_queues(hw);
  859. } else {
  860. /*
  861. * Another wiphy is on another channel, start the new
  862. * wiphy in paused state.
  863. */
  864. aphy->state = ATH_WIPHY_PAUSED;
  865. ieee80211_stop_queues(hw);
  866. }
  867. mutex_unlock(&sc->mutex);
  868. return 0;
  869. }
  870. aphy->state = ATH_WIPHY_ACTIVE;
  871. /* setup initial channel */
  872. sc->chan_idx = curchan->hw_value;
  873. init_channel = ath_get_curchannel(sc, hw);
  874. /* Reset SERDES registers */
  875. ath9k_hw_configpcipowersave(ah, 0, 0);
  876. /*
  877. * The basic interface to setting the hardware in a good
  878. * state is ``reset''. On return the hardware is known to
  879. * be powered up and with interrupts disabled. This must
  880. * be followed by initialization of the appropriate bits
  881. * and then setup of the interrupt mask.
  882. */
  883. spin_lock_bh(&sc->sc_resetlock);
  884. r = ath9k_hw_reset(ah, init_channel, false);
  885. if (r) {
  886. ath_print(common, ATH_DBG_FATAL,
  887. "Unable to reset hardware; reset status %d "
  888. "(freq %u MHz)\n", r,
  889. curchan->center_freq);
  890. spin_unlock_bh(&sc->sc_resetlock);
  891. goto mutex_unlock;
  892. }
  893. spin_unlock_bh(&sc->sc_resetlock);
  894. /*
  895. * This is needed only to setup initial state
  896. * but it's best done after a reset.
  897. */
  898. ath_update_txpow(sc);
  899. /*
  900. * Setup the hardware after reset:
  901. * The receive engine is set going.
  902. * Frame transmit is handled entirely
  903. * in the frame output path; there's nothing to do
  904. * here except setup the interrupt mask.
  905. */
  906. if (ath_startrecv(sc) != 0) {
  907. ath_print(common, ATH_DBG_FATAL,
  908. "Unable to start recv logic\n");
  909. r = -EIO;
  910. goto mutex_unlock;
  911. }
  912. /* Setup our intr mask. */
  913. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  914. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  915. ATH9K_INT_GLOBAL;
  916. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  917. ah->imask |= ATH9K_INT_RXHP |
  918. ATH9K_INT_RXLP |
  919. ATH9K_INT_BB_WATCHDOG;
  920. else
  921. ah->imask |= ATH9K_INT_RX;
  922. if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
  923. ah->imask |= ATH9K_INT_GTT;
  924. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  925. ah->imask |= ATH9K_INT_CST;
  926. ath_cache_conf_rate(sc, &hw->conf);
  927. sc->sc_flags &= ~SC_OP_INVALID;
  928. /* Disable BMISS interrupt when we're not associated */
  929. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  930. ath9k_hw_set_interrupts(ah, ah->imask);
  931. ieee80211_wake_queues(hw);
  932. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  933. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  934. !ah->btcoex_hw.enabled) {
  935. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  936. AR_STOMP_LOW_WLAN_WGHT);
  937. ath9k_hw_btcoex_enable(ah);
  938. if (common->bus_ops->bt_coex_prep)
  939. common->bus_ops->bt_coex_prep(common);
  940. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  941. ath9k_btcoex_timer_resume(sc);
  942. }
  943. mutex_unlock:
  944. mutex_unlock(&sc->mutex);
  945. return r;
  946. }
  947. static int ath9k_tx(struct ieee80211_hw *hw,
  948. struct sk_buff *skb)
  949. {
  950. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  951. struct ath_wiphy *aphy = hw->priv;
  952. struct ath_softc *sc = aphy->sc;
  953. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  954. struct ath_tx_control txctl;
  955. int padpos, padsize;
  956. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  957. int qnum;
  958. if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
  959. ath_print(common, ATH_DBG_XMIT,
  960. "ath9k: %s: TX in unexpected wiphy state "
  961. "%d\n", wiphy_name(hw->wiphy), aphy->state);
  962. goto exit;
  963. }
  964. if (sc->ps_enabled) {
  965. /*
  966. * mac80211 does not set PM field for normal data frames, so we
  967. * need to update that based on the current PS mode.
  968. */
  969. if (ieee80211_is_data(hdr->frame_control) &&
  970. !ieee80211_is_nullfunc(hdr->frame_control) &&
  971. !ieee80211_has_pm(hdr->frame_control)) {
  972. ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
  973. "while in PS mode\n");
  974. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  975. }
  976. }
  977. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  978. /*
  979. * We are using PS-Poll and mac80211 can request TX while in
  980. * power save mode. Need to wake up hardware for the TX to be
  981. * completed and if needed, also for RX of buffered frames.
  982. */
  983. ath9k_ps_wakeup(sc);
  984. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  985. ath9k_hw_setrxabort(sc->sc_ah, 0);
  986. if (ieee80211_is_pspoll(hdr->frame_control)) {
  987. ath_print(common, ATH_DBG_PS,
  988. "Sending PS-Poll to pick a buffered frame\n");
  989. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  990. } else {
  991. ath_print(common, ATH_DBG_PS,
  992. "Wake up to complete TX\n");
  993. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  994. }
  995. /*
  996. * The actual restore operation will happen only after
  997. * the sc_flags bit is cleared. We are just dropping
  998. * the ps_usecount here.
  999. */
  1000. ath9k_ps_restore(sc);
  1001. }
  1002. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1003. /*
  1004. * As a temporary workaround, assign seq# here; this will likely need
  1005. * to be cleaned up to work better with Beacon transmission and virtual
  1006. * BSSes.
  1007. */
  1008. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1009. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1010. sc->tx.seq_no += 0x10;
  1011. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1012. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1013. }
  1014. /* Add the padding after the header if this is not already done */
  1015. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1016. padsize = padpos & 3;
  1017. if (padsize && skb->len>padpos) {
  1018. if (skb_headroom(skb) < padsize)
  1019. return -1;
  1020. skb_push(skb, padsize);
  1021. memmove(skb->data, skb->data + padsize, padpos);
  1022. }
  1023. qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
  1024. txctl.txq = &sc->tx.txq[qnum];
  1025. ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  1026. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1027. ath_print(common, ATH_DBG_XMIT, "TX failed\n");
  1028. goto exit;
  1029. }
  1030. return 0;
  1031. exit:
  1032. dev_kfree_skb_any(skb);
  1033. return 0;
  1034. }
  1035. static void ath9k_stop(struct ieee80211_hw *hw)
  1036. {
  1037. struct ath_wiphy *aphy = hw->priv;
  1038. struct ath_softc *sc = aphy->sc;
  1039. struct ath_hw *ah = sc->sc_ah;
  1040. struct ath_common *common = ath9k_hw_common(ah);
  1041. mutex_lock(&sc->mutex);
  1042. aphy->state = ATH_WIPHY_INACTIVE;
  1043. if (led_blink)
  1044. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  1045. cancel_delayed_work_sync(&sc->tx_complete_work);
  1046. cancel_work_sync(&sc->paprd_work);
  1047. if (!sc->num_sec_wiphy) {
  1048. cancel_delayed_work_sync(&sc->wiphy_work);
  1049. cancel_work_sync(&sc->chan_work);
  1050. }
  1051. if (sc->sc_flags & SC_OP_INVALID) {
  1052. ath_print(common, ATH_DBG_ANY, "Device not present\n");
  1053. mutex_unlock(&sc->mutex);
  1054. return;
  1055. }
  1056. if (ath9k_wiphy_started(sc)) {
  1057. mutex_unlock(&sc->mutex);
  1058. return; /* another wiphy still in use */
  1059. }
  1060. /* Ensure HW is awake when we try to shut it down. */
  1061. ath9k_ps_wakeup(sc);
  1062. if (ah->btcoex_hw.enabled) {
  1063. ath9k_hw_btcoex_disable(ah);
  1064. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1065. ath9k_btcoex_timer_pause(sc);
  1066. }
  1067. /* make sure h/w will not generate any interrupt
  1068. * before setting the invalid flag. */
  1069. ath9k_hw_set_interrupts(ah, 0);
  1070. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1071. ath_drain_all_txq(sc, false);
  1072. ath_stoprecv(sc);
  1073. ath9k_hw_phy_disable(ah);
  1074. } else
  1075. sc->rx.rxlink = NULL;
  1076. /* disable HAL and put h/w to sleep */
  1077. ath9k_hw_disable(ah);
  1078. ath9k_hw_configpcipowersave(ah, 1, 1);
  1079. ath9k_ps_restore(sc);
  1080. /* Finally, put the chip in FULL SLEEP mode */
  1081. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  1082. sc->sc_flags |= SC_OP_INVALID;
  1083. mutex_unlock(&sc->mutex);
  1084. ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
  1085. }
  1086. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1087. struct ieee80211_vif *vif)
  1088. {
  1089. struct ath_wiphy *aphy = hw->priv;
  1090. struct ath_softc *sc = aphy->sc;
  1091. struct ath_hw *ah = sc->sc_ah;
  1092. struct ath_common *common = ath9k_hw_common(ah);
  1093. struct ath_vif *avp = (void *)vif->drv_priv;
  1094. enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
  1095. int ret = 0;
  1096. mutex_lock(&sc->mutex);
  1097. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
  1098. sc->nvifs > 0) {
  1099. ret = -ENOBUFS;
  1100. goto out;
  1101. }
  1102. switch (vif->type) {
  1103. case NL80211_IFTYPE_STATION:
  1104. ic_opmode = NL80211_IFTYPE_STATION;
  1105. break;
  1106. case NL80211_IFTYPE_ADHOC:
  1107. case NL80211_IFTYPE_AP:
  1108. case NL80211_IFTYPE_MESH_POINT:
  1109. if (sc->nbcnvifs >= ATH_BCBUF) {
  1110. ret = -ENOBUFS;
  1111. goto out;
  1112. }
  1113. ic_opmode = vif->type;
  1114. break;
  1115. default:
  1116. ath_print(common, ATH_DBG_FATAL,
  1117. "Interface type %d not yet supported\n", vif->type);
  1118. ret = -EOPNOTSUPP;
  1119. goto out;
  1120. }
  1121. ath_print(common, ATH_DBG_CONFIG,
  1122. "Attach a VIF of type: %d\n", ic_opmode);
  1123. /* Set the VIF opmode */
  1124. avp->av_opmode = ic_opmode;
  1125. avp->av_bslot = -1;
  1126. sc->nvifs++;
  1127. if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  1128. ath9k_set_bssid_mask(hw);
  1129. if (sc->nvifs > 1)
  1130. goto out; /* skip global settings for secondary vif */
  1131. if (ic_opmode == NL80211_IFTYPE_AP) {
  1132. ath9k_hw_set_tsfadjust(ah, 1);
  1133. sc->sc_flags |= SC_OP_TSF_RESET;
  1134. }
  1135. /* Set the device opmode */
  1136. ah->opmode = ic_opmode;
  1137. /*
  1138. * Enable MIB interrupts when there are hardware phy counters.
  1139. * Note we only do this (at the moment) for station mode.
  1140. */
  1141. if ((vif->type == NL80211_IFTYPE_STATION) ||
  1142. (vif->type == NL80211_IFTYPE_ADHOC) ||
  1143. (vif->type == NL80211_IFTYPE_MESH_POINT)) {
  1144. if (ah->config.enable_ani)
  1145. ah->imask |= ATH9K_INT_MIB;
  1146. ah->imask |= ATH9K_INT_TSFOOR;
  1147. }
  1148. ath9k_hw_set_interrupts(ah, ah->imask);
  1149. if (vif->type == NL80211_IFTYPE_AP ||
  1150. vif->type == NL80211_IFTYPE_ADHOC ||
  1151. vif->type == NL80211_IFTYPE_MONITOR)
  1152. ath_start_ani(common);
  1153. out:
  1154. mutex_unlock(&sc->mutex);
  1155. return ret;
  1156. }
  1157. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1158. struct ieee80211_vif *vif)
  1159. {
  1160. struct ath_wiphy *aphy = hw->priv;
  1161. struct ath_softc *sc = aphy->sc;
  1162. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1163. struct ath_vif *avp = (void *)vif->drv_priv;
  1164. int i;
  1165. ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1166. mutex_lock(&sc->mutex);
  1167. /* Stop ANI */
  1168. del_timer_sync(&common->ani.timer);
  1169. /* Reclaim beacon resources */
  1170. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  1171. (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1172. (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
  1173. ath9k_ps_wakeup(sc);
  1174. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1175. ath9k_ps_restore(sc);
  1176. }
  1177. ath_beacon_return(sc, avp);
  1178. sc->sc_flags &= ~SC_OP_BEACONS;
  1179. for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
  1180. if (sc->beacon.bslot[i] == vif) {
  1181. printk(KERN_DEBUG "%s: vif had allocated beacon "
  1182. "slot\n", __func__);
  1183. sc->beacon.bslot[i] = NULL;
  1184. sc->beacon.bslot_aphy[i] = NULL;
  1185. }
  1186. }
  1187. sc->nvifs--;
  1188. mutex_unlock(&sc->mutex);
  1189. }
  1190. void ath9k_enable_ps(struct ath_softc *sc)
  1191. {
  1192. struct ath_hw *ah = sc->sc_ah;
  1193. sc->ps_enabled = true;
  1194. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1195. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1196. ah->imask |= ATH9K_INT_TIM_TIMER;
  1197. ath9k_hw_set_interrupts(ah, ah->imask);
  1198. }
  1199. ath9k_hw_setrxabort(ah, 1);
  1200. }
  1201. }
  1202. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1203. {
  1204. struct ath_wiphy *aphy = hw->priv;
  1205. struct ath_softc *sc = aphy->sc;
  1206. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1207. struct ieee80211_conf *conf = &hw->conf;
  1208. struct ath_hw *ah = sc->sc_ah;
  1209. bool disable_radio;
  1210. mutex_lock(&sc->mutex);
  1211. /*
  1212. * Leave this as the first check because we need to turn on the
  1213. * radio if it was disabled before prior to processing the rest
  1214. * of the changes. Likewise we must only disable the radio towards
  1215. * the end.
  1216. */
  1217. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1218. bool enable_radio;
  1219. bool all_wiphys_idle;
  1220. bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1221. spin_lock_bh(&sc->wiphy_lock);
  1222. all_wiphys_idle = ath9k_all_wiphys_idle(sc);
  1223. ath9k_set_wiphy_idle(aphy, idle);
  1224. enable_radio = (!idle && all_wiphys_idle);
  1225. /*
  1226. * After we unlock here its possible another wiphy
  1227. * can be re-renabled so to account for that we will
  1228. * only disable the radio toward the end of this routine
  1229. * if by then all wiphys are still idle.
  1230. */
  1231. spin_unlock_bh(&sc->wiphy_lock);
  1232. if (enable_radio) {
  1233. sc->ps_idle = false;
  1234. ath_radio_enable(sc, hw);
  1235. ath_print(common, ATH_DBG_CONFIG,
  1236. "not-idle: enabling radio\n");
  1237. }
  1238. }
  1239. /*
  1240. * We just prepare to enable PS. We have to wait until our AP has
  1241. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1242. * those ACKs and end up retransmitting the same null data frames.
  1243. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1244. */
  1245. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1246. if (conf->flags & IEEE80211_CONF_PS) {
  1247. sc->ps_flags |= PS_ENABLED;
  1248. /*
  1249. * At this point we know hardware has received an ACK
  1250. * of a previously sent null data frame.
  1251. */
  1252. if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
  1253. sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
  1254. ath9k_enable_ps(sc);
  1255. }
  1256. } else {
  1257. sc->ps_enabled = false;
  1258. sc->ps_flags &= ~(PS_ENABLED |
  1259. PS_NULLFUNC_COMPLETED);
  1260. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  1261. if (!(ah->caps.hw_caps &
  1262. ATH9K_HW_CAP_AUTOSLEEP)) {
  1263. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1264. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1265. PS_WAIT_FOR_CAB |
  1266. PS_WAIT_FOR_PSPOLL_DATA |
  1267. PS_WAIT_FOR_TX_ACK);
  1268. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1269. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1270. ath9k_hw_set_interrupts(sc->sc_ah,
  1271. ah->imask);
  1272. }
  1273. }
  1274. }
  1275. }
  1276. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1277. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1278. ath_print(common, ATH_DBG_CONFIG,
  1279. "HW opmode set to Monitor mode\n");
  1280. sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
  1281. }
  1282. }
  1283. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1284. struct ieee80211_channel *curchan = hw->conf.channel;
  1285. int pos = curchan->hw_value;
  1286. aphy->chan_idx = pos;
  1287. aphy->chan_is_ht = conf_is_ht(conf);
  1288. if (aphy->state == ATH_WIPHY_SCAN ||
  1289. aphy->state == ATH_WIPHY_ACTIVE)
  1290. ath9k_wiphy_pause_all_forced(sc, aphy);
  1291. else {
  1292. /*
  1293. * Do not change operational channel based on a paused
  1294. * wiphy changes.
  1295. */
  1296. goto skip_chan_change;
  1297. }
  1298. ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1299. curchan->center_freq);
  1300. /* XXX: remove me eventualy */
  1301. ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
  1302. ath_update_chainmask(sc, conf_is_ht(conf));
  1303. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1304. ath_print(common, ATH_DBG_FATAL,
  1305. "Unable to set channel\n");
  1306. mutex_unlock(&sc->mutex);
  1307. return -EINVAL;
  1308. }
  1309. }
  1310. skip_chan_change:
  1311. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1312. sc->config.txpowlimit = 2 * conf->power_level;
  1313. ath_update_txpow(sc);
  1314. }
  1315. spin_lock_bh(&sc->wiphy_lock);
  1316. disable_radio = ath9k_all_wiphys_idle(sc);
  1317. spin_unlock_bh(&sc->wiphy_lock);
  1318. if (disable_radio) {
  1319. ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1320. sc->ps_idle = true;
  1321. ath_radio_disable(sc, hw);
  1322. }
  1323. mutex_unlock(&sc->mutex);
  1324. return 0;
  1325. }
  1326. #define SUPPORTED_FILTERS \
  1327. (FIF_PROMISC_IN_BSS | \
  1328. FIF_ALLMULTI | \
  1329. FIF_CONTROL | \
  1330. FIF_PSPOLL | \
  1331. FIF_OTHER_BSS | \
  1332. FIF_BCN_PRBRESP_PROMISC | \
  1333. FIF_FCSFAIL)
  1334. /* FIXME: sc->sc_full_reset ? */
  1335. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1336. unsigned int changed_flags,
  1337. unsigned int *total_flags,
  1338. u64 multicast)
  1339. {
  1340. struct ath_wiphy *aphy = hw->priv;
  1341. struct ath_softc *sc = aphy->sc;
  1342. u32 rfilt;
  1343. changed_flags &= SUPPORTED_FILTERS;
  1344. *total_flags &= SUPPORTED_FILTERS;
  1345. sc->rx.rxfilter = *total_flags;
  1346. ath9k_ps_wakeup(sc);
  1347. rfilt = ath_calcrxfilter(sc);
  1348. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1349. ath9k_ps_restore(sc);
  1350. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1351. "Set HW RX filter: 0x%x\n", rfilt);
  1352. }
  1353. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1354. struct ieee80211_vif *vif,
  1355. struct ieee80211_sta *sta)
  1356. {
  1357. struct ath_wiphy *aphy = hw->priv;
  1358. struct ath_softc *sc = aphy->sc;
  1359. ath_node_attach(sc, sta);
  1360. return 0;
  1361. }
  1362. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1363. struct ieee80211_vif *vif,
  1364. struct ieee80211_sta *sta)
  1365. {
  1366. struct ath_wiphy *aphy = hw->priv;
  1367. struct ath_softc *sc = aphy->sc;
  1368. ath_node_detach(sc, sta);
  1369. return 0;
  1370. }
  1371. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1372. const struct ieee80211_tx_queue_params *params)
  1373. {
  1374. struct ath_wiphy *aphy = hw->priv;
  1375. struct ath_softc *sc = aphy->sc;
  1376. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1377. struct ath9k_tx_queue_info qi;
  1378. int ret = 0, qnum;
  1379. if (queue >= WME_NUM_AC)
  1380. return 0;
  1381. mutex_lock(&sc->mutex);
  1382. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1383. qi.tqi_aifs = params->aifs;
  1384. qi.tqi_cwmin = params->cw_min;
  1385. qi.tqi_cwmax = params->cw_max;
  1386. qi.tqi_burstTime = params->txop;
  1387. qnum = ath_get_hal_qnum(queue, sc);
  1388. ath_print(common, ATH_DBG_CONFIG,
  1389. "Configure tx [queue/halq] [%d/%d], "
  1390. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1391. queue, qnum, params->aifs, params->cw_min,
  1392. params->cw_max, params->txop);
  1393. ret = ath_txq_update(sc, qnum, &qi);
  1394. if (ret)
  1395. ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
  1396. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1397. if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
  1398. ath_beaconq_config(sc);
  1399. mutex_unlock(&sc->mutex);
  1400. return ret;
  1401. }
  1402. static int ath9k_set_key(struct ieee80211_hw *hw,
  1403. enum set_key_cmd cmd,
  1404. struct ieee80211_vif *vif,
  1405. struct ieee80211_sta *sta,
  1406. struct ieee80211_key_conf *key)
  1407. {
  1408. struct ath_wiphy *aphy = hw->priv;
  1409. struct ath_softc *sc = aphy->sc;
  1410. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1411. int ret = 0;
  1412. if (modparam_nohwcrypt)
  1413. return -ENOSPC;
  1414. mutex_lock(&sc->mutex);
  1415. ath9k_ps_wakeup(sc);
  1416. ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1417. switch (cmd) {
  1418. case SET_KEY:
  1419. ret = ath9k_cmn_key_config(common, vif, sta, key);
  1420. if (ret >= 0) {
  1421. key->hw_key_idx = ret;
  1422. /* push IV and Michael MIC generation to stack */
  1423. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1424. if (key->alg == ALG_TKIP)
  1425. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1426. if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
  1427. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1428. ret = 0;
  1429. }
  1430. break;
  1431. case DISABLE_KEY:
  1432. ath9k_cmn_key_delete(common, key);
  1433. break;
  1434. default:
  1435. ret = -EINVAL;
  1436. }
  1437. ath9k_ps_restore(sc);
  1438. mutex_unlock(&sc->mutex);
  1439. return ret;
  1440. }
  1441. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1442. struct ieee80211_vif *vif,
  1443. struct ieee80211_bss_conf *bss_conf,
  1444. u32 changed)
  1445. {
  1446. struct ath_wiphy *aphy = hw->priv;
  1447. struct ath_softc *sc = aphy->sc;
  1448. struct ath_hw *ah = sc->sc_ah;
  1449. struct ath_common *common = ath9k_hw_common(ah);
  1450. struct ath_vif *avp = (void *)vif->drv_priv;
  1451. int slottime;
  1452. int error;
  1453. mutex_lock(&sc->mutex);
  1454. if (changed & BSS_CHANGED_BSSID) {
  1455. /* Set BSSID */
  1456. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1457. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1458. common->curaid = 0;
  1459. ath9k_hw_write_associd(ah);
  1460. /* Set aggregation protection mode parameters */
  1461. sc->config.ath_aggr_prot = 0;
  1462. /* Only legacy IBSS for now */
  1463. if (vif->type == NL80211_IFTYPE_ADHOC)
  1464. ath_update_chainmask(sc, 0);
  1465. ath_print(common, ATH_DBG_CONFIG,
  1466. "BSSID: %pM aid: 0x%x\n",
  1467. common->curbssid, common->curaid);
  1468. /* need to reconfigure the beacon */
  1469. sc->sc_flags &= ~SC_OP_BEACONS ;
  1470. }
  1471. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1472. if ((changed & BSS_CHANGED_BEACON) ||
  1473. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1474. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1475. error = ath_beacon_alloc(aphy, vif);
  1476. if (!error)
  1477. ath_beacon_config(sc, vif);
  1478. }
  1479. if (changed & BSS_CHANGED_ERP_SLOT) {
  1480. if (bss_conf->use_short_slot)
  1481. slottime = 9;
  1482. else
  1483. slottime = 20;
  1484. if (vif->type == NL80211_IFTYPE_AP) {
  1485. /*
  1486. * Defer update, so that connected stations can adjust
  1487. * their settings at the same time.
  1488. * See beacon.c for more details
  1489. */
  1490. sc->beacon.slottime = slottime;
  1491. sc->beacon.updateslot = UPDATE;
  1492. } else {
  1493. ah->slottime = slottime;
  1494. ath9k_hw_init_global_settings(ah);
  1495. }
  1496. }
  1497. /* Disable transmission of beacons */
  1498. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1499. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1500. if (changed & BSS_CHANGED_BEACON_INT) {
  1501. sc->beacon_interval = bss_conf->beacon_int;
  1502. /*
  1503. * In case of AP mode, the HW TSF has to be reset
  1504. * when the beacon interval changes.
  1505. */
  1506. if (vif->type == NL80211_IFTYPE_AP) {
  1507. sc->sc_flags |= SC_OP_TSF_RESET;
  1508. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1509. error = ath_beacon_alloc(aphy, vif);
  1510. if (!error)
  1511. ath_beacon_config(sc, vif);
  1512. } else {
  1513. ath_beacon_config(sc, vif);
  1514. }
  1515. }
  1516. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1517. ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1518. bss_conf->use_short_preamble);
  1519. if (bss_conf->use_short_preamble)
  1520. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1521. else
  1522. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1523. }
  1524. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1525. ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1526. bss_conf->use_cts_prot);
  1527. if (bss_conf->use_cts_prot &&
  1528. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1529. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1530. else
  1531. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1532. }
  1533. if (changed & BSS_CHANGED_ASSOC) {
  1534. ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1535. bss_conf->assoc);
  1536. ath9k_bss_assoc_info(sc, vif, bss_conf);
  1537. }
  1538. mutex_unlock(&sc->mutex);
  1539. }
  1540. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1541. {
  1542. u64 tsf;
  1543. struct ath_wiphy *aphy = hw->priv;
  1544. struct ath_softc *sc = aphy->sc;
  1545. mutex_lock(&sc->mutex);
  1546. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1547. mutex_unlock(&sc->mutex);
  1548. return tsf;
  1549. }
  1550. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1551. {
  1552. struct ath_wiphy *aphy = hw->priv;
  1553. struct ath_softc *sc = aphy->sc;
  1554. mutex_lock(&sc->mutex);
  1555. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1556. mutex_unlock(&sc->mutex);
  1557. }
  1558. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1559. {
  1560. struct ath_wiphy *aphy = hw->priv;
  1561. struct ath_softc *sc = aphy->sc;
  1562. mutex_lock(&sc->mutex);
  1563. ath9k_ps_wakeup(sc);
  1564. ath9k_hw_reset_tsf(sc->sc_ah);
  1565. ath9k_ps_restore(sc);
  1566. mutex_unlock(&sc->mutex);
  1567. }
  1568. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1569. struct ieee80211_vif *vif,
  1570. enum ieee80211_ampdu_mlme_action action,
  1571. struct ieee80211_sta *sta,
  1572. u16 tid, u16 *ssn)
  1573. {
  1574. struct ath_wiphy *aphy = hw->priv;
  1575. struct ath_softc *sc = aphy->sc;
  1576. int ret = 0;
  1577. local_bh_disable();
  1578. switch (action) {
  1579. case IEEE80211_AMPDU_RX_START:
  1580. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1581. ret = -ENOTSUPP;
  1582. break;
  1583. case IEEE80211_AMPDU_RX_STOP:
  1584. break;
  1585. case IEEE80211_AMPDU_TX_START:
  1586. ath9k_ps_wakeup(sc);
  1587. ath_tx_aggr_start(sc, sta, tid, ssn);
  1588. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1589. ath9k_ps_restore(sc);
  1590. break;
  1591. case IEEE80211_AMPDU_TX_STOP:
  1592. ath9k_ps_wakeup(sc);
  1593. ath_tx_aggr_stop(sc, sta, tid);
  1594. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1595. ath9k_ps_restore(sc);
  1596. break;
  1597. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1598. ath9k_ps_wakeup(sc);
  1599. ath_tx_aggr_resume(sc, sta, tid);
  1600. ath9k_ps_restore(sc);
  1601. break;
  1602. default:
  1603. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  1604. "Unknown AMPDU action\n");
  1605. }
  1606. local_bh_enable();
  1607. return ret;
  1608. }
  1609. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1610. struct survey_info *survey)
  1611. {
  1612. struct ath_wiphy *aphy = hw->priv;
  1613. struct ath_softc *sc = aphy->sc;
  1614. struct ath_hw *ah = sc->sc_ah;
  1615. struct ath_common *common = ath9k_hw_common(ah);
  1616. struct ieee80211_conf *conf = &hw->conf;
  1617. if (idx != 0)
  1618. return -ENOENT;
  1619. survey->channel = conf->channel;
  1620. survey->filled = SURVEY_INFO_NOISE_DBM;
  1621. survey->noise = common->ani.noise_floor;
  1622. return 0;
  1623. }
  1624. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1625. {
  1626. struct ath_wiphy *aphy = hw->priv;
  1627. struct ath_softc *sc = aphy->sc;
  1628. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1629. mutex_lock(&sc->mutex);
  1630. if (ath9k_wiphy_scanning(sc)) {
  1631. printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
  1632. "same time\n");
  1633. /*
  1634. * Do not allow the concurrent scanning state for now. This
  1635. * could be improved with scanning control moved into ath9k.
  1636. */
  1637. mutex_unlock(&sc->mutex);
  1638. return;
  1639. }
  1640. aphy->state = ATH_WIPHY_SCAN;
  1641. ath9k_wiphy_pause_all_forced(sc, aphy);
  1642. sc->sc_flags |= SC_OP_SCANNING;
  1643. del_timer_sync(&common->ani.timer);
  1644. cancel_work_sync(&sc->paprd_work);
  1645. cancel_delayed_work_sync(&sc->tx_complete_work);
  1646. mutex_unlock(&sc->mutex);
  1647. }
  1648. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1649. {
  1650. struct ath_wiphy *aphy = hw->priv;
  1651. struct ath_softc *sc = aphy->sc;
  1652. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1653. mutex_lock(&sc->mutex);
  1654. aphy->state = ATH_WIPHY_ACTIVE;
  1655. sc->sc_flags &= ~SC_OP_SCANNING;
  1656. sc->sc_flags |= SC_OP_FULL_RESET;
  1657. ath_start_ani(common);
  1658. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  1659. ath_beacon_config(sc, NULL);
  1660. mutex_unlock(&sc->mutex);
  1661. }
  1662. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1663. {
  1664. struct ath_wiphy *aphy = hw->priv;
  1665. struct ath_softc *sc = aphy->sc;
  1666. struct ath_hw *ah = sc->sc_ah;
  1667. mutex_lock(&sc->mutex);
  1668. ah->coverage_class = coverage_class;
  1669. ath9k_hw_init_global_settings(ah);
  1670. mutex_unlock(&sc->mutex);
  1671. }
  1672. struct ieee80211_ops ath9k_ops = {
  1673. .tx = ath9k_tx,
  1674. .start = ath9k_start,
  1675. .stop = ath9k_stop,
  1676. .add_interface = ath9k_add_interface,
  1677. .remove_interface = ath9k_remove_interface,
  1678. .config = ath9k_config,
  1679. .configure_filter = ath9k_configure_filter,
  1680. .sta_add = ath9k_sta_add,
  1681. .sta_remove = ath9k_sta_remove,
  1682. .conf_tx = ath9k_conf_tx,
  1683. .bss_info_changed = ath9k_bss_info_changed,
  1684. .set_key = ath9k_set_key,
  1685. .get_tsf = ath9k_get_tsf,
  1686. .set_tsf = ath9k_set_tsf,
  1687. .reset_tsf = ath9k_reset_tsf,
  1688. .ampdu_action = ath9k_ampdu_action,
  1689. .get_survey = ath9k_get_survey,
  1690. .sw_scan_start = ath9k_sw_scan_start,
  1691. .sw_scan_complete = ath9k_sw_scan_complete,
  1692. .rfkill_poll = ath9k_rfkill_poll_state,
  1693. .set_coverage_class = ath9k_set_coverage_class,
  1694. };