au1000_eth.c 33 KB

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  1. /*
  2. *
  3. * Alchemy Au1x00 ethernet driver
  4. *
  5. * Copyright 2001-2003, 2006 MontaVista Software Inc.
  6. * Copyright 2002 TimeSys Corp.
  7. * Added ethtool/mii-tool support,
  8. * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
  9. * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
  10. * or riemer@riemer-nt.de: fixed the link beat detection with
  11. * ioctls (SIOCGMIIPHY)
  12. * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
  13. * converted to use linux-2.6.x's PHY framework
  14. *
  15. * Author: MontaVista Software, Inc.
  16. * ppopov@mvista.com or source@mvista.com
  17. *
  18. * ########################################################################
  19. *
  20. * This program is free software; you can distribute it and/or modify it
  21. * under the terms of the GNU General Public License (Version 2) as
  22. * published by the Free Software Foundation.
  23. *
  24. * This program is distributed in the hope it will be useful, but WITHOUT
  25. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  26. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  27. * for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License along
  30. * with this program; if not, write to the Free Software Foundation, Inc.,
  31. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  32. *
  33. * ########################################################################
  34. *
  35. *
  36. */
  37. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  38. #include <linux/capability.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/module.h>
  41. #include <linux/kernel.h>
  42. #include <linux/string.h>
  43. #include <linux/timer.h>
  44. #include <linux/errno.h>
  45. #include <linux/in.h>
  46. #include <linux/ioport.h>
  47. #include <linux/bitops.h>
  48. #include <linux/slab.h>
  49. #include <linux/interrupt.h>
  50. #include <linux/init.h>
  51. #include <linux/netdevice.h>
  52. #include <linux/etherdevice.h>
  53. #include <linux/ethtool.h>
  54. #include <linux/mii.h>
  55. #include <linux/skbuff.h>
  56. #include <linux/delay.h>
  57. #include <linux/crc32.h>
  58. #include <linux/phy.h>
  59. #include <linux/platform_device.h>
  60. #include <linux/cpu.h>
  61. #include <linux/io.h>
  62. #include <asm/mipsregs.h>
  63. #include <asm/irq.h>
  64. #include <asm/processor.h>
  65. #include <au1000.h>
  66. #include <au1xxx_eth.h>
  67. #include <prom.h>
  68. #include "au1000_eth.h"
  69. #ifdef AU1000_ETH_DEBUG
  70. static int au1000_debug = 5;
  71. #else
  72. static int au1000_debug = 3;
  73. #endif
  74. #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
  75. NETIF_MSG_PROBE | \
  76. NETIF_MSG_LINK)
  77. #define DRV_NAME "au1000_eth"
  78. #define DRV_VERSION "1.7"
  79. #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
  80. #define DRV_DESC "Au1xxx on-chip Ethernet driver"
  81. MODULE_AUTHOR(DRV_AUTHOR);
  82. MODULE_DESCRIPTION(DRV_DESC);
  83. MODULE_LICENSE("GPL");
  84. MODULE_VERSION(DRV_VERSION);
  85. /*
  86. * Theory of operation
  87. *
  88. * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
  89. * There are four receive and four transmit descriptors. These
  90. * descriptors are not in memory; rather, they are just a set of
  91. * hardware registers.
  92. *
  93. * Since the Au1000 has a coherent data cache, the receive and
  94. * transmit buffers are allocated from the KSEG0 segment. The
  95. * hardware registers, however, are still mapped at KSEG1 to
  96. * make sure there's no out-of-order writes, and that all writes
  97. * complete immediately.
  98. */
  99. struct au1000_private *au_macs[NUM_ETH_INTERFACES];
  100. /*
  101. * board-specific configurations
  102. *
  103. * PHY detection algorithm
  104. *
  105. * If phy_static_config is undefined, the PHY setup is
  106. * autodetected:
  107. *
  108. * mii_probe() first searches the current MAC's MII bus for a PHY,
  109. * selecting the first (or last, if phy_search_highest_addr is
  110. * defined) PHY address not already claimed by another netdev.
  111. *
  112. * If nothing was found that way when searching for the 2nd ethernet
  113. * controller's PHY and phy1_search_mac0 is defined, then
  114. * the first MII bus is searched as well for an unclaimed PHY; this is
  115. * needed in case of a dual-PHY accessible only through the MAC0's MII
  116. * bus.
  117. *
  118. * Finally, if no PHY is found, then the corresponding ethernet
  119. * controller is not registered to the network subsystem.
  120. */
  121. /* autodetection defaults: phy1_search_mac0 */
  122. /* static PHY setup
  123. *
  124. * most boards PHY setup should be detectable properly with the
  125. * autodetection algorithm in mii_probe(), but in some cases (e.g. if
  126. * you have a switch attached, or want to use the PHY's interrupt
  127. * notification capabilities) you can provide a static PHY
  128. * configuration here
  129. *
  130. * IRQs may only be set, if a PHY address was configured
  131. * If a PHY address is given, also a bus id is required to be set
  132. *
  133. * ps: make sure the used irqs are configured properly in the board
  134. * specific irq-map
  135. */
  136. static void au1000_enable_mac(struct net_device *dev, int force_reset)
  137. {
  138. unsigned long flags;
  139. struct au1000_private *aup = netdev_priv(dev);
  140. spin_lock_irqsave(&aup->lock, flags);
  141. if (force_reset || (!aup->mac_enabled)) {
  142. writel(MAC_EN_CLOCK_ENABLE, &aup->enable);
  143. au_sync_delay(2);
  144. writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
  145. | MAC_EN_CLOCK_ENABLE), &aup->enable);
  146. au_sync_delay(2);
  147. aup->mac_enabled = 1;
  148. }
  149. spin_unlock_irqrestore(&aup->lock, flags);
  150. }
  151. /*
  152. * MII operations
  153. */
  154. static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
  155. {
  156. struct au1000_private *aup = netdev_priv(dev);
  157. u32 *const mii_control_reg = &aup->mac->mii_control;
  158. u32 *const mii_data_reg = &aup->mac->mii_data;
  159. u32 timedout = 20;
  160. u32 mii_control;
  161. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  162. mdelay(1);
  163. if (--timedout == 0) {
  164. netdev_err(dev, "read_MII busy timeout!!\n");
  165. return -1;
  166. }
  167. }
  168. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  169. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
  170. writel(mii_control, mii_control_reg);
  171. timedout = 20;
  172. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  173. mdelay(1);
  174. if (--timedout == 0) {
  175. netdev_err(dev, "mdio_read busy timeout!!\n");
  176. return -1;
  177. }
  178. }
  179. return readl(mii_data_reg);
  180. }
  181. static void au1000_mdio_write(struct net_device *dev, int phy_addr,
  182. int reg, u16 value)
  183. {
  184. struct au1000_private *aup = netdev_priv(dev);
  185. u32 *const mii_control_reg = &aup->mac->mii_control;
  186. u32 *const mii_data_reg = &aup->mac->mii_data;
  187. u32 timedout = 20;
  188. u32 mii_control;
  189. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  190. mdelay(1);
  191. if (--timedout == 0) {
  192. netdev_err(dev, "mdio_write busy timeout!!\n");
  193. return;
  194. }
  195. }
  196. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  197. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
  198. writel(value, mii_data_reg);
  199. writel(mii_control, mii_control_reg);
  200. }
  201. static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
  202. {
  203. /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
  204. * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
  205. struct net_device *const dev = bus->priv;
  206. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  207. * mii_bus is enabled */
  208. return au1000_mdio_read(dev, phy_addr, regnum);
  209. }
  210. static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
  211. u16 value)
  212. {
  213. struct net_device *const dev = bus->priv;
  214. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  215. * mii_bus is enabled */
  216. au1000_mdio_write(dev, phy_addr, regnum, value);
  217. return 0;
  218. }
  219. static int au1000_mdiobus_reset(struct mii_bus *bus)
  220. {
  221. struct net_device *const dev = bus->priv;
  222. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  223. * mii_bus is enabled */
  224. return 0;
  225. }
  226. static void au1000_hard_stop(struct net_device *dev)
  227. {
  228. struct au1000_private *aup = netdev_priv(dev);
  229. u32 reg;
  230. netif_dbg(aup, drv, dev, "hard stop\n");
  231. reg = readl(&aup->mac->control);
  232. reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
  233. writel(reg, &aup->mac->control);
  234. au_sync_delay(10);
  235. }
  236. static void au1000_enable_rx_tx(struct net_device *dev)
  237. {
  238. struct au1000_private *aup = netdev_priv(dev);
  239. u32 reg;
  240. netif_dbg(aup, hw, dev, "enable_rx_tx\n");
  241. reg = readl(&aup->mac->control);
  242. reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
  243. writel(reg, &aup->mac->control);
  244. au_sync_delay(10);
  245. }
  246. static void
  247. au1000_adjust_link(struct net_device *dev)
  248. {
  249. struct au1000_private *aup = netdev_priv(dev);
  250. struct phy_device *phydev = aup->phy_dev;
  251. unsigned long flags;
  252. u32 reg;
  253. int status_change = 0;
  254. BUG_ON(!aup->phy_dev);
  255. spin_lock_irqsave(&aup->lock, flags);
  256. if (phydev->link && (aup->old_speed != phydev->speed)) {
  257. /* speed changed */
  258. switch (phydev->speed) {
  259. case SPEED_10:
  260. case SPEED_100:
  261. break;
  262. default:
  263. netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
  264. phydev->speed);
  265. break;
  266. }
  267. aup->old_speed = phydev->speed;
  268. status_change = 1;
  269. }
  270. if (phydev->link && (aup->old_duplex != phydev->duplex)) {
  271. /* duplex mode changed */
  272. /* switching duplex mode requires to disable rx and tx! */
  273. au1000_hard_stop(dev);
  274. reg = readl(&aup->mac->control);
  275. if (DUPLEX_FULL == phydev->duplex) {
  276. reg |= MAC_FULL_DUPLEX;
  277. reg &= ~MAC_DISABLE_RX_OWN;
  278. } else {
  279. reg &= ~MAC_FULL_DUPLEX;
  280. reg |= MAC_DISABLE_RX_OWN;
  281. }
  282. writel(reg, &aup->mac->control);
  283. au_sync_delay(1);
  284. au1000_enable_rx_tx(dev);
  285. aup->old_duplex = phydev->duplex;
  286. status_change = 1;
  287. }
  288. if (phydev->link != aup->old_link) {
  289. /* link state changed */
  290. if (!phydev->link) {
  291. /* link went down */
  292. aup->old_speed = 0;
  293. aup->old_duplex = -1;
  294. }
  295. aup->old_link = phydev->link;
  296. status_change = 1;
  297. }
  298. spin_unlock_irqrestore(&aup->lock, flags);
  299. if (status_change) {
  300. if (phydev->link)
  301. netdev_info(dev, "link up (%d/%s)\n",
  302. phydev->speed,
  303. DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
  304. else
  305. netdev_info(dev, "link down\n");
  306. }
  307. }
  308. static int au1000_mii_probe(struct net_device *dev)
  309. {
  310. struct au1000_private *const aup = netdev_priv(dev);
  311. struct phy_device *phydev = NULL;
  312. int phy_addr;
  313. if (aup->phy_static_config) {
  314. BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
  315. if (aup->phy_addr)
  316. phydev = aup->mii_bus->phy_map[aup->phy_addr];
  317. else
  318. netdev_info(dev, "using PHY-less setup\n");
  319. return 0;
  320. }
  321. /* find the first (lowest address) PHY
  322. * on the current MAC's MII bus */
  323. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
  324. if (aup->mii_bus->phy_map[phy_addr]) {
  325. phydev = aup->mii_bus->phy_map[phy_addr];
  326. if (!aup->phy_search_highest_addr)
  327. /* break out with first one found */
  328. break;
  329. }
  330. if (aup->phy1_search_mac0) {
  331. /* try harder to find a PHY */
  332. if (!phydev && (aup->mac_id == 1)) {
  333. /* no PHY found, maybe we have a dual PHY? */
  334. dev_info(&dev->dev, ": no PHY found on MAC1, "
  335. "let's see if it's attached to MAC0...\n");
  336. /* find the first (lowest address) non-attached
  337. * PHY on the MAC0 MII bus
  338. */
  339. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  340. struct phy_device *const tmp_phydev =
  341. aup->mii_bus->phy_map[phy_addr];
  342. if (aup->mac_id == 1)
  343. break;
  344. /* no PHY here... */
  345. if (!tmp_phydev)
  346. continue;
  347. /* already claimed by MAC0 */
  348. if (tmp_phydev->attached_dev)
  349. continue;
  350. phydev = tmp_phydev;
  351. break; /* found it */
  352. }
  353. }
  354. }
  355. if (!phydev) {
  356. netdev_err(dev, "no PHY found\n");
  357. return -1;
  358. }
  359. /* now we are supposed to have a proper phydev, to attach to... */
  360. BUG_ON(phydev->attached_dev);
  361. phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link,
  362. 0, PHY_INTERFACE_MODE_MII);
  363. if (IS_ERR(phydev)) {
  364. netdev_err(dev, "Could not attach to PHY\n");
  365. return PTR_ERR(phydev);
  366. }
  367. /* mask with MAC supported features */
  368. phydev->supported &= (SUPPORTED_10baseT_Half
  369. | SUPPORTED_10baseT_Full
  370. | SUPPORTED_100baseT_Half
  371. | SUPPORTED_100baseT_Full
  372. | SUPPORTED_Autoneg
  373. /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
  374. | SUPPORTED_MII
  375. | SUPPORTED_TP);
  376. phydev->advertising = phydev->supported;
  377. aup->old_link = 0;
  378. aup->old_speed = 0;
  379. aup->old_duplex = -1;
  380. aup->phy_dev = phydev;
  381. netdev_info(dev, "attached PHY driver [%s] "
  382. "(mii_bus:phy_addr=%s, irq=%d)\n",
  383. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  384. return 0;
  385. }
  386. /*
  387. * Buffer allocation/deallocation routines. The buffer descriptor returned
  388. * has the virtual and dma address of a buffer suitable for
  389. * both, receive and transmit operations.
  390. */
  391. static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
  392. {
  393. struct db_dest *pDB;
  394. pDB = aup->pDBfree;
  395. if (pDB)
  396. aup->pDBfree = pDB->pnext;
  397. return pDB;
  398. }
  399. void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
  400. {
  401. struct db_dest *pDBfree = aup->pDBfree;
  402. if (pDBfree)
  403. pDBfree->pnext = pDB;
  404. aup->pDBfree = pDB;
  405. }
  406. static void au1000_reset_mac_unlocked(struct net_device *dev)
  407. {
  408. struct au1000_private *const aup = netdev_priv(dev);
  409. int i;
  410. au1000_hard_stop(dev);
  411. writel(MAC_EN_CLOCK_ENABLE, &aup->enable);
  412. au_sync_delay(2);
  413. writel(0, &aup->enable);
  414. au_sync_delay(2);
  415. aup->tx_full = 0;
  416. for (i = 0; i < NUM_RX_DMA; i++) {
  417. /* reset control bits */
  418. aup->rx_dma_ring[i]->buff_stat &= ~0xf;
  419. }
  420. for (i = 0; i < NUM_TX_DMA; i++) {
  421. /* reset control bits */
  422. aup->tx_dma_ring[i]->buff_stat &= ~0xf;
  423. }
  424. aup->mac_enabled = 0;
  425. }
  426. static void au1000_reset_mac(struct net_device *dev)
  427. {
  428. struct au1000_private *const aup = netdev_priv(dev);
  429. unsigned long flags;
  430. netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
  431. (unsigned)aup);
  432. spin_lock_irqsave(&aup->lock, flags);
  433. au1000_reset_mac_unlocked(dev);
  434. spin_unlock_irqrestore(&aup->lock, flags);
  435. }
  436. /*
  437. * Setup the receive and transmit "rings". These pointers are the addresses
  438. * of the rx and tx MAC DMA registers so they are fixed by the hardware --
  439. * these are not descriptors sitting in memory.
  440. */
  441. static void
  442. au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
  443. {
  444. int i;
  445. for (i = 0; i < NUM_RX_DMA; i++) {
  446. aup->rx_dma_ring[i] =
  447. (struct rx_dma *)
  448. (rx_base + sizeof(struct rx_dma)*i);
  449. }
  450. for (i = 0; i < NUM_TX_DMA; i++) {
  451. aup->tx_dma_ring[i] =
  452. (struct tx_dma *)
  453. (tx_base + sizeof(struct tx_dma)*i);
  454. }
  455. }
  456. /*
  457. * ethtool operations
  458. */
  459. static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  460. {
  461. struct au1000_private *aup = netdev_priv(dev);
  462. if (aup->phy_dev)
  463. return phy_ethtool_gset(aup->phy_dev, cmd);
  464. return -EINVAL;
  465. }
  466. static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  467. {
  468. struct au1000_private *aup = netdev_priv(dev);
  469. if (!capable(CAP_NET_ADMIN))
  470. return -EPERM;
  471. if (aup->phy_dev)
  472. return phy_ethtool_sset(aup->phy_dev, cmd);
  473. return -EINVAL;
  474. }
  475. static void
  476. au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  477. {
  478. struct au1000_private *aup = netdev_priv(dev);
  479. strcpy(info->driver, DRV_NAME);
  480. strcpy(info->version, DRV_VERSION);
  481. info->fw_version[0] = '\0';
  482. sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
  483. info->regdump_len = 0;
  484. }
  485. static void au1000_set_msglevel(struct net_device *dev, u32 value)
  486. {
  487. struct au1000_private *aup = netdev_priv(dev);
  488. aup->msg_enable = value;
  489. }
  490. static u32 au1000_get_msglevel(struct net_device *dev)
  491. {
  492. struct au1000_private *aup = netdev_priv(dev);
  493. return aup->msg_enable;
  494. }
  495. static const struct ethtool_ops au1000_ethtool_ops = {
  496. .get_settings = au1000_get_settings,
  497. .set_settings = au1000_set_settings,
  498. .get_drvinfo = au1000_get_drvinfo,
  499. .get_link = ethtool_op_get_link,
  500. .get_msglevel = au1000_get_msglevel,
  501. .set_msglevel = au1000_set_msglevel,
  502. };
  503. /*
  504. * Initialize the interface.
  505. *
  506. * When the device powers up, the clocks are disabled and the
  507. * mac is in reset state. When the interface is closed, we
  508. * do the same -- reset the device and disable the clocks to
  509. * conserve power. Thus, whenever au1000_init() is called,
  510. * the device should already be in reset state.
  511. */
  512. static int au1000_init(struct net_device *dev)
  513. {
  514. struct au1000_private *aup = netdev_priv(dev);
  515. unsigned long flags;
  516. int i;
  517. u32 control;
  518. netif_dbg(aup, hw, dev, "au1000_init\n");
  519. /* bring the device out of reset */
  520. au1000_enable_mac(dev, 1);
  521. spin_lock_irqsave(&aup->lock, flags);
  522. writel(0, &aup->mac->control);
  523. aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
  524. aup->tx_tail = aup->tx_head;
  525. aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
  526. writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
  527. &aup->mac->mac_addr_high);
  528. writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
  529. dev->dev_addr[1]<<8 | dev->dev_addr[0],
  530. &aup->mac->mac_addr_low);
  531. for (i = 0; i < NUM_RX_DMA; i++)
  532. aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
  533. au_sync();
  534. control = MAC_RX_ENABLE | MAC_TX_ENABLE;
  535. #ifndef CONFIG_CPU_LITTLE_ENDIAN
  536. control |= MAC_BIG_ENDIAN;
  537. #endif
  538. if (aup->phy_dev) {
  539. if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
  540. control |= MAC_FULL_DUPLEX;
  541. else
  542. control |= MAC_DISABLE_RX_OWN;
  543. } else { /* PHY-less op, assume full-duplex */
  544. control |= MAC_FULL_DUPLEX;
  545. }
  546. writel(control, &aup->mac->control);
  547. writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
  548. au_sync();
  549. spin_unlock_irqrestore(&aup->lock, flags);
  550. return 0;
  551. }
  552. static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
  553. {
  554. struct net_device_stats *ps = &dev->stats;
  555. ps->rx_packets++;
  556. if (status & RX_MCAST_FRAME)
  557. ps->multicast++;
  558. if (status & RX_ERROR) {
  559. ps->rx_errors++;
  560. if (status & RX_MISSED_FRAME)
  561. ps->rx_missed_errors++;
  562. if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
  563. ps->rx_length_errors++;
  564. if (status & RX_CRC_ERROR)
  565. ps->rx_crc_errors++;
  566. if (status & RX_COLL)
  567. ps->collisions++;
  568. } else
  569. ps->rx_bytes += status & RX_FRAME_LEN_MASK;
  570. }
  571. /*
  572. * Au1000 receive routine.
  573. */
  574. static int au1000_rx(struct net_device *dev)
  575. {
  576. struct au1000_private *aup = netdev_priv(dev);
  577. struct sk_buff *skb;
  578. struct rx_dma *prxd;
  579. u32 buff_stat, status;
  580. struct db_dest *pDB;
  581. u32 frmlen;
  582. netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
  583. prxd = aup->rx_dma_ring[aup->rx_head];
  584. buff_stat = prxd->buff_stat;
  585. while (buff_stat & RX_T_DONE) {
  586. status = prxd->status;
  587. pDB = aup->rx_db_inuse[aup->rx_head];
  588. au1000_update_rx_stats(dev, status);
  589. if (!(status & RX_ERROR)) {
  590. /* good frame */
  591. frmlen = (status & RX_FRAME_LEN_MASK);
  592. frmlen -= 4; /* Remove FCS */
  593. skb = dev_alloc_skb(frmlen + 2);
  594. if (skb == NULL) {
  595. netdev_err(dev, "Memory squeeze, dropping packet.\n");
  596. dev->stats.rx_dropped++;
  597. continue;
  598. }
  599. skb_reserve(skb, 2); /* 16 byte IP header align */
  600. skb_copy_to_linear_data(skb,
  601. (unsigned char *)pDB->vaddr, frmlen);
  602. skb_put(skb, frmlen);
  603. skb->protocol = eth_type_trans(skb, dev);
  604. netif_rx(skb); /* pass the packet to upper layers */
  605. } else {
  606. if (au1000_debug > 4) {
  607. pr_err("rx_error(s):");
  608. if (status & RX_MISSED_FRAME)
  609. pr_cont(" miss");
  610. if (status & RX_WDOG_TIMER)
  611. pr_cont(" wdog");
  612. if (status & RX_RUNT)
  613. pr_cont(" runt");
  614. if (status & RX_OVERLEN)
  615. pr_cont(" overlen");
  616. if (status & RX_COLL)
  617. pr_cont(" coll");
  618. if (status & RX_MII_ERROR)
  619. pr_cont(" mii error");
  620. if (status & RX_CRC_ERROR)
  621. pr_cont(" crc error");
  622. if (status & RX_LEN_ERROR)
  623. pr_cont(" len error");
  624. if (status & RX_U_CNTRL_FRAME)
  625. pr_cont(" u control frame");
  626. pr_cont("\n");
  627. }
  628. }
  629. prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
  630. aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
  631. au_sync();
  632. /* next descriptor */
  633. prxd = aup->rx_dma_ring[aup->rx_head];
  634. buff_stat = prxd->buff_stat;
  635. }
  636. return 0;
  637. }
  638. static void au1000_update_tx_stats(struct net_device *dev, u32 status)
  639. {
  640. struct au1000_private *aup = netdev_priv(dev);
  641. struct net_device_stats *ps = &dev->stats;
  642. if (status & TX_FRAME_ABORTED) {
  643. if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
  644. if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
  645. /* any other tx errors are only valid
  646. * in half duplex mode */
  647. ps->tx_errors++;
  648. ps->tx_aborted_errors++;
  649. }
  650. } else {
  651. ps->tx_errors++;
  652. ps->tx_aborted_errors++;
  653. if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
  654. ps->tx_carrier_errors++;
  655. }
  656. }
  657. }
  658. /*
  659. * Called from the interrupt service routine to acknowledge
  660. * the TX DONE bits. This is a must if the irq is setup as
  661. * edge triggered.
  662. */
  663. static void au1000_tx_ack(struct net_device *dev)
  664. {
  665. struct au1000_private *aup = netdev_priv(dev);
  666. struct tx_dma *ptxd;
  667. ptxd = aup->tx_dma_ring[aup->tx_tail];
  668. while (ptxd->buff_stat & TX_T_DONE) {
  669. au1000_update_tx_stats(dev, ptxd->status);
  670. ptxd->buff_stat &= ~TX_T_DONE;
  671. ptxd->len = 0;
  672. au_sync();
  673. aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
  674. ptxd = aup->tx_dma_ring[aup->tx_tail];
  675. if (aup->tx_full) {
  676. aup->tx_full = 0;
  677. netif_wake_queue(dev);
  678. }
  679. }
  680. }
  681. /*
  682. * Au1000 interrupt service routine.
  683. */
  684. static irqreturn_t au1000_interrupt(int irq, void *dev_id)
  685. {
  686. struct net_device *dev = dev_id;
  687. /* Handle RX interrupts first to minimize chance of overrun */
  688. au1000_rx(dev);
  689. au1000_tx_ack(dev);
  690. return IRQ_RETVAL(1);
  691. }
  692. static int au1000_open(struct net_device *dev)
  693. {
  694. int retval;
  695. struct au1000_private *aup = netdev_priv(dev);
  696. netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
  697. retval = request_irq(dev->irq, au1000_interrupt, 0,
  698. dev->name, dev);
  699. if (retval) {
  700. netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
  701. return retval;
  702. }
  703. retval = au1000_init(dev);
  704. if (retval) {
  705. netdev_err(dev, "error in au1000_init\n");
  706. free_irq(dev->irq, dev);
  707. return retval;
  708. }
  709. if (aup->phy_dev) {
  710. /* cause the PHY state machine to schedule a link state check */
  711. aup->phy_dev->state = PHY_CHANGELINK;
  712. phy_start(aup->phy_dev);
  713. }
  714. netif_start_queue(dev);
  715. netif_dbg(aup, drv, dev, "open: Initialization done.\n");
  716. return 0;
  717. }
  718. static int au1000_close(struct net_device *dev)
  719. {
  720. unsigned long flags;
  721. struct au1000_private *const aup = netdev_priv(dev);
  722. netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
  723. if (aup->phy_dev)
  724. phy_stop(aup->phy_dev);
  725. spin_lock_irqsave(&aup->lock, flags);
  726. au1000_reset_mac_unlocked(dev);
  727. /* stop the device */
  728. netif_stop_queue(dev);
  729. /* disable the interrupt */
  730. free_irq(dev->irq, dev);
  731. spin_unlock_irqrestore(&aup->lock, flags);
  732. return 0;
  733. }
  734. /*
  735. * Au1000 transmit routine.
  736. */
  737. static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
  738. {
  739. struct au1000_private *aup = netdev_priv(dev);
  740. struct net_device_stats *ps = &dev->stats;
  741. struct tx_dma *ptxd;
  742. u32 buff_stat;
  743. struct db_dest *pDB;
  744. int i;
  745. netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
  746. (unsigned)aup, skb->len,
  747. skb->data, aup->tx_head);
  748. ptxd = aup->tx_dma_ring[aup->tx_head];
  749. buff_stat = ptxd->buff_stat;
  750. if (buff_stat & TX_DMA_ENABLE) {
  751. /* We've wrapped around and the transmitter is still busy */
  752. netif_stop_queue(dev);
  753. aup->tx_full = 1;
  754. return NETDEV_TX_BUSY;
  755. } else if (buff_stat & TX_T_DONE) {
  756. au1000_update_tx_stats(dev, ptxd->status);
  757. ptxd->len = 0;
  758. }
  759. if (aup->tx_full) {
  760. aup->tx_full = 0;
  761. netif_wake_queue(dev);
  762. }
  763. pDB = aup->tx_db_inuse[aup->tx_head];
  764. skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
  765. if (skb->len < ETH_ZLEN) {
  766. for (i = skb->len; i < ETH_ZLEN; i++)
  767. ((char *)pDB->vaddr)[i] = 0;
  768. ptxd->len = ETH_ZLEN;
  769. } else
  770. ptxd->len = skb->len;
  771. ps->tx_packets++;
  772. ps->tx_bytes += ptxd->len;
  773. ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
  774. au_sync();
  775. dev_kfree_skb(skb);
  776. aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
  777. return NETDEV_TX_OK;
  778. }
  779. /*
  780. * The Tx ring has been full longer than the watchdog timeout
  781. * value. The transmitter must be hung?
  782. */
  783. static void au1000_tx_timeout(struct net_device *dev)
  784. {
  785. netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
  786. au1000_reset_mac(dev);
  787. au1000_init(dev);
  788. dev->trans_start = jiffies; /* prevent tx timeout */
  789. netif_wake_queue(dev);
  790. }
  791. static void au1000_multicast_list(struct net_device *dev)
  792. {
  793. struct au1000_private *aup = netdev_priv(dev);
  794. u32 reg;
  795. netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
  796. reg = readl(&aup->mac->control);
  797. if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
  798. reg |= MAC_PROMISCUOUS;
  799. } else if ((dev->flags & IFF_ALLMULTI) ||
  800. netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
  801. reg |= MAC_PASS_ALL_MULTI;
  802. reg &= ~MAC_PROMISCUOUS;
  803. netdev_info(dev, "Pass all multicast\n");
  804. } else {
  805. struct netdev_hw_addr *ha;
  806. u32 mc_filter[2]; /* Multicast hash filter */
  807. mc_filter[1] = mc_filter[0] = 0;
  808. netdev_for_each_mc_addr(ha, dev)
  809. set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
  810. (long *)mc_filter);
  811. writel(mc_filter[1], &aup->mac->multi_hash_high);
  812. writel(mc_filter[0], &aup->mac->multi_hash_low);
  813. reg &= ~MAC_PROMISCUOUS;
  814. reg |= MAC_HASH_MODE;
  815. }
  816. writel(reg, &aup->mac->control);
  817. }
  818. static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  819. {
  820. struct au1000_private *aup = netdev_priv(dev);
  821. if (!netif_running(dev))
  822. return -EINVAL;
  823. if (!aup->phy_dev)
  824. return -EINVAL; /* PHY not controllable */
  825. return phy_mii_ioctl(aup->phy_dev, rq, cmd);
  826. }
  827. static const struct net_device_ops au1000_netdev_ops = {
  828. .ndo_open = au1000_open,
  829. .ndo_stop = au1000_close,
  830. .ndo_start_xmit = au1000_tx,
  831. .ndo_set_multicast_list = au1000_multicast_list,
  832. .ndo_do_ioctl = au1000_ioctl,
  833. .ndo_tx_timeout = au1000_tx_timeout,
  834. .ndo_set_mac_address = eth_mac_addr,
  835. .ndo_validate_addr = eth_validate_addr,
  836. .ndo_change_mtu = eth_change_mtu,
  837. };
  838. static int __devinit au1000_probe(struct platform_device *pdev)
  839. {
  840. static unsigned version_printed;
  841. struct au1000_private *aup = NULL;
  842. struct au1000_eth_platform_data *pd;
  843. struct net_device *dev = NULL;
  844. struct db_dest *pDB, *pDBfree;
  845. int irq, i, err = 0;
  846. struct resource *base, *macen;
  847. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  848. if (!base) {
  849. dev_err(&pdev->dev, "failed to retrieve base register\n");
  850. err = -ENODEV;
  851. goto out;
  852. }
  853. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  854. if (!macen) {
  855. dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
  856. err = -ENODEV;
  857. goto out;
  858. }
  859. irq = platform_get_irq(pdev, 0);
  860. if (irq < 0) {
  861. dev_err(&pdev->dev, "failed to retrieve IRQ\n");
  862. err = -ENODEV;
  863. goto out;
  864. }
  865. if (!request_mem_region(base->start, resource_size(base),
  866. pdev->name)) {
  867. dev_err(&pdev->dev, "failed to request memory region for base registers\n");
  868. err = -ENXIO;
  869. goto out;
  870. }
  871. if (!request_mem_region(macen->start, resource_size(macen),
  872. pdev->name)) {
  873. dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
  874. err = -ENXIO;
  875. goto err_request;
  876. }
  877. dev = alloc_etherdev(sizeof(struct au1000_private));
  878. if (!dev) {
  879. dev_err(&pdev->dev, "alloc_etherdev failed\n");
  880. err = -ENOMEM;
  881. goto err_alloc;
  882. }
  883. SET_NETDEV_DEV(dev, &pdev->dev);
  884. platform_set_drvdata(pdev, dev);
  885. aup = netdev_priv(dev);
  886. spin_lock_init(&aup->lock);
  887. aup->msg_enable = (au1000_debug < 4 ?
  888. AU1000_DEF_MSG_ENABLE : au1000_debug);
  889. /* Allocate the data buffers */
  890. /* Snooping works fine with eth on all au1xxx */
  891. aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
  892. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  893. &aup->dma_addr, 0);
  894. if (!aup->vaddr) {
  895. dev_err(&pdev->dev, "failed to allocate data buffers\n");
  896. err = -ENOMEM;
  897. goto err_vaddr;
  898. }
  899. /* aup->mac is the base address of the MAC's registers */
  900. aup->mac = (struct mac_reg *)
  901. ioremap_nocache(base->start, resource_size(base));
  902. if (!aup->mac) {
  903. dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
  904. err = -ENXIO;
  905. goto err_remap1;
  906. }
  907. /* Setup some variables for quick register address access */
  908. aup->enable = (u32 *)ioremap_nocache(macen->start,
  909. resource_size(macen));
  910. if (!aup->enable) {
  911. dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
  912. err = -ENXIO;
  913. goto err_remap2;
  914. }
  915. aup->mac_id = pdev->id;
  916. if (pdev->id == 0)
  917. au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
  918. else if (pdev->id == 1)
  919. au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
  920. /* set a random MAC now in case platform_data doesn't provide one */
  921. random_ether_addr(dev->dev_addr);
  922. writel(0, &aup->enable);
  923. aup->mac_enabled = 0;
  924. pd = pdev->dev.platform_data;
  925. if (!pd) {
  926. dev_info(&pdev->dev, "no platform_data passed,"
  927. " PHY search on MAC0\n");
  928. aup->phy1_search_mac0 = 1;
  929. } else {
  930. if (is_valid_ether_addr(pd->mac))
  931. memcpy(dev->dev_addr, pd->mac, 6);
  932. aup->phy_static_config = pd->phy_static_config;
  933. aup->phy_search_highest_addr = pd->phy_search_highest_addr;
  934. aup->phy1_search_mac0 = pd->phy1_search_mac0;
  935. aup->phy_addr = pd->phy_addr;
  936. aup->phy_busid = pd->phy_busid;
  937. aup->phy_irq = pd->phy_irq;
  938. }
  939. if (aup->phy_busid && aup->phy_busid > 0) {
  940. dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
  941. err = -ENODEV;
  942. goto err_mdiobus_alloc;
  943. }
  944. aup->mii_bus = mdiobus_alloc();
  945. if (aup->mii_bus == NULL) {
  946. dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
  947. err = -ENOMEM;
  948. goto err_mdiobus_alloc;
  949. }
  950. aup->mii_bus->priv = dev;
  951. aup->mii_bus->read = au1000_mdiobus_read;
  952. aup->mii_bus->write = au1000_mdiobus_write;
  953. aup->mii_bus->reset = au1000_mdiobus_reset;
  954. aup->mii_bus->name = "au1000_eth_mii";
  955. snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
  956. aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  957. if (aup->mii_bus->irq == NULL)
  958. goto err_out;
  959. for (i = 0; i < PHY_MAX_ADDR; ++i)
  960. aup->mii_bus->irq[i] = PHY_POLL;
  961. /* if known, set corresponding PHY IRQs */
  962. if (aup->phy_static_config)
  963. if (aup->phy_irq && aup->phy_busid == aup->mac_id)
  964. aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
  965. err = mdiobus_register(aup->mii_bus);
  966. if (err) {
  967. dev_err(&pdev->dev, "failed to register MDIO bus\n");
  968. goto err_mdiobus_reg;
  969. }
  970. if (au1000_mii_probe(dev) != 0)
  971. goto err_out;
  972. pDBfree = NULL;
  973. /* setup the data buffer descriptors and attach a buffer to each one */
  974. pDB = aup->db;
  975. for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
  976. pDB->pnext = pDBfree;
  977. pDBfree = pDB;
  978. pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
  979. pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
  980. pDB++;
  981. }
  982. aup->pDBfree = pDBfree;
  983. for (i = 0; i < NUM_RX_DMA; i++) {
  984. pDB = au1000_GetFreeDB(aup);
  985. if (!pDB)
  986. goto err_out;
  987. aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  988. aup->rx_db_inuse[i] = pDB;
  989. }
  990. for (i = 0; i < NUM_TX_DMA; i++) {
  991. pDB = au1000_GetFreeDB(aup);
  992. if (!pDB)
  993. goto err_out;
  994. aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  995. aup->tx_dma_ring[i]->len = 0;
  996. aup->tx_db_inuse[i] = pDB;
  997. }
  998. dev->base_addr = base->start;
  999. dev->irq = irq;
  1000. dev->netdev_ops = &au1000_netdev_ops;
  1001. SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
  1002. dev->watchdog_timeo = ETH_TX_TIMEOUT;
  1003. /*
  1004. * The boot code uses the ethernet controller, so reset it to start
  1005. * fresh. au1000_init() expects that the device is in reset state.
  1006. */
  1007. au1000_reset_mac(dev);
  1008. err = register_netdev(dev);
  1009. if (err) {
  1010. netdev_err(dev, "Cannot register net device, aborting.\n");
  1011. goto err_out;
  1012. }
  1013. netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
  1014. (unsigned long)base->start, irq);
  1015. if (version_printed++ == 0)
  1016. pr_info("%s version %s %s\n",
  1017. DRV_NAME, DRV_VERSION, DRV_AUTHOR);
  1018. return 0;
  1019. err_out:
  1020. if (aup->mii_bus != NULL)
  1021. mdiobus_unregister(aup->mii_bus);
  1022. /* here we should have a valid dev plus aup-> register addresses
  1023. * so we can reset the mac properly.*/
  1024. au1000_reset_mac(dev);
  1025. for (i = 0; i < NUM_RX_DMA; i++) {
  1026. if (aup->rx_db_inuse[i])
  1027. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1028. }
  1029. for (i = 0; i < NUM_TX_DMA; i++) {
  1030. if (aup->tx_db_inuse[i])
  1031. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1032. }
  1033. err_mdiobus_reg:
  1034. mdiobus_free(aup->mii_bus);
  1035. err_mdiobus_alloc:
  1036. iounmap(aup->enable);
  1037. err_remap2:
  1038. iounmap(aup->mac);
  1039. err_remap1:
  1040. dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1041. (void *)aup->vaddr, aup->dma_addr);
  1042. err_vaddr:
  1043. free_netdev(dev);
  1044. err_alloc:
  1045. release_mem_region(macen->start, resource_size(macen));
  1046. err_request:
  1047. release_mem_region(base->start, resource_size(base));
  1048. out:
  1049. return err;
  1050. }
  1051. static int __devexit au1000_remove(struct platform_device *pdev)
  1052. {
  1053. struct net_device *dev = platform_get_drvdata(pdev);
  1054. struct au1000_private *aup = netdev_priv(dev);
  1055. int i;
  1056. struct resource *base, *macen;
  1057. platform_set_drvdata(pdev, NULL);
  1058. unregister_netdev(dev);
  1059. mdiobus_unregister(aup->mii_bus);
  1060. mdiobus_free(aup->mii_bus);
  1061. for (i = 0; i < NUM_RX_DMA; i++)
  1062. if (aup->rx_db_inuse[i])
  1063. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1064. for (i = 0; i < NUM_TX_DMA; i++)
  1065. if (aup->tx_db_inuse[i])
  1066. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1067. dma_free_noncoherent(NULL, MAX_BUF_SIZE *
  1068. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1069. (void *)aup->vaddr, aup->dma_addr);
  1070. iounmap(aup->mac);
  1071. iounmap(aup->enable);
  1072. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1073. release_mem_region(base->start, resource_size(base));
  1074. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1075. release_mem_region(macen->start, resource_size(macen));
  1076. free_netdev(dev);
  1077. return 0;
  1078. }
  1079. static struct platform_driver au1000_eth_driver = {
  1080. .probe = au1000_probe,
  1081. .remove = __devexit_p(au1000_remove),
  1082. .driver = {
  1083. .name = "au1000-eth",
  1084. .owner = THIS_MODULE,
  1085. },
  1086. };
  1087. MODULE_ALIAS("platform:au1000-eth");
  1088. static int __init au1000_init_module(void)
  1089. {
  1090. return platform_driver_register(&au1000_eth_driver);
  1091. }
  1092. static void __exit au1000_exit_module(void)
  1093. {
  1094. platform_driver_unregister(&au1000_eth_driver);
  1095. }
  1096. module_init(au1000_init_module);
  1097. module_exit(au1000_exit_module);