intel_pm.c 102 KB

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  1. /*
  2. * Copyright © 2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eugeni Dodonov <eugeni.dodonov@intel.com>
  25. *
  26. */
  27. #include <linux/cpufreq.h>
  28. #include "i915_drv.h"
  29. #include "intel_drv.h"
  30. #include "../../../platform/x86/intel_ips.h"
  31. #include <linux/module.h>
  32. /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  33. * framebuffer contents in-memory, aiming at reducing the required bandwidth
  34. * during in-memory transfers and, therefore, reduce the power packet.
  35. *
  36. * The benefits of FBC are mostly visible with solid backgrounds and
  37. * variation-less patterns.
  38. *
  39. * FBC-related functionality can be enabled by the means of the
  40. * i915.i915_enable_fbc parameter
  41. */
  42. static void i8xx_disable_fbc(struct drm_device *dev)
  43. {
  44. struct drm_i915_private *dev_priv = dev->dev_private;
  45. u32 fbc_ctl;
  46. /* Disable compression */
  47. fbc_ctl = I915_READ(FBC_CONTROL);
  48. if ((fbc_ctl & FBC_CTL_EN) == 0)
  49. return;
  50. fbc_ctl &= ~FBC_CTL_EN;
  51. I915_WRITE(FBC_CONTROL, fbc_ctl);
  52. /* Wait for compressing bit to clear */
  53. if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  54. DRM_DEBUG_KMS("FBC idle timed out\n");
  55. return;
  56. }
  57. DRM_DEBUG_KMS("disabled FBC\n");
  58. }
  59. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  60. {
  61. struct drm_device *dev = crtc->dev;
  62. struct drm_i915_private *dev_priv = dev->dev_private;
  63. struct drm_framebuffer *fb = crtc->fb;
  64. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  65. struct drm_i915_gem_object *obj = intel_fb->obj;
  66. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  67. int cfb_pitch;
  68. int plane, i;
  69. u32 fbc_ctl, fbc_ctl2;
  70. cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  71. if (fb->pitches[0] < cfb_pitch)
  72. cfb_pitch = fb->pitches[0];
  73. /* FBC_CTL wants 64B units */
  74. cfb_pitch = (cfb_pitch / 64) - 1;
  75. plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  76. /* Clear old tags */
  77. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  78. I915_WRITE(FBC_TAG + (i * 4), 0);
  79. /* Set it up... */
  80. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  81. fbc_ctl2 |= plane;
  82. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  83. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  84. /* enable it... */
  85. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  86. if (IS_I945GM(dev))
  87. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  88. fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  89. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  90. fbc_ctl |= obj->fence_reg;
  91. I915_WRITE(FBC_CONTROL, fbc_ctl);
  92. DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
  93. cfb_pitch, crtc->y, intel_crtc->plane);
  94. }
  95. static bool i8xx_fbc_enabled(struct drm_device *dev)
  96. {
  97. struct drm_i915_private *dev_priv = dev->dev_private;
  98. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  99. }
  100. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  101. {
  102. struct drm_device *dev = crtc->dev;
  103. struct drm_i915_private *dev_priv = dev->dev_private;
  104. struct drm_framebuffer *fb = crtc->fb;
  105. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  106. struct drm_i915_gem_object *obj = intel_fb->obj;
  107. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  108. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  109. unsigned long stall_watermark = 200;
  110. u32 dpfc_ctl;
  111. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  112. dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
  113. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  114. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  115. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  116. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  117. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  118. /* enable it... */
  119. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  120. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  121. }
  122. static void g4x_disable_fbc(struct drm_device *dev)
  123. {
  124. struct drm_i915_private *dev_priv = dev->dev_private;
  125. u32 dpfc_ctl;
  126. /* Disable compression */
  127. dpfc_ctl = I915_READ(DPFC_CONTROL);
  128. if (dpfc_ctl & DPFC_CTL_EN) {
  129. dpfc_ctl &= ~DPFC_CTL_EN;
  130. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  131. DRM_DEBUG_KMS("disabled FBC\n");
  132. }
  133. }
  134. static bool g4x_fbc_enabled(struct drm_device *dev)
  135. {
  136. struct drm_i915_private *dev_priv = dev->dev_private;
  137. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  138. }
  139. static void sandybridge_blit_fbc_update(struct drm_device *dev)
  140. {
  141. struct drm_i915_private *dev_priv = dev->dev_private;
  142. u32 blt_ecoskpd;
  143. /* Make sure blitter notifies FBC of writes */
  144. gen6_gt_force_wake_get(dev_priv);
  145. blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
  146. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
  147. GEN6_BLITTER_LOCK_SHIFT;
  148. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  149. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
  150. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  151. blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
  152. GEN6_BLITTER_LOCK_SHIFT);
  153. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  154. POSTING_READ(GEN6_BLITTER_ECOSKPD);
  155. gen6_gt_force_wake_put(dev_priv);
  156. }
  157. static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  158. {
  159. struct drm_device *dev = crtc->dev;
  160. struct drm_i915_private *dev_priv = dev->dev_private;
  161. struct drm_framebuffer *fb = crtc->fb;
  162. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  163. struct drm_i915_gem_object *obj = intel_fb->obj;
  164. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  165. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  166. unsigned long stall_watermark = 200;
  167. u32 dpfc_ctl;
  168. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  169. dpfc_ctl &= DPFC_RESERVED;
  170. dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
  171. /* Set persistent mode for front-buffer rendering, ala X. */
  172. dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
  173. dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
  174. I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
  175. I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  176. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  177. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  178. I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
  179. I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
  180. /* enable it... */
  181. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
  182. if (IS_GEN6(dev)) {
  183. I915_WRITE(SNB_DPFC_CTL_SA,
  184. SNB_CPU_FENCE_ENABLE | obj->fence_reg);
  185. I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  186. sandybridge_blit_fbc_update(dev);
  187. }
  188. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  189. }
  190. static void ironlake_disable_fbc(struct drm_device *dev)
  191. {
  192. struct drm_i915_private *dev_priv = dev->dev_private;
  193. u32 dpfc_ctl;
  194. /* Disable compression */
  195. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  196. if (dpfc_ctl & DPFC_CTL_EN) {
  197. dpfc_ctl &= ~DPFC_CTL_EN;
  198. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  199. DRM_DEBUG_KMS("disabled FBC\n");
  200. }
  201. }
  202. static bool ironlake_fbc_enabled(struct drm_device *dev)
  203. {
  204. struct drm_i915_private *dev_priv = dev->dev_private;
  205. return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  206. }
  207. bool intel_fbc_enabled(struct drm_device *dev)
  208. {
  209. struct drm_i915_private *dev_priv = dev->dev_private;
  210. if (!dev_priv->display.fbc_enabled)
  211. return false;
  212. return dev_priv->display.fbc_enabled(dev);
  213. }
  214. static void intel_fbc_work_fn(struct work_struct *__work)
  215. {
  216. struct intel_fbc_work *work =
  217. container_of(to_delayed_work(__work),
  218. struct intel_fbc_work, work);
  219. struct drm_device *dev = work->crtc->dev;
  220. struct drm_i915_private *dev_priv = dev->dev_private;
  221. mutex_lock(&dev->struct_mutex);
  222. if (work == dev_priv->fbc_work) {
  223. /* Double check that we haven't switched fb without cancelling
  224. * the prior work.
  225. */
  226. if (work->crtc->fb == work->fb) {
  227. dev_priv->display.enable_fbc(work->crtc,
  228. work->interval);
  229. dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
  230. dev_priv->cfb_fb = work->crtc->fb->base.id;
  231. dev_priv->cfb_y = work->crtc->y;
  232. }
  233. dev_priv->fbc_work = NULL;
  234. }
  235. mutex_unlock(&dev->struct_mutex);
  236. kfree(work);
  237. }
  238. static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
  239. {
  240. if (dev_priv->fbc_work == NULL)
  241. return;
  242. DRM_DEBUG_KMS("cancelling pending FBC enable\n");
  243. /* Synchronisation is provided by struct_mutex and checking of
  244. * dev_priv->fbc_work, so we can perform the cancellation
  245. * entirely asynchronously.
  246. */
  247. if (cancel_delayed_work(&dev_priv->fbc_work->work))
  248. /* tasklet was killed before being run, clean up */
  249. kfree(dev_priv->fbc_work);
  250. /* Mark the work as no longer wanted so that if it does
  251. * wake-up (because the work was already running and waiting
  252. * for our mutex), it will discover that is no longer
  253. * necessary to run.
  254. */
  255. dev_priv->fbc_work = NULL;
  256. }
  257. void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  258. {
  259. struct intel_fbc_work *work;
  260. struct drm_device *dev = crtc->dev;
  261. struct drm_i915_private *dev_priv = dev->dev_private;
  262. if (!dev_priv->display.enable_fbc)
  263. return;
  264. intel_cancel_fbc_work(dev_priv);
  265. work = kzalloc(sizeof *work, GFP_KERNEL);
  266. if (work == NULL) {
  267. dev_priv->display.enable_fbc(crtc, interval);
  268. return;
  269. }
  270. work->crtc = crtc;
  271. work->fb = crtc->fb;
  272. work->interval = interval;
  273. INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
  274. dev_priv->fbc_work = work;
  275. DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
  276. /* Delay the actual enabling to let pageflipping cease and the
  277. * display to settle before starting the compression. Note that
  278. * this delay also serves a second purpose: it allows for a
  279. * vblank to pass after disabling the FBC before we attempt
  280. * to modify the control registers.
  281. *
  282. * A more complicated solution would involve tracking vblanks
  283. * following the termination of the page-flipping sequence
  284. * and indeed performing the enable as a co-routine and not
  285. * waiting synchronously upon the vblank.
  286. */
  287. schedule_delayed_work(&work->work, msecs_to_jiffies(50));
  288. }
  289. void intel_disable_fbc(struct drm_device *dev)
  290. {
  291. struct drm_i915_private *dev_priv = dev->dev_private;
  292. intel_cancel_fbc_work(dev_priv);
  293. if (!dev_priv->display.disable_fbc)
  294. return;
  295. dev_priv->display.disable_fbc(dev);
  296. dev_priv->cfb_plane = -1;
  297. }
  298. /**
  299. * intel_update_fbc - enable/disable FBC as needed
  300. * @dev: the drm_device
  301. *
  302. * Set up the framebuffer compression hardware at mode set time. We
  303. * enable it if possible:
  304. * - plane A only (on pre-965)
  305. * - no pixel mulitply/line duplication
  306. * - no alpha buffer discard
  307. * - no dual wide
  308. * - framebuffer <= 2048 in width, 1536 in height
  309. *
  310. * We can't assume that any compression will take place (worst case),
  311. * so the compressed buffer has to be the same size as the uncompressed
  312. * one. It also must reside (along with the line length buffer) in
  313. * stolen memory.
  314. *
  315. * We need to enable/disable FBC on a global basis.
  316. */
  317. void intel_update_fbc(struct drm_device *dev)
  318. {
  319. struct drm_i915_private *dev_priv = dev->dev_private;
  320. struct drm_crtc *crtc = NULL, *tmp_crtc;
  321. struct intel_crtc *intel_crtc;
  322. struct drm_framebuffer *fb;
  323. struct intel_framebuffer *intel_fb;
  324. struct drm_i915_gem_object *obj;
  325. int enable_fbc;
  326. DRM_DEBUG_KMS("\n");
  327. if (!i915_powersave)
  328. return;
  329. if (!I915_HAS_FBC(dev))
  330. return;
  331. /*
  332. * If FBC is already on, we just have to verify that we can
  333. * keep it that way...
  334. * Need to disable if:
  335. * - more than one pipe is active
  336. * - changing FBC params (stride, fence, mode)
  337. * - new fb is too large to fit in compressed buffer
  338. * - going to an unsupported config (interlace, pixel multiply, etc.)
  339. */
  340. list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
  341. if (tmp_crtc->enabled && tmp_crtc->fb) {
  342. if (crtc) {
  343. DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
  344. dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
  345. goto out_disable;
  346. }
  347. crtc = tmp_crtc;
  348. }
  349. }
  350. if (!crtc || crtc->fb == NULL) {
  351. DRM_DEBUG_KMS("no output, disabling\n");
  352. dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
  353. goto out_disable;
  354. }
  355. intel_crtc = to_intel_crtc(crtc);
  356. fb = crtc->fb;
  357. intel_fb = to_intel_framebuffer(fb);
  358. obj = intel_fb->obj;
  359. enable_fbc = i915_enable_fbc;
  360. if (enable_fbc < 0) {
  361. DRM_DEBUG_KMS("fbc set to per-chip default\n");
  362. enable_fbc = 1;
  363. if (INTEL_INFO(dev)->gen <= 6)
  364. enable_fbc = 0;
  365. }
  366. if (!enable_fbc) {
  367. DRM_DEBUG_KMS("fbc disabled per module param\n");
  368. dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
  369. goto out_disable;
  370. }
  371. if (intel_fb->obj->base.size > dev_priv->cfb_size) {
  372. DRM_DEBUG_KMS("framebuffer too large, disabling "
  373. "compression\n");
  374. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  375. goto out_disable;
  376. }
  377. if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
  378. (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
  379. DRM_DEBUG_KMS("mode incompatible with compression, "
  380. "disabling\n");
  381. dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  382. goto out_disable;
  383. }
  384. if ((crtc->mode.hdisplay > 2048) ||
  385. (crtc->mode.vdisplay > 1536)) {
  386. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  387. dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  388. goto out_disable;
  389. }
  390. if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
  391. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  392. dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  393. goto out_disable;
  394. }
  395. /* The use of a CPU fence is mandatory in order to detect writes
  396. * by the CPU to the scanout and trigger updates to the FBC.
  397. */
  398. if (obj->tiling_mode != I915_TILING_X ||
  399. obj->fence_reg == I915_FENCE_REG_NONE) {
  400. DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
  401. dev_priv->no_fbc_reason = FBC_NOT_TILED;
  402. goto out_disable;
  403. }
  404. /* If the kernel debugger is active, always disable compression */
  405. if (in_dbg_master())
  406. goto out_disable;
  407. /* If the scanout has not changed, don't modify the FBC settings.
  408. * Note that we make the fundamental assumption that the fb->obj
  409. * cannot be unpinned (and have its GTT offset and fence revoked)
  410. * without first being decoupled from the scanout and FBC disabled.
  411. */
  412. if (dev_priv->cfb_plane == intel_crtc->plane &&
  413. dev_priv->cfb_fb == fb->base.id &&
  414. dev_priv->cfb_y == crtc->y)
  415. return;
  416. if (intel_fbc_enabled(dev)) {
  417. /* We update FBC along two paths, after changing fb/crtc
  418. * configuration (modeswitching) and after page-flipping
  419. * finishes. For the latter, we know that not only did
  420. * we disable the FBC at the start of the page-flip
  421. * sequence, but also more than one vblank has passed.
  422. *
  423. * For the former case of modeswitching, it is possible
  424. * to switch between two FBC valid configurations
  425. * instantaneously so we do need to disable the FBC
  426. * before we can modify its control registers. We also
  427. * have to wait for the next vblank for that to take
  428. * effect. However, since we delay enabling FBC we can
  429. * assume that a vblank has passed since disabling and
  430. * that we can safely alter the registers in the deferred
  431. * callback.
  432. *
  433. * In the scenario that we go from a valid to invalid
  434. * and then back to valid FBC configuration we have
  435. * no strict enforcement that a vblank occurred since
  436. * disabling the FBC. However, along all current pipe
  437. * disabling paths we do need to wait for a vblank at
  438. * some point. And we wait before enabling FBC anyway.
  439. */
  440. DRM_DEBUG_KMS("disabling active FBC for update\n");
  441. intel_disable_fbc(dev);
  442. }
  443. intel_enable_fbc(crtc, 500);
  444. return;
  445. out_disable:
  446. /* Multiple disables should be harmless */
  447. if (intel_fbc_enabled(dev)) {
  448. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  449. intel_disable_fbc(dev);
  450. }
  451. }
  452. static void i915_pineview_get_mem_freq(struct drm_device *dev)
  453. {
  454. drm_i915_private_t *dev_priv = dev->dev_private;
  455. u32 tmp;
  456. tmp = I915_READ(CLKCFG);
  457. switch (tmp & CLKCFG_FSB_MASK) {
  458. case CLKCFG_FSB_533:
  459. dev_priv->fsb_freq = 533; /* 133*4 */
  460. break;
  461. case CLKCFG_FSB_800:
  462. dev_priv->fsb_freq = 800; /* 200*4 */
  463. break;
  464. case CLKCFG_FSB_667:
  465. dev_priv->fsb_freq = 667; /* 167*4 */
  466. break;
  467. case CLKCFG_FSB_400:
  468. dev_priv->fsb_freq = 400; /* 100*4 */
  469. break;
  470. }
  471. switch (tmp & CLKCFG_MEM_MASK) {
  472. case CLKCFG_MEM_533:
  473. dev_priv->mem_freq = 533;
  474. break;
  475. case CLKCFG_MEM_667:
  476. dev_priv->mem_freq = 667;
  477. break;
  478. case CLKCFG_MEM_800:
  479. dev_priv->mem_freq = 800;
  480. break;
  481. }
  482. /* detect pineview DDR3 setting */
  483. tmp = I915_READ(CSHRDDR3CTL);
  484. dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
  485. }
  486. static void i915_ironlake_get_mem_freq(struct drm_device *dev)
  487. {
  488. drm_i915_private_t *dev_priv = dev->dev_private;
  489. u16 ddrpll, csipll;
  490. ddrpll = I915_READ16(DDRMPLL1);
  491. csipll = I915_READ16(CSIPLL0);
  492. switch (ddrpll & 0xff) {
  493. case 0xc:
  494. dev_priv->mem_freq = 800;
  495. break;
  496. case 0x10:
  497. dev_priv->mem_freq = 1066;
  498. break;
  499. case 0x14:
  500. dev_priv->mem_freq = 1333;
  501. break;
  502. case 0x18:
  503. dev_priv->mem_freq = 1600;
  504. break;
  505. default:
  506. DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
  507. ddrpll & 0xff);
  508. dev_priv->mem_freq = 0;
  509. break;
  510. }
  511. dev_priv->r_t = dev_priv->mem_freq;
  512. switch (csipll & 0x3ff) {
  513. case 0x00c:
  514. dev_priv->fsb_freq = 3200;
  515. break;
  516. case 0x00e:
  517. dev_priv->fsb_freq = 3733;
  518. break;
  519. case 0x010:
  520. dev_priv->fsb_freq = 4266;
  521. break;
  522. case 0x012:
  523. dev_priv->fsb_freq = 4800;
  524. break;
  525. case 0x014:
  526. dev_priv->fsb_freq = 5333;
  527. break;
  528. case 0x016:
  529. dev_priv->fsb_freq = 5866;
  530. break;
  531. case 0x018:
  532. dev_priv->fsb_freq = 6400;
  533. break;
  534. default:
  535. DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
  536. csipll & 0x3ff);
  537. dev_priv->fsb_freq = 0;
  538. break;
  539. }
  540. if (dev_priv->fsb_freq == 3200) {
  541. dev_priv->c_m = 0;
  542. } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
  543. dev_priv->c_m = 1;
  544. } else {
  545. dev_priv->c_m = 2;
  546. }
  547. }
  548. static const struct cxsr_latency cxsr_latency_table[] = {
  549. {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  550. {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  551. {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  552. {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
  553. {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
  554. {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  555. {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  556. {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  557. {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
  558. {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
  559. {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  560. {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  561. {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  562. {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
  563. {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
  564. {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  565. {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  566. {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  567. {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
  568. {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
  569. {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  570. {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  571. {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  572. {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
  573. {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
  574. {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  575. {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  576. {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  577. {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
  578. {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
  579. };
  580. static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
  581. int is_ddr3,
  582. int fsb,
  583. int mem)
  584. {
  585. const struct cxsr_latency *latency;
  586. int i;
  587. if (fsb == 0 || mem == 0)
  588. return NULL;
  589. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  590. latency = &cxsr_latency_table[i];
  591. if (is_desktop == latency->is_desktop &&
  592. is_ddr3 == latency->is_ddr3 &&
  593. fsb == latency->fsb_freq && mem == latency->mem_freq)
  594. return latency;
  595. }
  596. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  597. return NULL;
  598. }
  599. static void pineview_disable_cxsr(struct drm_device *dev)
  600. {
  601. struct drm_i915_private *dev_priv = dev->dev_private;
  602. /* deactivate cxsr */
  603. I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
  604. }
  605. /*
  606. * Latency for FIFO fetches is dependent on several factors:
  607. * - memory configuration (speed, channels)
  608. * - chipset
  609. * - current MCH state
  610. * It can be fairly high in some situations, so here we assume a fairly
  611. * pessimal value. It's a tradeoff between extra memory fetches (if we
  612. * set this value too high, the FIFO will fetch frequently to stay full)
  613. * and power consumption (set it too low to save power and we might see
  614. * FIFO underruns and display "flicker").
  615. *
  616. * A value of 5us seems to be a good balance; safe for very low end
  617. * platforms but not overly aggressive on lower latency configs.
  618. */
  619. static const int latency_ns = 5000;
  620. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  621. {
  622. struct drm_i915_private *dev_priv = dev->dev_private;
  623. uint32_t dsparb = I915_READ(DSPARB);
  624. int size;
  625. size = dsparb & 0x7f;
  626. if (plane)
  627. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  628. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  629. plane ? "B" : "A", size);
  630. return size;
  631. }
  632. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  633. {
  634. struct drm_i915_private *dev_priv = dev->dev_private;
  635. uint32_t dsparb = I915_READ(DSPARB);
  636. int size;
  637. size = dsparb & 0x1ff;
  638. if (plane)
  639. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  640. size >>= 1; /* Convert to cachelines */
  641. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  642. plane ? "B" : "A", size);
  643. return size;
  644. }
  645. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  646. {
  647. struct drm_i915_private *dev_priv = dev->dev_private;
  648. uint32_t dsparb = I915_READ(DSPARB);
  649. int size;
  650. size = dsparb & 0x7f;
  651. size >>= 2; /* Convert to cachelines */
  652. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  653. plane ? "B" : "A",
  654. size);
  655. return size;
  656. }
  657. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  658. {
  659. struct drm_i915_private *dev_priv = dev->dev_private;
  660. uint32_t dsparb = I915_READ(DSPARB);
  661. int size;
  662. size = dsparb & 0x7f;
  663. size >>= 1; /* Convert to cachelines */
  664. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  665. plane ? "B" : "A", size);
  666. return size;
  667. }
  668. /* Pineview has different values for various configs */
  669. static const struct intel_watermark_params pineview_display_wm = {
  670. PINEVIEW_DISPLAY_FIFO,
  671. PINEVIEW_MAX_WM,
  672. PINEVIEW_DFT_WM,
  673. PINEVIEW_GUARD_WM,
  674. PINEVIEW_FIFO_LINE_SIZE
  675. };
  676. static const struct intel_watermark_params pineview_display_hplloff_wm = {
  677. PINEVIEW_DISPLAY_FIFO,
  678. PINEVIEW_MAX_WM,
  679. PINEVIEW_DFT_HPLLOFF_WM,
  680. PINEVIEW_GUARD_WM,
  681. PINEVIEW_FIFO_LINE_SIZE
  682. };
  683. static const struct intel_watermark_params pineview_cursor_wm = {
  684. PINEVIEW_CURSOR_FIFO,
  685. PINEVIEW_CURSOR_MAX_WM,
  686. PINEVIEW_CURSOR_DFT_WM,
  687. PINEVIEW_CURSOR_GUARD_WM,
  688. PINEVIEW_FIFO_LINE_SIZE,
  689. };
  690. static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
  691. PINEVIEW_CURSOR_FIFO,
  692. PINEVIEW_CURSOR_MAX_WM,
  693. PINEVIEW_CURSOR_DFT_WM,
  694. PINEVIEW_CURSOR_GUARD_WM,
  695. PINEVIEW_FIFO_LINE_SIZE
  696. };
  697. static const struct intel_watermark_params g4x_wm_info = {
  698. G4X_FIFO_SIZE,
  699. G4X_MAX_WM,
  700. G4X_MAX_WM,
  701. 2,
  702. G4X_FIFO_LINE_SIZE,
  703. };
  704. static const struct intel_watermark_params g4x_cursor_wm_info = {
  705. I965_CURSOR_FIFO,
  706. I965_CURSOR_MAX_WM,
  707. I965_CURSOR_DFT_WM,
  708. 2,
  709. G4X_FIFO_LINE_SIZE,
  710. };
  711. static const struct intel_watermark_params valleyview_wm_info = {
  712. VALLEYVIEW_FIFO_SIZE,
  713. VALLEYVIEW_MAX_WM,
  714. VALLEYVIEW_MAX_WM,
  715. 2,
  716. G4X_FIFO_LINE_SIZE,
  717. };
  718. static const struct intel_watermark_params valleyview_cursor_wm_info = {
  719. I965_CURSOR_FIFO,
  720. VALLEYVIEW_CURSOR_MAX_WM,
  721. I965_CURSOR_DFT_WM,
  722. 2,
  723. G4X_FIFO_LINE_SIZE,
  724. };
  725. static const struct intel_watermark_params i965_cursor_wm_info = {
  726. I965_CURSOR_FIFO,
  727. I965_CURSOR_MAX_WM,
  728. I965_CURSOR_DFT_WM,
  729. 2,
  730. I915_FIFO_LINE_SIZE,
  731. };
  732. static const struct intel_watermark_params i945_wm_info = {
  733. I945_FIFO_SIZE,
  734. I915_MAX_WM,
  735. 1,
  736. 2,
  737. I915_FIFO_LINE_SIZE
  738. };
  739. static const struct intel_watermark_params i915_wm_info = {
  740. I915_FIFO_SIZE,
  741. I915_MAX_WM,
  742. 1,
  743. 2,
  744. I915_FIFO_LINE_SIZE
  745. };
  746. static const struct intel_watermark_params i855_wm_info = {
  747. I855GM_FIFO_SIZE,
  748. I915_MAX_WM,
  749. 1,
  750. 2,
  751. I830_FIFO_LINE_SIZE
  752. };
  753. static const struct intel_watermark_params i830_wm_info = {
  754. I830_FIFO_SIZE,
  755. I915_MAX_WM,
  756. 1,
  757. 2,
  758. I830_FIFO_LINE_SIZE
  759. };
  760. static const struct intel_watermark_params ironlake_display_wm_info = {
  761. ILK_DISPLAY_FIFO,
  762. ILK_DISPLAY_MAXWM,
  763. ILK_DISPLAY_DFTWM,
  764. 2,
  765. ILK_FIFO_LINE_SIZE
  766. };
  767. static const struct intel_watermark_params ironlake_cursor_wm_info = {
  768. ILK_CURSOR_FIFO,
  769. ILK_CURSOR_MAXWM,
  770. ILK_CURSOR_DFTWM,
  771. 2,
  772. ILK_FIFO_LINE_SIZE
  773. };
  774. static const struct intel_watermark_params ironlake_display_srwm_info = {
  775. ILK_DISPLAY_SR_FIFO,
  776. ILK_DISPLAY_MAX_SRWM,
  777. ILK_DISPLAY_DFT_SRWM,
  778. 2,
  779. ILK_FIFO_LINE_SIZE
  780. };
  781. static const struct intel_watermark_params ironlake_cursor_srwm_info = {
  782. ILK_CURSOR_SR_FIFO,
  783. ILK_CURSOR_MAX_SRWM,
  784. ILK_CURSOR_DFT_SRWM,
  785. 2,
  786. ILK_FIFO_LINE_SIZE
  787. };
  788. static const struct intel_watermark_params sandybridge_display_wm_info = {
  789. SNB_DISPLAY_FIFO,
  790. SNB_DISPLAY_MAXWM,
  791. SNB_DISPLAY_DFTWM,
  792. 2,
  793. SNB_FIFO_LINE_SIZE
  794. };
  795. static const struct intel_watermark_params sandybridge_cursor_wm_info = {
  796. SNB_CURSOR_FIFO,
  797. SNB_CURSOR_MAXWM,
  798. SNB_CURSOR_DFTWM,
  799. 2,
  800. SNB_FIFO_LINE_SIZE
  801. };
  802. static const struct intel_watermark_params sandybridge_display_srwm_info = {
  803. SNB_DISPLAY_SR_FIFO,
  804. SNB_DISPLAY_MAX_SRWM,
  805. SNB_DISPLAY_DFT_SRWM,
  806. 2,
  807. SNB_FIFO_LINE_SIZE
  808. };
  809. static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
  810. SNB_CURSOR_SR_FIFO,
  811. SNB_CURSOR_MAX_SRWM,
  812. SNB_CURSOR_DFT_SRWM,
  813. 2,
  814. SNB_FIFO_LINE_SIZE
  815. };
  816. /**
  817. * intel_calculate_wm - calculate watermark level
  818. * @clock_in_khz: pixel clock
  819. * @wm: chip FIFO params
  820. * @pixel_size: display pixel size
  821. * @latency_ns: memory latency for the platform
  822. *
  823. * Calculate the watermark level (the level at which the display plane will
  824. * start fetching from memory again). Each chip has a different display
  825. * FIFO size and allocation, so the caller needs to figure that out and pass
  826. * in the correct intel_watermark_params structure.
  827. *
  828. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  829. * on the pixel size. When it reaches the watermark level, it'll start
  830. * fetching FIFO line sized based chunks from memory until the FIFO fills
  831. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  832. * will occur, and a display engine hang could result.
  833. */
  834. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  835. const struct intel_watermark_params *wm,
  836. int fifo_size,
  837. int pixel_size,
  838. unsigned long latency_ns)
  839. {
  840. long entries_required, wm_size;
  841. /*
  842. * Note: we need to make sure we don't overflow for various clock &
  843. * latency values.
  844. * clocks go from a few thousand to several hundred thousand.
  845. * latency is usually a few thousand
  846. */
  847. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  848. 1000;
  849. entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  850. DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
  851. wm_size = fifo_size - (entries_required + wm->guard_size);
  852. DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
  853. /* Don't promote wm_size to unsigned... */
  854. if (wm_size > (long)wm->max_wm)
  855. wm_size = wm->max_wm;
  856. if (wm_size <= 0)
  857. wm_size = wm->default_wm;
  858. return wm_size;
  859. }
  860. static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
  861. {
  862. struct drm_crtc *crtc, *enabled = NULL;
  863. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  864. if (crtc->enabled && crtc->fb) {
  865. if (enabled)
  866. return NULL;
  867. enabled = crtc;
  868. }
  869. }
  870. return enabled;
  871. }
  872. static void pineview_update_wm(struct drm_device *dev)
  873. {
  874. struct drm_i915_private *dev_priv = dev->dev_private;
  875. struct drm_crtc *crtc;
  876. const struct cxsr_latency *latency;
  877. u32 reg;
  878. unsigned long wm;
  879. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  880. dev_priv->fsb_freq, dev_priv->mem_freq);
  881. if (!latency) {
  882. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  883. pineview_disable_cxsr(dev);
  884. return;
  885. }
  886. crtc = single_enabled_crtc(dev);
  887. if (crtc) {
  888. int clock = crtc->mode.clock;
  889. int pixel_size = crtc->fb->bits_per_pixel / 8;
  890. /* Display SR */
  891. wm = intel_calculate_wm(clock, &pineview_display_wm,
  892. pineview_display_wm.fifo_size,
  893. pixel_size, latency->display_sr);
  894. reg = I915_READ(DSPFW1);
  895. reg &= ~DSPFW_SR_MASK;
  896. reg |= wm << DSPFW_SR_SHIFT;
  897. I915_WRITE(DSPFW1, reg);
  898. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  899. /* cursor SR */
  900. wm = intel_calculate_wm(clock, &pineview_cursor_wm,
  901. pineview_display_wm.fifo_size,
  902. pixel_size, latency->cursor_sr);
  903. reg = I915_READ(DSPFW3);
  904. reg &= ~DSPFW_CURSOR_SR_MASK;
  905. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  906. I915_WRITE(DSPFW3, reg);
  907. /* Display HPLL off SR */
  908. wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
  909. pineview_display_hplloff_wm.fifo_size,
  910. pixel_size, latency->display_hpll_disable);
  911. reg = I915_READ(DSPFW3);
  912. reg &= ~DSPFW_HPLL_SR_MASK;
  913. reg |= wm & DSPFW_HPLL_SR_MASK;
  914. I915_WRITE(DSPFW3, reg);
  915. /* cursor HPLL off SR */
  916. wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
  917. pineview_display_hplloff_wm.fifo_size,
  918. pixel_size, latency->cursor_hpll_disable);
  919. reg = I915_READ(DSPFW3);
  920. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  921. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  922. I915_WRITE(DSPFW3, reg);
  923. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  924. /* activate cxsr */
  925. I915_WRITE(DSPFW3,
  926. I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
  927. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  928. } else {
  929. pineview_disable_cxsr(dev);
  930. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  931. }
  932. }
  933. static bool g4x_compute_wm0(struct drm_device *dev,
  934. int plane,
  935. const struct intel_watermark_params *display,
  936. int display_latency_ns,
  937. const struct intel_watermark_params *cursor,
  938. int cursor_latency_ns,
  939. int *plane_wm,
  940. int *cursor_wm)
  941. {
  942. struct drm_crtc *crtc;
  943. int htotal, hdisplay, clock, pixel_size;
  944. int line_time_us, line_count;
  945. int entries, tlb_miss;
  946. crtc = intel_get_crtc_for_plane(dev, plane);
  947. if (crtc->fb == NULL || !crtc->enabled) {
  948. *cursor_wm = cursor->guard_size;
  949. *plane_wm = display->guard_size;
  950. return false;
  951. }
  952. htotal = crtc->mode.htotal;
  953. hdisplay = crtc->mode.hdisplay;
  954. clock = crtc->mode.clock;
  955. pixel_size = crtc->fb->bits_per_pixel / 8;
  956. /* Use the small buffer method to calculate plane watermark */
  957. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  958. tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
  959. if (tlb_miss > 0)
  960. entries += tlb_miss;
  961. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  962. *plane_wm = entries + display->guard_size;
  963. if (*plane_wm > (int)display->max_wm)
  964. *plane_wm = display->max_wm;
  965. /* Use the large buffer method to calculate cursor watermark */
  966. line_time_us = ((htotal * 1000) / clock);
  967. line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
  968. entries = line_count * 64 * pixel_size;
  969. tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
  970. if (tlb_miss > 0)
  971. entries += tlb_miss;
  972. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  973. *cursor_wm = entries + cursor->guard_size;
  974. if (*cursor_wm > (int)cursor->max_wm)
  975. *cursor_wm = (int)cursor->max_wm;
  976. return true;
  977. }
  978. /*
  979. * Check the wm result.
  980. *
  981. * If any calculated watermark values is larger than the maximum value that
  982. * can be programmed into the associated watermark register, that watermark
  983. * must be disabled.
  984. */
  985. static bool g4x_check_srwm(struct drm_device *dev,
  986. int display_wm, int cursor_wm,
  987. const struct intel_watermark_params *display,
  988. const struct intel_watermark_params *cursor)
  989. {
  990. DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
  991. display_wm, cursor_wm);
  992. if (display_wm > display->max_wm) {
  993. DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
  994. display_wm, display->max_wm);
  995. return false;
  996. }
  997. if (cursor_wm > cursor->max_wm) {
  998. DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
  999. cursor_wm, cursor->max_wm);
  1000. return false;
  1001. }
  1002. if (!(display_wm || cursor_wm)) {
  1003. DRM_DEBUG_KMS("SR latency is 0, disabling\n");
  1004. return false;
  1005. }
  1006. return true;
  1007. }
  1008. static bool g4x_compute_srwm(struct drm_device *dev,
  1009. int plane,
  1010. int latency_ns,
  1011. const struct intel_watermark_params *display,
  1012. const struct intel_watermark_params *cursor,
  1013. int *display_wm, int *cursor_wm)
  1014. {
  1015. struct drm_crtc *crtc;
  1016. int hdisplay, htotal, pixel_size, clock;
  1017. unsigned long line_time_us;
  1018. int line_count, line_size;
  1019. int small, large;
  1020. int entries;
  1021. if (!latency_ns) {
  1022. *display_wm = *cursor_wm = 0;
  1023. return false;
  1024. }
  1025. crtc = intel_get_crtc_for_plane(dev, plane);
  1026. hdisplay = crtc->mode.hdisplay;
  1027. htotal = crtc->mode.htotal;
  1028. clock = crtc->mode.clock;
  1029. pixel_size = crtc->fb->bits_per_pixel / 8;
  1030. line_time_us = (htotal * 1000) / clock;
  1031. line_count = (latency_ns / line_time_us + 1000) / 1000;
  1032. line_size = hdisplay * pixel_size;
  1033. /* Use the minimum of the small and large buffer method for primary */
  1034. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1035. large = line_count * line_size;
  1036. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1037. *display_wm = entries + display->guard_size;
  1038. /* calculate the self-refresh watermark for display cursor */
  1039. entries = line_count * pixel_size * 64;
  1040. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1041. *cursor_wm = entries + cursor->guard_size;
  1042. return g4x_check_srwm(dev,
  1043. *display_wm, *cursor_wm,
  1044. display, cursor);
  1045. }
  1046. static bool vlv_compute_drain_latency(struct drm_device *dev,
  1047. int plane,
  1048. int *plane_prec_mult,
  1049. int *plane_dl,
  1050. int *cursor_prec_mult,
  1051. int *cursor_dl)
  1052. {
  1053. struct drm_crtc *crtc;
  1054. int clock, pixel_size;
  1055. int entries;
  1056. crtc = intel_get_crtc_for_plane(dev, plane);
  1057. if (crtc->fb == NULL || !crtc->enabled)
  1058. return false;
  1059. clock = crtc->mode.clock; /* VESA DOT Clock */
  1060. pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
  1061. entries = (clock / 1000) * pixel_size;
  1062. *plane_prec_mult = (entries > 256) ?
  1063. DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
  1064. *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
  1065. pixel_size);
  1066. entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
  1067. *cursor_prec_mult = (entries > 256) ?
  1068. DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
  1069. *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
  1070. return true;
  1071. }
  1072. /*
  1073. * Update drain latency registers of memory arbiter
  1074. *
  1075. * Valleyview SoC has a new memory arbiter and needs drain latency registers
  1076. * to be programmed. Each plane has a drain latency multiplier and a drain
  1077. * latency value.
  1078. */
  1079. static void vlv_update_drain_latency(struct drm_device *dev)
  1080. {
  1081. struct drm_i915_private *dev_priv = dev->dev_private;
  1082. int planea_prec, planea_dl, planeb_prec, planeb_dl;
  1083. int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
  1084. int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
  1085. either 16 or 32 */
  1086. /* For plane A, Cursor A */
  1087. if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
  1088. &cursor_prec_mult, &cursora_dl)) {
  1089. cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1090. DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
  1091. planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1092. DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
  1093. I915_WRITE(VLV_DDL1, cursora_prec |
  1094. (cursora_dl << DDL_CURSORA_SHIFT) |
  1095. planea_prec | planea_dl);
  1096. }
  1097. /* For plane B, Cursor B */
  1098. if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
  1099. &cursor_prec_mult, &cursorb_dl)) {
  1100. cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1101. DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
  1102. planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1103. DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
  1104. I915_WRITE(VLV_DDL2, cursorb_prec |
  1105. (cursorb_dl << DDL_CURSORB_SHIFT) |
  1106. planeb_prec | planeb_dl);
  1107. }
  1108. }
  1109. #define single_plane_enabled(mask) is_power_of_2(mask)
  1110. static void valleyview_update_wm(struct drm_device *dev)
  1111. {
  1112. static const int sr_latency_ns = 12000;
  1113. struct drm_i915_private *dev_priv = dev->dev_private;
  1114. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  1115. int plane_sr, cursor_sr;
  1116. unsigned int enabled = 0;
  1117. vlv_update_drain_latency(dev);
  1118. if (g4x_compute_wm0(dev, 0,
  1119. &valleyview_wm_info, latency_ns,
  1120. &valleyview_cursor_wm_info, latency_ns,
  1121. &planea_wm, &cursora_wm))
  1122. enabled |= 1;
  1123. if (g4x_compute_wm0(dev, 1,
  1124. &valleyview_wm_info, latency_ns,
  1125. &valleyview_cursor_wm_info, latency_ns,
  1126. &planeb_wm, &cursorb_wm))
  1127. enabled |= 2;
  1128. plane_sr = cursor_sr = 0;
  1129. if (single_plane_enabled(enabled) &&
  1130. g4x_compute_srwm(dev, ffs(enabled) - 1,
  1131. sr_latency_ns,
  1132. &valleyview_wm_info,
  1133. &valleyview_cursor_wm_info,
  1134. &plane_sr, &cursor_sr))
  1135. I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
  1136. else
  1137. I915_WRITE(FW_BLC_SELF_VLV,
  1138. I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
  1139. DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  1140. planea_wm, cursora_wm,
  1141. planeb_wm, cursorb_wm,
  1142. plane_sr, cursor_sr);
  1143. I915_WRITE(DSPFW1,
  1144. (plane_sr << DSPFW_SR_SHIFT) |
  1145. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  1146. (planeb_wm << DSPFW_PLANEB_SHIFT) |
  1147. planea_wm);
  1148. I915_WRITE(DSPFW2,
  1149. (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  1150. (cursora_wm << DSPFW_CURSORA_SHIFT));
  1151. I915_WRITE(DSPFW3,
  1152. (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
  1153. }
  1154. static void g4x_update_wm(struct drm_device *dev)
  1155. {
  1156. static const int sr_latency_ns = 12000;
  1157. struct drm_i915_private *dev_priv = dev->dev_private;
  1158. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  1159. int plane_sr, cursor_sr;
  1160. unsigned int enabled = 0;
  1161. if (g4x_compute_wm0(dev, 0,
  1162. &g4x_wm_info, latency_ns,
  1163. &g4x_cursor_wm_info, latency_ns,
  1164. &planea_wm, &cursora_wm))
  1165. enabled |= 1;
  1166. if (g4x_compute_wm0(dev, 1,
  1167. &g4x_wm_info, latency_ns,
  1168. &g4x_cursor_wm_info, latency_ns,
  1169. &planeb_wm, &cursorb_wm))
  1170. enabled |= 2;
  1171. plane_sr = cursor_sr = 0;
  1172. if (single_plane_enabled(enabled) &&
  1173. g4x_compute_srwm(dev, ffs(enabled) - 1,
  1174. sr_latency_ns,
  1175. &g4x_wm_info,
  1176. &g4x_cursor_wm_info,
  1177. &plane_sr, &cursor_sr))
  1178. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  1179. else
  1180. I915_WRITE(FW_BLC_SELF,
  1181. I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
  1182. DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  1183. planea_wm, cursora_wm,
  1184. planeb_wm, cursorb_wm,
  1185. plane_sr, cursor_sr);
  1186. I915_WRITE(DSPFW1,
  1187. (plane_sr << DSPFW_SR_SHIFT) |
  1188. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  1189. (planeb_wm << DSPFW_PLANEB_SHIFT) |
  1190. planea_wm);
  1191. I915_WRITE(DSPFW2,
  1192. (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  1193. (cursora_wm << DSPFW_CURSORA_SHIFT));
  1194. /* HPLL off in SR has some issues on G4x... disable it */
  1195. I915_WRITE(DSPFW3,
  1196. (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  1197. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1198. }
  1199. static void i965_update_wm(struct drm_device *dev)
  1200. {
  1201. struct drm_i915_private *dev_priv = dev->dev_private;
  1202. struct drm_crtc *crtc;
  1203. int srwm = 1;
  1204. int cursor_sr = 16;
  1205. /* Calc sr entries for one plane configs */
  1206. crtc = single_enabled_crtc(dev);
  1207. if (crtc) {
  1208. /* self-refresh has much higher latency */
  1209. static const int sr_latency_ns = 12000;
  1210. int clock = crtc->mode.clock;
  1211. int htotal = crtc->mode.htotal;
  1212. int hdisplay = crtc->mode.hdisplay;
  1213. int pixel_size = crtc->fb->bits_per_pixel / 8;
  1214. unsigned long line_time_us;
  1215. int entries;
  1216. line_time_us = ((htotal * 1000) / clock);
  1217. /* Use ns/us then divide to preserve precision */
  1218. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1219. pixel_size * hdisplay;
  1220. entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
  1221. srwm = I965_FIFO_SIZE - entries;
  1222. if (srwm < 0)
  1223. srwm = 1;
  1224. srwm &= 0x1ff;
  1225. DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
  1226. entries, srwm);
  1227. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1228. pixel_size * 64;
  1229. entries = DIV_ROUND_UP(entries,
  1230. i965_cursor_wm_info.cacheline_size);
  1231. cursor_sr = i965_cursor_wm_info.fifo_size -
  1232. (entries + i965_cursor_wm_info.guard_size);
  1233. if (cursor_sr > i965_cursor_wm_info.max_wm)
  1234. cursor_sr = i965_cursor_wm_info.max_wm;
  1235. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  1236. "cursor %d\n", srwm, cursor_sr);
  1237. if (IS_CRESTLINE(dev))
  1238. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  1239. } else {
  1240. /* Turn off self refresh if both pipes are enabled */
  1241. if (IS_CRESTLINE(dev))
  1242. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  1243. & ~FW_BLC_SELF_EN);
  1244. }
  1245. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  1246. srwm);
  1247. /* 965 has limitations... */
  1248. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
  1249. (8 << 16) | (8 << 8) | (8 << 0));
  1250. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  1251. /* update cursor SR watermark */
  1252. I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1253. }
  1254. static void i9xx_update_wm(struct drm_device *dev)
  1255. {
  1256. struct drm_i915_private *dev_priv = dev->dev_private;
  1257. const struct intel_watermark_params *wm_info;
  1258. uint32_t fwater_lo;
  1259. uint32_t fwater_hi;
  1260. int cwm, srwm = 1;
  1261. int fifo_size;
  1262. int planea_wm, planeb_wm;
  1263. struct drm_crtc *crtc, *enabled = NULL;
  1264. if (IS_I945GM(dev))
  1265. wm_info = &i945_wm_info;
  1266. else if (!IS_GEN2(dev))
  1267. wm_info = &i915_wm_info;
  1268. else
  1269. wm_info = &i855_wm_info;
  1270. fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  1271. crtc = intel_get_crtc_for_plane(dev, 0);
  1272. if (crtc->enabled && crtc->fb) {
  1273. planea_wm = intel_calculate_wm(crtc->mode.clock,
  1274. wm_info, fifo_size,
  1275. crtc->fb->bits_per_pixel / 8,
  1276. latency_ns);
  1277. enabled = crtc;
  1278. } else
  1279. planea_wm = fifo_size - wm_info->guard_size;
  1280. fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  1281. crtc = intel_get_crtc_for_plane(dev, 1);
  1282. if (crtc->enabled && crtc->fb) {
  1283. planeb_wm = intel_calculate_wm(crtc->mode.clock,
  1284. wm_info, fifo_size,
  1285. crtc->fb->bits_per_pixel / 8,
  1286. latency_ns);
  1287. if (enabled == NULL)
  1288. enabled = crtc;
  1289. else
  1290. enabled = NULL;
  1291. } else
  1292. planeb_wm = fifo_size - wm_info->guard_size;
  1293. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  1294. /*
  1295. * Overlay gets an aggressive default since video jitter is bad.
  1296. */
  1297. cwm = 2;
  1298. /* Play safe and disable self-refresh before adjusting watermarks. */
  1299. if (IS_I945G(dev) || IS_I945GM(dev))
  1300. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
  1301. else if (IS_I915GM(dev))
  1302. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  1303. /* Calc sr entries for one plane configs */
  1304. if (HAS_FW_BLC(dev) && enabled) {
  1305. /* self-refresh has much higher latency */
  1306. static const int sr_latency_ns = 6000;
  1307. int clock = enabled->mode.clock;
  1308. int htotal = enabled->mode.htotal;
  1309. int hdisplay = enabled->mode.hdisplay;
  1310. int pixel_size = enabled->fb->bits_per_pixel / 8;
  1311. unsigned long line_time_us;
  1312. int entries;
  1313. line_time_us = (htotal * 1000) / clock;
  1314. /* Use ns/us then divide to preserve precision */
  1315. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1316. pixel_size * hdisplay;
  1317. entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
  1318. DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
  1319. srwm = wm_info->fifo_size - entries;
  1320. if (srwm < 0)
  1321. srwm = 1;
  1322. if (IS_I945G(dev) || IS_I945GM(dev))
  1323. I915_WRITE(FW_BLC_SELF,
  1324. FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  1325. else if (IS_I915GM(dev))
  1326. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  1327. }
  1328. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  1329. planea_wm, planeb_wm, cwm, srwm);
  1330. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  1331. fwater_hi = (cwm & 0x1f);
  1332. /* Set request length to 8 cachelines per fetch */
  1333. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  1334. fwater_hi = fwater_hi | (1 << 8);
  1335. I915_WRITE(FW_BLC, fwater_lo);
  1336. I915_WRITE(FW_BLC2, fwater_hi);
  1337. if (HAS_FW_BLC(dev)) {
  1338. if (enabled) {
  1339. if (IS_I945G(dev) || IS_I945GM(dev))
  1340. I915_WRITE(FW_BLC_SELF,
  1341. FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  1342. else if (IS_I915GM(dev))
  1343. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  1344. DRM_DEBUG_KMS("memory self refresh enabled\n");
  1345. } else
  1346. DRM_DEBUG_KMS("memory self refresh disabled\n");
  1347. }
  1348. }
  1349. static void i830_update_wm(struct drm_device *dev)
  1350. {
  1351. struct drm_i915_private *dev_priv = dev->dev_private;
  1352. struct drm_crtc *crtc;
  1353. uint32_t fwater_lo;
  1354. int planea_wm;
  1355. crtc = single_enabled_crtc(dev);
  1356. if (crtc == NULL)
  1357. return;
  1358. planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
  1359. dev_priv->display.get_fifo_size(dev, 0),
  1360. crtc->fb->bits_per_pixel / 8,
  1361. latency_ns);
  1362. fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  1363. fwater_lo |= (3<<8) | planea_wm;
  1364. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  1365. I915_WRITE(FW_BLC, fwater_lo);
  1366. }
  1367. #define ILK_LP0_PLANE_LATENCY 700
  1368. #define ILK_LP0_CURSOR_LATENCY 1300
  1369. /*
  1370. * Check the wm result.
  1371. *
  1372. * If any calculated watermark values is larger than the maximum value that
  1373. * can be programmed into the associated watermark register, that watermark
  1374. * must be disabled.
  1375. */
  1376. static bool ironlake_check_srwm(struct drm_device *dev, int level,
  1377. int fbc_wm, int display_wm, int cursor_wm,
  1378. const struct intel_watermark_params *display,
  1379. const struct intel_watermark_params *cursor)
  1380. {
  1381. struct drm_i915_private *dev_priv = dev->dev_private;
  1382. DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
  1383. " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
  1384. if (fbc_wm > SNB_FBC_MAX_SRWM) {
  1385. DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
  1386. fbc_wm, SNB_FBC_MAX_SRWM, level);
  1387. /* fbc has it's own way to disable FBC WM */
  1388. I915_WRITE(DISP_ARB_CTL,
  1389. I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
  1390. return false;
  1391. }
  1392. if (display_wm > display->max_wm) {
  1393. DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
  1394. display_wm, SNB_DISPLAY_MAX_SRWM, level);
  1395. return false;
  1396. }
  1397. if (cursor_wm > cursor->max_wm) {
  1398. DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
  1399. cursor_wm, SNB_CURSOR_MAX_SRWM, level);
  1400. return false;
  1401. }
  1402. if (!(fbc_wm || display_wm || cursor_wm)) {
  1403. DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
  1404. return false;
  1405. }
  1406. return true;
  1407. }
  1408. /*
  1409. * Compute watermark values of WM[1-3],
  1410. */
  1411. static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
  1412. int latency_ns,
  1413. const struct intel_watermark_params *display,
  1414. const struct intel_watermark_params *cursor,
  1415. int *fbc_wm, int *display_wm, int *cursor_wm)
  1416. {
  1417. struct drm_crtc *crtc;
  1418. unsigned long line_time_us;
  1419. int hdisplay, htotal, pixel_size, clock;
  1420. int line_count, line_size;
  1421. int small, large;
  1422. int entries;
  1423. if (!latency_ns) {
  1424. *fbc_wm = *display_wm = *cursor_wm = 0;
  1425. return false;
  1426. }
  1427. crtc = intel_get_crtc_for_plane(dev, plane);
  1428. hdisplay = crtc->mode.hdisplay;
  1429. htotal = crtc->mode.htotal;
  1430. clock = crtc->mode.clock;
  1431. pixel_size = crtc->fb->bits_per_pixel / 8;
  1432. line_time_us = (htotal * 1000) / clock;
  1433. line_count = (latency_ns / line_time_us + 1000) / 1000;
  1434. line_size = hdisplay * pixel_size;
  1435. /* Use the minimum of the small and large buffer method for primary */
  1436. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1437. large = line_count * line_size;
  1438. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1439. *display_wm = entries + display->guard_size;
  1440. /*
  1441. * Spec says:
  1442. * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
  1443. */
  1444. *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
  1445. /* calculate the self-refresh watermark for display cursor */
  1446. entries = line_count * pixel_size * 64;
  1447. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1448. *cursor_wm = entries + cursor->guard_size;
  1449. return ironlake_check_srwm(dev, level,
  1450. *fbc_wm, *display_wm, *cursor_wm,
  1451. display, cursor);
  1452. }
  1453. static void ironlake_update_wm(struct drm_device *dev)
  1454. {
  1455. struct drm_i915_private *dev_priv = dev->dev_private;
  1456. int fbc_wm, plane_wm, cursor_wm;
  1457. unsigned int enabled;
  1458. enabled = 0;
  1459. if (g4x_compute_wm0(dev, 0,
  1460. &ironlake_display_wm_info,
  1461. ILK_LP0_PLANE_LATENCY,
  1462. &ironlake_cursor_wm_info,
  1463. ILK_LP0_CURSOR_LATENCY,
  1464. &plane_wm, &cursor_wm)) {
  1465. I915_WRITE(WM0_PIPEA_ILK,
  1466. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  1467. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1468. " plane %d, " "cursor: %d\n",
  1469. plane_wm, cursor_wm);
  1470. enabled |= 1;
  1471. }
  1472. if (g4x_compute_wm0(dev, 1,
  1473. &ironlake_display_wm_info,
  1474. ILK_LP0_PLANE_LATENCY,
  1475. &ironlake_cursor_wm_info,
  1476. ILK_LP0_CURSOR_LATENCY,
  1477. &plane_wm, &cursor_wm)) {
  1478. I915_WRITE(WM0_PIPEB_ILK,
  1479. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  1480. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1481. " plane %d, cursor: %d\n",
  1482. plane_wm, cursor_wm);
  1483. enabled |= 2;
  1484. }
  1485. /*
  1486. * Calculate and update the self-refresh watermark only when one
  1487. * display plane is used.
  1488. */
  1489. I915_WRITE(WM3_LP_ILK, 0);
  1490. I915_WRITE(WM2_LP_ILK, 0);
  1491. I915_WRITE(WM1_LP_ILK, 0);
  1492. if (!single_plane_enabled(enabled))
  1493. return;
  1494. enabled = ffs(enabled) - 1;
  1495. /* WM1 */
  1496. if (!ironlake_compute_srwm(dev, 1, enabled,
  1497. ILK_READ_WM1_LATENCY() * 500,
  1498. &ironlake_display_srwm_info,
  1499. &ironlake_cursor_srwm_info,
  1500. &fbc_wm, &plane_wm, &cursor_wm))
  1501. return;
  1502. I915_WRITE(WM1_LP_ILK,
  1503. WM1_LP_SR_EN |
  1504. (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1505. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1506. (plane_wm << WM1_LP_SR_SHIFT) |
  1507. cursor_wm);
  1508. /* WM2 */
  1509. if (!ironlake_compute_srwm(dev, 2, enabled,
  1510. ILK_READ_WM2_LATENCY() * 500,
  1511. &ironlake_display_srwm_info,
  1512. &ironlake_cursor_srwm_info,
  1513. &fbc_wm, &plane_wm, &cursor_wm))
  1514. return;
  1515. I915_WRITE(WM2_LP_ILK,
  1516. WM2_LP_EN |
  1517. (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1518. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1519. (plane_wm << WM1_LP_SR_SHIFT) |
  1520. cursor_wm);
  1521. /*
  1522. * WM3 is unsupported on ILK, probably because we don't have latency
  1523. * data for that power state
  1524. */
  1525. }
  1526. static void sandybridge_update_wm(struct drm_device *dev)
  1527. {
  1528. struct drm_i915_private *dev_priv = dev->dev_private;
  1529. int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
  1530. u32 val;
  1531. int fbc_wm, plane_wm, cursor_wm;
  1532. unsigned int enabled;
  1533. enabled = 0;
  1534. if (g4x_compute_wm0(dev, 0,
  1535. &sandybridge_display_wm_info, latency,
  1536. &sandybridge_cursor_wm_info, latency,
  1537. &plane_wm, &cursor_wm)) {
  1538. val = I915_READ(WM0_PIPEA_ILK);
  1539. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1540. I915_WRITE(WM0_PIPEA_ILK, val |
  1541. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1542. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1543. " plane %d, " "cursor: %d\n",
  1544. plane_wm, cursor_wm);
  1545. enabled |= 1;
  1546. }
  1547. if (g4x_compute_wm0(dev, 1,
  1548. &sandybridge_display_wm_info, latency,
  1549. &sandybridge_cursor_wm_info, latency,
  1550. &plane_wm, &cursor_wm)) {
  1551. val = I915_READ(WM0_PIPEB_ILK);
  1552. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1553. I915_WRITE(WM0_PIPEB_ILK, val |
  1554. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1555. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1556. " plane %d, cursor: %d\n",
  1557. plane_wm, cursor_wm);
  1558. enabled |= 2;
  1559. }
  1560. if ((dev_priv->num_pipe == 3) &&
  1561. g4x_compute_wm0(dev, 2,
  1562. &sandybridge_display_wm_info, latency,
  1563. &sandybridge_cursor_wm_info, latency,
  1564. &plane_wm, &cursor_wm)) {
  1565. val = I915_READ(WM0_PIPEC_IVB);
  1566. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1567. I915_WRITE(WM0_PIPEC_IVB, val |
  1568. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1569. DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
  1570. " plane %d, cursor: %d\n",
  1571. plane_wm, cursor_wm);
  1572. enabled |= 3;
  1573. }
  1574. /*
  1575. * Calculate and update the self-refresh watermark only when one
  1576. * display plane is used.
  1577. *
  1578. * SNB support 3 levels of watermark.
  1579. *
  1580. * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
  1581. * and disabled in the descending order
  1582. *
  1583. */
  1584. I915_WRITE(WM3_LP_ILK, 0);
  1585. I915_WRITE(WM2_LP_ILK, 0);
  1586. I915_WRITE(WM1_LP_ILK, 0);
  1587. if (!single_plane_enabled(enabled) ||
  1588. dev_priv->sprite_scaling_enabled)
  1589. return;
  1590. enabled = ffs(enabled) - 1;
  1591. /* WM1 */
  1592. if (!ironlake_compute_srwm(dev, 1, enabled,
  1593. SNB_READ_WM1_LATENCY() * 500,
  1594. &sandybridge_display_srwm_info,
  1595. &sandybridge_cursor_srwm_info,
  1596. &fbc_wm, &plane_wm, &cursor_wm))
  1597. return;
  1598. I915_WRITE(WM1_LP_ILK,
  1599. WM1_LP_SR_EN |
  1600. (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1601. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1602. (plane_wm << WM1_LP_SR_SHIFT) |
  1603. cursor_wm);
  1604. /* WM2 */
  1605. if (!ironlake_compute_srwm(dev, 2, enabled,
  1606. SNB_READ_WM2_LATENCY() * 500,
  1607. &sandybridge_display_srwm_info,
  1608. &sandybridge_cursor_srwm_info,
  1609. &fbc_wm, &plane_wm, &cursor_wm))
  1610. return;
  1611. I915_WRITE(WM2_LP_ILK,
  1612. WM2_LP_EN |
  1613. (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1614. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1615. (plane_wm << WM1_LP_SR_SHIFT) |
  1616. cursor_wm);
  1617. /* WM3 */
  1618. if (!ironlake_compute_srwm(dev, 3, enabled,
  1619. SNB_READ_WM3_LATENCY() * 500,
  1620. &sandybridge_display_srwm_info,
  1621. &sandybridge_cursor_srwm_info,
  1622. &fbc_wm, &plane_wm, &cursor_wm))
  1623. return;
  1624. I915_WRITE(WM3_LP_ILK,
  1625. WM3_LP_EN |
  1626. (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1627. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1628. (plane_wm << WM1_LP_SR_SHIFT) |
  1629. cursor_wm);
  1630. }
  1631. static bool
  1632. sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
  1633. uint32_t sprite_width, int pixel_size,
  1634. const struct intel_watermark_params *display,
  1635. int display_latency_ns, int *sprite_wm)
  1636. {
  1637. struct drm_crtc *crtc;
  1638. int clock;
  1639. int entries, tlb_miss;
  1640. crtc = intel_get_crtc_for_plane(dev, plane);
  1641. if (crtc->fb == NULL || !crtc->enabled) {
  1642. *sprite_wm = display->guard_size;
  1643. return false;
  1644. }
  1645. clock = crtc->mode.clock;
  1646. /* Use the small buffer method to calculate the sprite watermark */
  1647. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  1648. tlb_miss = display->fifo_size*display->cacheline_size -
  1649. sprite_width * 8;
  1650. if (tlb_miss > 0)
  1651. entries += tlb_miss;
  1652. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  1653. *sprite_wm = entries + display->guard_size;
  1654. if (*sprite_wm > (int)display->max_wm)
  1655. *sprite_wm = display->max_wm;
  1656. return true;
  1657. }
  1658. static bool
  1659. sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
  1660. uint32_t sprite_width, int pixel_size,
  1661. const struct intel_watermark_params *display,
  1662. int latency_ns, int *sprite_wm)
  1663. {
  1664. struct drm_crtc *crtc;
  1665. unsigned long line_time_us;
  1666. int clock;
  1667. int line_count, line_size;
  1668. int small, large;
  1669. int entries;
  1670. if (!latency_ns) {
  1671. *sprite_wm = 0;
  1672. return false;
  1673. }
  1674. crtc = intel_get_crtc_for_plane(dev, plane);
  1675. clock = crtc->mode.clock;
  1676. if (!clock) {
  1677. *sprite_wm = 0;
  1678. return false;
  1679. }
  1680. line_time_us = (sprite_width * 1000) / clock;
  1681. if (!line_time_us) {
  1682. *sprite_wm = 0;
  1683. return false;
  1684. }
  1685. line_count = (latency_ns / line_time_us + 1000) / 1000;
  1686. line_size = sprite_width * pixel_size;
  1687. /* Use the minimum of the small and large buffer method for primary */
  1688. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1689. large = line_count * line_size;
  1690. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1691. *sprite_wm = entries + display->guard_size;
  1692. return *sprite_wm > 0x3ff ? false : true;
  1693. }
  1694. static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
  1695. uint32_t sprite_width, int pixel_size)
  1696. {
  1697. struct drm_i915_private *dev_priv = dev->dev_private;
  1698. int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
  1699. u32 val;
  1700. int sprite_wm, reg;
  1701. int ret;
  1702. switch (pipe) {
  1703. case 0:
  1704. reg = WM0_PIPEA_ILK;
  1705. break;
  1706. case 1:
  1707. reg = WM0_PIPEB_ILK;
  1708. break;
  1709. case 2:
  1710. reg = WM0_PIPEC_IVB;
  1711. break;
  1712. default:
  1713. return; /* bad pipe */
  1714. }
  1715. ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
  1716. &sandybridge_display_wm_info,
  1717. latency, &sprite_wm);
  1718. if (!ret) {
  1719. DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
  1720. pipe);
  1721. return;
  1722. }
  1723. val = I915_READ(reg);
  1724. val &= ~WM0_PIPE_SPRITE_MASK;
  1725. I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
  1726. DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
  1727. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  1728. pixel_size,
  1729. &sandybridge_display_srwm_info,
  1730. SNB_READ_WM1_LATENCY() * 500,
  1731. &sprite_wm);
  1732. if (!ret) {
  1733. DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
  1734. pipe);
  1735. return;
  1736. }
  1737. I915_WRITE(WM1S_LP_ILK, sprite_wm);
  1738. /* Only IVB has two more LP watermarks for sprite */
  1739. if (!IS_IVYBRIDGE(dev))
  1740. return;
  1741. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  1742. pixel_size,
  1743. &sandybridge_display_srwm_info,
  1744. SNB_READ_WM2_LATENCY() * 500,
  1745. &sprite_wm);
  1746. if (!ret) {
  1747. DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
  1748. pipe);
  1749. return;
  1750. }
  1751. I915_WRITE(WM2S_LP_IVB, sprite_wm);
  1752. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  1753. pixel_size,
  1754. &sandybridge_display_srwm_info,
  1755. SNB_READ_WM3_LATENCY() * 500,
  1756. &sprite_wm);
  1757. if (!ret) {
  1758. DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
  1759. pipe);
  1760. return;
  1761. }
  1762. I915_WRITE(WM3S_LP_IVB, sprite_wm);
  1763. }
  1764. /**
  1765. * intel_update_watermarks - update FIFO watermark values based on current modes
  1766. *
  1767. * Calculate watermark values for the various WM regs based on current mode
  1768. * and plane configuration.
  1769. *
  1770. * There are several cases to deal with here:
  1771. * - normal (i.e. non-self-refresh)
  1772. * - self-refresh (SR) mode
  1773. * - lines are large relative to FIFO size (buffer can hold up to 2)
  1774. * - lines are small relative to FIFO size (buffer can hold more than 2
  1775. * lines), so need to account for TLB latency
  1776. *
  1777. * The normal calculation is:
  1778. * watermark = dotclock * bytes per pixel * latency
  1779. * where latency is platform & configuration dependent (we assume pessimal
  1780. * values here).
  1781. *
  1782. * The SR calculation is:
  1783. * watermark = (trunc(latency/line time)+1) * surface width *
  1784. * bytes per pixel
  1785. * where
  1786. * line time = htotal / dotclock
  1787. * surface width = hdisplay for normal plane and 64 for cursor
  1788. * and latency is assumed to be high, as above.
  1789. *
  1790. * The final value programmed to the register should always be rounded up,
  1791. * and include an extra 2 entries to account for clock crossings.
  1792. *
  1793. * We don't use the sprite, so we can ignore that. And on Crestline we have
  1794. * to set the non-SR watermarks to 8.
  1795. */
  1796. void intel_update_watermarks(struct drm_device *dev)
  1797. {
  1798. struct drm_i915_private *dev_priv = dev->dev_private;
  1799. if (dev_priv->display.update_wm)
  1800. dev_priv->display.update_wm(dev);
  1801. }
  1802. void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
  1803. uint32_t sprite_width, int pixel_size)
  1804. {
  1805. struct drm_i915_private *dev_priv = dev->dev_private;
  1806. if (dev_priv->display.update_sprite_wm)
  1807. dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
  1808. pixel_size);
  1809. }
  1810. static struct drm_i915_gem_object *
  1811. intel_alloc_context_page(struct drm_device *dev)
  1812. {
  1813. struct drm_i915_gem_object *ctx;
  1814. int ret;
  1815. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  1816. ctx = i915_gem_alloc_object(dev, 4096);
  1817. if (!ctx) {
  1818. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  1819. return NULL;
  1820. }
  1821. ret = i915_gem_object_pin(ctx, 4096, true);
  1822. if (ret) {
  1823. DRM_ERROR("failed to pin power context: %d\n", ret);
  1824. goto err_unref;
  1825. }
  1826. ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
  1827. if (ret) {
  1828. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  1829. goto err_unpin;
  1830. }
  1831. return ctx;
  1832. err_unpin:
  1833. i915_gem_object_unpin(ctx);
  1834. err_unref:
  1835. drm_gem_object_unreference(&ctx->base);
  1836. mutex_unlock(&dev->struct_mutex);
  1837. return NULL;
  1838. }
  1839. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  1840. {
  1841. struct drm_i915_private *dev_priv = dev->dev_private;
  1842. u16 rgvswctl;
  1843. rgvswctl = I915_READ16(MEMSWCTL);
  1844. if (rgvswctl & MEMCTL_CMD_STS) {
  1845. DRM_DEBUG("gpu busy, RCS change rejected\n");
  1846. return false; /* still busy with another command */
  1847. }
  1848. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  1849. (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  1850. I915_WRITE16(MEMSWCTL, rgvswctl);
  1851. POSTING_READ16(MEMSWCTL);
  1852. rgvswctl |= MEMCTL_CMD_STS;
  1853. I915_WRITE16(MEMSWCTL, rgvswctl);
  1854. return true;
  1855. }
  1856. void ironlake_enable_drps(struct drm_device *dev)
  1857. {
  1858. struct drm_i915_private *dev_priv = dev->dev_private;
  1859. u32 rgvmodectl = I915_READ(MEMMODECTL);
  1860. u8 fmax, fmin, fstart, vstart;
  1861. /* Enable temp reporting */
  1862. I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
  1863. I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
  1864. /* 100ms RC evaluation intervals */
  1865. I915_WRITE(RCUPEI, 100000);
  1866. I915_WRITE(RCDNEI, 100000);
  1867. /* Set max/min thresholds to 90ms and 80ms respectively */
  1868. I915_WRITE(RCBMAXAVG, 90000);
  1869. I915_WRITE(RCBMINAVG, 80000);
  1870. I915_WRITE(MEMIHYST, 1);
  1871. /* Set up min, max, and cur for interrupt handling */
  1872. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  1873. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  1874. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  1875. MEMMODE_FSTART_SHIFT;
  1876. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  1877. PXVFREQ_PX_SHIFT;
  1878. dev_priv->fmax = fmax; /* IPS callback will increase this */
  1879. dev_priv->fstart = fstart;
  1880. dev_priv->max_delay = fstart;
  1881. dev_priv->min_delay = fmin;
  1882. dev_priv->cur_delay = fstart;
  1883. DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
  1884. fmax, fmin, fstart);
  1885. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  1886. /*
  1887. * Interrupts will be enabled in ironlake_irq_postinstall
  1888. */
  1889. I915_WRITE(VIDSTART, vstart);
  1890. POSTING_READ(VIDSTART);
  1891. rgvmodectl |= MEMMODE_SWMODE_EN;
  1892. I915_WRITE(MEMMODECTL, rgvmodectl);
  1893. if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
  1894. DRM_ERROR("stuck trying to change perf mode\n");
  1895. msleep(1);
  1896. ironlake_set_drps(dev, fstart);
  1897. dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  1898. I915_READ(0x112e0);
  1899. dev_priv->last_time1 = jiffies_to_msecs(jiffies);
  1900. dev_priv->last_count2 = I915_READ(0x112f4);
  1901. getrawmonotonic(&dev_priv->last_time2);
  1902. }
  1903. void ironlake_disable_drps(struct drm_device *dev)
  1904. {
  1905. struct drm_i915_private *dev_priv = dev->dev_private;
  1906. u16 rgvswctl = I915_READ16(MEMSWCTL);
  1907. /* Ack interrupts, disable EFC interrupt */
  1908. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  1909. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  1910. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  1911. I915_WRITE(DEIIR, DE_PCU_EVENT);
  1912. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  1913. /* Go back to the starting frequency */
  1914. ironlake_set_drps(dev, dev_priv->fstart);
  1915. msleep(1);
  1916. rgvswctl |= MEMCTL_CMD_STS;
  1917. I915_WRITE(MEMSWCTL, rgvswctl);
  1918. msleep(1);
  1919. }
  1920. void gen6_set_rps(struct drm_device *dev, u8 val)
  1921. {
  1922. struct drm_i915_private *dev_priv = dev->dev_private;
  1923. u32 swreq;
  1924. swreq = (val & 0x3ff) << 25;
  1925. I915_WRITE(GEN6_RPNSWREQ, swreq);
  1926. }
  1927. void gen6_disable_rps(struct drm_device *dev)
  1928. {
  1929. struct drm_i915_private *dev_priv = dev->dev_private;
  1930. I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
  1931. I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
  1932. I915_WRITE(GEN6_PMIER, 0);
  1933. /* Complete PM interrupt masking here doesn't race with the rps work
  1934. * item again unmasking PM interrupts because that is using a different
  1935. * register (PMIMR) to mask PM interrupts. The only risk is in leaving
  1936. * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
  1937. spin_lock_irq(&dev_priv->rps_lock);
  1938. dev_priv->pm_iir = 0;
  1939. spin_unlock_irq(&dev_priv->rps_lock);
  1940. I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
  1941. }
  1942. int intel_enable_rc6(const struct drm_device *dev)
  1943. {
  1944. /*
  1945. * Respect the kernel parameter if it is set
  1946. */
  1947. if (i915_enable_rc6 >= 0)
  1948. return i915_enable_rc6;
  1949. /*
  1950. * Disable RC6 on Ironlake
  1951. */
  1952. if (INTEL_INFO(dev)->gen == 5)
  1953. return 0;
  1954. /* Sorry Haswell, no RC6 for you for now. */
  1955. if (IS_HASWELL(dev))
  1956. return 0;
  1957. /*
  1958. * Disable rc6 on Sandybridge
  1959. */
  1960. if (INTEL_INFO(dev)->gen == 6) {
  1961. DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
  1962. return INTEL_RC6_ENABLE;
  1963. }
  1964. DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
  1965. return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
  1966. }
  1967. void gen6_enable_rps(struct drm_i915_private *dev_priv)
  1968. {
  1969. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  1970. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  1971. u32 pcu_mbox, rc6_mask = 0;
  1972. u32 gtfifodbg;
  1973. int cur_freq, min_freq, max_freq;
  1974. int rc6_mode;
  1975. int i;
  1976. /* Here begins a magic sequence of register writes to enable
  1977. * auto-downclocking.
  1978. *
  1979. * Perhaps there might be some value in exposing these to
  1980. * userspace...
  1981. */
  1982. I915_WRITE(GEN6_RC_STATE, 0);
  1983. mutex_lock(&dev_priv->dev->struct_mutex);
  1984. /* Clear the DBG now so we don't confuse earlier errors */
  1985. if ((gtfifodbg = I915_READ(GTFIFODBG))) {
  1986. DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
  1987. I915_WRITE(GTFIFODBG, gtfifodbg);
  1988. }
  1989. gen6_gt_force_wake_get(dev_priv);
  1990. /* disable the counters and set deterministic thresholds */
  1991. I915_WRITE(GEN6_RC_CONTROL, 0);
  1992. I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
  1993. I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
  1994. I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
  1995. I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
  1996. I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
  1997. for (i = 0; i < I915_NUM_RINGS; i++)
  1998. I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
  1999. I915_WRITE(GEN6_RC_SLEEP, 0);
  2000. I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
  2001. I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
  2002. I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
  2003. I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
  2004. rc6_mode = intel_enable_rc6(dev_priv->dev);
  2005. if (rc6_mode & INTEL_RC6_ENABLE)
  2006. rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
  2007. if (rc6_mode & INTEL_RC6p_ENABLE)
  2008. rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
  2009. if (rc6_mode & INTEL_RC6pp_ENABLE)
  2010. rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
  2011. DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
  2012. (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
  2013. (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
  2014. (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
  2015. I915_WRITE(GEN6_RC_CONTROL,
  2016. rc6_mask |
  2017. GEN6_RC_CTL_EI_MODE(1) |
  2018. GEN6_RC_CTL_HW_ENABLE);
  2019. I915_WRITE(GEN6_RPNSWREQ,
  2020. GEN6_FREQUENCY(10) |
  2021. GEN6_OFFSET(0) |
  2022. GEN6_AGGRESSIVE_TURBO);
  2023. I915_WRITE(GEN6_RC_VIDEO_FREQ,
  2024. GEN6_FREQUENCY(12));
  2025. I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
  2026. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
  2027. 18 << 24 |
  2028. 6 << 16);
  2029. I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
  2030. I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
  2031. I915_WRITE(GEN6_RP_UP_EI, 100000);
  2032. I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
  2033. I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
  2034. I915_WRITE(GEN6_RP_CONTROL,
  2035. GEN6_RP_MEDIA_TURBO |
  2036. GEN6_RP_MEDIA_HW_MODE |
  2037. GEN6_RP_MEDIA_IS_GFX |
  2038. GEN6_RP_ENABLE |
  2039. GEN6_RP_UP_BUSY_AVG |
  2040. GEN6_RP_DOWN_IDLE_CONT);
  2041. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2042. 500))
  2043. DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  2044. I915_WRITE(GEN6_PCODE_DATA, 0);
  2045. I915_WRITE(GEN6_PCODE_MAILBOX,
  2046. GEN6_PCODE_READY |
  2047. GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
  2048. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2049. 500))
  2050. DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  2051. min_freq = (rp_state_cap & 0xff0000) >> 16;
  2052. max_freq = rp_state_cap & 0xff;
  2053. cur_freq = (gt_perf_status & 0xff00) >> 8;
  2054. /* Check for overclock support */
  2055. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2056. 500))
  2057. DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  2058. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
  2059. pcu_mbox = I915_READ(GEN6_PCODE_DATA);
  2060. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2061. 500))
  2062. DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  2063. if (pcu_mbox & (1<<31)) { /* OC supported */
  2064. max_freq = pcu_mbox & 0xff;
  2065. DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
  2066. }
  2067. /* In units of 100MHz */
  2068. dev_priv->max_delay = max_freq;
  2069. dev_priv->min_delay = min_freq;
  2070. dev_priv->cur_delay = cur_freq;
  2071. /* requires MSI enabled */
  2072. I915_WRITE(GEN6_PMIER,
  2073. GEN6_PM_MBOX_EVENT |
  2074. GEN6_PM_THERMAL_EVENT |
  2075. GEN6_PM_RP_DOWN_TIMEOUT |
  2076. GEN6_PM_RP_UP_THRESHOLD |
  2077. GEN6_PM_RP_DOWN_THRESHOLD |
  2078. GEN6_PM_RP_UP_EI_EXPIRED |
  2079. GEN6_PM_RP_DOWN_EI_EXPIRED);
  2080. spin_lock_irq(&dev_priv->rps_lock);
  2081. WARN_ON(dev_priv->pm_iir != 0);
  2082. I915_WRITE(GEN6_PMIMR, 0);
  2083. spin_unlock_irq(&dev_priv->rps_lock);
  2084. /* enable all PM interrupts */
  2085. I915_WRITE(GEN6_PMINTRMSK, 0);
  2086. gen6_gt_force_wake_put(dev_priv);
  2087. mutex_unlock(&dev_priv->dev->struct_mutex);
  2088. }
  2089. void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
  2090. {
  2091. int min_freq = 15;
  2092. int gpu_freq, ia_freq, max_ia_freq;
  2093. int scaling_factor = 180;
  2094. max_ia_freq = cpufreq_quick_get_max(0);
  2095. /*
  2096. * Default to measured freq if none found, PCU will ensure we don't go
  2097. * over
  2098. */
  2099. if (!max_ia_freq)
  2100. max_ia_freq = tsc_khz;
  2101. /* Convert from kHz to MHz */
  2102. max_ia_freq /= 1000;
  2103. mutex_lock(&dev_priv->dev->struct_mutex);
  2104. /*
  2105. * For each potential GPU frequency, load a ring frequency we'd like
  2106. * to use for memory access. We do this by specifying the IA frequency
  2107. * the PCU should use as a reference to determine the ring frequency.
  2108. */
  2109. for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
  2110. gpu_freq--) {
  2111. int diff = dev_priv->max_delay - gpu_freq;
  2112. /*
  2113. * For GPU frequencies less than 750MHz, just use the lowest
  2114. * ring freq.
  2115. */
  2116. if (gpu_freq < min_freq)
  2117. ia_freq = 800;
  2118. else
  2119. ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
  2120. ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
  2121. I915_WRITE(GEN6_PCODE_DATA,
  2122. (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
  2123. gpu_freq);
  2124. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
  2125. GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
  2126. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
  2127. GEN6_PCODE_READY) == 0, 10)) {
  2128. DRM_ERROR("pcode write of freq table timed out\n");
  2129. continue;
  2130. }
  2131. }
  2132. mutex_unlock(&dev_priv->dev->struct_mutex);
  2133. }
  2134. static void ironlake_teardown_rc6(struct drm_device *dev)
  2135. {
  2136. struct drm_i915_private *dev_priv = dev->dev_private;
  2137. if (dev_priv->renderctx) {
  2138. i915_gem_object_unpin(dev_priv->renderctx);
  2139. drm_gem_object_unreference(&dev_priv->renderctx->base);
  2140. dev_priv->renderctx = NULL;
  2141. }
  2142. if (dev_priv->pwrctx) {
  2143. i915_gem_object_unpin(dev_priv->pwrctx);
  2144. drm_gem_object_unreference(&dev_priv->pwrctx->base);
  2145. dev_priv->pwrctx = NULL;
  2146. }
  2147. }
  2148. void ironlake_disable_rc6(struct drm_device *dev)
  2149. {
  2150. struct drm_i915_private *dev_priv = dev->dev_private;
  2151. if (I915_READ(PWRCTXA)) {
  2152. /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
  2153. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
  2154. wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
  2155. 50);
  2156. I915_WRITE(PWRCTXA, 0);
  2157. POSTING_READ(PWRCTXA);
  2158. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  2159. POSTING_READ(RSTDBYCTL);
  2160. }
  2161. ironlake_teardown_rc6(dev);
  2162. }
  2163. static int ironlake_setup_rc6(struct drm_device *dev)
  2164. {
  2165. struct drm_i915_private *dev_priv = dev->dev_private;
  2166. if (dev_priv->renderctx == NULL)
  2167. dev_priv->renderctx = intel_alloc_context_page(dev);
  2168. if (!dev_priv->renderctx)
  2169. return -ENOMEM;
  2170. if (dev_priv->pwrctx == NULL)
  2171. dev_priv->pwrctx = intel_alloc_context_page(dev);
  2172. if (!dev_priv->pwrctx) {
  2173. ironlake_teardown_rc6(dev);
  2174. return -ENOMEM;
  2175. }
  2176. return 0;
  2177. }
  2178. void ironlake_enable_rc6(struct drm_device *dev)
  2179. {
  2180. struct drm_i915_private *dev_priv = dev->dev_private;
  2181. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  2182. int ret;
  2183. /* rc6 disabled by default due to repeated reports of hanging during
  2184. * boot and resume.
  2185. */
  2186. if (!intel_enable_rc6(dev))
  2187. return;
  2188. mutex_lock(&dev->struct_mutex);
  2189. ret = ironlake_setup_rc6(dev);
  2190. if (ret) {
  2191. mutex_unlock(&dev->struct_mutex);
  2192. return;
  2193. }
  2194. /*
  2195. * GPU can automatically power down the render unit if given a page
  2196. * to save state.
  2197. */
  2198. ret = intel_ring_begin(ring, 6);
  2199. if (ret) {
  2200. ironlake_teardown_rc6(dev);
  2201. mutex_unlock(&dev->struct_mutex);
  2202. return;
  2203. }
  2204. intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
  2205. intel_ring_emit(ring, MI_SET_CONTEXT);
  2206. intel_ring_emit(ring, dev_priv->renderctx->gtt_offset |
  2207. MI_MM_SPACE_GTT |
  2208. MI_SAVE_EXT_STATE_EN |
  2209. MI_RESTORE_EXT_STATE_EN |
  2210. MI_RESTORE_INHIBIT);
  2211. intel_ring_emit(ring, MI_SUSPEND_FLUSH);
  2212. intel_ring_emit(ring, MI_NOOP);
  2213. intel_ring_emit(ring, MI_FLUSH);
  2214. intel_ring_advance(ring);
  2215. /*
  2216. * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
  2217. * does an implicit flush, combined with MI_FLUSH above, it should be
  2218. * safe to assume that renderctx is valid
  2219. */
  2220. ret = intel_wait_ring_idle(ring);
  2221. if (ret) {
  2222. DRM_ERROR("failed to enable ironlake power power savings\n");
  2223. ironlake_teardown_rc6(dev);
  2224. mutex_unlock(&dev->struct_mutex);
  2225. return;
  2226. }
  2227. I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
  2228. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  2229. mutex_unlock(&dev->struct_mutex);
  2230. }
  2231. static unsigned long intel_pxfreq(u32 vidfreq)
  2232. {
  2233. unsigned long freq;
  2234. int div = (vidfreq & 0x3f0000) >> 16;
  2235. int post = (vidfreq & 0x3000) >> 12;
  2236. int pre = (vidfreq & 0x7);
  2237. if (!pre)
  2238. return 0;
  2239. freq = ((div * 133333) / ((1<<post) * pre));
  2240. return freq;
  2241. }
  2242. static const struct cparams {
  2243. u16 i;
  2244. u16 t;
  2245. u16 m;
  2246. u16 c;
  2247. } cparams[] = {
  2248. { 1, 1333, 301, 28664 },
  2249. { 1, 1066, 294, 24460 },
  2250. { 1, 800, 294, 25192 },
  2251. { 0, 1333, 276, 27605 },
  2252. { 0, 1066, 276, 27605 },
  2253. { 0, 800, 231, 23784 },
  2254. };
  2255. unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
  2256. {
  2257. u64 total_count, diff, ret;
  2258. u32 count1, count2, count3, m = 0, c = 0;
  2259. unsigned long now = jiffies_to_msecs(jiffies), diff1;
  2260. int i;
  2261. diff1 = now - dev_priv->last_time1;
  2262. /* Prevent division-by-zero if we are asking too fast.
  2263. * Also, we don't get interesting results if we are polling
  2264. * faster than once in 10ms, so just return the saved value
  2265. * in such cases.
  2266. */
  2267. if (diff1 <= 10)
  2268. return dev_priv->chipset_power;
  2269. count1 = I915_READ(DMIEC);
  2270. count2 = I915_READ(DDREC);
  2271. count3 = I915_READ(CSIEC);
  2272. total_count = count1 + count2 + count3;
  2273. /* FIXME: handle per-counter overflow */
  2274. if (total_count < dev_priv->last_count1) {
  2275. diff = ~0UL - dev_priv->last_count1;
  2276. diff += total_count;
  2277. } else {
  2278. diff = total_count - dev_priv->last_count1;
  2279. }
  2280. for (i = 0; i < ARRAY_SIZE(cparams); i++) {
  2281. if (cparams[i].i == dev_priv->c_m &&
  2282. cparams[i].t == dev_priv->r_t) {
  2283. m = cparams[i].m;
  2284. c = cparams[i].c;
  2285. break;
  2286. }
  2287. }
  2288. diff = div_u64(diff, diff1);
  2289. ret = ((m * diff) + c);
  2290. ret = div_u64(ret, 10);
  2291. dev_priv->last_count1 = total_count;
  2292. dev_priv->last_time1 = now;
  2293. dev_priv->chipset_power = ret;
  2294. return ret;
  2295. }
  2296. unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
  2297. {
  2298. unsigned long m, x, b;
  2299. u32 tsfs;
  2300. tsfs = I915_READ(TSFS);
  2301. m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
  2302. x = I915_READ8(TR1);
  2303. b = tsfs & TSFS_INTR_MASK;
  2304. return ((m * x) / 127) - b;
  2305. }
  2306. static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
  2307. {
  2308. static const struct v_table {
  2309. u16 vd; /* in .1 mil */
  2310. u16 vm; /* in .1 mil */
  2311. } v_table[] = {
  2312. { 0, 0, },
  2313. { 375, 0, },
  2314. { 500, 0, },
  2315. { 625, 0, },
  2316. { 750, 0, },
  2317. { 875, 0, },
  2318. { 1000, 0, },
  2319. { 1125, 0, },
  2320. { 4125, 3000, },
  2321. { 4125, 3000, },
  2322. { 4125, 3000, },
  2323. { 4125, 3000, },
  2324. { 4125, 3000, },
  2325. { 4125, 3000, },
  2326. { 4125, 3000, },
  2327. { 4125, 3000, },
  2328. { 4125, 3000, },
  2329. { 4125, 3000, },
  2330. { 4125, 3000, },
  2331. { 4125, 3000, },
  2332. { 4125, 3000, },
  2333. { 4125, 3000, },
  2334. { 4125, 3000, },
  2335. { 4125, 3000, },
  2336. { 4125, 3000, },
  2337. { 4125, 3000, },
  2338. { 4125, 3000, },
  2339. { 4125, 3000, },
  2340. { 4125, 3000, },
  2341. { 4125, 3000, },
  2342. { 4125, 3000, },
  2343. { 4125, 3000, },
  2344. { 4250, 3125, },
  2345. { 4375, 3250, },
  2346. { 4500, 3375, },
  2347. { 4625, 3500, },
  2348. { 4750, 3625, },
  2349. { 4875, 3750, },
  2350. { 5000, 3875, },
  2351. { 5125, 4000, },
  2352. { 5250, 4125, },
  2353. { 5375, 4250, },
  2354. { 5500, 4375, },
  2355. { 5625, 4500, },
  2356. { 5750, 4625, },
  2357. { 5875, 4750, },
  2358. { 6000, 4875, },
  2359. { 6125, 5000, },
  2360. { 6250, 5125, },
  2361. { 6375, 5250, },
  2362. { 6500, 5375, },
  2363. { 6625, 5500, },
  2364. { 6750, 5625, },
  2365. { 6875, 5750, },
  2366. { 7000, 5875, },
  2367. { 7125, 6000, },
  2368. { 7250, 6125, },
  2369. { 7375, 6250, },
  2370. { 7500, 6375, },
  2371. { 7625, 6500, },
  2372. { 7750, 6625, },
  2373. { 7875, 6750, },
  2374. { 8000, 6875, },
  2375. { 8125, 7000, },
  2376. { 8250, 7125, },
  2377. { 8375, 7250, },
  2378. { 8500, 7375, },
  2379. { 8625, 7500, },
  2380. { 8750, 7625, },
  2381. { 8875, 7750, },
  2382. { 9000, 7875, },
  2383. { 9125, 8000, },
  2384. { 9250, 8125, },
  2385. { 9375, 8250, },
  2386. { 9500, 8375, },
  2387. { 9625, 8500, },
  2388. { 9750, 8625, },
  2389. { 9875, 8750, },
  2390. { 10000, 8875, },
  2391. { 10125, 9000, },
  2392. { 10250, 9125, },
  2393. { 10375, 9250, },
  2394. { 10500, 9375, },
  2395. { 10625, 9500, },
  2396. { 10750, 9625, },
  2397. { 10875, 9750, },
  2398. { 11000, 9875, },
  2399. { 11125, 10000, },
  2400. { 11250, 10125, },
  2401. { 11375, 10250, },
  2402. { 11500, 10375, },
  2403. { 11625, 10500, },
  2404. { 11750, 10625, },
  2405. { 11875, 10750, },
  2406. { 12000, 10875, },
  2407. { 12125, 11000, },
  2408. { 12250, 11125, },
  2409. { 12375, 11250, },
  2410. { 12500, 11375, },
  2411. { 12625, 11500, },
  2412. { 12750, 11625, },
  2413. { 12875, 11750, },
  2414. { 13000, 11875, },
  2415. { 13125, 12000, },
  2416. { 13250, 12125, },
  2417. { 13375, 12250, },
  2418. { 13500, 12375, },
  2419. { 13625, 12500, },
  2420. { 13750, 12625, },
  2421. { 13875, 12750, },
  2422. { 14000, 12875, },
  2423. { 14125, 13000, },
  2424. { 14250, 13125, },
  2425. { 14375, 13250, },
  2426. { 14500, 13375, },
  2427. { 14625, 13500, },
  2428. { 14750, 13625, },
  2429. { 14875, 13750, },
  2430. { 15000, 13875, },
  2431. { 15125, 14000, },
  2432. { 15250, 14125, },
  2433. { 15375, 14250, },
  2434. { 15500, 14375, },
  2435. { 15625, 14500, },
  2436. { 15750, 14625, },
  2437. { 15875, 14750, },
  2438. { 16000, 14875, },
  2439. { 16125, 15000, },
  2440. };
  2441. if (dev_priv->info->is_mobile)
  2442. return v_table[pxvid].vm;
  2443. else
  2444. return v_table[pxvid].vd;
  2445. }
  2446. void i915_update_gfx_val(struct drm_i915_private *dev_priv)
  2447. {
  2448. struct timespec now, diff1;
  2449. u64 diff;
  2450. unsigned long diffms;
  2451. u32 count;
  2452. if (dev_priv->info->gen != 5)
  2453. return;
  2454. getrawmonotonic(&now);
  2455. diff1 = timespec_sub(now, dev_priv->last_time2);
  2456. /* Don't divide by 0 */
  2457. diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
  2458. if (!diffms)
  2459. return;
  2460. count = I915_READ(GFXEC);
  2461. if (count < dev_priv->last_count2) {
  2462. diff = ~0UL - dev_priv->last_count2;
  2463. diff += count;
  2464. } else {
  2465. diff = count - dev_priv->last_count2;
  2466. }
  2467. dev_priv->last_count2 = count;
  2468. dev_priv->last_time2 = now;
  2469. /* More magic constants... */
  2470. diff = diff * 1181;
  2471. diff = div_u64(diff, diffms * 10);
  2472. dev_priv->gfx_power = diff;
  2473. }
  2474. unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
  2475. {
  2476. unsigned long t, corr, state1, corr2, state2;
  2477. u32 pxvid, ext_v;
  2478. pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
  2479. pxvid = (pxvid >> 24) & 0x7f;
  2480. ext_v = pvid_to_extvid(dev_priv, pxvid);
  2481. state1 = ext_v;
  2482. t = i915_mch_val(dev_priv);
  2483. /* Revel in the empirically derived constants */
  2484. /* Correction factor in 1/100000 units */
  2485. if (t > 80)
  2486. corr = ((t * 2349) + 135940);
  2487. else if (t >= 50)
  2488. corr = ((t * 964) + 29317);
  2489. else /* < 50 */
  2490. corr = ((t * 301) + 1004);
  2491. corr = corr * ((150142 * state1) / 10000 - 78642);
  2492. corr /= 100000;
  2493. corr2 = (corr * dev_priv->corr);
  2494. state2 = (corr2 * state1) / 10000;
  2495. state2 /= 100; /* convert to mW */
  2496. i915_update_gfx_val(dev_priv);
  2497. return dev_priv->gfx_power + state2;
  2498. }
  2499. /* Global for IPS driver to get at the current i915 device */
  2500. static struct drm_i915_private *i915_mch_dev;
  2501. /*
  2502. * Lock protecting IPS related data structures
  2503. * - i915_mch_dev
  2504. * - dev_priv->max_delay
  2505. * - dev_priv->min_delay
  2506. * - dev_priv->fmax
  2507. * - dev_priv->gpu_busy
  2508. */
  2509. static DEFINE_SPINLOCK(mchdev_lock);
  2510. /**
  2511. * i915_read_mch_val - return value for IPS use
  2512. *
  2513. * Calculate and return a value for the IPS driver to use when deciding whether
  2514. * we have thermal and power headroom to increase CPU or GPU power budget.
  2515. */
  2516. unsigned long i915_read_mch_val(void)
  2517. {
  2518. struct drm_i915_private *dev_priv;
  2519. unsigned long chipset_val, graphics_val, ret = 0;
  2520. spin_lock(&mchdev_lock);
  2521. if (!i915_mch_dev)
  2522. goto out_unlock;
  2523. dev_priv = i915_mch_dev;
  2524. chipset_val = i915_chipset_val(dev_priv);
  2525. graphics_val = i915_gfx_val(dev_priv);
  2526. ret = chipset_val + graphics_val;
  2527. out_unlock:
  2528. spin_unlock(&mchdev_lock);
  2529. return ret;
  2530. }
  2531. EXPORT_SYMBOL_GPL(i915_read_mch_val);
  2532. /**
  2533. * i915_gpu_raise - raise GPU frequency limit
  2534. *
  2535. * Raise the limit; IPS indicates we have thermal headroom.
  2536. */
  2537. bool i915_gpu_raise(void)
  2538. {
  2539. struct drm_i915_private *dev_priv;
  2540. bool ret = true;
  2541. spin_lock(&mchdev_lock);
  2542. if (!i915_mch_dev) {
  2543. ret = false;
  2544. goto out_unlock;
  2545. }
  2546. dev_priv = i915_mch_dev;
  2547. if (dev_priv->max_delay > dev_priv->fmax)
  2548. dev_priv->max_delay--;
  2549. out_unlock:
  2550. spin_unlock(&mchdev_lock);
  2551. return ret;
  2552. }
  2553. EXPORT_SYMBOL_GPL(i915_gpu_raise);
  2554. /**
  2555. * i915_gpu_lower - lower GPU frequency limit
  2556. *
  2557. * IPS indicates we're close to a thermal limit, so throttle back the GPU
  2558. * frequency maximum.
  2559. */
  2560. bool i915_gpu_lower(void)
  2561. {
  2562. struct drm_i915_private *dev_priv;
  2563. bool ret = true;
  2564. spin_lock(&mchdev_lock);
  2565. if (!i915_mch_dev) {
  2566. ret = false;
  2567. goto out_unlock;
  2568. }
  2569. dev_priv = i915_mch_dev;
  2570. if (dev_priv->max_delay < dev_priv->min_delay)
  2571. dev_priv->max_delay++;
  2572. out_unlock:
  2573. spin_unlock(&mchdev_lock);
  2574. return ret;
  2575. }
  2576. EXPORT_SYMBOL_GPL(i915_gpu_lower);
  2577. /**
  2578. * i915_gpu_busy - indicate GPU business to IPS
  2579. *
  2580. * Tell the IPS driver whether or not the GPU is busy.
  2581. */
  2582. bool i915_gpu_busy(void)
  2583. {
  2584. struct drm_i915_private *dev_priv;
  2585. bool ret = false;
  2586. spin_lock(&mchdev_lock);
  2587. if (!i915_mch_dev)
  2588. goto out_unlock;
  2589. dev_priv = i915_mch_dev;
  2590. ret = dev_priv->busy;
  2591. out_unlock:
  2592. spin_unlock(&mchdev_lock);
  2593. return ret;
  2594. }
  2595. EXPORT_SYMBOL_GPL(i915_gpu_busy);
  2596. /**
  2597. * i915_gpu_turbo_disable - disable graphics turbo
  2598. *
  2599. * Disable graphics turbo by resetting the max frequency and setting the
  2600. * current frequency to the default.
  2601. */
  2602. bool i915_gpu_turbo_disable(void)
  2603. {
  2604. struct drm_i915_private *dev_priv;
  2605. bool ret = true;
  2606. spin_lock(&mchdev_lock);
  2607. if (!i915_mch_dev) {
  2608. ret = false;
  2609. goto out_unlock;
  2610. }
  2611. dev_priv = i915_mch_dev;
  2612. dev_priv->max_delay = dev_priv->fstart;
  2613. if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
  2614. ret = false;
  2615. out_unlock:
  2616. spin_unlock(&mchdev_lock);
  2617. return ret;
  2618. }
  2619. EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
  2620. /**
  2621. * Tells the intel_ips driver that the i915 driver is now loaded, if
  2622. * IPS got loaded first.
  2623. *
  2624. * This awkward dance is so that neither module has to depend on the
  2625. * other in order for IPS to do the appropriate communication of
  2626. * GPU turbo limits to i915.
  2627. */
  2628. static void
  2629. ips_ping_for_i915_load(void)
  2630. {
  2631. void (*link)(void);
  2632. link = symbol_get(ips_link_to_i915_driver);
  2633. if (link) {
  2634. link();
  2635. symbol_put(ips_link_to_i915_driver);
  2636. }
  2637. }
  2638. void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
  2639. {
  2640. spin_lock(&mchdev_lock);
  2641. i915_mch_dev = dev_priv;
  2642. dev_priv->mchdev_lock = &mchdev_lock;
  2643. spin_unlock(&mchdev_lock);
  2644. ips_ping_for_i915_load();
  2645. }
  2646. void intel_gpu_ips_teardown(void)
  2647. {
  2648. spin_lock(&mchdev_lock);
  2649. i915_mch_dev = NULL;
  2650. spin_unlock(&mchdev_lock);
  2651. }
  2652. void intel_init_emon(struct drm_device *dev)
  2653. {
  2654. struct drm_i915_private *dev_priv = dev->dev_private;
  2655. u32 lcfuse;
  2656. u8 pxw[16];
  2657. int i;
  2658. /* Disable to program */
  2659. I915_WRITE(ECR, 0);
  2660. POSTING_READ(ECR);
  2661. /* Program energy weights for various events */
  2662. I915_WRITE(SDEW, 0x15040d00);
  2663. I915_WRITE(CSIEW0, 0x007f0000);
  2664. I915_WRITE(CSIEW1, 0x1e220004);
  2665. I915_WRITE(CSIEW2, 0x04000004);
  2666. for (i = 0; i < 5; i++)
  2667. I915_WRITE(PEW + (i * 4), 0);
  2668. for (i = 0; i < 3; i++)
  2669. I915_WRITE(DEW + (i * 4), 0);
  2670. /* Program P-state weights to account for frequency power adjustment */
  2671. for (i = 0; i < 16; i++) {
  2672. u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  2673. unsigned long freq = intel_pxfreq(pxvidfreq);
  2674. unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  2675. PXVFREQ_PX_SHIFT;
  2676. unsigned long val;
  2677. val = vid * vid;
  2678. val *= (freq / 1000);
  2679. val *= 255;
  2680. val /= (127*127*900);
  2681. if (val > 0xff)
  2682. DRM_ERROR("bad pxval: %ld\n", val);
  2683. pxw[i] = val;
  2684. }
  2685. /* Render standby states get 0 weight */
  2686. pxw[14] = 0;
  2687. pxw[15] = 0;
  2688. for (i = 0; i < 4; i++) {
  2689. u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  2690. (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  2691. I915_WRITE(PXW + (i * 4), val);
  2692. }
  2693. /* Adjust magic regs to magic values (more experimental results) */
  2694. I915_WRITE(OGW0, 0);
  2695. I915_WRITE(OGW1, 0);
  2696. I915_WRITE(EG0, 0x00007f00);
  2697. I915_WRITE(EG1, 0x0000000e);
  2698. I915_WRITE(EG2, 0x000e0000);
  2699. I915_WRITE(EG3, 0x68000300);
  2700. I915_WRITE(EG4, 0x42000000);
  2701. I915_WRITE(EG5, 0x00140031);
  2702. I915_WRITE(EG6, 0);
  2703. I915_WRITE(EG7, 0);
  2704. for (i = 0; i < 8; i++)
  2705. I915_WRITE(PXWL + (i * 4), 0);
  2706. /* Enable PMON + select events */
  2707. I915_WRITE(ECR, 0x80000019);
  2708. lcfuse = I915_READ(LCFUSE02);
  2709. dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
  2710. }
  2711. static void ironlake_init_clock_gating(struct drm_device *dev)
  2712. {
  2713. struct drm_i915_private *dev_priv = dev->dev_private;
  2714. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  2715. /* Required for FBC */
  2716. dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
  2717. DPFCRUNIT_CLOCK_GATE_DISABLE |
  2718. DPFDUNIT_CLOCK_GATE_DISABLE;
  2719. /* Required for CxSR */
  2720. dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
  2721. I915_WRITE(PCH_3DCGDIS0,
  2722. MARIUNIT_CLOCK_GATE_DISABLE |
  2723. SVSMUNIT_CLOCK_GATE_DISABLE);
  2724. I915_WRITE(PCH_3DCGDIS1,
  2725. VFMUNIT_CLOCK_GATE_DISABLE);
  2726. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  2727. /*
  2728. * According to the spec the following bits should be set in
  2729. * order to enable memory self-refresh
  2730. * The bit 22/21 of 0x42004
  2731. * The bit 5 of 0x42020
  2732. * The bit 15 of 0x45000
  2733. */
  2734. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  2735. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  2736. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  2737. I915_WRITE(ILK_DSPCLK_GATE,
  2738. (I915_READ(ILK_DSPCLK_GATE) |
  2739. ILK_DPARB_CLK_GATE));
  2740. I915_WRITE(DISP_ARB_CTL,
  2741. (I915_READ(DISP_ARB_CTL) |
  2742. DISP_FBC_WM_DIS));
  2743. I915_WRITE(WM3_LP_ILK, 0);
  2744. I915_WRITE(WM2_LP_ILK, 0);
  2745. I915_WRITE(WM1_LP_ILK, 0);
  2746. /*
  2747. * Based on the document from hardware guys the following bits
  2748. * should be set unconditionally in order to enable FBC.
  2749. * The bit 22 of 0x42000
  2750. * The bit 22 of 0x42004
  2751. * The bit 7,8,9 of 0x42020.
  2752. */
  2753. if (IS_IRONLAKE_M(dev)) {
  2754. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  2755. I915_READ(ILK_DISPLAY_CHICKEN1) |
  2756. ILK_FBCQ_DIS);
  2757. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  2758. I915_READ(ILK_DISPLAY_CHICKEN2) |
  2759. ILK_DPARB_GATE);
  2760. I915_WRITE(ILK_DSPCLK_GATE,
  2761. I915_READ(ILK_DSPCLK_GATE) |
  2762. ILK_DPFC_DIS1 |
  2763. ILK_DPFC_DIS2 |
  2764. ILK_CLK_FBC);
  2765. }
  2766. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  2767. I915_READ(ILK_DISPLAY_CHICKEN2) |
  2768. ILK_ELPIN_409_SELECT);
  2769. I915_WRITE(_3D_CHICKEN2,
  2770. _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
  2771. _3D_CHICKEN2_WM_READ_PIPELINED);
  2772. }
  2773. static void gen6_init_clock_gating(struct drm_device *dev)
  2774. {
  2775. struct drm_i915_private *dev_priv = dev->dev_private;
  2776. int pipe;
  2777. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  2778. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  2779. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  2780. I915_READ(ILK_DISPLAY_CHICKEN2) |
  2781. ILK_ELPIN_409_SELECT);
  2782. I915_WRITE(WM3_LP_ILK, 0);
  2783. I915_WRITE(WM2_LP_ILK, 0);
  2784. I915_WRITE(WM1_LP_ILK, 0);
  2785. I915_WRITE(CACHE_MODE_0,
  2786. _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
  2787. I915_WRITE(GEN6_UCGCTL1,
  2788. I915_READ(GEN6_UCGCTL1) |
  2789. GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
  2790. GEN6_CSUNIT_CLOCK_GATE_DISABLE);
  2791. /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  2792. * gating disable must be set. Failure to set it results in
  2793. * flickering pixels due to Z write ordering failures after
  2794. * some amount of runtime in the Mesa "fire" demo, and Unigine
  2795. * Sanctuary and Tropics, and apparently anything else with
  2796. * alpha test or pixel discard.
  2797. *
  2798. * According to the spec, bit 11 (RCCUNIT) must also be set,
  2799. * but we didn't debug actual testcases to find it out.
  2800. */
  2801. I915_WRITE(GEN6_UCGCTL2,
  2802. GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
  2803. GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  2804. /* Bspec says we need to always set all mask bits. */
  2805. I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
  2806. _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
  2807. /*
  2808. * According to the spec the following bits should be
  2809. * set in order to enable memory self-refresh and fbc:
  2810. * The bit21 and bit22 of 0x42000
  2811. * The bit21 and bit22 of 0x42004
  2812. * The bit5 and bit7 of 0x42020
  2813. * The bit14 of 0x70180
  2814. * The bit14 of 0x71180
  2815. */
  2816. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  2817. I915_READ(ILK_DISPLAY_CHICKEN1) |
  2818. ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
  2819. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  2820. I915_READ(ILK_DISPLAY_CHICKEN2) |
  2821. ILK_DPARB_GATE | ILK_VSDPFD_FULL);
  2822. I915_WRITE(ILK_DSPCLK_GATE,
  2823. I915_READ(ILK_DSPCLK_GATE) |
  2824. ILK_DPARB_CLK_GATE |
  2825. ILK_DPFD_CLK_GATE);
  2826. for_each_pipe(pipe) {
  2827. I915_WRITE(DSPCNTR(pipe),
  2828. I915_READ(DSPCNTR(pipe)) |
  2829. DISPPLANE_TRICKLE_FEED_DISABLE);
  2830. intel_flush_display_plane(dev_priv, pipe);
  2831. }
  2832. }
  2833. static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
  2834. {
  2835. uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
  2836. reg &= ~GEN7_FF_SCHED_MASK;
  2837. reg |= GEN7_FF_TS_SCHED_HW;
  2838. reg |= GEN7_FF_VS_SCHED_HW;
  2839. reg |= GEN7_FF_DS_SCHED_HW;
  2840. I915_WRITE(GEN7_FF_THREAD_MODE, reg);
  2841. }
  2842. static void ivybridge_init_clock_gating(struct drm_device *dev)
  2843. {
  2844. struct drm_i915_private *dev_priv = dev->dev_private;
  2845. int pipe;
  2846. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  2847. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  2848. I915_WRITE(WM3_LP_ILK, 0);
  2849. I915_WRITE(WM2_LP_ILK, 0);
  2850. I915_WRITE(WM1_LP_ILK, 0);
  2851. /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  2852. * This implements the WaDisableRCZUnitClockGating workaround.
  2853. */
  2854. I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
  2855. I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  2856. I915_WRITE(IVB_CHICKEN3,
  2857. CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  2858. CHICKEN3_DGMG_DONE_FIX_DISABLE);
  2859. /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
  2860. I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  2861. GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  2862. /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
  2863. I915_WRITE(GEN7_L3CNTLREG1,
  2864. GEN7_WA_FOR_GEN7_L3_CONTROL);
  2865. I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
  2866. GEN7_WA_L3_CHICKEN_MODE);
  2867. /* This is required by WaCatErrorRejectionIssue */
  2868. I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  2869. I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  2870. GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  2871. for_each_pipe(pipe) {
  2872. I915_WRITE(DSPCNTR(pipe),
  2873. I915_READ(DSPCNTR(pipe)) |
  2874. DISPPLANE_TRICKLE_FEED_DISABLE);
  2875. intel_flush_display_plane(dev_priv, pipe);
  2876. }
  2877. gen7_setup_fixed_func_scheduler(dev_priv);
  2878. /* WaDisable4x2SubspanOptimization */
  2879. I915_WRITE(CACHE_MODE_1,
  2880. _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  2881. }
  2882. static void valleyview_init_clock_gating(struct drm_device *dev)
  2883. {
  2884. struct drm_i915_private *dev_priv = dev->dev_private;
  2885. int pipe;
  2886. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  2887. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  2888. I915_WRITE(WM3_LP_ILK, 0);
  2889. I915_WRITE(WM2_LP_ILK, 0);
  2890. I915_WRITE(WM1_LP_ILK, 0);
  2891. /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  2892. * This implements the WaDisableRCZUnitClockGating workaround.
  2893. */
  2894. I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
  2895. I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  2896. I915_WRITE(IVB_CHICKEN3,
  2897. CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  2898. CHICKEN3_DGMG_DONE_FIX_DISABLE);
  2899. /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
  2900. I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  2901. GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  2902. /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
  2903. I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
  2904. I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
  2905. /* This is required by WaCatErrorRejectionIssue */
  2906. I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  2907. I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  2908. GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  2909. for_each_pipe(pipe) {
  2910. I915_WRITE(DSPCNTR(pipe),
  2911. I915_READ(DSPCNTR(pipe)) |
  2912. DISPPLANE_TRICKLE_FEED_DISABLE);
  2913. intel_flush_display_plane(dev_priv, pipe);
  2914. }
  2915. I915_WRITE(CACHE_MODE_1,
  2916. _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  2917. }
  2918. static void g4x_init_clock_gating(struct drm_device *dev)
  2919. {
  2920. struct drm_i915_private *dev_priv = dev->dev_private;
  2921. uint32_t dspclk_gate;
  2922. I915_WRITE(RENCLK_GATE_D1, 0);
  2923. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  2924. GS_UNIT_CLOCK_GATE_DISABLE |
  2925. CL_UNIT_CLOCK_GATE_DISABLE);
  2926. I915_WRITE(RAMCLK_GATE_D, 0);
  2927. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  2928. OVRUNIT_CLOCK_GATE_DISABLE |
  2929. OVCUNIT_CLOCK_GATE_DISABLE;
  2930. if (IS_GM45(dev))
  2931. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  2932. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  2933. }
  2934. static void crestline_init_clock_gating(struct drm_device *dev)
  2935. {
  2936. struct drm_i915_private *dev_priv = dev->dev_private;
  2937. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  2938. I915_WRITE(RENCLK_GATE_D2, 0);
  2939. I915_WRITE(DSPCLK_GATE_D, 0);
  2940. I915_WRITE(RAMCLK_GATE_D, 0);
  2941. I915_WRITE16(DEUC, 0);
  2942. }
  2943. static void broadwater_init_clock_gating(struct drm_device *dev)
  2944. {
  2945. struct drm_i915_private *dev_priv = dev->dev_private;
  2946. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  2947. I965_RCC_CLOCK_GATE_DISABLE |
  2948. I965_RCPB_CLOCK_GATE_DISABLE |
  2949. I965_ISC_CLOCK_GATE_DISABLE |
  2950. I965_FBC_CLOCK_GATE_DISABLE);
  2951. I915_WRITE(RENCLK_GATE_D2, 0);
  2952. }
  2953. static void gen3_init_clock_gating(struct drm_device *dev)
  2954. {
  2955. struct drm_i915_private *dev_priv = dev->dev_private;
  2956. u32 dstate = I915_READ(D_STATE);
  2957. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  2958. DSTATE_DOT_CLOCK_GATING;
  2959. I915_WRITE(D_STATE, dstate);
  2960. if (IS_PINEVIEW(dev))
  2961. I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
  2962. }
  2963. static void i85x_init_clock_gating(struct drm_device *dev)
  2964. {
  2965. struct drm_i915_private *dev_priv = dev->dev_private;
  2966. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  2967. }
  2968. static void i830_init_clock_gating(struct drm_device *dev)
  2969. {
  2970. struct drm_i915_private *dev_priv = dev->dev_private;
  2971. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  2972. }
  2973. static void ibx_init_clock_gating(struct drm_device *dev)
  2974. {
  2975. struct drm_i915_private *dev_priv = dev->dev_private;
  2976. /*
  2977. * On Ibex Peak and Cougar Point, we need to disable clock
  2978. * gating for the panel power sequencer or it will fail to
  2979. * start up when no ports are active.
  2980. */
  2981. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  2982. }
  2983. static void cpt_init_clock_gating(struct drm_device *dev)
  2984. {
  2985. struct drm_i915_private *dev_priv = dev->dev_private;
  2986. int pipe;
  2987. /*
  2988. * On Ibex Peak and Cougar Point, we need to disable clock
  2989. * gating for the panel power sequencer or it will fail to
  2990. * start up when no ports are active.
  2991. */
  2992. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  2993. I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
  2994. DPLS_EDP_PPS_FIX_DIS);
  2995. /* Without this, mode sets may fail silently on FDI */
  2996. for_each_pipe(pipe)
  2997. I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
  2998. }
  2999. void intel_init_clock_gating(struct drm_device *dev)
  3000. {
  3001. struct drm_i915_private *dev_priv = dev->dev_private;
  3002. dev_priv->display.init_clock_gating(dev);
  3003. if (dev_priv->display.init_pch_clock_gating)
  3004. dev_priv->display.init_pch_clock_gating(dev);
  3005. }
  3006. static void gen6_sanitize_pm(struct drm_device *dev)
  3007. {
  3008. struct drm_i915_private *dev_priv = dev->dev_private;
  3009. u32 limits, delay, old;
  3010. gen6_gt_force_wake_get(dev_priv);
  3011. old = limits = I915_READ(GEN6_RP_INTERRUPT_LIMITS);
  3012. /* Make sure we continue to get interrupts
  3013. * until we hit the minimum or maximum frequencies.
  3014. */
  3015. limits &= ~(0x3f << 16 | 0x3f << 24);
  3016. delay = dev_priv->cur_delay;
  3017. if (delay < dev_priv->max_delay)
  3018. limits |= (dev_priv->max_delay & 0x3f) << 24;
  3019. if (delay > dev_priv->min_delay)
  3020. limits |= (dev_priv->min_delay & 0x3f) << 16;
  3021. if (old != limits) {
  3022. DRM_ERROR("Power management discrepancy: GEN6_RP_INTERRUPT_LIMITS expected %08x, was %08x\n",
  3023. limits, old);
  3024. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
  3025. }
  3026. gen6_gt_force_wake_put(dev_priv);
  3027. }
  3028. void intel_sanitize_pm(struct drm_device *dev)
  3029. {
  3030. struct drm_i915_private *dev_priv = dev->dev_private;
  3031. if (dev_priv->display.sanitize_pm)
  3032. dev_priv->display.sanitize_pm(dev);
  3033. }
  3034. /* Starting with Haswell, we have different power wells for
  3035. * different parts of the GPU. This attempts to enable them all.
  3036. */
  3037. void intel_init_power_wells(struct drm_device *dev)
  3038. {
  3039. struct drm_i915_private *dev_priv = dev->dev_private;
  3040. unsigned long power_wells[] = {
  3041. HSW_PWR_WELL_CTL1,
  3042. HSW_PWR_WELL_CTL2,
  3043. HSW_PWR_WELL_CTL4
  3044. };
  3045. int i;
  3046. if (!IS_HASWELL(dev))
  3047. return;
  3048. mutex_lock(&dev->struct_mutex);
  3049. for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
  3050. int well = I915_READ(power_wells[i]);
  3051. if ((well & HSW_PWR_WELL_STATE) == 0) {
  3052. I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
  3053. if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
  3054. DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
  3055. }
  3056. }
  3057. mutex_unlock(&dev->struct_mutex);
  3058. }
  3059. /* Set up chip specific power management-related functions */
  3060. void intel_init_pm(struct drm_device *dev)
  3061. {
  3062. struct drm_i915_private *dev_priv = dev->dev_private;
  3063. if (I915_HAS_FBC(dev)) {
  3064. if (HAS_PCH_SPLIT(dev)) {
  3065. dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
  3066. dev_priv->display.enable_fbc = ironlake_enable_fbc;
  3067. dev_priv->display.disable_fbc = ironlake_disable_fbc;
  3068. } else if (IS_GM45(dev)) {
  3069. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  3070. dev_priv->display.enable_fbc = g4x_enable_fbc;
  3071. dev_priv->display.disable_fbc = g4x_disable_fbc;
  3072. } else if (IS_CRESTLINE(dev)) {
  3073. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  3074. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  3075. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  3076. }
  3077. /* 855GM needs testing */
  3078. }
  3079. /* For cxsr */
  3080. if (IS_PINEVIEW(dev))
  3081. i915_pineview_get_mem_freq(dev);
  3082. else if (IS_GEN5(dev))
  3083. i915_ironlake_get_mem_freq(dev);
  3084. /* For FIFO watermark updates */
  3085. if (HAS_PCH_SPLIT(dev)) {
  3086. dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
  3087. dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
  3088. /* IVB configs may use multi-threaded forcewake */
  3089. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  3090. u32 ecobus;
  3091. /* A small trick here - if the bios hasn't configured MT forcewake,
  3092. * and if the device is in RC6, then force_wake_mt_get will not wake
  3093. * the device and the ECOBUS read will return zero. Which will be
  3094. * (correctly) interpreted by the test below as MT forcewake being
  3095. * disabled.
  3096. */
  3097. mutex_lock(&dev->struct_mutex);
  3098. __gen6_gt_force_wake_mt_get(dev_priv);
  3099. ecobus = I915_READ_NOTRACE(ECOBUS);
  3100. __gen6_gt_force_wake_mt_put(dev_priv);
  3101. mutex_unlock(&dev->struct_mutex);
  3102. if (ecobus & FORCEWAKE_MT_ENABLE) {
  3103. DRM_DEBUG_KMS("Using MT version of forcewake\n");
  3104. dev_priv->display.force_wake_get =
  3105. __gen6_gt_force_wake_mt_get;
  3106. dev_priv->display.force_wake_put =
  3107. __gen6_gt_force_wake_mt_put;
  3108. }
  3109. }
  3110. if (HAS_PCH_IBX(dev))
  3111. dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
  3112. else if (HAS_PCH_CPT(dev))
  3113. dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
  3114. if (IS_GEN5(dev)) {
  3115. if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  3116. dev_priv->display.update_wm = ironlake_update_wm;
  3117. else {
  3118. DRM_DEBUG_KMS("Failed to get proper latency. "
  3119. "Disable CxSR\n");
  3120. dev_priv->display.update_wm = NULL;
  3121. }
  3122. dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
  3123. } else if (IS_GEN6(dev)) {
  3124. if (SNB_READ_WM0_LATENCY()) {
  3125. dev_priv->display.update_wm = sandybridge_update_wm;
  3126. dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  3127. } else {
  3128. DRM_DEBUG_KMS("Failed to read display plane latency. "
  3129. "Disable CxSR\n");
  3130. dev_priv->display.update_wm = NULL;
  3131. }
  3132. dev_priv->display.init_clock_gating = gen6_init_clock_gating;
  3133. dev_priv->display.sanitize_pm = gen6_sanitize_pm;
  3134. } else if (IS_IVYBRIDGE(dev)) {
  3135. /* FIXME: detect B0+ stepping and use auto training */
  3136. if (SNB_READ_WM0_LATENCY()) {
  3137. dev_priv->display.update_wm = sandybridge_update_wm;
  3138. dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  3139. } else {
  3140. DRM_DEBUG_KMS("Failed to read display plane latency. "
  3141. "Disable CxSR\n");
  3142. dev_priv->display.update_wm = NULL;
  3143. }
  3144. dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
  3145. dev_priv->display.sanitize_pm = gen6_sanitize_pm;
  3146. } else
  3147. dev_priv->display.update_wm = NULL;
  3148. } else if (IS_VALLEYVIEW(dev)) {
  3149. dev_priv->display.update_wm = valleyview_update_wm;
  3150. dev_priv->display.init_clock_gating =
  3151. valleyview_init_clock_gating;
  3152. dev_priv->display.force_wake_get = vlv_force_wake_get;
  3153. dev_priv->display.force_wake_put = vlv_force_wake_put;
  3154. } else if (IS_PINEVIEW(dev)) {
  3155. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  3156. dev_priv->is_ddr3,
  3157. dev_priv->fsb_freq,
  3158. dev_priv->mem_freq)) {
  3159. DRM_INFO("failed to find known CxSR latency "
  3160. "(found ddr%s fsb freq %d, mem freq %d), "
  3161. "disabling CxSR\n",
  3162. (dev_priv->is_ddr3 == 1) ? "3" : "2",
  3163. dev_priv->fsb_freq, dev_priv->mem_freq);
  3164. /* Disable CxSR and never update its watermark again */
  3165. pineview_disable_cxsr(dev);
  3166. dev_priv->display.update_wm = NULL;
  3167. } else
  3168. dev_priv->display.update_wm = pineview_update_wm;
  3169. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  3170. } else if (IS_G4X(dev)) {
  3171. dev_priv->display.update_wm = g4x_update_wm;
  3172. dev_priv->display.init_clock_gating = g4x_init_clock_gating;
  3173. } else if (IS_GEN4(dev)) {
  3174. dev_priv->display.update_wm = i965_update_wm;
  3175. if (IS_CRESTLINE(dev))
  3176. dev_priv->display.init_clock_gating = crestline_init_clock_gating;
  3177. else if (IS_BROADWATER(dev))
  3178. dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
  3179. } else if (IS_GEN3(dev)) {
  3180. dev_priv->display.update_wm = i9xx_update_wm;
  3181. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  3182. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  3183. } else if (IS_I865G(dev)) {
  3184. dev_priv->display.update_wm = i830_update_wm;
  3185. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  3186. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  3187. } else if (IS_I85X(dev)) {
  3188. dev_priv->display.update_wm = i9xx_update_wm;
  3189. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  3190. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  3191. } else {
  3192. dev_priv->display.update_wm = i830_update_wm;
  3193. dev_priv->display.init_clock_gating = i830_init_clock_gating;
  3194. if (IS_845G(dev))
  3195. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  3196. else
  3197. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  3198. }
  3199. /* We attempt to init the necessary power wells early in the initialization
  3200. * time, so the subsystems that expect power to be enabled can work.
  3201. */
  3202. intel_init_power_wells(dev);
  3203. }