oxygen_pcm.c 20 KB

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  1. /*
  2. * C-Media CMI8788 driver - PCM code
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2.
  9. *
  10. * This driver is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this driver; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <sound/driver.h>
  20. #include <linux/pci.h>
  21. #include <sound/control.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include "oxygen.h"
  26. static struct snd_pcm_hardware oxygen_hardware[PCM_COUNT] = {
  27. [PCM_A] = {
  28. .info = SNDRV_PCM_INFO_MMAP |
  29. SNDRV_PCM_INFO_MMAP_VALID |
  30. SNDRV_PCM_INFO_INTERLEAVED |
  31. SNDRV_PCM_INFO_PAUSE |
  32. SNDRV_PCM_INFO_SYNC_START,
  33. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  34. SNDRV_PCM_FMTBIT_S32_LE,
  35. .rates = SNDRV_PCM_RATE_44100 |
  36. SNDRV_PCM_RATE_48000 |
  37. SNDRV_PCM_RATE_96000 |
  38. SNDRV_PCM_RATE_192000,
  39. .rate_min = 44100,
  40. .rate_max = 192000,
  41. .channels_min = 2,
  42. .channels_max = 2,
  43. .buffer_bytes_max = 256 * 1024,
  44. .period_bytes_min = 128,
  45. .period_bytes_max = 128 * 1024,
  46. .periods_min = 2,
  47. .periods_max = 2048,
  48. },
  49. [PCM_B] = {
  50. .info = SNDRV_PCM_INFO_MMAP |
  51. SNDRV_PCM_INFO_MMAP_VALID |
  52. SNDRV_PCM_INFO_INTERLEAVED |
  53. SNDRV_PCM_INFO_PAUSE |
  54. SNDRV_PCM_INFO_SYNC_START,
  55. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  56. SNDRV_PCM_FMTBIT_S32_LE,
  57. .rates = SNDRV_PCM_RATE_32000 |
  58. SNDRV_PCM_RATE_44100 |
  59. SNDRV_PCM_RATE_48000 |
  60. SNDRV_PCM_RATE_64000 |
  61. SNDRV_PCM_RATE_88200 |
  62. SNDRV_PCM_RATE_96000 |
  63. SNDRV_PCM_RATE_176400 |
  64. SNDRV_PCM_RATE_192000,
  65. .rate_min = 32000,
  66. .rate_max = 192000,
  67. .channels_min = 2,
  68. .channels_max = 2,
  69. .buffer_bytes_max = 256 * 1024,
  70. .period_bytes_min = 128,
  71. .period_bytes_max = 128 * 1024,
  72. .periods_min = 2,
  73. .periods_max = 2048,
  74. },
  75. [PCM_C] = {
  76. .info = SNDRV_PCM_INFO_MMAP |
  77. SNDRV_PCM_INFO_MMAP_VALID |
  78. SNDRV_PCM_INFO_INTERLEAVED |
  79. SNDRV_PCM_INFO_PAUSE |
  80. SNDRV_PCM_INFO_SYNC_START,
  81. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  82. SNDRV_PCM_FMTBIT_S32_LE,
  83. .rates = SNDRV_PCM_RATE_44100 |
  84. SNDRV_PCM_RATE_48000 |
  85. SNDRV_PCM_RATE_88200 |
  86. SNDRV_PCM_RATE_96000,
  87. .rate_min = 44100,
  88. .rate_max = 96000,
  89. .channels_min = 2,
  90. .channels_max = 2,
  91. .buffer_bytes_max = 256 * 1024,
  92. .period_bytes_min = 128,
  93. .period_bytes_max = 128 * 1024,
  94. .periods_min = 2,
  95. .periods_max = 2048,
  96. },
  97. [PCM_SPDIF] = {
  98. .info = SNDRV_PCM_INFO_MMAP |
  99. SNDRV_PCM_INFO_MMAP_VALID |
  100. SNDRV_PCM_INFO_INTERLEAVED |
  101. SNDRV_PCM_INFO_PAUSE |
  102. SNDRV_PCM_INFO_SYNC_START,
  103. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  104. SNDRV_PCM_FMTBIT_S32_LE,
  105. .rates = SNDRV_PCM_RATE_32000 |
  106. SNDRV_PCM_RATE_44100 |
  107. SNDRV_PCM_RATE_48000 |
  108. SNDRV_PCM_RATE_64000 |
  109. SNDRV_PCM_RATE_88200 |
  110. SNDRV_PCM_RATE_96000 |
  111. SNDRV_PCM_RATE_176400 |
  112. SNDRV_PCM_RATE_192000,
  113. .rate_min = 32000,
  114. .rate_max = 192000,
  115. .channels_min = 2,
  116. .channels_max = 2,
  117. .buffer_bytes_max = 256 * 1024,
  118. .period_bytes_min = 128,
  119. .period_bytes_max = 128 * 1024,
  120. .periods_min = 2,
  121. .periods_max = 2048,
  122. },
  123. [PCM_MULTICH] = {
  124. .info = SNDRV_PCM_INFO_MMAP |
  125. SNDRV_PCM_INFO_MMAP_VALID |
  126. SNDRV_PCM_INFO_INTERLEAVED |
  127. SNDRV_PCM_INFO_PAUSE |
  128. SNDRV_PCM_INFO_SYNC_START,
  129. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  130. SNDRV_PCM_FMTBIT_S32_LE,
  131. .rates = SNDRV_PCM_RATE_32000 |
  132. SNDRV_PCM_RATE_44100 |
  133. SNDRV_PCM_RATE_48000 |
  134. SNDRV_PCM_RATE_64000 |
  135. SNDRV_PCM_RATE_88200 |
  136. SNDRV_PCM_RATE_96000 |
  137. SNDRV_PCM_RATE_176400 |
  138. SNDRV_PCM_RATE_192000,
  139. .rate_min = 32000,
  140. .rate_max = 192000,
  141. .channels_min = 2,
  142. .channels_max = 8,
  143. .buffer_bytes_max = 2048 * 1024,
  144. .period_bytes_min = 128,
  145. .period_bytes_max = 256 * 1024,
  146. .periods_min = 2,
  147. .periods_max = 16384,
  148. },
  149. [PCM_AC97] = {
  150. .info = SNDRV_PCM_INFO_MMAP |
  151. SNDRV_PCM_INFO_MMAP_VALID |
  152. SNDRV_PCM_INFO_INTERLEAVED |
  153. SNDRV_PCM_INFO_PAUSE |
  154. SNDRV_PCM_INFO_SYNC_START,
  155. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  156. .rates = SNDRV_PCM_RATE_48000,
  157. .rate_min = 48000,
  158. .rate_max = 48000,
  159. .channels_min = 2,
  160. .channels_max = 2,
  161. .buffer_bytes_max = 256 * 1024,
  162. .period_bytes_min = 128,
  163. .period_bytes_max = 128 * 1024,
  164. .periods_min = 2,
  165. .periods_max = 2048,
  166. },
  167. };
  168. static int oxygen_open(struct snd_pcm_substream *substream,
  169. unsigned int channel)
  170. {
  171. struct oxygen *chip = snd_pcm_substream_chip(substream);
  172. struct snd_pcm_runtime *runtime = substream->runtime;
  173. int err;
  174. runtime->private_data = (void *)channel;
  175. runtime->hw = oxygen_hardware[channel];
  176. err = snd_pcm_hw_constraint_step(runtime, 0,
  177. SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
  178. if (err < 0)
  179. return err;
  180. err = snd_pcm_hw_constraint_step(runtime, 0,
  181. SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
  182. if (err < 0)
  183. return err;
  184. if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
  185. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  186. if (err < 0)
  187. return err;
  188. }
  189. if (runtime->hw.channels_max > 2) {
  190. err = snd_pcm_hw_constraint_step(runtime, 0,
  191. SNDRV_PCM_HW_PARAM_CHANNELS,
  192. 2);
  193. if (err < 0)
  194. return err;
  195. }
  196. snd_pcm_set_sync(substream);
  197. chip->streams[channel] = substream;
  198. mutex_lock(&chip->mutex);
  199. chip->pcm_active |= 1 << channel;
  200. if (channel == PCM_SPDIF) {
  201. chip->spdif_pcm_bits = chip->spdif_bits;
  202. chip->spdif_pcm_ctl->vd[0].access &=
  203. ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  204. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  205. SNDRV_CTL_EVENT_MASK_INFO,
  206. &chip->spdif_pcm_ctl->id);
  207. }
  208. mutex_unlock(&chip->mutex);
  209. return 0;
  210. }
  211. static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
  212. {
  213. return oxygen_open(substream, PCM_A);
  214. }
  215. static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
  216. {
  217. return oxygen_open(substream, PCM_B);
  218. }
  219. static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
  220. {
  221. return oxygen_open(substream, PCM_C);
  222. }
  223. static int oxygen_spdif_open(struct snd_pcm_substream *substream)
  224. {
  225. return oxygen_open(substream, PCM_SPDIF);
  226. }
  227. static int oxygen_multich_open(struct snd_pcm_substream *substream)
  228. {
  229. return oxygen_open(substream, PCM_MULTICH);
  230. }
  231. static int oxygen_ac97_open(struct snd_pcm_substream *substream)
  232. {
  233. return oxygen_open(substream, PCM_AC97);
  234. }
  235. static int oxygen_close(struct snd_pcm_substream *substream)
  236. {
  237. struct oxygen *chip = snd_pcm_substream_chip(substream);
  238. unsigned int channel = (unsigned int)substream->runtime->private_data;
  239. mutex_lock(&chip->mutex);
  240. chip->pcm_active &= ~(1 << channel);
  241. if (channel == PCM_SPDIF) {
  242. chip->spdif_pcm_ctl->vd[0].access |=
  243. SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  244. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  245. SNDRV_CTL_EVENT_MASK_INFO,
  246. &chip->spdif_pcm_ctl->id);
  247. }
  248. if (channel == PCM_SPDIF || channel == PCM_MULTICH)
  249. oxygen_update_spdif_source(chip);
  250. mutex_unlock(&chip->mutex);
  251. chip->streams[channel] = NULL;
  252. return 0;
  253. }
  254. static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
  255. {
  256. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  257. return OXYGEN_FORMAT_24;
  258. else
  259. return OXYGEN_FORMAT_16;
  260. }
  261. static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
  262. {
  263. switch (params_rate(hw_params)) {
  264. case 32000:
  265. return OXYGEN_RATE_32000;
  266. case 44100:
  267. return OXYGEN_RATE_44100;
  268. default: /* 48000 */
  269. return OXYGEN_RATE_48000;
  270. case 64000:
  271. return OXYGEN_RATE_64000;
  272. case 88200:
  273. return OXYGEN_RATE_88200;
  274. case 96000:
  275. return OXYGEN_RATE_96000;
  276. case 176400:
  277. return OXYGEN_RATE_176400;
  278. case 192000:
  279. return OXYGEN_RATE_192000;
  280. }
  281. }
  282. static unsigned int oxygen_i2s_magic2(struct snd_pcm_hw_params *hw_params)
  283. {
  284. return params_rate(hw_params) <= 96000 ? 0x10 : 0x00;
  285. }
  286. static unsigned int oxygen_i2s_format(struct snd_pcm_hw_params *hw_params)
  287. {
  288. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  289. return OXYGEN_I2S_FORMAT_24;
  290. else
  291. return OXYGEN_I2S_FORMAT_16;
  292. }
  293. static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
  294. {
  295. switch (params_channels(hw_params)) {
  296. default: /* 2 */
  297. return OXYGEN_PLAY_CHANNELS_2;
  298. case 4:
  299. return OXYGEN_PLAY_CHANNELS_4;
  300. case 6:
  301. return OXYGEN_PLAY_CHANNELS_6;
  302. case 8:
  303. return OXYGEN_PLAY_CHANNELS_8;
  304. }
  305. }
  306. static const unsigned int channel_base_registers[PCM_COUNT] = {
  307. [PCM_A] = OXYGEN_DMA_A_ADDRESS,
  308. [PCM_B] = OXYGEN_DMA_B_ADDRESS,
  309. [PCM_C] = OXYGEN_DMA_C_ADDRESS,
  310. [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
  311. [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
  312. [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
  313. };
  314. static int oxygen_hw_params(struct snd_pcm_substream *substream,
  315. struct snd_pcm_hw_params *hw_params)
  316. {
  317. struct oxygen *chip = snd_pcm_substream_chip(substream);
  318. unsigned int channel = (unsigned int)substream->runtime->private_data;
  319. int err;
  320. err = snd_pcm_lib_malloc_pages(substream,
  321. params_buffer_bytes(hw_params));
  322. if (err < 0)
  323. return err;
  324. oxygen_write32(chip, channel_base_registers[channel],
  325. (u32)substream->runtime->dma_addr);
  326. if (channel == PCM_MULTICH) {
  327. oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
  328. params_buffer_bytes(hw_params) / 4 - 1);
  329. oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
  330. params_period_bytes(hw_params) / 4 - 1);
  331. } else {
  332. oxygen_write16(chip, channel_base_registers[channel] + 4,
  333. params_buffer_bytes(hw_params) / 4 - 1);
  334. oxygen_write16(chip, channel_base_registers[channel] + 6,
  335. params_period_bytes(hw_params) / 4 - 1);
  336. }
  337. return 0;
  338. }
  339. static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
  340. struct snd_pcm_hw_params *hw_params)
  341. {
  342. struct oxygen *chip = snd_pcm_substream_chip(substream);
  343. int err;
  344. err = oxygen_hw_params(substream, hw_params);
  345. if (err < 0)
  346. return err;
  347. spin_lock_irq(&chip->reg_lock);
  348. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  349. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
  350. OXYGEN_REC_FORMAT_A_MASK);
  351. oxygen_write8_masked(chip, OXYGEN_I2S_A_FORMAT,
  352. oxygen_rate(hw_params) |
  353. oxygen_i2s_magic2(hw_params) |
  354. oxygen_i2s_format(hw_params),
  355. OXYGEN_I2S_RATE_MASK |
  356. OXYGEN_I2S_MAGIC2_MASK |
  357. OXYGEN_I2S_FORMAT_MASK);
  358. oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x08);
  359. spin_unlock_irq(&chip->reg_lock);
  360. mutex_lock(&chip->mutex);
  361. chip->model->set_adc_params(chip, hw_params);
  362. mutex_unlock(&chip->mutex);
  363. return 0;
  364. }
  365. static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
  366. struct snd_pcm_hw_params *hw_params)
  367. {
  368. struct oxygen *chip = snd_pcm_substream_chip(substream);
  369. int err;
  370. err = oxygen_hw_params(substream, hw_params);
  371. if (err < 0)
  372. return err;
  373. spin_lock_irq(&chip->reg_lock);
  374. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  375. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
  376. OXYGEN_REC_FORMAT_B_MASK);
  377. oxygen_write8_masked(chip, OXYGEN_I2S_B_FORMAT,
  378. oxygen_rate(hw_params) |
  379. oxygen_i2s_magic2(hw_params) |
  380. oxygen_i2s_format(hw_params),
  381. OXYGEN_I2S_RATE_MASK |
  382. OXYGEN_I2S_MAGIC2_MASK |
  383. OXYGEN_I2S_FORMAT_MASK);
  384. oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x10);
  385. spin_unlock_irq(&chip->reg_lock);
  386. mutex_lock(&chip->mutex);
  387. chip->model->set_adc_params(chip, hw_params);
  388. mutex_unlock(&chip->mutex);
  389. return 0;
  390. }
  391. static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
  392. struct snd_pcm_hw_params *hw_params)
  393. {
  394. struct oxygen *chip = snd_pcm_substream_chip(substream);
  395. int err;
  396. err = oxygen_hw_params(substream, hw_params);
  397. if (err < 0)
  398. return err;
  399. spin_lock_irq(&chip->reg_lock);
  400. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  401. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
  402. OXYGEN_REC_FORMAT_C_MASK);
  403. oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x20);
  404. spin_unlock_irq(&chip->reg_lock);
  405. return 0;
  406. }
  407. static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
  408. struct snd_pcm_hw_params *hw_params)
  409. {
  410. struct oxygen *chip = snd_pcm_substream_chip(substream);
  411. int err;
  412. err = oxygen_hw_params(substream, hw_params);
  413. if (err < 0)
  414. return err;
  415. spin_lock_irq(&chip->reg_lock);
  416. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  417. OXYGEN_SPDIF_OUT_ENABLE);
  418. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  419. oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
  420. OXYGEN_SPDIF_FORMAT_MASK);
  421. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  422. oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
  423. OXYGEN_SPDIF_OUT_RATE_MASK);
  424. oxygen_update_spdif_source(chip);
  425. spin_unlock_irq(&chip->reg_lock);
  426. return 0;
  427. }
  428. static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
  429. struct snd_pcm_hw_params *hw_params)
  430. {
  431. struct oxygen *chip = snd_pcm_substream_chip(substream);
  432. int err;
  433. err = oxygen_hw_params(substream, hw_params);
  434. if (err < 0)
  435. return err;
  436. spin_lock_irq(&chip->reg_lock);
  437. oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
  438. oxygen_play_channels(hw_params),
  439. OXYGEN_PLAY_CHANNELS_MASK);
  440. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  441. oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
  442. OXYGEN_MULTICH_FORMAT_MASK);
  443. oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
  444. oxygen_rate(hw_params) | oxygen_i2s_format(hw_params),
  445. OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_FORMAT_MASK);
  446. oxygen_clear_bits16(chip, OXYGEN_PLAY_ROUTING, 0x001f);
  447. oxygen_update_dac_routing(chip);
  448. oxygen_update_spdif_source(chip);
  449. spin_unlock_irq(&chip->reg_lock);
  450. mutex_lock(&chip->mutex);
  451. chip->model->set_dac_params(chip, hw_params);
  452. mutex_unlock(&chip->mutex);
  453. return 0;
  454. }
  455. static int oxygen_ac97_hw_params(struct snd_pcm_substream *substream,
  456. struct snd_pcm_hw_params *hw_params)
  457. {
  458. struct oxygen *chip = snd_pcm_substream_chip(substream);
  459. int err;
  460. err = oxygen_hw_params(substream, hw_params);
  461. if (err < 0)
  462. return err;
  463. spin_lock_irq(&chip->reg_lock);
  464. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  465. oxygen_format(hw_params) << OXYGEN_AC97_FORMAT_SHIFT,
  466. OXYGEN_AC97_FORMAT_MASK);
  467. spin_unlock_irq(&chip->reg_lock);
  468. return 0;
  469. }
  470. static int oxygen_hw_free(struct snd_pcm_substream *substream)
  471. {
  472. struct oxygen *chip = snd_pcm_substream_chip(substream);
  473. unsigned int channel = (unsigned int)substream->runtime->private_data;
  474. spin_lock_irq(&chip->reg_lock);
  475. chip->interrupt_mask &= ~(1 << channel);
  476. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  477. spin_unlock_irq(&chip->reg_lock);
  478. return snd_pcm_lib_free_pages(substream);
  479. }
  480. static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
  481. {
  482. struct oxygen *chip = snd_pcm_substream_chip(substream);
  483. spin_lock_irq(&chip->reg_lock);
  484. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  485. OXYGEN_SPDIF_OUT_ENABLE);
  486. spin_unlock_irq(&chip->reg_lock);
  487. return oxygen_hw_free(substream);
  488. }
  489. static int oxygen_prepare(struct snd_pcm_substream *substream)
  490. {
  491. struct oxygen *chip = snd_pcm_substream_chip(substream);
  492. unsigned int channel = (unsigned int)substream->runtime->private_data;
  493. unsigned int channel_mask = 1 << channel;
  494. spin_lock_irq(&chip->reg_lock);
  495. oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  496. oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  497. chip->interrupt_mask |= channel_mask;
  498. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  499. spin_unlock_irq(&chip->reg_lock);
  500. return 0;
  501. }
  502. static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
  503. {
  504. struct oxygen *chip = snd_pcm_substream_chip(substream);
  505. struct snd_pcm_substream *s;
  506. unsigned int mask = 0;
  507. int running;
  508. switch (cmd) {
  509. case SNDRV_PCM_TRIGGER_STOP:
  510. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  511. running = 0;
  512. break;
  513. case SNDRV_PCM_TRIGGER_START:
  514. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  515. running = 1;
  516. break;
  517. default:
  518. return -EINVAL;
  519. }
  520. snd_pcm_group_for_each_entry(s, substream) {
  521. if (snd_pcm_substream_chip(s) == chip) {
  522. mask |= 1 << (unsigned int)s->runtime->private_data;
  523. snd_pcm_trigger_done(s, substream);
  524. }
  525. }
  526. spin_lock(&chip->reg_lock);
  527. if (running)
  528. chip->pcm_running |= mask;
  529. else
  530. chip->pcm_running &= ~mask;
  531. oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
  532. spin_unlock(&chip->reg_lock);
  533. return 0;
  534. }
  535. static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
  536. {
  537. struct oxygen *chip = snd_pcm_substream_chip(substream);
  538. struct snd_pcm_runtime *runtime = substream->runtime;
  539. unsigned int channel = (unsigned int)runtime->private_data;
  540. u32 curr_addr;
  541. /* no spinlock, this read should be atomic */
  542. curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
  543. return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
  544. }
  545. static struct snd_pcm_ops oxygen_rec_a_ops = {
  546. .open = oxygen_rec_a_open,
  547. .close = oxygen_close,
  548. .ioctl = snd_pcm_lib_ioctl,
  549. .hw_params = oxygen_rec_a_hw_params,
  550. .hw_free = oxygen_hw_free,
  551. .prepare = oxygen_prepare,
  552. .trigger = oxygen_trigger,
  553. .pointer = oxygen_pointer,
  554. };
  555. static struct snd_pcm_ops oxygen_rec_b_ops = {
  556. .open = oxygen_rec_b_open,
  557. .close = oxygen_close,
  558. .ioctl = snd_pcm_lib_ioctl,
  559. .hw_params = oxygen_rec_b_hw_params,
  560. .hw_free = oxygen_hw_free,
  561. .prepare = oxygen_prepare,
  562. .trigger = oxygen_trigger,
  563. .pointer = oxygen_pointer,
  564. };
  565. static struct snd_pcm_ops oxygen_rec_c_ops = {
  566. .open = oxygen_rec_c_open,
  567. .close = oxygen_close,
  568. .ioctl = snd_pcm_lib_ioctl,
  569. .hw_params = oxygen_rec_c_hw_params,
  570. .hw_free = oxygen_hw_free,
  571. .prepare = oxygen_prepare,
  572. .trigger = oxygen_trigger,
  573. .pointer = oxygen_pointer,
  574. };
  575. static struct snd_pcm_ops oxygen_spdif_ops = {
  576. .open = oxygen_spdif_open,
  577. .close = oxygen_close,
  578. .ioctl = snd_pcm_lib_ioctl,
  579. .hw_params = oxygen_spdif_hw_params,
  580. .hw_free = oxygen_spdif_hw_free,
  581. .prepare = oxygen_prepare,
  582. .trigger = oxygen_trigger,
  583. .pointer = oxygen_pointer,
  584. };
  585. static struct snd_pcm_ops oxygen_multich_ops = {
  586. .open = oxygen_multich_open,
  587. .close = oxygen_close,
  588. .ioctl = snd_pcm_lib_ioctl,
  589. .hw_params = oxygen_multich_hw_params,
  590. .hw_free = oxygen_hw_free,
  591. .prepare = oxygen_prepare,
  592. .trigger = oxygen_trigger,
  593. .pointer = oxygen_pointer,
  594. };
  595. static struct snd_pcm_ops oxygen_ac97_ops = {
  596. .open = oxygen_ac97_open,
  597. .close = oxygen_close,
  598. .ioctl = snd_pcm_lib_ioctl,
  599. .hw_params = oxygen_ac97_hw_params,
  600. .hw_free = oxygen_hw_free,
  601. .prepare = oxygen_prepare,
  602. .trigger = oxygen_trigger,
  603. .pointer = oxygen_pointer,
  604. };
  605. static void oxygen_pcm_free(struct snd_pcm *pcm)
  606. {
  607. snd_pcm_lib_preallocate_free_for_all(pcm);
  608. }
  609. int __devinit oxygen_pcm_init(struct oxygen *chip)
  610. {
  611. struct snd_pcm *pcm;
  612. int err;
  613. err = snd_pcm_new(chip->card, "Analog", 0, 1, 1, &pcm);
  614. if (err < 0)
  615. return err;
  616. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_multich_ops);
  617. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  618. chip->model->record_from_dma_b ?
  619. &oxygen_rec_b_ops : &oxygen_rec_a_ops);
  620. pcm->private_data = chip;
  621. pcm->private_free = oxygen_pcm_free;
  622. strcpy(pcm->name, "Analog");
  623. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
  624. SNDRV_DMA_TYPE_DEV,
  625. snd_dma_pci_data(chip->pci),
  626. 512 * 1024, 2048 * 1024);
  627. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
  628. SNDRV_DMA_TYPE_DEV,
  629. snd_dma_pci_data(chip->pci),
  630. 128 * 1024, 256 * 1024);
  631. err = snd_pcm_new(chip->card, "Digital", 1, 1, 1, &pcm);
  632. if (err < 0)
  633. return err;
  634. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_spdif_ops);
  635. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_c_ops);
  636. pcm->private_data = chip;
  637. pcm->private_free = oxygen_pcm_free;
  638. strcpy(pcm->name, "Digital");
  639. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  640. snd_dma_pci_data(chip->pci),
  641. 128 * 1024, 256 * 1024);
  642. if (chip->has_2nd_ac97_codec) {
  643. err = snd_pcm_new(chip->card, "AC97", 2, 1, 0, &pcm);
  644. if (err < 0)
  645. return err;
  646. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  647. &oxygen_ac97_ops);
  648. pcm->private_data = chip;
  649. pcm->private_free = oxygen_pcm_free;
  650. strcpy(pcm->name, "Front Panel");
  651. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  652. snd_dma_pci_data(chip->pci),
  653. 128 * 1024, 256 * 1024);
  654. }
  655. return 0;
  656. }