main.c 105 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921
  1. /*
  2. *
  3. * Broadcom B43legacy wireless driver
  4. *
  5. * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
  7. * Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
  8. * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
  9. * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10. * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
  11. *
  12. * Some parts of the code in this file are derived from the ipw2200
  13. * driver Copyright(c) 2003 - 2004 Intel Corporation.
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; see the file COPYING. If not, write to
  26. * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27. * Boston, MA 02110-1301, USA.
  28. *
  29. */
  30. #include <linux/delay.h>
  31. #include <linux/init.h>
  32. #include <linux/moduleparam.h>
  33. #include <linux/if_arp.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/version.h>
  36. #include <linux/firmware.h>
  37. #include <linux/wireless.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/dma-mapping.h>
  41. #include <net/dst.h>
  42. #include <asm/unaligned.h>
  43. #include "b43legacy.h"
  44. #include "main.h"
  45. #include "debugfs.h"
  46. #include "phy.h"
  47. #include "dma.h"
  48. #include "pio.h"
  49. #include "sysfs.h"
  50. #include "xmit.h"
  51. #include "radio.h"
  52. MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
  53. MODULE_AUTHOR("Martin Langer");
  54. MODULE_AUTHOR("Stefano Brivio");
  55. MODULE_AUTHOR("Michael Buesch");
  56. MODULE_LICENSE("GPL");
  57. MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
  58. #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
  59. static int modparam_pio;
  60. module_param_named(pio, modparam_pio, int, 0444);
  61. MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  62. #elif defined(CONFIG_B43LEGACY_DMA)
  63. # define modparam_pio 0
  64. #elif defined(CONFIG_B43LEGACY_PIO)
  65. # define modparam_pio 1
  66. #endif
  67. static int modparam_bad_frames_preempt;
  68. module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  69. MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
  70. " Preemption");
  71. static char modparam_fwpostfix[16];
  72. module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  73. MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
  74. /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
  75. static const struct ssb_device_id b43legacy_ssb_tbl[] = {
  76. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
  77. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
  78. SSB_DEVTABLE_END
  79. };
  80. MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
  81. /* Channel and ratetables are shared for all devices.
  82. * They can't be const, because ieee80211 puts some precalculated
  83. * data in there. This data is the same for all devices, so we don't
  84. * get concurrency issues */
  85. #define RATETAB_ENT(_rateid, _flags) \
  86. { \
  87. .bitrate = B43legacy_RATE_TO_100KBPS(_rateid), \
  88. .hw_value = (_rateid), \
  89. .flags = (_flags), \
  90. }
  91. /*
  92. * NOTE: When changing this, sync with xmit.c's
  93. * b43legacy_plcp_get_bitrate_idx_* functions!
  94. */
  95. static struct ieee80211_rate __b43legacy_ratetable[] = {
  96. RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
  97. RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
  98. RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
  99. RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
  100. RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
  101. RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
  102. RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
  103. RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
  104. RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
  105. RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
  106. RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
  107. RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
  108. };
  109. #define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
  110. #define b43legacy_b_ratetable_size 4
  111. #define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
  112. #define b43legacy_g_ratetable_size 12
  113. #define CHANTAB_ENT(_chanid, _freq) \
  114. { \
  115. .center_freq = (_freq), \
  116. .hw_value = (_chanid), \
  117. }
  118. static struct ieee80211_channel b43legacy_bg_chantable[] = {
  119. CHANTAB_ENT(1, 2412),
  120. CHANTAB_ENT(2, 2417),
  121. CHANTAB_ENT(3, 2422),
  122. CHANTAB_ENT(4, 2427),
  123. CHANTAB_ENT(5, 2432),
  124. CHANTAB_ENT(6, 2437),
  125. CHANTAB_ENT(7, 2442),
  126. CHANTAB_ENT(8, 2447),
  127. CHANTAB_ENT(9, 2452),
  128. CHANTAB_ENT(10, 2457),
  129. CHANTAB_ENT(11, 2462),
  130. CHANTAB_ENT(12, 2467),
  131. CHANTAB_ENT(13, 2472),
  132. CHANTAB_ENT(14, 2484),
  133. };
  134. static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
  135. .channels = b43legacy_bg_chantable,
  136. .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
  137. .bitrates = b43legacy_b_ratetable,
  138. .n_bitrates = b43legacy_b_ratetable_size,
  139. };
  140. static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
  141. .channels = b43legacy_bg_chantable,
  142. .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
  143. .bitrates = b43legacy_g_ratetable,
  144. .n_bitrates = b43legacy_g_ratetable_size,
  145. };
  146. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
  147. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
  148. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
  149. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
  150. static int b43legacy_ratelimit(struct b43legacy_wl *wl)
  151. {
  152. if (!wl || !wl->current_dev)
  153. return 1;
  154. if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
  155. return 1;
  156. /* We are up and running.
  157. * Ratelimit the messages to avoid DoS over the net. */
  158. return net_ratelimit();
  159. }
  160. void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
  161. {
  162. va_list args;
  163. if (!b43legacy_ratelimit(wl))
  164. return;
  165. va_start(args, fmt);
  166. printk(KERN_INFO "b43legacy-%s: ",
  167. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  168. vprintk(fmt, args);
  169. va_end(args);
  170. }
  171. void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
  172. {
  173. va_list args;
  174. if (!b43legacy_ratelimit(wl))
  175. return;
  176. va_start(args, fmt);
  177. printk(KERN_ERR "b43legacy-%s ERROR: ",
  178. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  179. vprintk(fmt, args);
  180. va_end(args);
  181. }
  182. void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
  183. {
  184. va_list args;
  185. if (!b43legacy_ratelimit(wl))
  186. return;
  187. va_start(args, fmt);
  188. printk(KERN_WARNING "b43legacy-%s warning: ",
  189. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  190. vprintk(fmt, args);
  191. va_end(args);
  192. }
  193. #if B43legacy_DEBUG
  194. void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
  195. {
  196. va_list args;
  197. va_start(args, fmt);
  198. printk(KERN_DEBUG "b43legacy-%s debug: ",
  199. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  200. vprintk(fmt, args);
  201. va_end(args);
  202. }
  203. #endif /* DEBUG */
  204. static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
  205. u32 val)
  206. {
  207. u32 status;
  208. B43legacy_WARN_ON(offset % 4 != 0);
  209. status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  210. if (status & B43legacy_MACCTL_BE)
  211. val = swab32(val);
  212. b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
  213. mmiowb();
  214. b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
  215. }
  216. static inline
  217. void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
  218. u16 routing, u16 offset)
  219. {
  220. u32 control;
  221. /* "offset" is the WORD offset. */
  222. control = routing;
  223. control <<= 16;
  224. control |= offset;
  225. b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
  226. }
  227. u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
  228. u16 routing, u16 offset)
  229. {
  230. u32 ret;
  231. if (routing == B43legacy_SHM_SHARED) {
  232. B43legacy_WARN_ON((offset & 0x0001) != 0);
  233. if (offset & 0x0003) {
  234. /* Unaligned access */
  235. b43legacy_shm_control_word(dev, routing, offset >> 2);
  236. ret = b43legacy_read16(dev,
  237. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  238. ret <<= 16;
  239. b43legacy_shm_control_word(dev, routing,
  240. (offset >> 2) + 1);
  241. ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  242. return ret;
  243. }
  244. offset >>= 2;
  245. }
  246. b43legacy_shm_control_word(dev, routing, offset);
  247. ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
  248. return ret;
  249. }
  250. u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
  251. u16 routing, u16 offset)
  252. {
  253. u16 ret;
  254. if (routing == B43legacy_SHM_SHARED) {
  255. B43legacy_WARN_ON((offset & 0x0001) != 0);
  256. if (offset & 0x0003) {
  257. /* Unaligned access */
  258. b43legacy_shm_control_word(dev, routing, offset >> 2);
  259. ret = b43legacy_read16(dev,
  260. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  261. return ret;
  262. }
  263. offset >>= 2;
  264. }
  265. b43legacy_shm_control_word(dev, routing, offset);
  266. ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  267. return ret;
  268. }
  269. void b43legacy_shm_write32(struct b43legacy_wldev *dev,
  270. u16 routing, u16 offset,
  271. u32 value)
  272. {
  273. if (routing == B43legacy_SHM_SHARED) {
  274. B43legacy_WARN_ON((offset & 0x0001) != 0);
  275. if (offset & 0x0003) {
  276. /* Unaligned access */
  277. b43legacy_shm_control_word(dev, routing, offset >> 2);
  278. mmiowb();
  279. b43legacy_write16(dev,
  280. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  281. (value >> 16) & 0xffff);
  282. mmiowb();
  283. b43legacy_shm_control_word(dev, routing,
  284. (offset >> 2) + 1);
  285. mmiowb();
  286. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
  287. value & 0xffff);
  288. return;
  289. }
  290. offset >>= 2;
  291. }
  292. b43legacy_shm_control_word(dev, routing, offset);
  293. mmiowb();
  294. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
  295. }
  296. void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
  297. u16 value)
  298. {
  299. if (routing == B43legacy_SHM_SHARED) {
  300. B43legacy_WARN_ON((offset & 0x0001) != 0);
  301. if (offset & 0x0003) {
  302. /* Unaligned access */
  303. b43legacy_shm_control_word(dev, routing, offset >> 2);
  304. mmiowb();
  305. b43legacy_write16(dev,
  306. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  307. value);
  308. return;
  309. }
  310. offset >>= 2;
  311. }
  312. b43legacy_shm_control_word(dev, routing, offset);
  313. mmiowb();
  314. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
  315. }
  316. /* Read HostFlags */
  317. u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
  318. {
  319. u32 ret;
  320. ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  321. B43legacy_SHM_SH_HOSTFHI);
  322. ret <<= 16;
  323. ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  324. B43legacy_SHM_SH_HOSTFLO);
  325. return ret;
  326. }
  327. /* Write HostFlags */
  328. void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
  329. {
  330. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  331. B43legacy_SHM_SH_HOSTFLO,
  332. (value & 0x0000FFFF));
  333. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  334. B43legacy_SHM_SH_HOSTFHI,
  335. ((value & 0xFFFF0000) >> 16));
  336. }
  337. void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
  338. {
  339. /* We need to be careful. As we read the TSF from multiple
  340. * registers, we should take care of register overflows.
  341. * In theory, the whole tsf read process should be atomic.
  342. * We try to be atomic here, by restaring the read process,
  343. * if any of the high registers changed (overflew).
  344. */
  345. if (dev->dev->id.revision >= 3) {
  346. u32 low;
  347. u32 high;
  348. u32 high2;
  349. do {
  350. high = b43legacy_read32(dev,
  351. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  352. low = b43legacy_read32(dev,
  353. B43legacy_MMIO_REV3PLUS_TSF_LOW);
  354. high2 = b43legacy_read32(dev,
  355. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  356. } while (unlikely(high != high2));
  357. *tsf = high;
  358. *tsf <<= 32;
  359. *tsf |= low;
  360. } else {
  361. u64 tmp;
  362. u16 v0;
  363. u16 v1;
  364. u16 v2;
  365. u16 v3;
  366. u16 test1;
  367. u16 test2;
  368. u16 test3;
  369. do {
  370. v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  371. v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  372. v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  373. v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
  374. test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  375. test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  376. test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  377. } while (v3 != test3 || v2 != test2 || v1 != test1);
  378. *tsf = v3;
  379. *tsf <<= 48;
  380. tmp = v2;
  381. tmp <<= 32;
  382. *tsf |= tmp;
  383. tmp = v1;
  384. tmp <<= 16;
  385. *tsf |= tmp;
  386. *tsf |= v0;
  387. }
  388. }
  389. static void b43legacy_time_lock(struct b43legacy_wldev *dev)
  390. {
  391. u32 status;
  392. status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  393. status |= B43legacy_MACCTL_TBTTHOLD;
  394. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
  395. mmiowb();
  396. }
  397. static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
  398. {
  399. u32 status;
  400. status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  401. status &= ~B43legacy_MACCTL_TBTTHOLD;
  402. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
  403. }
  404. static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
  405. {
  406. /* Be careful with the in-progress timer.
  407. * First zero out the low register, so we have a full
  408. * register-overflow duration to complete the operation.
  409. */
  410. if (dev->dev->id.revision >= 3) {
  411. u32 lo = (tsf & 0x00000000FFFFFFFFULL);
  412. u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
  413. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
  414. mmiowb();
  415. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
  416. hi);
  417. mmiowb();
  418. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
  419. lo);
  420. } else {
  421. u16 v0 = (tsf & 0x000000000000FFFFULL);
  422. u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
  423. u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
  424. u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
  425. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
  426. mmiowb();
  427. b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
  428. mmiowb();
  429. b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
  430. mmiowb();
  431. b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
  432. mmiowb();
  433. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
  434. }
  435. }
  436. void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
  437. {
  438. b43legacy_time_lock(dev);
  439. b43legacy_tsf_write_locked(dev, tsf);
  440. b43legacy_time_unlock(dev);
  441. }
  442. static
  443. void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
  444. u16 offset, const u8 *mac)
  445. {
  446. static const u8 zero_addr[ETH_ALEN] = { 0 };
  447. u16 data;
  448. if (!mac)
  449. mac = zero_addr;
  450. offset |= 0x0020;
  451. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
  452. data = mac[0];
  453. data |= mac[1] << 8;
  454. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  455. data = mac[2];
  456. data |= mac[3] << 8;
  457. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  458. data = mac[4];
  459. data |= mac[5] << 8;
  460. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  461. }
  462. static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
  463. {
  464. static const u8 zero_addr[ETH_ALEN] = { 0 };
  465. const u8 *mac = dev->wl->mac_addr;
  466. const u8 *bssid = dev->wl->bssid;
  467. u8 mac_bssid[ETH_ALEN * 2];
  468. int i;
  469. u32 tmp;
  470. if (!bssid)
  471. bssid = zero_addr;
  472. if (!mac)
  473. mac = zero_addr;
  474. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
  475. memcpy(mac_bssid, mac, ETH_ALEN);
  476. memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
  477. /* Write our MAC address and BSSID to template ram */
  478. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
  479. tmp = (u32)(mac_bssid[i + 0]);
  480. tmp |= (u32)(mac_bssid[i + 1]) << 8;
  481. tmp |= (u32)(mac_bssid[i + 2]) << 16;
  482. tmp |= (u32)(mac_bssid[i + 3]) << 24;
  483. b43legacy_ram_write(dev, 0x20 + i, tmp);
  484. b43legacy_ram_write(dev, 0x78 + i, tmp);
  485. b43legacy_ram_write(dev, 0x478 + i, tmp);
  486. }
  487. }
  488. static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
  489. {
  490. b43legacy_write_mac_bssid_templates(dev);
  491. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
  492. dev->wl->mac_addr);
  493. }
  494. static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
  495. u16 slot_time)
  496. {
  497. /* slot_time is in usec. */
  498. if (dev->phy.type != B43legacy_PHYTYPE_G)
  499. return;
  500. b43legacy_write16(dev, 0x684, 510 + slot_time);
  501. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
  502. slot_time);
  503. }
  504. static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
  505. {
  506. b43legacy_set_slot_time(dev, 9);
  507. dev->short_slot = 1;
  508. }
  509. static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
  510. {
  511. b43legacy_set_slot_time(dev, 20);
  512. dev->short_slot = 0;
  513. }
  514. /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
  515. * Returns the _previously_ enabled IRQ mask.
  516. */
  517. static inline u32 b43legacy_interrupt_enable(struct b43legacy_wldev *dev,
  518. u32 mask)
  519. {
  520. u32 old_mask;
  521. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  522. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask |
  523. mask);
  524. return old_mask;
  525. }
  526. /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
  527. * Returns the _previously_ enabled IRQ mask.
  528. */
  529. static inline u32 b43legacy_interrupt_disable(struct b43legacy_wldev *dev,
  530. u32 mask)
  531. {
  532. u32 old_mask;
  533. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  534. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
  535. return old_mask;
  536. }
  537. /* Synchronize IRQ top- and bottom-half.
  538. * IRQs must be masked before calling this.
  539. * This must not be called with the irq_lock held.
  540. */
  541. static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
  542. {
  543. synchronize_irq(dev->dev->irq);
  544. tasklet_kill(&dev->isr_tasklet);
  545. }
  546. /* DummyTransmission function, as documented on
  547. * http://bcm-specs.sipsolutions.net/DummyTransmission
  548. */
  549. void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
  550. {
  551. struct b43legacy_phy *phy = &dev->phy;
  552. unsigned int i;
  553. unsigned int max_loop;
  554. u16 value;
  555. u32 buffer[5] = {
  556. 0x00000000,
  557. 0x00D40000,
  558. 0x00000000,
  559. 0x01000000,
  560. 0x00000000,
  561. };
  562. switch (phy->type) {
  563. case B43legacy_PHYTYPE_B:
  564. case B43legacy_PHYTYPE_G:
  565. max_loop = 0xFA;
  566. buffer[0] = 0x000B846E;
  567. break;
  568. default:
  569. B43legacy_BUG_ON(1);
  570. return;
  571. }
  572. for (i = 0; i < 5; i++)
  573. b43legacy_ram_write(dev, i * 4, buffer[i]);
  574. /* dummy read follows */
  575. b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  576. b43legacy_write16(dev, 0x0568, 0x0000);
  577. b43legacy_write16(dev, 0x07C0, 0x0000);
  578. b43legacy_write16(dev, 0x050C, 0x0000);
  579. b43legacy_write16(dev, 0x0508, 0x0000);
  580. b43legacy_write16(dev, 0x050A, 0x0000);
  581. b43legacy_write16(dev, 0x054C, 0x0000);
  582. b43legacy_write16(dev, 0x056A, 0x0014);
  583. b43legacy_write16(dev, 0x0568, 0x0826);
  584. b43legacy_write16(dev, 0x0500, 0x0000);
  585. b43legacy_write16(dev, 0x0502, 0x0030);
  586. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  587. b43legacy_radio_write16(dev, 0x0051, 0x0017);
  588. for (i = 0x00; i < max_loop; i++) {
  589. value = b43legacy_read16(dev, 0x050E);
  590. if (value & 0x0080)
  591. break;
  592. udelay(10);
  593. }
  594. for (i = 0x00; i < 0x0A; i++) {
  595. value = b43legacy_read16(dev, 0x050E);
  596. if (value & 0x0400)
  597. break;
  598. udelay(10);
  599. }
  600. for (i = 0x00; i < 0x0A; i++) {
  601. value = b43legacy_read16(dev, 0x0690);
  602. if (!(value & 0x0100))
  603. break;
  604. udelay(10);
  605. }
  606. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  607. b43legacy_radio_write16(dev, 0x0051, 0x0037);
  608. }
  609. /* Turn the Analog ON/OFF */
  610. static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
  611. {
  612. b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
  613. }
  614. void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
  615. {
  616. u32 tmslow;
  617. u32 macctl;
  618. flags |= B43legacy_TMSLOW_PHYCLKEN;
  619. flags |= B43legacy_TMSLOW_PHYRESET;
  620. ssb_device_enable(dev->dev, flags);
  621. msleep(2); /* Wait for the PLL to turn on. */
  622. /* Now take the PHY out of Reset again */
  623. tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
  624. tmslow |= SSB_TMSLOW_FGC;
  625. tmslow &= ~B43legacy_TMSLOW_PHYRESET;
  626. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  627. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  628. msleep(1);
  629. tmslow &= ~SSB_TMSLOW_FGC;
  630. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  631. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  632. msleep(1);
  633. /* Turn Analog ON */
  634. b43legacy_switch_analog(dev, 1);
  635. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  636. macctl &= ~B43legacy_MACCTL_GMODE;
  637. if (flags & B43legacy_TMSLOW_GMODE) {
  638. macctl |= B43legacy_MACCTL_GMODE;
  639. dev->phy.gmode = 1;
  640. } else
  641. dev->phy.gmode = 0;
  642. macctl |= B43legacy_MACCTL_IHR_ENABLED;
  643. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  644. }
  645. static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
  646. {
  647. u32 v0;
  648. u32 v1;
  649. u16 tmp;
  650. struct b43legacy_txstatus stat;
  651. while (1) {
  652. v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  653. if (!(v0 & 0x00000001))
  654. break;
  655. v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  656. stat.cookie = (v0 >> 16);
  657. stat.seq = (v1 & 0x0000FFFF);
  658. stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
  659. tmp = (v0 & 0x0000FFFF);
  660. stat.frame_count = ((tmp & 0xF000) >> 12);
  661. stat.rts_count = ((tmp & 0x0F00) >> 8);
  662. stat.supp_reason = ((tmp & 0x001C) >> 2);
  663. stat.pm_indicated = !!(tmp & 0x0080);
  664. stat.intermediate = !!(tmp & 0x0040);
  665. stat.for_ampdu = !!(tmp & 0x0020);
  666. stat.acked = !!(tmp & 0x0002);
  667. b43legacy_handle_txstatus(dev, &stat);
  668. }
  669. }
  670. static void drain_txstatus_queue(struct b43legacy_wldev *dev)
  671. {
  672. u32 dummy;
  673. if (dev->dev->id.revision < 5)
  674. return;
  675. /* Read all entries from the microcode TXstatus FIFO
  676. * and throw them away.
  677. */
  678. while (1) {
  679. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  680. if (!(dummy & 0x00000001))
  681. break;
  682. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  683. }
  684. }
  685. static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
  686. {
  687. u32 val = 0;
  688. val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
  689. val <<= 16;
  690. val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
  691. return val;
  692. }
  693. static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
  694. {
  695. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
  696. (jssi & 0x0000FFFF));
  697. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
  698. (jssi & 0xFFFF0000) >> 16);
  699. }
  700. static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
  701. {
  702. b43legacy_jssi_write(dev, 0x7F7F7F7F);
  703. b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
  704. b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
  705. | B43legacy_MACCMD_BGNOISE);
  706. B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
  707. dev->phy.channel);
  708. }
  709. static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
  710. {
  711. /* Top half of Link Quality calculation. */
  712. if (dev->noisecalc.calculation_running)
  713. return;
  714. dev->noisecalc.channel_at_start = dev->phy.channel;
  715. dev->noisecalc.calculation_running = 1;
  716. dev->noisecalc.nr_samples = 0;
  717. b43legacy_generate_noise_sample(dev);
  718. }
  719. static void handle_irq_noise(struct b43legacy_wldev *dev)
  720. {
  721. struct b43legacy_phy *phy = &dev->phy;
  722. u16 tmp;
  723. u8 noise[4];
  724. u8 i;
  725. u8 j;
  726. s32 average;
  727. /* Bottom half of Link Quality calculation. */
  728. B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
  729. if (dev->noisecalc.channel_at_start != phy->channel)
  730. goto drop_calculation;
  731. *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
  732. if (noise[0] == 0x7F || noise[1] == 0x7F ||
  733. noise[2] == 0x7F || noise[3] == 0x7F)
  734. goto generate_new;
  735. /* Get the noise samples. */
  736. B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
  737. i = dev->noisecalc.nr_samples;
  738. noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  739. noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  740. noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  741. noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  742. dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
  743. dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
  744. dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
  745. dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
  746. dev->noisecalc.nr_samples++;
  747. if (dev->noisecalc.nr_samples == 8) {
  748. /* Calculate the Link Quality by the noise samples. */
  749. average = 0;
  750. for (i = 0; i < 8; i++) {
  751. for (j = 0; j < 4; j++)
  752. average += dev->noisecalc.samples[i][j];
  753. }
  754. average /= (8 * 4);
  755. average *= 125;
  756. average += 64;
  757. average /= 128;
  758. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  759. 0x40C);
  760. tmp = (tmp / 128) & 0x1F;
  761. if (tmp >= 8)
  762. average += 2;
  763. else
  764. average -= 25;
  765. if (tmp == 8)
  766. average -= 72;
  767. else
  768. average -= 48;
  769. dev->stats.link_noise = average;
  770. drop_calculation:
  771. dev->noisecalc.calculation_running = 0;
  772. return;
  773. }
  774. generate_new:
  775. b43legacy_generate_noise_sample(dev);
  776. }
  777. static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
  778. {
  779. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
  780. /* TODO: PS TBTT */
  781. } else {
  782. if (1/*FIXME: the last PSpoll frame was sent successfully */)
  783. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  784. }
  785. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
  786. dev->dfq_valid = 1;
  787. }
  788. static void handle_irq_atim_end(struct b43legacy_wldev *dev)
  789. {
  790. if (dev->dfq_valid) {
  791. b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
  792. b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
  793. | B43legacy_MACCMD_DFQ_VALID);
  794. dev->dfq_valid = 0;
  795. }
  796. }
  797. static void handle_irq_pmq(struct b43legacy_wldev *dev)
  798. {
  799. u32 tmp;
  800. /* TODO: AP mode. */
  801. while (1) {
  802. tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
  803. if (!(tmp & 0x00000008))
  804. break;
  805. }
  806. /* 16bit write is odd, but correct. */
  807. b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
  808. }
  809. static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
  810. const u8 *data, u16 size,
  811. u16 ram_offset,
  812. u16 shm_size_offset, u8 rate)
  813. {
  814. u32 i;
  815. u32 tmp;
  816. struct b43legacy_plcp_hdr4 plcp;
  817. plcp.data = 0;
  818. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  819. b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
  820. ram_offset += sizeof(u32);
  821. /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
  822. * So leave the first two bytes of the next write blank.
  823. */
  824. tmp = (u32)(data[0]) << 16;
  825. tmp |= (u32)(data[1]) << 24;
  826. b43legacy_ram_write(dev, ram_offset, tmp);
  827. ram_offset += sizeof(u32);
  828. for (i = 2; i < size; i += sizeof(u32)) {
  829. tmp = (u32)(data[i + 0]);
  830. if (i + 1 < size)
  831. tmp |= (u32)(data[i + 1]) << 8;
  832. if (i + 2 < size)
  833. tmp |= (u32)(data[i + 2]) << 16;
  834. if (i + 3 < size)
  835. tmp |= (u32)(data[i + 3]) << 24;
  836. b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
  837. }
  838. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
  839. size + sizeof(struct b43legacy_plcp_hdr6));
  840. }
  841. static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
  842. u16 ram_offset,
  843. u16 shm_size_offset, u8 rate)
  844. {
  845. unsigned int i, len, variable_len;
  846. const struct ieee80211_mgmt *bcn;
  847. const u8 *ie;
  848. bool tim_found = 0;
  849. bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
  850. len = min((size_t)dev->wl->current_beacon->len,
  851. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  852. b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
  853. shm_size_offset, rate);
  854. /* Find the position of the TIM and the DTIM_period value
  855. * and write them to SHM. */
  856. ie = bcn->u.beacon.variable;
  857. variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
  858. for (i = 0; i < variable_len - 2; ) {
  859. uint8_t ie_id, ie_len;
  860. ie_id = ie[i];
  861. ie_len = ie[i + 1];
  862. if (ie_id == 5) {
  863. u16 tim_position;
  864. u16 dtim_period;
  865. /* This is the TIM Information Element */
  866. /* Check whether the ie_len is in the beacon data range. */
  867. if (variable_len < ie_len + 2 + i)
  868. break;
  869. /* A valid TIM is at least 4 bytes long. */
  870. if (ie_len < 4)
  871. break;
  872. tim_found = 1;
  873. tim_position = sizeof(struct b43legacy_plcp_hdr6);
  874. tim_position += offsetof(struct ieee80211_mgmt,
  875. u.beacon.variable);
  876. tim_position += i;
  877. dtim_period = ie[i + 3];
  878. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  879. B43legacy_SHM_SH_TIMPOS, tim_position);
  880. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  881. B43legacy_SHM_SH_DTIMP, dtim_period);
  882. break;
  883. }
  884. i += ie_len + 2;
  885. }
  886. if (!tim_found) {
  887. b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
  888. "beacon template packet. AP or IBSS operation "
  889. "may be broken.\n");
  890. }
  891. }
  892. static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
  893. u16 shm_offset, u16 size,
  894. struct ieee80211_rate *rate)
  895. {
  896. struct b43legacy_plcp_hdr4 plcp;
  897. u32 tmp;
  898. __le16 dur;
  899. plcp.data = 0;
  900. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->bitrate);
  901. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  902. dev->wl->vif,
  903. size,
  904. rate);
  905. /* Write PLCP in two parts and timing for packet transfer */
  906. tmp = le32_to_cpu(plcp.data);
  907. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
  908. tmp & 0xFFFF);
  909. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
  910. tmp >> 16);
  911. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
  912. le16_to_cpu(dur));
  913. }
  914. /* Instead of using custom probe response template, this function
  915. * just patches custom beacon template by:
  916. * 1) Changing packet type
  917. * 2) Patching duration field
  918. * 3) Stripping TIM
  919. */
  920. static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
  921. u16 *dest_size,
  922. struct ieee80211_rate *rate)
  923. {
  924. const u8 *src_data;
  925. u8 *dest_data;
  926. u16 src_size, elem_size, src_pos, dest_pos;
  927. __le16 dur;
  928. struct ieee80211_hdr *hdr;
  929. size_t ie_start;
  930. src_size = dev->wl->current_beacon->len;
  931. src_data = (const u8 *)dev->wl->current_beacon->data;
  932. /* Get the start offset of the variable IEs in the packet. */
  933. ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
  934. B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
  935. u.beacon.variable));
  936. if (B43legacy_WARN_ON(src_size < ie_start))
  937. return NULL;
  938. dest_data = kmalloc(src_size, GFP_ATOMIC);
  939. if (unlikely(!dest_data))
  940. return NULL;
  941. /* Copy the static data and all Information Elements, except the TIM. */
  942. memcpy(dest_data, src_data, ie_start);
  943. src_pos = ie_start;
  944. dest_pos = ie_start;
  945. for ( ; src_pos < src_size - 2; src_pos += elem_size) {
  946. elem_size = src_data[src_pos + 1] + 2;
  947. if (src_data[src_pos] == 5) {
  948. /* This is the TIM. */
  949. continue;
  950. }
  951. memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
  952. dest_pos += elem_size;
  953. }
  954. *dest_size = dest_pos;
  955. hdr = (struct ieee80211_hdr *)dest_data;
  956. /* Set the frame control. */
  957. hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
  958. IEEE80211_STYPE_PROBE_RESP);
  959. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  960. dev->wl->vif,
  961. *dest_size,
  962. rate);
  963. hdr->duration_id = dur;
  964. return dest_data;
  965. }
  966. static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
  967. u16 ram_offset,
  968. u16 shm_size_offset,
  969. struct ieee80211_rate *rate)
  970. {
  971. const u8 *probe_resp_data;
  972. u16 size;
  973. size = dev->wl->current_beacon->len;
  974. probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
  975. if (unlikely(!probe_resp_data))
  976. return;
  977. /* Looks like PLCP headers plus packet timings are stored for
  978. * all possible basic rates
  979. */
  980. b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
  981. &b43legacy_b_ratetable[0]);
  982. b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
  983. &b43legacy_b_ratetable[1]);
  984. b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
  985. &b43legacy_b_ratetable[2]);
  986. b43legacy_write_probe_resp_plcp(dev, 0x350, size,
  987. &b43legacy_b_ratetable[3]);
  988. size = min((size_t)size,
  989. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  990. b43legacy_write_template_common(dev, probe_resp_data,
  991. size, ram_offset,
  992. shm_size_offset, rate->bitrate);
  993. kfree(probe_resp_data);
  994. }
  995. /* Asynchronously update the packet templates in template RAM.
  996. * Locking: Requires wl->irq_lock to be locked. */
  997. static void b43legacy_update_templates(struct b43legacy_wl *wl)
  998. {
  999. struct sk_buff *beacon;
  1000. /* This is the top half of the ansynchronous beacon update. The bottom
  1001. * half is the beacon IRQ. Beacon update must be asynchronous to avoid
  1002. * sending an invalid beacon. This can happen for example, if the
  1003. * firmware transmits a beacon while we are updating it. */
  1004. /* We could modify the existing beacon and set the aid bit in the TIM
  1005. * field, but that would probably require resizing and moving of data
  1006. * within the beacon template. Simply request a new beacon and let
  1007. * mac80211 do the hard work. */
  1008. beacon = ieee80211_beacon_get(wl->hw, wl->vif);
  1009. if (unlikely(!beacon))
  1010. return;
  1011. if (wl->current_beacon)
  1012. dev_kfree_skb_any(wl->current_beacon);
  1013. wl->current_beacon = beacon;
  1014. wl->beacon0_uploaded = 0;
  1015. wl->beacon1_uploaded = 0;
  1016. }
  1017. static void b43legacy_set_ssid(struct b43legacy_wldev *dev,
  1018. const u8 *ssid, u8 ssid_len)
  1019. {
  1020. u32 tmp;
  1021. u16 i;
  1022. u16 len;
  1023. len = min((u16)ssid_len, (u16)0x100);
  1024. for (i = 0; i < len; i += sizeof(u32)) {
  1025. tmp = (u32)(ssid[i + 0]);
  1026. if (i + 1 < len)
  1027. tmp |= (u32)(ssid[i + 1]) << 8;
  1028. if (i + 2 < len)
  1029. tmp |= (u32)(ssid[i + 2]) << 16;
  1030. if (i + 3 < len)
  1031. tmp |= (u32)(ssid[i + 3]) << 24;
  1032. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
  1033. 0x380 + i, tmp);
  1034. }
  1035. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1036. 0x48, len);
  1037. }
  1038. static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
  1039. u16 beacon_int)
  1040. {
  1041. b43legacy_time_lock(dev);
  1042. if (dev->dev->id.revision >= 3)
  1043. b43legacy_write32(dev, 0x188, (beacon_int << 16));
  1044. else {
  1045. b43legacy_write16(dev, 0x606, (beacon_int >> 6));
  1046. b43legacy_write16(dev, 0x610, beacon_int);
  1047. }
  1048. b43legacy_time_unlock(dev);
  1049. }
  1050. static void handle_irq_beacon(struct b43legacy_wldev *dev)
  1051. {
  1052. struct b43legacy_wl *wl = dev->wl;
  1053. u32 cmd;
  1054. if (!b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  1055. return;
  1056. /* This is the bottom half of the asynchronous beacon update. */
  1057. cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
  1058. if (!(cmd & B43legacy_MACCMD_BEACON0_VALID)) {
  1059. if (!wl->beacon0_uploaded) {
  1060. b43legacy_write_beacon_template(dev, 0x68,
  1061. B43legacy_SHM_SH_BTL0,
  1062. B43legacy_CCK_RATE_1MB);
  1063. b43legacy_write_probe_resp_template(dev, 0x268,
  1064. B43legacy_SHM_SH_PRTLEN,
  1065. &__b43legacy_ratetable[3]);
  1066. wl->beacon0_uploaded = 1;
  1067. }
  1068. cmd |= B43legacy_MACCMD_BEACON0_VALID;
  1069. }
  1070. if (!(cmd & B43legacy_MACCMD_BEACON1_VALID)) {
  1071. if (!wl->beacon1_uploaded) {
  1072. b43legacy_write_beacon_template(dev, 0x468,
  1073. B43legacy_SHM_SH_BTL1,
  1074. B43legacy_CCK_RATE_1MB);
  1075. wl->beacon1_uploaded = 1;
  1076. }
  1077. cmd |= B43legacy_MACCMD_BEACON1_VALID;
  1078. }
  1079. b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
  1080. }
  1081. static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
  1082. {
  1083. }
  1084. /* Interrupt handler bottom-half */
  1085. static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
  1086. {
  1087. u32 reason;
  1088. u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
  1089. u32 merged_dma_reason = 0;
  1090. int i;
  1091. unsigned long flags;
  1092. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1093. B43legacy_WARN_ON(b43legacy_status(dev) <
  1094. B43legacy_STAT_INITIALIZED);
  1095. reason = dev->irq_reason;
  1096. for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
  1097. dma_reason[i] = dev->dma_reason[i];
  1098. merged_dma_reason |= dma_reason[i];
  1099. }
  1100. if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
  1101. b43legacyerr(dev->wl, "MAC transmission error\n");
  1102. if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
  1103. b43legacyerr(dev->wl, "PHY transmission error\n");
  1104. rmb();
  1105. if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
  1106. b43legacyerr(dev->wl, "Too many PHY TX errors, "
  1107. "restarting the controller\n");
  1108. b43legacy_controller_restart(dev, "PHY TX errors");
  1109. }
  1110. }
  1111. if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
  1112. B43legacy_DMAIRQ_NONFATALMASK))) {
  1113. if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
  1114. b43legacyerr(dev->wl, "Fatal DMA error: "
  1115. "0x%08X, 0x%08X, 0x%08X, "
  1116. "0x%08X, 0x%08X, 0x%08X\n",
  1117. dma_reason[0], dma_reason[1],
  1118. dma_reason[2], dma_reason[3],
  1119. dma_reason[4], dma_reason[5]);
  1120. b43legacy_controller_restart(dev, "DMA error");
  1121. mmiowb();
  1122. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1123. return;
  1124. }
  1125. if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
  1126. b43legacyerr(dev->wl, "DMA error: "
  1127. "0x%08X, 0x%08X, 0x%08X, "
  1128. "0x%08X, 0x%08X, 0x%08X\n",
  1129. dma_reason[0], dma_reason[1],
  1130. dma_reason[2], dma_reason[3],
  1131. dma_reason[4], dma_reason[5]);
  1132. }
  1133. if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
  1134. handle_irq_ucode_debug(dev);
  1135. if (reason & B43legacy_IRQ_TBTT_INDI)
  1136. handle_irq_tbtt_indication(dev);
  1137. if (reason & B43legacy_IRQ_ATIM_END)
  1138. handle_irq_atim_end(dev);
  1139. if (reason & B43legacy_IRQ_BEACON)
  1140. handle_irq_beacon(dev);
  1141. if (reason & B43legacy_IRQ_PMQ)
  1142. handle_irq_pmq(dev);
  1143. if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
  1144. ;/*TODO*/
  1145. if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
  1146. handle_irq_noise(dev);
  1147. /* Check the DMA reason registers for received data. */
  1148. if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
  1149. if (b43legacy_using_pio(dev))
  1150. b43legacy_pio_rx(dev->pio.queue0);
  1151. else
  1152. b43legacy_dma_rx(dev->dma.rx_ring0);
  1153. }
  1154. B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
  1155. B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
  1156. if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
  1157. if (b43legacy_using_pio(dev))
  1158. b43legacy_pio_rx(dev->pio.queue3);
  1159. else
  1160. b43legacy_dma_rx(dev->dma.rx_ring3);
  1161. }
  1162. B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
  1163. B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
  1164. if (reason & B43legacy_IRQ_TX_OK)
  1165. handle_irq_transmit_status(dev);
  1166. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  1167. mmiowb();
  1168. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1169. }
  1170. static void pio_irq_workaround(struct b43legacy_wldev *dev,
  1171. u16 base, int queueidx)
  1172. {
  1173. u16 rxctl;
  1174. rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
  1175. if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
  1176. dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
  1177. else
  1178. dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
  1179. }
  1180. static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
  1181. {
  1182. if (b43legacy_using_pio(dev) &&
  1183. (dev->dev->id.revision < 3) &&
  1184. (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
  1185. /* Apply a PIO specific workaround to the dma_reasons */
  1186. pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
  1187. pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
  1188. pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
  1189. pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
  1190. }
  1191. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
  1192. b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
  1193. dev->dma_reason[0]);
  1194. b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
  1195. dev->dma_reason[1]);
  1196. b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
  1197. dev->dma_reason[2]);
  1198. b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
  1199. dev->dma_reason[3]);
  1200. b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
  1201. dev->dma_reason[4]);
  1202. b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
  1203. dev->dma_reason[5]);
  1204. }
  1205. /* Interrupt handler top-half */
  1206. static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
  1207. {
  1208. irqreturn_t ret = IRQ_NONE;
  1209. struct b43legacy_wldev *dev = dev_id;
  1210. u32 reason;
  1211. if (!dev)
  1212. return IRQ_NONE;
  1213. spin_lock(&dev->wl->irq_lock);
  1214. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  1215. goto out;
  1216. reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1217. if (reason == 0xffffffff) /* shared IRQ */
  1218. goto out;
  1219. ret = IRQ_HANDLED;
  1220. reason &= b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  1221. if (!reason)
  1222. goto out;
  1223. dev->dma_reason[0] = b43legacy_read32(dev,
  1224. B43legacy_MMIO_DMA0_REASON)
  1225. & 0x0001DC00;
  1226. dev->dma_reason[1] = b43legacy_read32(dev,
  1227. B43legacy_MMIO_DMA1_REASON)
  1228. & 0x0000DC00;
  1229. dev->dma_reason[2] = b43legacy_read32(dev,
  1230. B43legacy_MMIO_DMA2_REASON)
  1231. & 0x0000DC00;
  1232. dev->dma_reason[3] = b43legacy_read32(dev,
  1233. B43legacy_MMIO_DMA3_REASON)
  1234. & 0x0001DC00;
  1235. dev->dma_reason[4] = b43legacy_read32(dev,
  1236. B43legacy_MMIO_DMA4_REASON)
  1237. & 0x0000DC00;
  1238. dev->dma_reason[5] = b43legacy_read32(dev,
  1239. B43legacy_MMIO_DMA5_REASON)
  1240. & 0x0000DC00;
  1241. b43legacy_interrupt_ack(dev, reason);
  1242. /* disable all IRQs. They are enabled again in the bottom half. */
  1243. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  1244. B43legacy_IRQ_ALL);
  1245. /* save the reason code and call our bottom half. */
  1246. dev->irq_reason = reason;
  1247. tasklet_schedule(&dev->isr_tasklet);
  1248. out:
  1249. mmiowb();
  1250. spin_unlock(&dev->wl->irq_lock);
  1251. return ret;
  1252. }
  1253. static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
  1254. {
  1255. release_firmware(dev->fw.ucode);
  1256. dev->fw.ucode = NULL;
  1257. release_firmware(dev->fw.pcm);
  1258. dev->fw.pcm = NULL;
  1259. release_firmware(dev->fw.initvals);
  1260. dev->fw.initvals = NULL;
  1261. release_firmware(dev->fw.initvals_band);
  1262. dev->fw.initvals_band = NULL;
  1263. }
  1264. static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
  1265. {
  1266. b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
  1267. "Drivers/b43#devicefirmware "
  1268. "and download the correct firmware (version 3).\n");
  1269. }
  1270. static int do_request_fw(struct b43legacy_wldev *dev,
  1271. const char *name,
  1272. const struct firmware **fw)
  1273. {
  1274. char path[sizeof(modparam_fwpostfix) + 32];
  1275. struct b43legacy_fw_header *hdr;
  1276. u32 size;
  1277. int err;
  1278. if (!name)
  1279. return 0;
  1280. snprintf(path, ARRAY_SIZE(path),
  1281. "b43legacy%s/%s.fw",
  1282. modparam_fwpostfix, name);
  1283. err = request_firmware(fw, path, dev->dev->dev);
  1284. if (err) {
  1285. b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
  1286. "or load failed.\n", path);
  1287. return err;
  1288. }
  1289. if ((*fw)->size < sizeof(struct b43legacy_fw_header))
  1290. goto err_format;
  1291. hdr = (struct b43legacy_fw_header *)((*fw)->data);
  1292. switch (hdr->type) {
  1293. case B43legacy_FW_TYPE_UCODE:
  1294. case B43legacy_FW_TYPE_PCM:
  1295. size = be32_to_cpu(hdr->size);
  1296. if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
  1297. goto err_format;
  1298. /* fallthrough */
  1299. case B43legacy_FW_TYPE_IV:
  1300. if (hdr->ver != 1)
  1301. goto err_format;
  1302. break;
  1303. default:
  1304. goto err_format;
  1305. }
  1306. return err;
  1307. err_format:
  1308. b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
  1309. return -EPROTO;
  1310. }
  1311. static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
  1312. {
  1313. struct b43legacy_firmware *fw = &dev->fw;
  1314. const u8 rev = dev->dev->id.revision;
  1315. const char *filename;
  1316. u32 tmshigh;
  1317. int err;
  1318. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  1319. if (!fw->ucode) {
  1320. if (rev == 2)
  1321. filename = "ucode2";
  1322. else if (rev == 4)
  1323. filename = "ucode4";
  1324. else
  1325. filename = "ucode5";
  1326. err = do_request_fw(dev, filename, &fw->ucode);
  1327. if (err)
  1328. goto err_load;
  1329. }
  1330. if (!fw->pcm) {
  1331. if (rev < 5)
  1332. filename = "pcm4";
  1333. else
  1334. filename = "pcm5";
  1335. err = do_request_fw(dev, filename, &fw->pcm);
  1336. if (err)
  1337. goto err_load;
  1338. }
  1339. if (!fw->initvals) {
  1340. switch (dev->phy.type) {
  1341. case B43legacy_PHYTYPE_B:
  1342. case B43legacy_PHYTYPE_G:
  1343. if ((rev >= 5) && (rev <= 10))
  1344. filename = "b0g0initvals5";
  1345. else if (rev == 2 || rev == 4)
  1346. filename = "b0g0initvals2";
  1347. else
  1348. goto err_no_initvals;
  1349. break;
  1350. default:
  1351. goto err_no_initvals;
  1352. }
  1353. err = do_request_fw(dev, filename, &fw->initvals);
  1354. if (err)
  1355. goto err_load;
  1356. }
  1357. if (!fw->initvals_band) {
  1358. switch (dev->phy.type) {
  1359. case B43legacy_PHYTYPE_B:
  1360. case B43legacy_PHYTYPE_G:
  1361. if ((rev >= 5) && (rev <= 10))
  1362. filename = "b0g0bsinitvals5";
  1363. else if (rev >= 11)
  1364. filename = NULL;
  1365. else if (rev == 2 || rev == 4)
  1366. filename = NULL;
  1367. else
  1368. goto err_no_initvals;
  1369. break;
  1370. default:
  1371. goto err_no_initvals;
  1372. }
  1373. err = do_request_fw(dev, filename, &fw->initvals_band);
  1374. if (err)
  1375. goto err_load;
  1376. }
  1377. return 0;
  1378. err_load:
  1379. b43legacy_print_fw_helptext(dev->wl);
  1380. goto error;
  1381. err_no_initvals:
  1382. err = -ENODEV;
  1383. b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
  1384. "core rev %u\n", dev->phy.type, rev);
  1385. goto error;
  1386. error:
  1387. b43legacy_release_firmware(dev);
  1388. return err;
  1389. }
  1390. static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
  1391. {
  1392. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1393. const __be32 *data;
  1394. unsigned int i;
  1395. unsigned int len;
  1396. u16 fwrev;
  1397. u16 fwpatch;
  1398. u16 fwdate;
  1399. u16 fwtime;
  1400. u32 tmp, macctl;
  1401. int err = 0;
  1402. /* Jump the microcode PSM to offset 0 */
  1403. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1404. B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
  1405. macctl |= B43legacy_MACCTL_PSM_JMP0;
  1406. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1407. /* Zero out all microcode PSM registers and shared memory. */
  1408. for (i = 0; i < 64; i++)
  1409. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
  1410. for (i = 0; i < 4096; i += 2)
  1411. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
  1412. /* Upload Microcode. */
  1413. data = (__be32 *) (dev->fw.ucode->data + hdr_len);
  1414. len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
  1415. b43legacy_shm_control_word(dev,
  1416. B43legacy_SHM_UCODE |
  1417. B43legacy_SHM_AUTOINC_W,
  1418. 0x0000);
  1419. for (i = 0; i < len; i++) {
  1420. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1421. be32_to_cpu(data[i]));
  1422. udelay(10);
  1423. }
  1424. if (dev->fw.pcm) {
  1425. /* Upload PCM data. */
  1426. data = (__be32 *) (dev->fw.pcm->data + hdr_len);
  1427. len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
  1428. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
  1429. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
  1430. /* No need for autoinc bit in SHM_HW */
  1431. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
  1432. for (i = 0; i < len; i++) {
  1433. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1434. be32_to_cpu(data[i]));
  1435. udelay(10);
  1436. }
  1437. }
  1438. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1439. B43legacy_IRQ_ALL);
  1440. /* Start the microcode PSM */
  1441. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1442. macctl &= ~B43legacy_MACCTL_PSM_JMP0;
  1443. macctl |= B43legacy_MACCTL_PSM_RUN;
  1444. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1445. /* Wait for the microcode to load and respond */
  1446. i = 0;
  1447. while (1) {
  1448. tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1449. if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
  1450. break;
  1451. i++;
  1452. if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
  1453. b43legacyerr(dev->wl, "Microcode not responding\n");
  1454. b43legacy_print_fw_helptext(dev->wl);
  1455. err = -ENODEV;
  1456. goto error;
  1457. }
  1458. msleep_interruptible(50);
  1459. if (signal_pending(current)) {
  1460. err = -EINTR;
  1461. goto error;
  1462. }
  1463. }
  1464. /* dummy read follows */
  1465. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1466. /* Get and check the revisions. */
  1467. fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1468. B43legacy_SHM_SH_UCODEREV);
  1469. fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1470. B43legacy_SHM_SH_UCODEPATCH);
  1471. fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1472. B43legacy_SHM_SH_UCODEDATE);
  1473. fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1474. B43legacy_SHM_SH_UCODETIME);
  1475. if (fwrev > 0x128) {
  1476. b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
  1477. " Only firmware from binary drivers version 3.x"
  1478. " is supported. You must change your firmware"
  1479. " files.\n");
  1480. b43legacy_print_fw_helptext(dev->wl);
  1481. err = -EOPNOTSUPP;
  1482. goto error;
  1483. }
  1484. b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
  1485. "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
  1486. (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
  1487. (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
  1488. fwtime & 0x1F);
  1489. dev->fw.rev = fwrev;
  1490. dev->fw.patch = fwpatch;
  1491. return 0;
  1492. error:
  1493. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1494. macctl &= ~B43legacy_MACCTL_PSM_RUN;
  1495. macctl |= B43legacy_MACCTL_PSM_JMP0;
  1496. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1497. return err;
  1498. }
  1499. static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
  1500. const struct b43legacy_iv *ivals,
  1501. size_t count,
  1502. size_t array_size)
  1503. {
  1504. const struct b43legacy_iv *iv;
  1505. u16 offset;
  1506. size_t i;
  1507. bool bit32;
  1508. BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
  1509. iv = ivals;
  1510. for (i = 0; i < count; i++) {
  1511. if (array_size < sizeof(iv->offset_size))
  1512. goto err_format;
  1513. array_size -= sizeof(iv->offset_size);
  1514. offset = be16_to_cpu(iv->offset_size);
  1515. bit32 = !!(offset & B43legacy_IV_32BIT);
  1516. offset &= B43legacy_IV_OFFSET_MASK;
  1517. if (offset >= 0x1000)
  1518. goto err_format;
  1519. if (bit32) {
  1520. u32 value;
  1521. if (array_size < sizeof(iv->data.d32))
  1522. goto err_format;
  1523. array_size -= sizeof(iv->data.d32);
  1524. value = get_unaligned_be32(&iv->data.d32);
  1525. b43legacy_write32(dev, offset, value);
  1526. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1527. sizeof(__be16) +
  1528. sizeof(__be32));
  1529. } else {
  1530. u16 value;
  1531. if (array_size < sizeof(iv->data.d16))
  1532. goto err_format;
  1533. array_size -= sizeof(iv->data.d16);
  1534. value = be16_to_cpu(iv->data.d16);
  1535. b43legacy_write16(dev, offset, value);
  1536. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1537. sizeof(__be16) +
  1538. sizeof(__be16));
  1539. }
  1540. }
  1541. if (array_size)
  1542. goto err_format;
  1543. return 0;
  1544. err_format:
  1545. b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
  1546. b43legacy_print_fw_helptext(dev->wl);
  1547. return -EPROTO;
  1548. }
  1549. static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
  1550. {
  1551. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1552. const struct b43legacy_fw_header *hdr;
  1553. struct b43legacy_firmware *fw = &dev->fw;
  1554. const struct b43legacy_iv *ivals;
  1555. size_t count;
  1556. int err;
  1557. hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
  1558. ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
  1559. count = be32_to_cpu(hdr->size);
  1560. err = b43legacy_write_initvals(dev, ivals, count,
  1561. fw->initvals->size - hdr_len);
  1562. if (err)
  1563. goto out;
  1564. if (fw->initvals_band) {
  1565. hdr = (const struct b43legacy_fw_header *)
  1566. (fw->initvals_band->data);
  1567. ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
  1568. + hdr_len);
  1569. count = be32_to_cpu(hdr->size);
  1570. err = b43legacy_write_initvals(dev, ivals, count,
  1571. fw->initvals_band->size - hdr_len);
  1572. if (err)
  1573. goto out;
  1574. }
  1575. out:
  1576. return err;
  1577. }
  1578. /* Initialize the GPIOs
  1579. * http://bcm-specs.sipsolutions.net/GPIO
  1580. */
  1581. static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
  1582. {
  1583. struct ssb_bus *bus = dev->dev->bus;
  1584. struct ssb_device *gpiodev, *pcidev = NULL;
  1585. u32 mask;
  1586. u32 set;
  1587. b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
  1588. b43legacy_read32(dev,
  1589. B43legacy_MMIO_MACCTL)
  1590. & 0xFFFF3FFF);
  1591. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1592. b43legacy_read16(dev,
  1593. B43legacy_MMIO_GPIO_MASK)
  1594. | 0x000F);
  1595. mask = 0x0000001F;
  1596. set = 0x0000000F;
  1597. if (dev->dev->bus->chip_id == 0x4301) {
  1598. mask |= 0x0060;
  1599. set |= 0x0060;
  1600. }
  1601. if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
  1602. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1603. b43legacy_read16(dev,
  1604. B43legacy_MMIO_GPIO_MASK)
  1605. | 0x0200);
  1606. mask |= 0x0200;
  1607. set |= 0x0200;
  1608. }
  1609. if (dev->dev->id.revision >= 2)
  1610. mask |= 0x0010; /* FIXME: This is redundant. */
  1611. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1612. pcidev = bus->pcicore.dev;
  1613. #endif
  1614. gpiodev = bus->chipco.dev ? : pcidev;
  1615. if (!gpiodev)
  1616. return 0;
  1617. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
  1618. (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
  1619. & mask) | set);
  1620. return 0;
  1621. }
  1622. /* Turn off all GPIO stuff. Call this on module unload, for example. */
  1623. static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
  1624. {
  1625. struct ssb_bus *bus = dev->dev->bus;
  1626. struct ssb_device *gpiodev, *pcidev = NULL;
  1627. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1628. pcidev = bus->pcicore.dev;
  1629. #endif
  1630. gpiodev = bus->chipco.dev ? : pcidev;
  1631. if (!gpiodev)
  1632. return;
  1633. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
  1634. }
  1635. /* http://bcm-specs.sipsolutions.net/EnableMac */
  1636. void b43legacy_mac_enable(struct b43legacy_wldev *dev)
  1637. {
  1638. dev->mac_suspended--;
  1639. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1640. B43legacy_WARN_ON(irqs_disabled());
  1641. if (dev->mac_suspended == 0) {
  1642. b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
  1643. b43legacy_read32(dev,
  1644. B43legacy_MMIO_MACCTL)
  1645. | B43legacy_MACCTL_ENABLED);
  1646. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1647. B43legacy_IRQ_MAC_SUSPENDED);
  1648. /* the next two are dummy reads */
  1649. b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1650. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1651. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  1652. /* Re-enable IRQs. */
  1653. spin_lock_irq(&dev->wl->irq_lock);
  1654. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  1655. spin_unlock_irq(&dev->wl->irq_lock);
  1656. }
  1657. }
  1658. /* http://bcm-specs.sipsolutions.net/SuspendMAC */
  1659. void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
  1660. {
  1661. int i;
  1662. u32 tmp;
  1663. might_sleep();
  1664. B43legacy_WARN_ON(irqs_disabled());
  1665. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1666. if (dev->mac_suspended == 0) {
  1667. /* Mask IRQs before suspending MAC. Otherwise
  1668. * the MAC stays busy and won't suspend. */
  1669. spin_lock_irq(&dev->wl->irq_lock);
  1670. tmp = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
  1671. spin_unlock_irq(&dev->wl->irq_lock);
  1672. b43legacy_synchronize_irq(dev);
  1673. dev->irq_savedstate = tmp;
  1674. b43legacy_power_saving_ctl_bits(dev, -1, 1);
  1675. b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
  1676. b43legacy_read32(dev,
  1677. B43legacy_MMIO_MACCTL)
  1678. & ~B43legacy_MACCTL_ENABLED);
  1679. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1680. for (i = 40; i; i--) {
  1681. tmp = b43legacy_read32(dev,
  1682. B43legacy_MMIO_GEN_IRQ_REASON);
  1683. if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
  1684. goto out;
  1685. msleep(1);
  1686. }
  1687. b43legacyerr(dev->wl, "MAC suspend failed\n");
  1688. }
  1689. out:
  1690. dev->mac_suspended++;
  1691. }
  1692. static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
  1693. {
  1694. struct b43legacy_wl *wl = dev->wl;
  1695. u32 ctl;
  1696. u16 cfp_pretbtt;
  1697. ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1698. /* Reset status to STA infrastructure mode. */
  1699. ctl &= ~B43legacy_MACCTL_AP;
  1700. ctl &= ~B43legacy_MACCTL_KEEP_CTL;
  1701. ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
  1702. ctl &= ~B43legacy_MACCTL_KEEP_BAD;
  1703. ctl &= ~B43legacy_MACCTL_PROMISC;
  1704. ctl &= ~B43legacy_MACCTL_BEACPROMISC;
  1705. ctl |= B43legacy_MACCTL_INFRA;
  1706. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  1707. ctl |= B43legacy_MACCTL_AP;
  1708. else if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
  1709. ctl &= ~B43legacy_MACCTL_INFRA;
  1710. if (wl->filter_flags & FIF_CONTROL)
  1711. ctl |= B43legacy_MACCTL_KEEP_CTL;
  1712. if (wl->filter_flags & FIF_FCSFAIL)
  1713. ctl |= B43legacy_MACCTL_KEEP_BAD;
  1714. if (wl->filter_flags & FIF_PLCPFAIL)
  1715. ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
  1716. if (wl->filter_flags & FIF_PROMISC_IN_BSS)
  1717. ctl |= B43legacy_MACCTL_PROMISC;
  1718. if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
  1719. ctl |= B43legacy_MACCTL_BEACPROMISC;
  1720. /* Workaround: On old hardware the HW-MAC-address-filter
  1721. * doesn't work properly, so always run promisc in filter
  1722. * it in software. */
  1723. if (dev->dev->id.revision <= 4)
  1724. ctl |= B43legacy_MACCTL_PROMISC;
  1725. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
  1726. cfp_pretbtt = 2;
  1727. if ((ctl & B43legacy_MACCTL_INFRA) &&
  1728. !(ctl & B43legacy_MACCTL_AP)) {
  1729. if (dev->dev->bus->chip_id == 0x4306 &&
  1730. dev->dev->bus->chip_rev == 3)
  1731. cfp_pretbtt = 100;
  1732. else
  1733. cfp_pretbtt = 50;
  1734. }
  1735. b43legacy_write16(dev, 0x612, cfp_pretbtt);
  1736. }
  1737. static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
  1738. u16 rate,
  1739. int is_ofdm)
  1740. {
  1741. u16 offset;
  1742. if (is_ofdm) {
  1743. offset = 0x480;
  1744. offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
  1745. } else {
  1746. offset = 0x4C0;
  1747. offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
  1748. }
  1749. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
  1750. b43legacy_shm_read16(dev,
  1751. B43legacy_SHM_SHARED, offset));
  1752. }
  1753. static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
  1754. {
  1755. switch (dev->phy.type) {
  1756. case B43legacy_PHYTYPE_G:
  1757. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
  1758. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
  1759. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
  1760. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
  1761. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
  1762. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
  1763. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
  1764. /* fallthrough */
  1765. case B43legacy_PHYTYPE_B:
  1766. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
  1767. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
  1768. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
  1769. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
  1770. break;
  1771. default:
  1772. B43legacy_BUG_ON(1);
  1773. }
  1774. }
  1775. /* Set the TX-Antenna for management frames sent by firmware. */
  1776. static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
  1777. int antenna)
  1778. {
  1779. u16 ant = 0;
  1780. u16 tmp;
  1781. switch (antenna) {
  1782. case B43legacy_ANTENNA0:
  1783. ant |= B43legacy_TX4_PHY_ANT0;
  1784. break;
  1785. case B43legacy_ANTENNA1:
  1786. ant |= B43legacy_TX4_PHY_ANT1;
  1787. break;
  1788. case B43legacy_ANTENNA_AUTO:
  1789. ant |= B43legacy_TX4_PHY_ANTLAST;
  1790. break;
  1791. default:
  1792. B43legacy_BUG_ON(1);
  1793. }
  1794. /* FIXME We also need to set the other flags of the PHY control
  1795. * field somewhere. */
  1796. /* For Beacons */
  1797. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1798. B43legacy_SHM_SH_BEACPHYCTL);
  1799. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1800. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1801. B43legacy_SHM_SH_BEACPHYCTL, tmp);
  1802. /* For ACK/CTS */
  1803. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1804. B43legacy_SHM_SH_ACKCTSPHYCTL);
  1805. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1806. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1807. B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
  1808. /* For Probe Resposes */
  1809. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1810. B43legacy_SHM_SH_PRPHYCTL);
  1811. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1812. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1813. B43legacy_SHM_SH_PRPHYCTL, tmp);
  1814. }
  1815. /* This is the opposite of b43legacy_chip_init() */
  1816. static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
  1817. {
  1818. b43legacy_radio_turn_off(dev, 1);
  1819. b43legacy_gpio_cleanup(dev);
  1820. /* firmware is released later */
  1821. }
  1822. /* Initialize the chip
  1823. * http://bcm-specs.sipsolutions.net/ChipInit
  1824. */
  1825. static int b43legacy_chip_init(struct b43legacy_wldev *dev)
  1826. {
  1827. struct b43legacy_phy *phy = &dev->phy;
  1828. int err;
  1829. int tmp;
  1830. u32 value32, macctl;
  1831. u16 value16;
  1832. /* Initialize the MAC control */
  1833. macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
  1834. if (dev->phy.gmode)
  1835. macctl |= B43legacy_MACCTL_GMODE;
  1836. macctl |= B43legacy_MACCTL_INFRA;
  1837. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1838. err = b43legacy_request_firmware(dev);
  1839. if (err)
  1840. goto out;
  1841. err = b43legacy_upload_microcode(dev);
  1842. if (err)
  1843. goto out; /* firmware is released later */
  1844. err = b43legacy_gpio_init(dev);
  1845. if (err)
  1846. goto out; /* firmware is released later */
  1847. err = b43legacy_upload_initvals(dev);
  1848. if (err)
  1849. goto err_gpio_clean;
  1850. b43legacy_radio_turn_on(dev);
  1851. b43legacy_write16(dev, 0x03E6, 0x0000);
  1852. err = b43legacy_phy_init(dev);
  1853. if (err)
  1854. goto err_radio_off;
  1855. /* Select initial Interference Mitigation. */
  1856. tmp = phy->interfmode;
  1857. phy->interfmode = B43legacy_INTERFMODE_NONE;
  1858. b43legacy_radio_set_interference_mitigation(dev, tmp);
  1859. b43legacy_phy_set_antenna_diversity(dev);
  1860. b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
  1861. if (phy->type == B43legacy_PHYTYPE_B) {
  1862. value16 = b43legacy_read16(dev, 0x005E);
  1863. value16 |= 0x0004;
  1864. b43legacy_write16(dev, 0x005E, value16);
  1865. }
  1866. b43legacy_write32(dev, 0x0100, 0x01000000);
  1867. if (dev->dev->id.revision < 5)
  1868. b43legacy_write32(dev, 0x010C, 0x01000000);
  1869. value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1870. value32 &= ~B43legacy_MACCTL_INFRA;
  1871. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
  1872. value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1873. value32 |= B43legacy_MACCTL_INFRA;
  1874. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
  1875. if (b43legacy_using_pio(dev)) {
  1876. b43legacy_write32(dev, 0x0210, 0x00000100);
  1877. b43legacy_write32(dev, 0x0230, 0x00000100);
  1878. b43legacy_write32(dev, 0x0250, 0x00000100);
  1879. b43legacy_write32(dev, 0x0270, 0x00000100);
  1880. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
  1881. 0x0000);
  1882. }
  1883. /* Probe Response Timeout value */
  1884. /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
  1885. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
  1886. /* Initially set the wireless operation mode. */
  1887. b43legacy_adjust_opmode(dev);
  1888. if (dev->dev->id.revision < 3) {
  1889. b43legacy_write16(dev, 0x060E, 0x0000);
  1890. b43legacy_write16(dev, 0x0610, 0x8000);
  1891. b43legacy_write16(dev, 0x0604, 0x0000);
  1892. b43legacy_write16(dev, 0x0606, 0x0200);
  1893. } else {
  1894. b43legacy_write32(dev, 0x0188, 0x80000000);
  1895. b43legacy_write32(dev, 0x018C, 0x02000000);
  1896. }
  1897. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
  1898. b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
  1899. b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
  1900. b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
  1901. b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
  1902. b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
  1903. b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
  1904. value32 = ssb_read32(dev->dev, SSB_TMSLOW);
  1905. value32 |= 0x00100000;
  1906. ssb_write32(dev->dev, SSB_TMSLOW, value32);
  1907. b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
  1908. dev->dev->bus->chipco.fast_pwrup_delay);
  1909. /* PHY TX errors counter. */
  1910. atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
  1911. B43legacy_WARN_ON(err != 0);
  1912. b43legacydbg(dev->wl, "Chip initialized\n");
  1913. out:
  1914. return err;
  1915. err_radio_off:
  1916. b43legacy_radio_turn_off(dev, 1);
  1917. err_gpio_clean:
  1918. b43legacy_gpio_cleanup(dev);
  1919. goto out;
  1920. }
  1921. static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
  1922. {
  1923. struct b43legacy_phy *phy = &dev->phy;
  1924. if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
  1925. return;
  1926. b43legacy_mac_suspend(dev);
  1927. b43legacy_phy_lo_g_measure(dev);
  1928. b43legacy_mac_enable(dev);
  1929. }
  1930. static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
  1931. {
  1932. b43legacy_phy_lo_mark_all_unused(dev);
  1933. if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
  1934. b43legacy_mac_suspend(dev);
  1935. b43legacy_calc_nrssi_slope(dev);
  1936. b43legacy_mac_enable(dev);
  1937. }
  1938. }
  1939. static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
  1940. {
  1941. /* Update device statistics. */
  1942. b43legacy_calculate_link_quality(dev);
  1943. }
  1944. static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
  1945. {
  1946. b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
  1947. atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
  1948. wmb();
  1949. }
  1950. static void do_periodic_work(struct b43legacy_wldev *dev)
  1951. {
  1952. unsigned int state;
  1953. state = dev->periodic_state;
  1954. if (state % 8 == 0)
  1955. b43legacy_periodic_every120sec(dev);
  1956. if (state % 4 == 0)
  1957. b43legacy_periodic_every60sec(dev);
  1958. if (state % 2 == 0)
  1959. b43legacy_periodic_every30sec(dev);
  1960. b43legacy_periodic_every15sec(dev);
  1961. }
  1962. /* Periodic work locking policy:
  1963. * The whole periodic work handler is protected by
  1964. * wl->mutex. If another lock is needed somewhere in the
  1965. * pwork callchain, it's aquired in-place, where it's needed.
  1966. */
  1967. static void b43legacy_periodic_work_handler(struct work_struct *work)
  1968. {
  1969. struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
  1970. periodic_work.work);
  1971. struct b43legacy_wl *wl = dev->wl;
  1972. unsigned long delay;
  1973. mutex_lock(&wl->mutex);
  1974. if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
  1975. goto out;
  1976. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
  1977. goto out_requeue;
  1978. do_periodic_work(dev);
  1979. dev->periodic_state++;
  1980. out_requeue:
  1981. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
  1982. delay = msecs_to_jiffies(50);
  1983. else
  1984. delay = round_jiffies_relative(HZ * 15);
  1985. queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
  1986. out:
  1987. mutex_unlock(&wl->mutex);
  1988. }
  1989. static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
  1990. {
  1991. struct delayed_work *work = &dev->periodic_work;
  1992. dev->periodic_state = 0;
  1993. INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
  1994. queue_delayed_work(dev->wl->hw->workqueue, work, 0);
  1995. }
  1996. /* Validate access to the chip (SHM) */
  1997. static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
  1998. {
  1999. u32 value;
  2000. u32 shm_backup;
  2001. shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
  2002. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
  2003. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  2004. 0xAA5555AA)
  2005. goto error;
  2006. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
  2007. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  2008. 0x55AAAA55)
  2009. goto error;
  2010. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
  2011. value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  2012. if ((value | B43legacy_MACCTL_GMODE) !=
  2013. (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
  2014. goto error;
  2015. value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  2016. if (value)
  2017. goto error;
  2018. return 0;
  2019. error:
  2020. b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
  2021. return -ENODEV;
  2022. }
  2023. static void b43legacy_security_init(struct b43legacy_wldev *dev)
  2024. {
  2025. dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
  2026. B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
  2027. dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  2028. 0x0056);
  2029. /* KTP is a word address, but we address SHM bytewise.
  2030. * So multiply by two.
  2031. */
  2032. dev->ktp *= 2;
  2033. if (dev->dev->id.revision >= 5)
  2034. /* Number of RCMTA address slots */
  2035. b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
  2036. dev->max_nr_keys - 8);
  2037. }
  2038. static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
  2039. {
  2040. struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
  2041. unsigned long flags;
  2042. /* Don't take wl->mutex here, as it could deadlock with
  2043. * hwrng internal locking. It's not needed to take
  2044. * wl->mutex here, anyway. */
  2045. spin_lock_irqsave(&wl->irq_lock, flags);
  2046. *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
  2047. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2048. return (sizeof(u16));
  2049. }
  2050. static void b43legacy_rng_exit(struct b43legacy_wl *wl)
  2051. {
  2052. if (wl->rng_initialized)
  2053. hwrng_unregister(&wl->rng);
  2054. }
  2055. static int b43legacy_rng_init(struct b43legacy_wl *wl)
  2056. {
  2057. int err;
  2058. snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
  2059. "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
  2060. wl->rng.name = wl->rng_name;
  2061. wl->rng.data_read = b43legacy_rng_read;
  2062. wl->rng.priv = (unsigned long)wl;
  2063. wl->rng_initialized = 1;
  2064. err = hwrng_register(&wl->rng);
  2065. if (err) {
  2066. wl->rng_initialized = 0;
  2067. b43legacyerr(wl, "Failed to register the random "
  2068. "number generator (%d)\n", err);
  2069. }
  2070. return err;
  2071. }
  2072. static int b43legacy_op_tx(struct ieee80211_hw *hw,
  2073. struct sk_buff *skb)
  2074. {
  2075. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2076. struct b43legacy_wldev *dev = wl->current_dev;
  2077. int err = -ENODEV;
  2078. unsigned long flags;
  2079. if (unlikely(!dev))
  2080. goto out;
  2081. if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
  2082. goto out;
  2083. /* DMA-TX is done without a global lock. */
  2084. if (b43legacy_using_pio(dev)) {
  2085. spin_lock_irqsave(&wl->irq_lock, flags);
  2086. err = b43legacy_pio_tx(dev, skb);
  2087. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2088. } else
  2089. err = b43legacy_dma_tx(dev, skb);
  2090. out:
  2091. if (unlikely(err)) {
  2092. /* Drop the packet. */
  2093. dev_kfree_skb_any(skb);
  2094. }
  2095. return NETDEV_TX_OK;
  2096. }
  2097. static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
  2098. const struct ieee80211_tx_queue_params *params)
  2099. {
  2100. return 0;
  2101. }
  2102. static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
  2103. struct ieee80211_tx_queue_stats *stats)
  2104. {
  2105. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2106. struct b43legacy_wldev *dev = wl->current_dev;
  2107. unsigned long flags;
  2108. int err = -ENODEV;
  2109. if (!dev)
  2110. goto out;
  2111. spin_lock_irqsave(&wl->irq_lock, flags);
  2112. if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
  2113. if (b43legacy_using_pio(dev))
  2114. b43legacy_pio_get_tx_stats(dev, stats);
  2115. else
  2116. b43legacy_dma_get_tx_stats(dev, stats);
  2117. err = 0;
  2118. }
  2119. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2120. out:
  2121. return err;
  2122. }
  2123. static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
  2124. struct ieee80211_low_level_stats *stats)
  2125. {
  2126. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2127. unsigned long flags;
  2128. spin_lock_irqsave(&wl->irq_lock, flags);
  2129. memcpy(stats, &wl->ieee_stats, sizeof(*stats));
  2130. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2131. return 0;
  2132. }
  2133. static const char *phymode_to_string(unsigned int phymode)
  2134. {
  2135. switch (phymode) {
  2136. case B43legacy_PHYMODE_B:
  2137. return "B";
  2138. case B43legacy_PHYMODE_G:
  2139. return "G";
  2140. default:
  2141. B43legacy_BUG_ON(1);
  2142. }
  2143. return "";
  2144. }
  2145. static int find_wldev_for_phymode(struct b43legacy_wl *wl,
  2146. unsigned int phymode,
  2147. struct b43legacy_wldev **dev,
  2148. bool *gmode)
  2149. {
  2150. struct b43legacy_wldev *d;
  2151. list_for_each_entry(d, &wl->devlist, list) {
  2152. if (d->phy.possible_phymodes & phymode) {
  2153. /* Ok, this device supports the PHY-mode.
  2154. * Set the gmode bit. */
  2155. *gmode = 1;
  2156. *dev = d;
  2157. return 0;
  2158. }
  2159. }
  2160. return -ESRCH;
  2161. }
  2162. static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
  2163. {
  2164. struct ssb_device *sdev = dev->dev;
  2165. u32 tmslow;
  2166. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2167. tmslow &= ~B43legacy_TMSLOW_GMODE;
  2168. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2169. tmslow |= SSB_TMSLOW_FGC;
  2170. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2171. msleep(1);
  2172. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2173. tmslow &= ~SSB_TMSLOW_FGC;
  2174. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2175. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2176. msleep(1);
  2177. }
  2178. /* Expects wl->mutex locked */
  2179. static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
  2180. unsigned int new_mode)
  2181. {
  2182. struct b43legacy_wldev *up_dev;
  2183. struct b43legacy_wldev *down_dev;
  2184. int err;
  2185. bool gmode = 0;
  2186. int prev_status;
  2187. err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
  2188. if (err) {
  2189. b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
  2190. phymode_to_string(new_mode));
  2191. return err;
  2192. }
  2193. if ((up_dev == wl->current_dev) &&
  2194. (!!wl->current_dev->phy.gmode == !!gmode))
  2195. /* This device is already running. */
  2196. return 0;
  2197. b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
  2198. phymode_to_string(new_mode));
  2199. down_dev = wl->current_dev;
  2200. prev_status = b43legacy_status(down_dev);
  2201. /* Shutdown the currently running core. */
  2202. if (prev_status >= B43legacy_STAT_STARTED)
  2203. b43legacy_wireless_core_stop(down_dev);
  2204. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2205. b43legacy_wireless_core_exit(down_dev);
  2206. if (down_dev != up_dev)
  2207. /* We switch to a different core, so we put PHY into
  2208. * RESET on the old core. */
  2209. b43legacy_put_phy_into_reset(down_dev);
  2210. /* Now start the new core. */
  2211. up_dev->phy.gmode = gmode;
  2212. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2213. err = b43legacy_wireless_core_init(up_dev);
  2214. if (err) {
  2215. b43legacyerr(wl, "Fatal: Could not initialize device"
  2216. " for newly selected %s-PHY mode\n",
  2217. phymode_to_string(new_mode));
  2218. goto init_failure;
  2219. }
  2220. }
  2221. if (prev_status >= B43legacy_STAT_STARTED) {
  2222. err = b43legacy_wireless_core_start(up_dev);
  2223. if (err) {
  2224. b43legacyerr(wl, "Fatal: Coult not start device for "
  2225. "newly selected %s-PHY mode\n",
  2226. phymode_to_string(new_mode));
  2227. b43legacy_wireless_core_exit(up_dev);
  2228. goto init_failure;
  2229. }
  2230. }
  2231. B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
  2232. b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
  2233. wl->current_dev = up_dev;
  2234. return 0;
  2235. init_failure:
  2236. /* Whoops, failed to init the new core. No core is operating now. */
  2237. wl->current_dev = NULL;
  2238. return err;
  2239. }
  2240. static int b43legacy_antenna_from_ieee80211(u8 antenna)
  2241. {
  2242. switch (antenna) {
  2243. case 0: /* default/diversity */
  2244. return B43legacy_ANTENNA_DEFAULT;
  2245. case 1: /* Antenna 0 */
  2246. return B43legacy_ANTENNA0;
  2247. case 2: /* Antenna 1 */
  2248. return B43legacy_ANTENNA1;
  2249. default:
  2250. return B43legacy_ANTENNA_DEFAULT;
  2251. }
  2252. }
  2253. static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
  2254. struct ieee80211_conf *conf)
  2255. {
  2256. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2257. struct b43legacy_wldev *dev;
  2258. struct b43legacy_phy *phy;
  2259. unsigned long flags;
  2260. unsigned int new_phymode = 0xFFFF;
  2261. int antenna_tx;
  2262. int antenna_rx;
  2263. int err = 0;
  2264. u32 savedirqs;
  2265. antenna_tx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_tx);
  2266. antenna_rx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_rx);
  2267. mutex_lock(&wl->mutex);
  2268. dev = wl->current_dev;
  2269. phy = &dev->phy;
  2270. /* Switch the PHY mode (if necessary). */
  2271. switch (conf->channel->band) {
  2272. case IEEE80211_BAND_2GHZ:
  2273. if (phy->type == B43legacy_PHYTYPE_B)
  2274. new_phymode = B43legacy_PHYMODE_B;
  2275. else
  2276. new_phymode = B43legacy_PHYMODE_G;
  2277. break;
  2278. default:
  2279. B43legacy_WARN_ON(1);
  2280. }
  2281. err = b43legacy_switch_phymode(wl, new_phymode);
  2282. if (err)
  2283. goto out_unlock_mutex;
  2284. /* Disable IRQs while reconfiguring the device.
  2285. * This makes it possible to drop the spinlock throughout
  2286. * the reconfiguration process. */
  2287. spin_lock_irqsave(&wl->irq_lock, flags);
  2288. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2289. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2290. goto out_unlock_mutex;
  2291. }
  2292. savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
  2293. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2294. b43legacy_synchronize_irq(dev);
  2295. /* Switch to the requested channel.
  2296. * The firmware takes care of races with the TX handler. */
  2297. if (conf->channel->hw_value != phy->channel)
  2298. b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
  2299. /* Enable/Disable ShortSlot timing. */
  2300. if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME))
  2301. != dev->short_slot) {
  2302. B43legacy_WARN_ON(phy->type != B43legacy_PHYTYPE_G);
  2303. if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
  2304. b43legacy_short_slot_timing_enable(dev);
  2305. else
  2306. b43legacy_short_slot_timing_disable(dev);
  2307. }
  2308. dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  2309. /* Adjust the desired TX power level. */
  2310. if (conf->power_level != 0) {
  2311. if (conf->power_level != phy->power_level) {
  2312. phy->power_level = conf->power_level;
  2313. b43legacy_phy_xmitpower(dev);
  2314. }
  2315. }
  2316. /* Antennas for RX and management frame TX. */
  2317. b43legacy_mgmtframe_txantenna(dev, antenna_tx);
  2318. /* Update templates for AP mode. */
  2319. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  2320. b43legacy_set_beacon_int(dev, conf->beacon_int);
  2321. if (!!conf->radio_enabled != phy->radio_on) {
  2322. if (conf->radio_enabled) {
  2323. b43legacy_radio_turn_on(dev);
  2324. b43legacyinfo(dev->wl, "Radio turned on by software\n");
  2325. if (!dev->radio_hw_enable)
  2326. b43legacyinfo(dev->wl, "The hardware RF-kill"
  2327. " button still turns the radio"
  2328. " physically off. Press the"
  2329. " button to turn it on.\n");
  2330. } else {
  2331. b43legacy_radio_turn_off(dev, 0);
  2332. b43legacyinfo(dev->wl, "Radio turned off by"
  2333. " software\n");
  2334. }
  2335. }
  2336. spin_lock_irqsave(&wl->irq_lock, flags);
  2337. b43legacy_interrupt_enable(dev, savedirqs);
  2338. mmiowb();
  2339. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2340. out_unlock_mutex:
  2341. mutex_unlock(&wl->mutex);
  2342. return err;
  2343. }
  2344. static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
  2345. unsigned int changed,
  2346. unsigned int *fflags,
  2347. int mc_count,
  2348. struct dev_addr_list *mc_list)
  2349. {
  2350. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2351. struct b43legacy_wldev *dev = wl->current_dev;
  2352. unsigned long flags;
  2353. if (!dev) {
  2354. *fflags = 0;
  2355. return;
  2356. }
  2357. spin_lock_irqsave(&wl->irq_lock, flags);
  2358. *fflags &= FIF_PROMISC_IN_BSS |
  2359. FIF_ALLMULTI |
  2360. FIF_FCSFAIL |
  2361. FIF_PLCPFAIL |
  2362. FIF_CONTROL |
  2363. FIF_OTHER_BSS |
  2364. FIF_BCN_PRBRESP_PROMISC;
  2365. changed &= FIF_PROMISC_IN_BSS |
  2366. FIF_ALLMULTI |
  2367. FIF_FCSFAIL |
  2368. FIF_PLCPFAIL |
  2369. FIF_CONTROL |
  2370. FIF_OTHER_BSS |
  2371. FIF_BCN_PRBRESP_PROMISC;
  2372. wl->filter_flags = *fflags;
  2373. if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
  2374. b43legacy_adjust_opmode(dev);
  2375. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2376. }
  2377. static int b43legacy_op_config_interface(struct ieee80211_hw *hw,
  2378. struct ieee80211_vif *vif,
  2379. struct ieee80211_if_conf *conf)
  2380. {
  2381. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2382. struct b43legacy_wldev *dev = wl->current_dev;
  2383. unsigned long flags;
  2384. if (!dev)
  2385. return -ENODEV;
  2386. mutex_lock(&wl->mutex);
  2387. spin_lock_irqsave(&wl->irq_lock, flags);
  2388. B43legacy_WARN_ON(wl->vif != vif);
  2389. if (conf->bssid)
  2390. memcpy(wl->bssid, conf->bssid, ETH_ALEN);
  2391. else
  2392. memset(wl->bssid, 0, ETH_ALEN);
  2393. if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
  2394. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
  2395. B43legacy_WARN_ON(vif->type != IEEE80211_IF_TYPE_AP);
  2396. b43legacy_set_ssid(dev, conf->ssid, conf->ssid_len);
  2397. if (conf->changed & IEEE80211_IFCC_BEACON)
  2398. b43legacy_update_templates(wl);
  2399. } else if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_IBSS)) {
  2400. if (conf->changed & IEEE80211_IFCC_BEACON)
  2401. b43legacy_update_templates(wl);
  2402. }
  2403. b43legacy_write_mac_bssid_templates(dev);
  2404. }
  2405. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2406. mutex_unlock(&wl->mutex);
  2407. return 0;
  2408. }
  2409. /* Locking: wl->mutex */
  2410. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
  2411. {
  2412. struct b43legacy_wl *wl = dev->wl;
  2413. unsigned long flags;
  2414. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  2415. return;
  2416. /* Disable and sync interrupts. We must do this before than
  2417. * setting the status to INITIALIZED, as the interrupt handler
  2418. * won't care about IRQs then. */
  2419. spin_lock_irqsave(&wl->irq_lock, flags);
  2420. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  2421. B43legacy_IRQ_ALL);
  2422. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
  2423. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2424. b43legacy_synchronize_irq(dev);
  2425. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2426. mutex_unlock(&wl->mutex);
  2427. /* Must unlock as it would otherwise deadlock. No races here.
  2428. * Cancel the possibly running self-rearming periodic work. */
  2429. cancel_delayed_work_sync(&dev->periodic_work);
  2430. mutex_lock(&wl->mutex);
  2431. ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
  2432. b43legacy_mac_suspend(dev);
  2433. free_irq(dev->dev->irq, dev);
  2434. b43legacydbg(wl, "Wireless interface stopped\n");
  2435. }
  2436. /* Locking: wl->mutex */
  2437. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
  2438. {
  2439. int err;
  2440. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
  2441. drain_txstatus_queue(dev);
  2442. err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
  2443. IRQF_SHARED, KBUILD_MODNAME, dev);
  2444. if (err) {
  2445. b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
  2446. dev->dev->irq);
  2447. goto out;
  2448. }
  2449. /* We are ready to run. */
  2450. b43legacy_set_status(dev, B43legacy_STAT_STARTED);
  2451. /* Start data flow (TX/RX) */
  2452. b43legacy_mac_enable(dev);
  2453. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  2454. /* Start maintenance work */
  2455. b43legacy_periodic_tasks_setup(dev);
  2456. b43legacydbg(dev->wl, "Wireless interface started\n");
  2457. out:
  2458. return err;
  2459. }
  2460. /* Get PHY and RADIO versioning numbers */
  2461. static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
  2462. {
  2463. struct b43legacy_phy *phy = &dev->phy;
  2464. u32 tmp;
  2465. u8 analog_type;
  2466. u8 phy_type;
  2467. u8 phy_rev;
  2468. u16 radio_manuf;
  2469. u16 radio_ver;
  2470. u16 radio_rev;
  2471. int unsupported = 0;
  2472. /* Get PHY versioning */
  2473. tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
  2474. analog_type = (tmp & B43legacy_PHYVER_ANALOG)
  2475. >> B43legacy_PHYVER_ANALOG_SHIFT;
  2476. phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
  2477. phy_rev = (tmp & B43legacy_PHYVER_VERSION);
  2478. switch (phy_type) {
  2479. case B43legacy_PHYTYPE_B:
  2480. if (phy_rev != 2 && phy_rev != 4
  2481. && phy_rev != 6 && phy_rev != 7)
  2482. unsupported = 1;
  2483. break;
  2484. case B43legacy_PHYTYPE_G:
  2485. if (phy_rev > 8)
  2486. unsupported = 1;
  2487. break;
  2488. default:
  2489. unsupported = 1;
  2490. };
  2491. if (unsupported) {
  2492. b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
  2493. "(Analog %u, Type %u, Revision %u)\n",
  2494. analog_type, phy_type, phy_rev);
  2495. return -EOPNOTSUPP;
  2496. }
  2497. b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
  2498. analog_type, phy_type, phy_rev);
  2499. /* Get RADIO versioning */
  2500. if (dev->dev->bus->chip_id == 0x4317) {
  2501. if (dev->dev->bus->chip_rev == 0)
  2502. tmp = 0x3205017F;
  2503. else if (dev->dev->bus->chip_rev == 1)
  2504. tmp = 0x4205017F;
  2505. else
  2506. tmp = 0x5205017F;
  2507. } else {
  2508. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2509. B43legacy_RADIOCTL_ID);
  2510. tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
  2511. tmp <<= 16;
  2512. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2513. B43legacy_RADIOCTL_ID);
  2514. tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
  2515. }
  2516. radio_manuf = (tmp & 0x00000FFF);
  2517. radio_ver = (tmp & 0x0FFFF000) >> 12;
  2518. radio_rev = (tmp & 0xF0000000) >> 28;
  2519. switch (phy_type) {
  2520. case B43legacy_PHYTYPE_B:
  2521. if ((radio_ver & 0xFFF0) != 0x2050)
  2522. unsupported = 1;
  2523. break;
  2524. case B43legacy_PHYTYPE_G:
  2525. if (radio_ver != 0x2050)
  2526. unsupported = 1;
  2527. break;
  2528. default:
  2529. B43legacy_BUG_ON(1);
  2530. }
  2531. if (unsupported) {
  2532. b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
  2533. "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
  2534. radio_manuf, radio_ver, radio_rev);
  2535. return -EOPNOTSUPP;
  2536. }
  2537. b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
  2538. " Revision %u\n", radio_manuf, radio_ver, radio_rev);
  2539. phy->radio_manuf = radio_manuf;
  2540. phy->radio_ver = radio_ver;
  2541. phy->radio_rev = radio_rev;
  2542. phy->analog = analog_type;
  2543. phy->type = phy_type;
  2544. phy->rev = phy_rev;
  2545. return 0;
  2546. }
  2547. static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
  2548. struct b43legacy_phy *phy)
  2549. {
  2550. struct b43legacy_lopair *lo;
  2551. int i;
  2552. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2553. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2554. /* Assume the radio is enabled. If it's not enabled, the state will
  2555. * immediately get fixed on the first periodic work run. */
  2556. dev->radio_hw_enable = 1;
  2557. phy->savedpctlreg = 0xFFFF;
  2558. phy->aci_enable = 0;
  2559. phy->aci_wlan_automatic = 0;
  2560. phy->aci_hw_rssi = 0;
  2561. lo = phy->_lo_pairs;
  2562. if (lo)
  2563. memset(lo, 0, sizeof(struct b43legacy_lopair) *
  2564. B43legacy_LO_COUNT);
  2565. phy->max_lb_gain = 0;
  2566. phy->trsw_rx_gain = 0;
  2567. /* Set default attenuation values. */
  2568. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2569. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2570. phy->txctl1 = b43legacy_default_txctl1(dev);
  2571. phy->txpwr_offset = 0;
  2572. /* NRSSI */
  2573. phy->nrssislope = 0;
  2574. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2575. phy->nrssi[i] = -1000;
  2576. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2577. phy->nrssi_lt[i] = i;
  2578. phy->lofcal = 0xFFFF;
  2579. phy->initval = 0xFFFF;
  2580. phy->interfmode = B43legacy_INTERFMODE_NONE;
  2581. phy->channel = 0xFF;
  2582. }
  2583. static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
  2584. {
  2585. /* Flags */
  2586. dev->dfq_valid = 0;
  2587. /* Stats */
  2588. memset(&dev->stats, 0, sizeof(dev->stats));
  2589. setup_struct_phy_for_init(dev, &dev->phy);
  2590. /* IRQ related flags */
  2591. dev->irq_reason = 0;
  2592. memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
  2593. dev->irq_savedstate = B43legacy_IRQ_MASKTEMPLATE;
  2594. dev->mac_suspended = 1;
  2595. /* Noise calculation context */
  2596. memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
  2597. }
  2598. static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
  2599. {
  2600. #ifdef CONFIG_SSB_DRIVER_PCICORE
  2601. struct ssb_bus *bus = dev->dev->bus;
  2602. u32 tmp;
  2603. if (bus->pcicore.dev &&
  2604. bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
  2605. bus->pcicore.dev->id.revision <= 5) {
  2606. /* IMCFGLO timeouts workaround. */
  2607. tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
  2608. tmp &= ~SSB_IMCFGLO_REQTO;
  2609. tmp &= ~SSB_IMCFGLO_SERTO;
  2610. switch (bus->bustype) {
  2611. case SSB_BUSTYPE_PCI:
  2612. case SSB_BUSTYPE_PCMCIA:
  2613. tmp |= 0x32;
  2614. break;
  2615. case SSB_BUSTYPE_SSB:
  2616. tmp |= 0x53;
  2617. break;
  2618. }
  2619. ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
  2620. }
  2621. #endif /* CONFIG_SSB_DRIVER_PCICORE */
  2622. }
  2623. /* Write the short and long frame retry limit values. */
  2624. static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
  2625. unsigned int short_retry,
  2626. unsigned int long_retry)
  2627. {
  2628. /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
  2629. * the chip-internal counter. */
  2630. short_retry = min(short_retry, (unsigned int)0xF);
  2631. long_retry = min(long_retry, (unsigned int)0xF);
  2632. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
  2633. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
  2634. }
  2635. static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,
  2636. bool idle) {
  2637. u16 pu_delay = 1050;
  2638. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS) || idle)
  2639. pu_delay = 500;
  2640. if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
  2641. pu_delay = max(pu_delay, (u16)2400);
  2642. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2643. B43legacy_SHM_SH_SPUWKUP, pu_delay);
  2644. }
  2645. /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
  2646. static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev)
  2647. {
  2648. u16 pretbtt;
  2649. /* The time value is in microseconds. */
  2650. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
  2651. pretbtt = 2;
  2652. else
  2653. pretbtt = 250;
  2654. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2655. B43legacy_SHM_SH_PRETBTT, pretbtt);
  2656. b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt);
  2657. }
  2658. /* Shutdown a wireless core */
  2659. /* Locking: wl->mutex */
  2660. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
  2661. {
  2662. struct b43legacy_phy *phy = &dev->phy;
  2663. u32 macctl;
  2664. B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
  2665. if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
  2666. return;
  2667. b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
  2668. /* Stop the microcode PSM. */
  2669. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  2670. macctl &= ~B43legacy_MACCTL_PSM_RUN;
  2671. macctl |= B43legacy_MACCTL_PSM_JMP0;
  2672. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  2673. b43legacy_leds_exit(dev);
  2674. b43legacy_rng_exit(dev->wl);
  2675. b43legacy_pio_free(dev);
  2676. b43legacy_dma_free(dev);
  2677. b43legacy_chip_exit(dev);
  2678. b43legacy_radio_turn_off(dev, 1);
  2679. b43legacy_switch_analog(dev, 0);
  2680. if (phy->dyn_tssi_tbl)
  2681. kfree(phy->tssi2dbm);
  2682. kfree(phy->lo_control);
  2683. phy->lo_control = NULL;
  2684. if (dev->wl->current_beacon) {
  2685. dev_kfree_skb_any(dev->wl->current_beacon);
  2686. dev->wl->current_beacon = NULL;
  2687. }
  2688. ssb_device_disable(dev->dev, 0);
  2689. ssb_bus_may_powerdown(dev->dev->bus);
  2690. }
  2691. static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
  2692. {
  2693. struct b43legacy_phy *phy = &dev->phy;
  2694. int i;
  2695. /* Set default attenuation values. */
  2696. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2697. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2698. phy->txctl1 = b43legacy_default_txctl1(dev);
  2699. phy->txctl2 = 0xFFFF;
  2700. phy->txpwr_offset = 0;
  2701. /* NRSSI */
  2702. phy->nrssislope = 0;
  2703. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2704. phy->nrssi[i] = -1000;
  2705. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2706. phy->nrssi_lt[i] = i;
  2707. phy->lofcal = 0xFFFF;
  2708. phy->initval = 0xFFFF;
  2709. phy->aci_enable = 0;
  2710. phy->aci_wlan_automatic = 0;
  2711. phy->aci_hw_rssi = 0;
  2712. phy->antenna_diversity = 0xFFFF;
  2713. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2714. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2715. /* Flags */
  2716. phy->calibrated = 0;
  2717. if (phy->_lo_pairs)
  2718. memset(phy->_lo_pairs, 0,
  2719. sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
  2720. memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
  2721. }
  2722. /* Initialize a wireless core */
  2723. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
  2724. {
  2725. struct b43legacy_wl *wl = dev->wl;
  2726. struct ssb_bus *bus = dev->dev->bus;
  2727. struct b43legacy_phy *phy = &dev->phy;
  2728. struct ssb_sprom *sprom = &dev->dev->bus->sprom;
  2729. int err;
  2730. u32 hf;
  2731. u32 tmp;
  2732. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2733. err = ssb_bus_powerup(bus, 0);
  2734. if (err)
  2735. goto out;
  2736. if (!ssb_device_is_enabled(dev->dev)) {
  2737. tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
  2738. b43legacy_wireless_core_reset(dev, tmp);
  2739. }
  2740. if ((phy->type == B43legacy_PHYTYPE_B) ||
  2741. (phy->type == B43legacy_PHYTYPE_G)) {
  2742. phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
  2743. * B43legacy_LO_COUNT,
  2744. GFP_KERNEL);
  2745. if (!phy->_lo_pairs)
  2746. return -ENOMEM;
  2747. }
  2748. setup_struct_wldev_for_init(dev);
  2749. err = b43legacy_phy_init_tssi2dbm_table(dev);
  2750. if (err)
  2751. goto err_kfree_lo_control;
  2752. /* Enable IRQ routing to this device. */
  2753. ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
  2754. b43legacy_imcfglo_timeouts_workaround(dev);
  2755. prepare_phy_data_for_init(dev);
  2756. b43legacy_phy_calibrate(dev);
  2757. err = b43legacy_chip_init(dev);
  2758. if (err)
  2759. goto err_kfree_tssitbl;
  2760. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2761. B43legacy_SHM_SH_WLCOREREV,
  2762. dev->dev->id.revision);
  2763. hf = b43legacy_hf_read(dev);
  2764. if (phy->type == B43legacy_PHYTYPE_G) {
  2765. hf |= B43legacy_HF_SYMW;
  2766. if (phy->rev == 1)
  2767. hf |= B43legacy_HF_GDCW;
  2768. if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
  2769. hf |= B43legacy_HF_OFDMPABOOST;
  2770. } else if (phy->type == B43legacy_PHYTYPE_B) {
  2771. hf |= B43legacy_HF_SYMW;
  2772. if (phy->rev >= 2 && phy->radio_ver == 0x2050)
  2773. hf &= ~B43legacy_HF_GDCW;
  2774. }
  2775. b43legacy_hf_write(dev, hf);
  2776. b43legacy_set_retry_limits(dev,
  2777. B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
  2778. B43legacy_DEFAULT_LONG_RETRY_LIMIT);
  2779. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2780. 0x0044, 3);
  2781. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2782. 0x0046, 2);
  2783. /* Disable sending probe responses from firmware.
  2784. * Setting the MaxTime to one usec will always trigger
  2785. * a timeout, so we never send any probe resp.
  2786. * A timeout of zero is infinite. */
  2787. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2788. B43legacy_SHM_SH_PRMAXTIME, 1);
  2789. b43legacy_rate_memory_init(dev);
  2790. /* Minimum Contention Window */
  2791. if (phy->type == B43legacy_PHYTYPE_B)
  2792. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2793. 0x0003, 31);
  2794. else
  2795. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2796. 0x0003, 15);
  2797. /* Maximum Contention Window */
  2798. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2799. 0x0004, 1023);
  2800. do {
  2801. if (b43legacy_using_pio(dev))
  2802. err = b43legacy_pio_init(dev);
  2803. else {
  2804. err = b43legacy_dma_init(dev);
  2805. if (!err)
  2806. b43legacy_qos_init(dev);
  2807. }
  2808. } while (err == -EAGAIN);
  2809. if (err)
  2810. goto err_chip_exit;
  2811. b43legacy_set_synth_pu_delay(dev, 1);
  2812. ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
  2813. b43legacy_upload_card_macaddress(dev);
  2814. b43legacy_security_init(dev);
  2815. b43legacy_rng_init(wl);
  2816. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2817. b43legacy_leds_init(dev);
  2818. out:
  2819. return err;
  2820. err_chip_exit:
  2821. b43legacy_chip_exit(dev);
  2822. err_kfree_tssitbl:
  2823. if (phy->dyn_tssi_tbl)
  2824. kfree(phy->tssi2dbm);
  2825. err_kfree_lo_control:
  2826. kfree(phy->lo_control);
  2827. phy->lo_control = NULL;
  2828. ssb_bus_may_powerdown(bus);
  2829. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2830. return err;
  2831. }
  2832. static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
  2833. struct ieee80211_if_init_conf *conf)
  2834. {
  2835. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2836. struct b43legacy_wldev *dev;
  2837. unsigned long flags;
  2838. int err = -EOPNOTSUPP;
  2839. /* TODO: allow WDS/AP devices to coexist */
  2840. if (conf->type != IEEE80211_IF_TYPE_AP &&
  2841. conf->type != IEEE80211_IF_TYPE_STA &&
  2842. conf->type != IEEE80211_IF_TYPE_WDS &&
  2843. conf->type != IEEE80211_IF_TYPE_IBSS)
  2844. return -EOPNOTSUPP;
  2845. mutex_lock(&wl->mutex);
  2846. if (wl->operating)
  2847. goto out_mutex_unlock;
  2848. b43legacydbg(wl, "Adding Interface type %d\n", conf->type);
  2849. dev = wl->current_dev;
  2850. wl->operating = 1;
  2851. wl->vif = conf->vif;
  2852. wl->if_type = conf->type;
  2853. memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
  2854. spin_lock_irqsave(&wl->irq_lock, flags);
  2855. b43legacy_adjust_opmode(dev);
  2856. b43legacy_set_pretbtt(dev);
  2857. b43legacy_set_synth_pu_delay(dev, 0);
  2858. b43legacy_upload_card_macaddress(dev);
  2859. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2860. err = 0;
  2861. out_mutex_unlock:
  2862. mutex_unlock(&wl->mutex);
  2863. return err;
  2864. }
  2865. static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
  2866. struct ieee80211_if_init_conf *conf)
  2867. {
  2868. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2869. struct b43legacy_wldev *dev = wl->current_dev;
  2870. unsigned long flags;
  2871. b43legacydbg(wl, "Removing Interface type %d\n", conf->type);
  2872. mutex_lock(&wl->mutex);
  2873. B43legacy_WARN_ON(!wl->operating);
  2874. B43legacy_WARN_ON(wl->vif != conf->vif);
  2875. wl->vif = NULL;
  2876. wl->operating = 0;
  2877. spin_lock_irqsave(&wl->irq_lock, flags);
  2878. b43legacy_adjust_opmode(dev);
  2879. memset(wl->mac_addr, 0, ETH_ALEN);
  2880. b43legacy_upload_card_macaddress(dev);
  2881. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2882. mutex_unlock(&wl->mutex);
  2883. }
  2884. static int b43legacy_op_start(struct ieee80211_hw *hw)
  2885. {
  2886. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2887. struct b43legacy_wldev *dev = wl->current_dev;
  2888. int did_init = 0;
  2889. int err = 0;
  2890. bool do_rfkill_exit = 0;
  2891. /* First register RFkill.
  2892. * LEDs that are registered later depend on it. */
  2893. b43legacy_rfkill_init(dev);
  2894. /* Kill all old instance specific information to make sure
  2895. * the card won't use it in the short timeframe between start
  2896. * and mac80211 reconfiguring it. */
  2897. memset(wl->bssid, 0, ETH_ALEN);
  2898. memset(wl->mac_addr, 0, ETH_ALEN);
  2899. wl->filter_flags = 0;
  2900. mutex_lock(&wl->mutex);
  2901. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
  2902. err = b43legacy_wireless_core_init(dev);
  2903. if (err) {
  2904. do_rfkill_exit = 1;
  2905. goto out_mutex_unlock;
  2906. }
  2907. did_init = 1;
  2908. }
  2909. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2910. err = b43legacy_wireless_core_start(dev);
  2911. if (err) {
  2912. if (did_init)
  2913. b43legacy_wireless_core_exit(dev);
  2914. do_rfkill_exit = 1;
  2915. goto out_mutex_unlock;
  2916. }
  2917. }
  2918. out_mutex_unlock:
  2919. mutex_unlock(&wl->mutex);
  2920. if (do_rfkill_exit)
  2921. b43legacy_rfkill_exit(dev);
  2922. return err;
  2923. }
  2924. static void b43legacy_op_stop(struct ieee80211_hw *hw)
  2925. {
  2926. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2927. struct b43legacy_wldev *dev = wl->current_dev;
  2928. b43legacy_rfkill_exit(dev);
  2929. mutex_lock(&wl->mutex);
  2930. if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
  2931. b43legacy_wireless_core_stop(dev);
  2932. b43legacy_wireless_core_exit(dev);
  2933. mutex_unlock(&wl->mutex);
  2934. }
  2935. static int b43legacy_op_set_retry_limit(struct ieee80211_hw *hw,
  2936. u32 short_retry_limit,
  2937. u32 long_retry_limit)
  2938. {
  2939. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2940. struct b43legacy_wldev *dev;
  2941. int err = 0;
  2942. mutex_lock(&wl->mutex);
  2943. dev = wl->current_dev;
  2944. if (unlikely(!dev ||
  2945. (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED))) {
  2946. err = -ENODEV;
  2947. goto out_unlock;
  2948. }
  2949. b43legacy_set_retry_limits(dev, short_retry_limit, long_retry_limit);
  2950. out_unlock:
  2951. mutex_unlock(&wl->mutex);
  2952. return err;
  2953. }
  2954. static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw,
  2955. int aid, int set)
  2956. {
  2957. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2958. unsigned long flags;
  2959. spin_lock_irqsave(&wl->irq_lock, flags);
  2960. b43legacy_update_templates(wl);
  2961. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2962. return 0;
  2963. }
  2964. static const struct ieee80211_ops b43legacy_hw_ops = {
  2965. .tx = b43legacy_op_tx,
  2966. .conf_tx = b43legacy_op_conf_tx,
  2967. .add_interface = b43legacy_op_add_interface,
  2968. .remove_interface = b43legacy_op_remove_interface,
  2969. .config = b43legacy_op_dev_config,
  2970. .config_interface = b43legacy_op_config_interface,
  2971. .configure_filter = b43legacy_op_configure_filter,
  2972. .get_stats = b43legacy_op_get_stats,
  2973. .get_tx_stats = b43legacy_op_get_tx_stats,
  2974. .start = b43legacy_op_start,
  2975. .stop = b43legacy_op_stop,
  2976. .set_retry_limit = b43legacy_op_set_retry_limit,
  2977. .set_tim = b43legacy_op_beacon_set_tim,
  2978. };
  2979. /* Hard-reset the chip. Do not call this directly.
  2980. * Use b43legacy_controller_restart()
  2981. */
  2982. static void b43legacy_chip_reset(struct work_struct *work)
  2983. {
  2984. struct b43legacy_wldev *dev =
  2985. container_of(work, struct b43legacy_wldev, restart_work);
  2986. struct b43legacy_wl *wl = dev->wl;
  2987. int err = 0;
  2988. int prev_status;
  2989. mutex_lock(&wl->mutex);
  2990. prev_status = b43legacy_status(dev);
  2991. /* Bring the device down... */
  2992. if (prev_status >= B43legacy_STAT_STARTED)
  2993. b43legacy_wireless_core_stop(dev);
  2994. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2995. b43legacy_wireless_core_exit(dev);
  2996. /* ...and up again. */
  2997. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2998. err = b43legacy_wireless_core_init(dev);
  2999. if (err)
  3000. goto out;
  3001. }
  3002. if (prev_status >= B43legacy_STAT_STARTED) {
  3003. err = b43legacy_wireless_core_start(dev);
  3004. if (err) {
  3005. b43legacy_wireless_core_exit(dev);
  3006. goto out;
  3007. }
  3008. }
  3009. out:
  3010. if (err)
  3011. wl->current_dev = NULL; /* Failed to init the dev. */
  3012. mutex_unlock(&wl->mutex);
  3013. if (err)
  3014. b43legacyerr(wl, "Controller restart FAILED\n");
  3015. else
  3016. b43legacyinfo(wl, "Controller restarted\n");
  3017. }
  3018. static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
  3019. int have_bphy,
  3020. int have_gphy)
  3021. {
  3022. struct ieee80211_hw *hw = dev->wl->hw;
  3023. struct b43legacy_phy *phy = &dev->phy;
  3024. phy->possible_phymodes = 0;
  3025. if (have_bphy) {
  3026. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3027. &b43legacy_band_2GHz_BPHY;
  3028. phy->possible_phymodes |= B43legacy_PHYMODE_B;
  3029. }
  3030. if (have_gphy) {
  3031. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3032. &b43legacy_band_2GHz_GPHY;
  3033. phy->possible_phymodes |= B43legacy_PHYMODE_G;
  3034. }
  3035. return 0;
  3036. }
  3037. static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
  3038. {
  3039. /* We release firmware that late to not be required to re-request
  3040. * is all the time when we reinit the core. */
  3041. b43legacy_release_firmware(dev);
  3042. }
  3043. static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
  3044. {
  3045. struct b43legacy_wl *wl = dev->wl;
  3046. struct ssb_bus *bus = dev->dev->bus;
  3047. struct pci_dev *pdev = bus->host_pci;
  3048. int err;
  3049. int have_bphy = 0;
  3050. int have_gphy = 0;
  3051. u32 tmp;
  3052. /* Do NOT do any device initialization here.
  3053. * Do it in wireless_core_init() instead.
  3054. * This function is for gathering basic information about the HW, only.
  3055. * Also some structs may be set up here. But most likely you want to
  3056. * have that in core_init(), too.
  3057. */
  3058. err = ssb_bus_powerup(bus, 0);
  3059. if (err) {
  3060. b43legacyerr(wl, "Bus powerup failed\n");
  3061. goto out;
  3062. }
  3063. /* Get the PHY type. */
  3064. if (dev->dev->id.revision >= 5) {
  3065. u32 tmshigh;
  3066. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  3067. have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
  3068. if (!have_gphy)
  3069. have_bphy = 1;
  3070. } else if (dev->dev->id.revision == 4)
  3071. have_gphy = 1;
  3072. else
  3073. have_bphy = 1;
  3074. dev->phy.gmode = (have_gphy || have_bphy);
  3075. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  3076. b43legacy_wireless_core_reset(dev, tmp);
  3077. err = b43legacy_phy_versioning(dev);
  3078. if (err)
  3079. goto err_powerdown;
  3080. /* Check if this device supports multiband. */
  3081. if (!pdev ||
  3082. (pdev->device != 0x4312 &&
  3083. pdev->device != 0x4319 &&
  3084. pdev->device != 0x4324)) {
  3085. /* No multiband support. */
  3086. have_bphy = 0;
  3087. have_gphy = 0;
  3088. switch (dev->phy.type) {
  3089. case B43legacy_PHYTYPE_B:
  3090. have_bphy = 1;
  3091. break;
  3092. case B43legacy_PHYTYPE_G:
  3093. have_gphy = 1;
  3094. break;
  3095. default:
  3096. B43legacy_BUG_ON(1);
  3097. }
  3098. }
  3099. dev->phy.gmode = (have_gphy || have_bphy);
  3100. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  3101. b43legacy_wireless_core_reset(dev, tmp);
  3102. err = b43legacy_validate_chipaccess(dev);
  3103. if (err)
  3104. goto err_powerdown;
  3105. err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
  3106. if (err)
  3107. goto err_powerdown;
  3108. /* Now set some default "current_dev" */
  3109. if (!wl->current_dev)
  3110. wl->current_dev = dev;
  3111. INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
  3112. b43legacy_radio_turn_off(dev, 1);
  3113. b43legacy_switch_analog(dev, 0);
  3114. ssb_device_disable(dev->dev, 0);
  3115. ssb_bus_may_powerdown(bus);
  3116. out:
  3117. return err;
  3118. err_powerdown:
  3119. ssb_bus_may_powerdown(bus);
  3120. return err;
  3121. }
  3122. static void b43legacy_one_core_detach(struct ssb_device *dev)
  3123. {
  3124. struct b43legacy_wldev *wldev;
  3125. struct b43legacy_wl *wl;
  3126. /* Do not cancel ieee80211-workqueue based work here.
  3127. * See comment in b43legacy_remove(). */
  3128. wldev = ssb_get_drvdata(dev);
  3129. wl = wldev->wl;
  3130. b43legacy_debugfs_remove_device(wldev);
  3131. b43legacy_wireless_core_detach(wldev);
  3132. list_del(&wldev->list);
  3133. wl->nr_devs--;
  3134. ssb_set_drvdata(dev, NULL);
  3135. kfree(wldev);
  3136. }
  3137. static int b43legacy_one_core_attach(struct ssb_device *dev,
  3138. struct b43legacy_wl *wl)
  3139. {
  3140. struct b43legacy_wldev *wldev;
  3141. struct pci_dev *pdev;
  3142. int err = -ENOMEM;
  3143. if (!list_empty(&wl->devlist)) {
  3144. /* We are not the first core on this chip. */
  3145. pdev = dev->bus->host_pci;
  3146. /* Only special chips support more than one wireless
  3147. * core, although some of the other chips have more than
  3148. * one wireless core as well. Check for this and
  3149. * bail out early.
  3150. */
  3151. if (!pdev ||
  3152. ((pdev->device != 0x4321) &&
  3153. (pdev->device != 0x4313) &&
  3154. (pdev->device != 0x431A))) {
  3155. b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
  3156. return -ENODEV;
  3157. }
  3158. }
  3159. wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
  3160. if (!wldev)
  3161. goto out;
  3162. wldev->dev = dev;
  3163. wldev->wl = wl;
  3164. b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
  3165. wldev->bad_frames_preempt = modparam_bad_frames_preempt;
  3166. tasklet_init(&wldev->isr_tasklet,
  3167. (void (*)(unsigned long))b43legacy_interrupt_tasklet,
  3168. (unsigned long)wldev);
  3169. if (modparam_pio)
  3170. wldev->__using_pio = 1;
  3171. INIT_LIST_HEAD(&wldev->list);
  3172. err = b43legacy_wireless_core_attach(wldev);
  3173. if (err)
  3174. goto err_kfree_wldev;
  3175. list_add(&wldev->list, &wl->devlist);
  3176. wl->nr_devs++;
  3177. ssb_set_drvdata(dev, wldev);
  3178. b43legacy_debugfs_add_device(wldev);
  3179. out:
  3180. return err;
  3181. err_kfree_wldev:
  3182. kfree(wldev);
  3183. return err;
  3184. }
  3185. static void b43legacy_sprom_fixup(struct ssb_bus *bus)
  3186. {
  3187. /* boardflags workarounds */
  3188. if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
  3189. bus->boardinfo.type == 0x4E &&
  3190. bus->boardinfo.rev > 0x40)
  3191. bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
  3192. }
  3193. static void b43legacy_wireless_exit(struct ssb_device *dev,
  3194. struct b43legacy_wl *wl)
  3195. {
  3196. struct ieee80211_hw *hw = wl->hw;
  3197. ssb_set_devtypedata(dev, NULL);
  3198. ieee80211_free_hw(hw);
  3199. }
  3200. static int b43legacy_wireless_init(struct ssb_device *dev)
  3201. {
  3202. struct ssb_sprom *sprom = &dev->bus->sprom;
  3203. struct ieee80211_hw *hw;
  3204. struct b43legacy_wl *wl;
  3205. int err = -ENOMEM;
  3206. b43legacy_sprom_fixup(dev->bus);
  3207. hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
  3208. if (!hw) {
  3209. b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
  3210. goto out;
  3211. }
  3212. /* fill hw info */
  3213. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  3214. IEEE80211_HW_SIGNAL_DBM |
  3215. IEEE80211_HW_NOISE_DBM;
  3216. hw->queues = 1; /* FIXME: hardware has more queues */
  3217. SET_IEEE80211_DEV(hw, dev->dev);
  3218. if (is_valid_ether_addr(sprom->et1mac))
  3219. SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
  3220. else
  3221. SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
  3222. /* Get and initialize struct b43legacy_wl */
  3223. wl = hw_to_b43legacy_wl(hw);
  3224. memset(wl, 0, sizeof(*wl));
  3225. wl->hw = hw;
  3226. spin_lock_init(&wl->irq_lock);
  3227. spin_lock_init(&wl->leds_lock);
  3228. mutex_init(&wl->mutex);
  3229. INIT_LIST_HEAD(&wl->devlist);
  3230. ssb_set_devtypedata(dev, wl);
  3231. b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
  3232. err = 0;
  3233. out:
  3234. return err;
  3235. }
  3236. static int b43legacy_probe(struct ssb_device *dev,
  3237. const struct ssb_device_id *id)
  3238. {
  3239. struct b43legacy_wl *wl;
  3240. int err;
  3241. int first = 0;
  3242. wl = ssb_get_devtypedata(dev);
  3243. if (!wl) {
  3244. /* Probing the first core - setup common struct b43legacy_wl */
  3245. first = 1;
  3246. err = b43legacy_wireless_init(dev);
  3247. if (err)
  3248. goto out;
  3249. wl = ssb_get_devtypedata(dev);
  3250. B43legacy_WARN_ON(!wl);
  3251. }
  3252. err = b43legacy_one_core_attach(dev, wl);
  3253. if (err)
  3254. goto err_wireless_exit;
  3255. if (first) {
  3256. err = ieee80211_register_hw(wl->hw);
  3257. if (err)
  3258. goto err_one_core_detach;
  3259. }
  3260. out:
  3261. return err;
  3262. err_one_core_detach:
  3263. b43legacy_one_core_detach(dev);
  3264. err_wireless_exit:
  3265. if (first)
  3266. b43legacy_wireless_exit(dev, wl);
  3267. return err;
  3268. }
  3269. static void b43legacy_remove(struct ssb_device *dev)
  3270. {
  3271. struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
  3272. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3273. /* We must cancel any work here before unregistering from ieee80211,
  3274. * as the ieee80211 unreg will destroy the workqueue. */
  3275. cancel_work_sync(&wldev->restart_work);
  3276. B43legacy_WARN_ON(!wl);
  3277. if (wl->current_dev == wldev)
  3278. ieee80211_unregister_hw(wl->hw);
  3279. b43legacy_one_core_detach(dev);
  3280. if (list_empty(&wl->devlist))
  3281. /* Last core on the chip unregistered.
  3282. * We can destroy common struct b43legacy_wl.
  3283. */
  3284. b43legacy_wireless_exit(dev, wl);
  3285. }
  3286. /* Perform a hardware reset. This can be called from any context. */
  3287. void b43legacy_controller_restart(struct b43legacy_wldev *dev,
  3288. const char *reason)
  3289. {
  3290. /* Must avoid requeueing, if we are in shutdown. */
  3291. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
  3292. return;
  3293. b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
  3294. queue_work(dev->wl->hw->workqueue, &dev->restart_work);
  3295. }
  3296. #ifdef CONFIG_PM
  3297. static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
  3298. {
  3299. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3300. struct b43legacy_wl *wl = wldev->wl;
  3301. b43legacydbg(wl, "Suspending...\n");
  3302. mutex_lock(&wl->mutex);
  3303. wldev->suspend_init_status = b43legacy_status(wldev);
  3304. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
  3305. b43legacy_wireless_core_stop(wldev);
  3306. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
  3307. b43legacy_wireless_core_exit(wldev);
  3308. mutex_unlock(&wl->mutex);
  3309. b43legacydbg(wl, "Device suspended.\n");
  3310. return 0;
  3311. }
  3312. static int b43legacy_resume(struct ssb_device *dev)
  3313. {
  3314. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3315. struct b43legacy_wl *wl = wldev->wl;
  3316. int err = 0;
  3317. b43legacydbg(wl, "Resuming...\n");
  3318. mutex_lock(&wl->mutex);
  3319. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
  3320. err = b43legacy_wireless_core_init(wldev);
  3321. if (err) {
  3322. b43legacyerr(wl, "Resume failed at core init\n");
  3323. goto out;
  3324. }
  3325. }
  3326. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
  3327. err = b43legacy_wireless_core_start(wldev);
  3328. if (err) {
  3329. b43legacy_wireless_core_exit(wldev);
  3330. b43legacyerr(wl, "Resume failed at core start\n");
  3331. goto out;
  3332. }
  3333. }
  3334. b43legacydbg(wl, "Device resumed.\n");
  3335. out:
  3336. mutex_unlock(&wl->mutex);
  3337. return err;
  3338. }
  3339. #else /* CONFIG_PM */
  3340. # define b43legacy_suspend NULL
  3341. # define b43legacy_resume NULL
  3342. #endif /* CONFIG_PM */
  3343. static struct ssb_driver b43legacy_ssb_driver = {
  3344. .name = KBUILD_MODNAME,
  3345. .id_table = b43legacy_ssb_tbl,
  3346. .probe = b43legacy_probe,
  3347. .remove = b43legacy_remove,
  3348. .suspend = b43legacy_suspend,
  3349. .resume = b43legacy_resume,
  3350. };
  3351. static void b43legacy_print_driverinfo(void)
  3352. {
  3353. const char *feat_pci = "", *feat_leds = "", *feat_rfkill = "",
  3354. *feat_pio = "", *feat_dma = "";
  3355. #ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
  3356. feat_pci = "P";
  3357. #endif
  3358. #ifdef CONFIG_B43LEGACY_LEDS
  3359. feat_leds = "L";
  3360. #endif
  3361. #ifdef CONFIG_B43LEGACY_RFKILL
  3362. feat_rfkill = "R";
  3363. #endif
  3364. #ifdef CONFIG_B43LEGACY_PIO
  3365. feat_pio = "I";
  3366. #endif
  3367. #ifdef CONFIG_B43LEGACY_DMA
  3368. feat_dma = "D";
  3369. #endif
  3370. printk(KERN_INFO "Broadcom 43xx-legacy driver loaded "
  3371. "[ Features: %s%s%s%s%s, Firmware-ID: "
  3372. B43legacy_SUPPORTED_FIRMWARE_ID " ]\n",
  3373. feat_pci, feat_leds, feat_rfkill, feat_pio, feat_dma);
  3374. }
  3375. static int __init b43legacy_init(void)
  3376. {
  3377. int err;
  3378. b43legacy_debugfs_init();
  3379. err = ssb_driver_register(&b43legacy_ssb_driver);
  3380. if (err)
  3381. goto err_dfs_exit;
  3382. b43legacy_print_driverinfo();
  3383. return err;
  3384. err_dfs_exit:
  3385. b43legacy_debugfs_exit();
  3386. return err;
  3387. }
  3388. static void __exit b43legacy_exit(void)
  3389. {
  3390. ssb_driver_unregister(&b43legacy_ssb_driver);
  3391. b43legacy_debugfs_exit();
  3392. }
  3393. module_init(b43legacy_init)
  3394. module_exit(b43legacy_exit)