tg3.c 391 KB

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  1. /*
  2. * tg3.c: Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2005-2007 Broadcom Corporation.
  8. *
  9. * Firmware is:
  10. * Derived from proprietary unpublished source code,
  11. * Copyright (C) 2000-2003 Broadcom Corporation.
  12. *
  13. * Permission is hereby granted for the distribution of this firmware
  14. * data in hexadecimal or equivalent format, provided this copyright
  15. * notice is accompanying it.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include <linux/compiler.h>
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #include <linux/in.h>
  25. #include <linux/init.h>
  26. #include <linux/ioport.h>
  27. #include <linux/pci.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/skbuff.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/mii.h>
  33. #include <linux/phy.h>
  34. #include <linux/brcmphy.h>
  35. #include <linux/if_vlan.h>
  36. #include <linux/ip.h>
  37. #include <linux/tcp.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/prefetch.h>
  40. #include <linux/dma-mapping.h>
  41. #include <net/checksum.h>
  42. #include <net/ip.h>
  43. #include <asm/system.h>
  44. #include <asm/io.h>
  45. #include <asm/byteorder.h>
  46. #include <asm/uaccess.h>
  47. #ifdef CONFIG_SPARC
  48. #include <asm/idprom.h>
  49. #include <asm/prom.h>
  50. #endif
  51. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  52. #define TG3_VLAN_TAG_USED 1
  53. #else
  54. #define TG3_VLAN_TAG_USED 0
  55. #endif
  56. #define TG3_TSO_SUPPORT 1
  57. #include "tg3.h"
  58. #define DRV_MODULE_NAME "tg3"
  59. #define PFX DRV_MODULE_NAME ": "
  60. #define DRV_MODULE_VERSION "3.94"
  61. #define DRV_MODULE_RELDATE "August 14, 2008"
  62. #define TG3_DEF_MAC_MODE 0
  63. #define TG3_DEF_RX_MODE 0
  64. #define TG3_DEF_TX_MODE 0
  65. #define TG3_DEF_MSG_ENABLE \
  66. (NETIF_MSG_DRV | \
  67. NETIF_MSG_PROBE | \
  68. NETIF_MSG_LINK | \
  69. NETIF_MSG_TIMER | \
  70. NETIF_MSG_IFDOWN | \
  71. NETIF_MSG_IFUP | \
  72. NETIF_MSG_RX_ERR | \
  73. NETIF_MSG_TX_ERR)
  74. /* length of time before we decide the hardware is borked,
  75. * and dev->tx_timeout() should be called to fix the problem
  76. */
  77. #define TG3_TX_TIMEOUT (5 * HZ)
  78. /* hardware minimum and maximum for a single frame's data payload */
  79. #define TG3_MIN_MTU 60
  80. #define TG3_MAX_MTU(tp) \
  81. ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  82. /* These numbers seem to be hard coded in the NIC firmware somehow.
  83. * You can't change the ring sizes, but you can change where you place
  84. * them in the NIC onboard memory.
  85. */
  86. #define TG3_RX_RING_SIZE 512
  87. #define TG3_DEF_RX_RING_PENDING 200
  88. #define TG3_RX_JUMBO_RING_SIZE 256
  89. #define TG3_DEF_RX_JUMBO_RING_PENDING 100
  90. /* Do not place this n-ring entries value into the tp struct itself,
  91. * we really want to expose these constants to GCC so that modulo et
  92. * al. operations are done with shifts and masks instead of with
  93. * hw multiply/modulo instructions. Another solution would be to
  94. * replace things like '% foo' with '& (foo - 1)'.
  95. */
  96. #define TG3_RX_RCB_RING_SIZE(tp) \
  97. ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
  98. #define TG3_TX_RING_SIZE 512
  99. #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
  100. #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  101. TG3_RX_RING_SIZE)
  102. #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  103. TG3_RX_JUMBO_RING_SIZE)
  104. #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
  105. TG3_RX_RCB_RING_SIZE(tp))
  106. #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
  107. TG3_TX_RING_SIZE)
  108. #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  109. #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
  110. #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
  111. /* minimum number of free TX descriptors required to wake up TX process */
  112. #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
  113. /* number of ETHTOOL_GSTATS u64's */
  114. #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
  115. #define TG3_NUM_TEST 6
  116. static char version[] __devinitdata =
  117. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  118. MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
  119. MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
  120. MODULE_LICENSE("GPL");
  121. MODULE_VERSION(DRV_MODULE_VERSION);
  122. static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
  123. module_param(tg3_debug, int, 0);
  124. MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
  125. static struct pci_device_id tg3_pci_tbl[] = {
  126. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
  127. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
  128. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
  129. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
  130. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
  131. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
  132. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
  133. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
  134. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
  135. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
  136. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
  137. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
  138. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
  139. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
  140. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
  141. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
  142. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
  143. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
  144. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
  145. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
  146. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
  152. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  153. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
  154. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  155. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
  156. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
  157. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
  158. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
  159. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
  160. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
  161. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
  162. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
  163. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
  164. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
  165. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
  166. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
  167. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
  168. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
  169. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
  170. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
  171. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
  172. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
  173. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
  174. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
  175. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
  176. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
  177. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
  178. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
  179. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
  180. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
  181. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
  182. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
  183. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
  184. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
  185. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  186. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  187. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  188. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
  189. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
  190. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
  191. {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
  192. {}
  193. };
  194. MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
  195. static const struct {
  196. const char string[ETH_GSTRING_LEN];
  197. } ethtool_stats_keys[TG3_NUM_STATS] = {
  198. { "rx_octets" },
  199. { "rx_fragments" },
  200. { "rx_ucast_packets" },
  201. { "rx_mcast_packets" },
  202. { "rx_bcast_packets" },
  203. { "rx_fcs_errors" },
  204. { "rx_align_errors" },
  205. { "rx_xon_pause_rcvd" },
  206. { "rx_xoff_pause_rcvd" },
  207. { "rx_mac_ctrl_rcvd" },
  208. { "rx_xoff_entered" },
  209. { "rx_frame_too_long_errors" },
  210. { "rx_jabbers" },
  211. { "rx_undersize_packets" },
  212. { "rx_in_length_errors" },
  213. { "rx_out_length_errors" },
  214. { "rx_64_or_less_octet_packets" },
  215. { "rx_65_to_127_octet_packets" },
  216. { "rx_128_to_255_octet_packets" },
  217. { "rx_256_to_511_octet_packets" },
  218. { "rx_512_to_1023_octet_packets" },
  219. { "rx_1024_to_1522_octet_packets" },
  220. { "rx_1523_to_2047_octet_packets" },
  221. { "rx_2048_to_4095_octet_packets" },
  222. { "rx_4096_to_8191_octet_packets" },
  223. { "rx_8192_to_9022_octet_packets" },
  224. { "tx_octets" },
  225. { "tx_collisions" },
  226. { "tx_xon_sent" },
  227. { "tx_xoff_sent" },
  228. { "tx_flow_control" },
  229. { "tx_mac_errors" },
  230. { "tx_single_collisions" },
  231. { "tx_mult_collisions" },
  232. { "tx_deferred" },
  233. { "tx_excessive_collisions" },
  234. { "tx_late_collisions" },
  235. { "tx_collide_2times" },
  236. { "tx_collide_3times" },
  237. { "tx_collide_4times" },
  238. { "tx_collide_5times" },
  239. { "tx_collide_6times" },
  240. { "tx_collide_7times" },
  241. { "tx_collide_8times" },
  242. { "tx_collide_9times" },
  243. { "tx_collide_10times" },
  244. { "tx_collide_11times" },
  245. { "tx_collide_12times" },
  246. { "tx_collide_13times" },
  247. { "tx_collide_14times" },
  248. { "tx_collide_15times" },
  249. { "tx_ucast_packets" },
  250. { "tx_mcast_packets" },
  251. { "tx_bcast_packets" },
  252. { "tx_carrier_sense_errors" },
  253. { "tx_discards" },
  254. { "tx_errors" },
  255. { "dma_writeq_full" },
  256. { "dma_write_prioq_full" },
  257. { "rxbds_empty" },
  258. { "rx_discards" },
  259. { "rx_errors" },
  260. { "rx_threshold_hit" },
  261. { "dma_readq_full" },
  262. { "dma_read_prioq_full" },
  263. { "tx_comp_queue_full" },
  264. { "ring_set_send_prod_index" },
  265. { "ring_status_update" },
  266. { "nic_irqs" },
  267. { "nic_avoided_irqs" },
  268. { "nic_tx_threshold_hit" }
  269. };
  270. static const struct {
  271. const char string[ETH_GSTRING_LEN];
  272. } ethtool_test_keys[TG3_NUM_TEST] = {
  273. { "nvram test (online) " },
  274. { "link test (online) " },
  275. { "register test (offline)" },
  276. { "memory test (offline)" },
  277. { "loopback test (offline)" },
  278. { "interrupt test (offline)" },
  279. };
  280. static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
  281. {
  282. writel(val, tp->regs + off);
  283. }
  284. static u32 tg3_read32(struct tg3 *tp, u32 off)
  285. {
  286. return (readl(tp->regs + off));
  287. }
  288. static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
  289. {
  290. writel(val, tp->aperegs + off);
  291. }
  292. static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
  293. {
  294. return (readl(tp->aperegs + off));
  295. }
  296. static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
  297. {
  298. unsigned long flags;
  299. spin_lock_irqsave(&tp->indirect_lock, flags);
  300. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  301. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  302. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  303. }
  304. static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
  305. {
  306. writel(val, tp->regs + off);
  307. readl(tp->regs + off);
  308. }
  309. static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
  310. {
  311. unsigned long flags;
  312. u32 val;
  313. spin_lock_irqsave(&tp->indirect_lock, flags);
  314. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  315. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  316. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  317. return val;
  318. }
  319. static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
  320. {
  321. unsigned long flags;
  322. if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
  323. pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
  324. TG3_64BIT_REG_LOW, val);
  325. return;
  326. }
  327. if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
  328. pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
  329. TG3_64BIT_REG_LOW, val);
  330. return;
  331. }
  332. spin_lock_irqsave(&tp->indirect_lock, flags);
  333. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  334. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  335. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  336. /* In indirect mode when disabling interrupts, we also need
  337. * to clear the interrupt bit in the GRC local ctrl register.
  338. */
  339. if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
  340. (val == 0x1)) {
  341. pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
  342. tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
  343. }
  344. }
  345. static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  346. {
  347. unsigned long flags;
  348. u32 val;
  349. spin_lock_irqsave(&tp->indirect_lock, flags);
  350. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  351. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  352. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  353. return val;
  354. }
  355. /* usec_wait specifies the wait time in usec when writing to certain registers
  356. * where it is unsafe to read back the register without some delay.
  357. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
  358. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
  359. */
  360. static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  361. {
  362. if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
  363. (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  364. /* Non-posted methods */
  365. tp->write32(tp, off, val);
  366. else {
  367. /* Posted method */
  368. tg3_write32(tp, off, val);
  369. if (usec_wait)
  370. udelay(usec_wait);
  371. tp->read32(tp, off);
  372. }
  373. /* Wait again after the read for the posted method to guarantee that
  374. * the wait time is met.
  375. */
  376. if (usec_wait)
  377. udelay(usec_wait);
  378. }
  379. static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  380. {
  381. tp->write32_mbox(tp, off, val);
  382. if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
  383. !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  384. tp->read32_mbox(tp, off);
  385. }
  386. static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  387. {
  388. void __iomem *mbox = tp->regs + off;
  389. writel(val, mbox);
  390. if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
  391. writel(val, mbox);
  392. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  393. readl(mbox);
  394. }
  395. static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
  396. {
  397. return (readl(tp->regs + off + GRCMBOX_BASE));
  398. }
  399. static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
  400. {
  401. writel(val, tp->regs + off + GRCMBOX_BASE);
  402. }
  403. #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
  404. #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
  405. #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
  406. #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
  407. #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
  408. #define tw32(reg,val) tp->write32(tp, reg, val)
  409. #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
  410. #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
  411. #define tr32(reg) tp->read32(tp, reg)
  412. static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
  413. {
  414. unsigned long flags;
  415. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  416. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
  417. return;
  418. spin_lock_irqsave(&tp->indirect_lock, flags);
  419. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  420. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  421. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  422. /* Always leave this as zero. */
  423. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  424. } else {
  425. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  426. tw32_f(TG3PCI_MEM_WIN_DATA, val);
  427. /* Always leave this as zero. */
  428. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  429. }
  430. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  431. }
  432. static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
  433. {
  434. unsigned long flags;
  435. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  436. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
  437. *val = 0;
  438. return;
  439. }
  440. spin_lock_irqsave(&tp->indirect_lock, flags);
  441. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  442. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  443. pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  444. /* Always leave this as zero. */
  445. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  446. } else {
  447. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  448. *val = tr32(TG3PCI_MEM_WIN_DATA);
  449. /* Always leave this as zero. */
  450. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  451. }
  452. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  453. }
  454. static void tg3_ape_lock_init(struct tg3 *tp)
  455. {
  456. int i;
  457. /* Make sure the driver hasn't any stale locks. */
  458. for (i = 0; i < 8; i++)
  459. tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
  460. APE_LOCK_GRANT_DRIVER);
  461. }
  462. static int tg3_ape_lock(struct tg3 *tp, int locknum)
  463. {
  464. int i, off;
  465. int ret = 0;
  466. u32 status;
  467. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  468. return 0;
  469. switch (locknum) {
  470. case TG3_APE_LOCK_GRC:
  471. case TG3_APE_LOCK_MEM:
  472. break;
  473. default:
  474. return -EINVAL;
  475. }
  476. off = 4 * locknum;
  477. tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
  478. /* Wait for up to 1 millisecond to acquire lock. */
  479. for (i = 0; i < 100; i++) {
  480. status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
  481. if (status == APE_LOCK_GRANT_DRIVER)
  482. break;
  483. udelay(10);
  484. }
  485. if (status != APE_LOCK_GRANT_DRIVER) {
  486. /* Revoke the lock request. */
  487. tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
  488. APE_LOCK_GRANT_DRIVER);
  489. ret = -EBUSY;
  490. }
  491. return ret;
  492. }
  493. static void tg3_ape_unlock(struct tg3 *tp, int locknum)
  494. {
  495. int off;
  496. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  497. return;
  498. switch (locknum) {
  499. case TG3_APE_LOCK_GRC:
  500. case TG3_APE_LOCK_MEM:
  501. break;
  502. default:
  503. return;
  504. }
  505. off = 4 * locknum;
  506. tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
  507. }
  508. static void tg3_disable_ints(struct tg3 *tp)
  509. {
  510. tw32(TG3PCI_MISC_HOST_CTRL,
  511. (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
  512. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  513. }
  514. static inline void tg3_cond_int(struct tg3 *tp)
  515. {
  516. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  517. (tp->hw_status->status & SD_STATUS_UPDATED))
  518. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  519. else
  520. tw32(HOSTCC_MODE, tp->coalesce_mode |
  521. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  522. }
  523. static void tg3_enable_ints(struct tg3 *tp)
  524. {
  525. tp->irq_sync = 0;
  526. wmb();
  527. tw32(TG3PCI_MISC_HOST_CTRL,
  528. (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
  529. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  530. (tp->last_tag << 24));
  531. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  532. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  533. (tp->last_tag << 24));
  534. tg3_cond_int(tp);
  535. }
  536. static inline unsigned int tg3_has_work(struct tg3 *tp)
  537. {
  538. struct tg3_hw_status *sblk = tp->hw_status;
  539. unsigned int work_exists = 0;
  540. /* check for phy events */
  541. if (!(tp->tg3_flags &
  542. (TG3_FLAG_USE_LINKCHG_REG |
  543. TG3_FLAG_POLL_SERDES))) {
  544. if (sblk->status & SD_STATUS_LINK_CHG)
  545. work_exists = 1;
  546. }
  547. /* check for RX/TX work to do */
  548. if (sblk->idx[0].tx_consumer != tp->tx_cons ||
  549. sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
  550. work_exists = 1;
  551. return work_exists;
  552. }
  553. /* tg3_restart_ints
  554. * similar to tg3_enable_ints, but it accurately determines whether there
  555. * is new work pending and can return without flushing the PIO write
  556. * which reenables interrupts
  557. */
  558. static void tg3_restart_ints(struct tg3 *tp)
  559. {
  560. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  561. tp->last_tag << 24);
  562. mmiowb();
  563. /* When doing tagged status, this work check is unnecessary.
  564. * The last_tag we write above tells the chip which piece of
  565. * work we've completed.
  566. */
  567. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  568. tg3_has_work(tp))
  569. tw32(HOSTCC_MODE, tp->coalesce_mode |
  570. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  571. }
  572. static inline void tg3_netif_stop(struct tg3 *tp)
  573. {
  574. tp->dev->trans_start = jiffies; /* prevent tx timeout */
  575. napi_disable(&tp->napi);
  576. netif_tx_disable(tp->dev);
  577. }
  578. static inline void tg3_netif_start(struct tg3 *tp)
  579. {
  580. netif_wake_queue(tp->dev);
  581. /* NOTE: unconditional netif_wake_queue is only appropriate
  582. * so long as all callers are assured to have free tx slots
  583. * (such as after tg3_init_hw)
  584. */
  585. napi_enable(&tp->napi);
  586. tp->hw_status->status |= SD_STATUS_UPDATED;
  587. tg3_enable_ints(tp);
  588. }
  589. static void tg3_switch_clocks(struct tg3 *tp)
  590. {
  591. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
  592. u32 orig_clock_ctrl;
  593. if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
  594. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  595. return;
  596. orig_clock_ctrl = clock_ctrl;
  597. clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
  598. CLOCK_CTRL_CLKRUN_OENABLE |
  599. 0x1f);
  600. tp->pci_clock_ctrl = clock_ctrl;
  601. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  602. if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
  603. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  604. clock_ctrl | CLOCK_CTRL_625_CORE, 40);
  605. }
  606. } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
  607. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  608. clock_ctrl |
  609. (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
  610. 40);
  611. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  612. clock_ctrl | (CLOCK_CTRL_ALTCLK),
  613. 40);
  614. }
  615. tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
  616. }
  617. #define PHY_BUSY_LOOPS 5000
  618. static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  619. {
  620. u32 frame_val;
  621. unsigned int loops;
  622. int ret;
  623. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  624. tw32_f(MAC_MI_MODE,
  625. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  626. udelay(80);
  627. }
  628. *val = 0x0;
  629. frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  630. MI_COM_PHY_ADDR_MASK);
  631. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  632. MI_COM_REG_ADDR_MASK);
  633. frame_val |= (MI_COM_CMD_READ | MI_COM_START);
  634. tw32_f(MAC_MI_COM, frame_val);
  635. loops = PHY_BUSY_LOOPS;
  636. while (loops != 0) {
  637. udelay(10);
  638. frame_val = tr32(MAC_MI_COM);
  639. if ((frame_val & MI_COM_BUSY) == 0) {
  640. udelay(5);
  641. frame_val = tr32(MAC_MI_COM);
  642. break;
  643. }
  644. loops -= 1;
  645. }
  646. ret = -EBUSY;
  647. if (loops != 0) {
  648. *val = frame_val & MI_COM_DATA_MASK;
  649. ret = 0;
  650. }
  651. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  652. tw32_f(MAC_MI_MODE, tp->mi_mode);
  653. udelay(80);
  654. }
  655. return ret;
  656. }
  657. static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  658. {
  659. u32 frame_val;
  660. unsigned int loops;
  661. int ret;
  662. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
  663. (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
  664. return 0;
  665. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  666. tw32_f(MAC_MI_MODE,
  667. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  668. udelay(80);
  669. }
  670. frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  671. MI_COM_PHY_ADDR_MASK);
  672. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  673. MI_COM_REG_ADDR_MASK);
  674. frame_val |= (val & MI_COM_DATA_MASK);
  675. frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
  676. tw32_f(MAC_MI_COM, frame_val);
  677. loops = PHY_BUSY_LOOPS;
  678. while (loops != 0) {
  679. udelay(10);
  680. frame_val = tr32(MAC_MI_COM);
  681. if ((frame_val & MI_COM_BUSY) == 0) {
  682. udelay(5);
  683. frame_val = tr32(MAC_MI_COM);
  684. break;
  685. }
  686. loops -= 1;
  687. }
  688. ret = -EBUSY;
  689. if (loops != 0)
  690. ret = 0;
  691. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  692. tw32_f(MAC_MI_MODE, tp->mi_mode);
  693. udelay(80);
  694. }
  695. return ret;
  696. }
  697. static int tg3_bmcr_reset(struct tg3 *tp)
  698. {
  699. u32 phy_control;
  700. int limit, err;
  701. /* OK, reset it, and poll the BMCR_RESET bit until it
  702. * clears or we time out.
  703. */
  704. phy_control = BMCR_RESET;
  705. err = tg3_writephy(tp, MII_BMCR, phy_control);
  706. if (err != 0)
  707. return -EBUSY;
  708. limit = 5000;
  709. while (limit--) {
  710. err = tg3_readphy(tp, MII_BMCR, &phy_control);
  711. if (err != 0)
  712. return -EBUSY;
  713. if ((phy_control & BMCR_RESET) == 0) {
  714. udelay(40);
  715. break;
  716. }
  717. udelay(10);
  718. }
  719. if (limit <= 0)
  720. return -EBUSY;
  721. return 0;
  722. }
  723. static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
  724. {
  725. struct tg3 *tp = (struct tg3 *)bp->priv;
  726. u32 val;
  727. if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
  728. return -EAGAIN;
  729. if (tg3_readphy(tp, reg, &val))
  730. return -EIO;
  731. return val;
  732. }
  733. static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
  734. {
  735. struct tg3 *tp = (struct tg3 *)bp->priv;
  736. if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
  737. return -EAGAIN;
  738. if (tg3_writephy(tp, reg, val))
  739. return -EIO;
  740. return 0;
  741. }
  742. static int tg3_mdio_reset(struct mii_bus *bp)
  743. {
  744. return 0;
  745. }
  746. static void tg3_mdio_config(struct tg3 *tp)
  747. {
  748. u32 val;
  749. if (tp->mdio_bus.phy_map[PHY_ADDR]->interface !=
  750. PHY_INTERFACE_MODE_RGMII)
  751. return;
  752. val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
  753. MAC_PHYCFG1_RGMII_SND_STAT_EN);
  754. if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
  755. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
  756. val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
  757. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
  758. val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
  759. }
  760. tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
  761. val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
  762. if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
  763. val |= MAC_PHYCFG2_INBAND_ENABLE;
  764. tw32(MAC_PHYCFG2, val);
  765. val = tr32(MAC_EXT_RGMII_MODE);
  766. val &= ~(MAC_RGMII_MODE_RX_INT_B |
  767. MAC_RGMII_MODE_RX_QUALITY |
  768. MAC_RGMII_MODE_RX_ACTIVITY |
  769. MAC_RGMII_MODE_RX_ENG_DET |
  770. MAC_RGMII_MODE_TX_ENABLE |
  771. MAC_RGMII_MODE_TX_LOWPWR |
  772. MAC_RGMII_MODE_TX_RESET);
  773. if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
  774. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
  775. val |= MAC_RGMII_MODE_RX_INT_B |
  776. MAC_RGMII_MODE_RX_QUALITY |
  777. MAC_RGMII_MODE_RX_ACTIVITY |
  778. MAC_RGMII_MODE_RX_ENG_DET;
  779. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
  780. val |= MAC_RGMII_MODE_TX_ENABLE |
  781. MAC_RGMII_MODE_TX_LOWPWR |
  782. MAC_RGMII_MODE_TX_RESET;
  783. }
  784. tw32(MAC_EXT_RGMII_MODE, val);
  785. }
  786. static void tg3_mdio_start(struct tg3 *tp)
  787. {
  788. if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
  789. mutex_lock(&tp->mdio_bus.mdio_lock);
  790. tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
  791. mutex_unlock(&tp->mdio_bus.mdio_lock);
  792. }
  793. tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
  794. tw32_f(MAC_MI_MODE, tp->mi_mode);
  795. udelay(80);
  796. if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)
  797. tg3_mdio_config(tp);
  798. }
  799. static void tg3_mdio_stop(struct tg3 *tp)
  800. {
  801. if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
  802. mutex_lock(&tp->mdio_bus.mdio_lock);
  803. tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
  804. mutex_unlock(&tp->mdio_bus.mdio_lock);
  805. }
  806. }
  807. static int tg3_mdio_init(struct tg3 *tp)
  808. {
  809. int i;
  810. u32 reg;
  811. struct phy_device *phydev;
  812. struct mii_bus *mdio_bus = &tp->mdio_bus;
  813. tg3_mdio_start(tp);
  814. if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
  815. (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
  816. return 0;
  817. memset(mdio_bus, 0, sizeof(*mdio_bus));
  818. mdio_bus->name = "tg3 mdio bus";
  819. snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
  820. (tp->pdev->bus->number << 8) | tp->pdev->devfn);
  821. mdio_bus->priv = tp;
  822. mdio_bus->dev = &tp->pdev->dev;
  823. mdio_bus->read = &tg3_mdio_read;
  824. mdio_bus->write = &tg3_mdio_write;
  825. mdio_bus->reset = &tg3_mdio_reset;
  826. mdio_bus->phy_mask = ~(1 << PHY_ADDR);
  827. mdio_bus->irq = &tp->mdio_irq[0];
  828. for (i = 0; i < PHY_MAX_ADDR; i++)
  829. mdio_bus->irq[i] = PHY_POLL;
  830. /* The bus registration will look for all the PHYs on the mdio bus.
  831. * Unfortunately, it does not ensure the PHY is powered up before
  832. * accessing the PHY ID registers. A chip reset is the
  833. * quickest way to bring the device back to an operational state..
  834. */
  835. if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
  836. tg3_bmcr_reset(tp);
  837. i = mdiobus_register(mdio_bus);
  838. if (i) {
  839. printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
  840. tp->dev->name, i);
  841. return i;
  842. }
  843. tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
  844. phydev = tp->mdio_bus.phy_map[PHY_ADDR];
  845. switch (phydev->phy_id) {
  846. case TG3_PHY_ID_BCM50610:
  847. phydev->interface = PHY_INTERFACE_MODE_RGMII;
  848. if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
  849. phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
  850. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
  851. phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
  852. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
  853. phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
  854. break;
  855. case TG3_PHY_ID_BCMAC131:
  856. phydev->interface = PHY_INTERFACE_MODE_MII;
  857. break;
  858. }
  859. tg3_mdio_config(tp);
  860. return 0;
  861. }
  862. static void tg3_mdio_fini(struct tg3 *tp)
  863. {
  864. if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
  865. tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
  866. mdiobus_unregister(&tp->mdio_bus);
  867. tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
  868. }
  869. }
  870. /* tp->lock is held. */
  871. static inline void tg3_generate_fw_event(struct tg3 *tp)
  872. {
  873. u32 val;
  874. val = tr32(GRC_RX_CPU_EVENT);
  875. val |= GRC_RX_CPU_DRIVER_EVENT;
  876. tw32_f(GRC_RX_CPU_EVENT, val);
  877. tp->last_event_jiffies = jiffies;
  878. }
  879. #define TG3_FW_EVENT_TIMEOUT_USEC 2500
  880. /* tp->lock is held. */
  881. static void tg3_wait_for_event_ack(struct tg3 *tp)
  882. {
  883. int i;
  884. unsigned int delay_cnt;
  885. long time_remain;
  886. /* If enough time has passed, no wait is necessary. */
  887. time_remain = (long)(tp->last_event_jiffies + 1 +
  888. usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
  889. (long)jiffies;
  890. if (time_remain < 0)
  891. return;
  892. /* Check if we can shorten the wait time. */
  893. delay_cnt = jiffies_to_usecs(time_remain);
  894. if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
  895. delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
  896. delay_cnt = (delay_cnt >> 3) + 1;
  897. for (i = 0; i < delay_cnt; i++) {
  898. if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
  899. break;
  900. udelay(8);
  901. }
  902. }
  903. /* tp->lock is held. */
  904. static void tg3_ump_link_report(struct tg3 *tp)
  905. {
  906. u32 reg;
  907. u32 val;
  908. if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  909. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  910. return;
  911. tg3_wait_for_event_ack(tp);
  912. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
  913. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
  914. val = 0;
  915. if (!tg3_readphy(tp, MII_BMCR, &reg))
  916. val = reg << 16;
  917. if (!tg3_readphy(tp, MII_BMSR, &reg))
  918. val |= (reg & 0xffff);
  919. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
  920. val = 0;
  921. if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
  922. val = reg << 16;
  923. if (!tg3_readphy(tp, MII_LPA, &reg))
  924. val |= (reg & 0xffff);
  925. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
  926. val = 0;
  927. if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
  928. if (!tg3_readphy(tp, MII_CTRL1000, &reg))
  929. val = reg << 16;
  930. if (!tg3_readphy(tp, MII_STAT1000, &reg))
  931. val |= (reg & 0xffff);
  932. }
  933. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
  934. if (!tg3_readphy(tp, MII_PHYADDR, &reg))
  935. val = reg << 16;
  936. else
  937. val = 0;
  938. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
  939. tg3_generate_fw_event(tp);
  940. }
  941. static void tg3_link_report(struct tg3 *tp)
  942. {
  943. if (!netif_carrier_ok(tp->dev)) {
  944. if (netif_msg_link(tp))
  945. printk(KERN_INFO PFX "%s: Link is down.\n",
  946. tp->dev->name);
  947. tg3_ump_link_report(tp);
  948. } else if (netif_msg_link(tp)) {
  949. printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
  950. tp->dev->name,
  951. (tp->link_config.active_speed == SPEED_1000 ?
  952. 1000 :
  953. (tp->link_config.active_speed == SPEED_100 ?
  954. 100 : 10)),
  955. (tp->link_config.active_duplex == DUPLEX_FULL ?
  956. "full" : "half"));
  957. printk(KERN_INFO PFX
  958. "%s: Flow control is %s for TX and %s for RX.\n",
  959. tp->dev->name,
  960. (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
  961. "on" : "off",
  962. (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
  963. "on" : "off");
  964. tg3_ump_link_report(tp);
  965. }
  966. }
  967. static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
  968. {
  969. u16 miireg;
  970. if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
  971. miireg = ADVERTISE_PAUSE_CAP;
  972. else if (flow_ctrl & TG3_FLOW_CTRL_TX)
  973. miireg = ADVERTISE_PAUSE_ASYM;
  974. else if (flow_ctrl & TG3_FLOW_CTRL_RX)
  975. miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  976. else
  977. miireg = 0;
  978. return miireg;
  979. }
  980. static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
  981. {
  982. u16 miireg;
  983. if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
  984. miireg = ADVERTISE_1000XPAUSE;
  985. else if (flow_ctrl & TG3_FLOW_CTRL_TX)
  986. miireg = ADVERTISE_1000XPSE_ASYM;
  987. else if (flow_ctrl & TG3_FLOW_CTRL_RX)
  988. miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  989. else
  990. miireg = 0;
  991. return miireg;
  992. }
  993. static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
  994. {
  995. u8 cap = 0;
  996. if (lcladv & ADVERTISE_PAUSE_CAP) {
  997. if (lcladv & ADVERTISE_PAUSE_ASYM) {
  998. if (rmtadv & LPA_PAUSE_CAP)
  999. cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
  1000. else if (rmtadv & LPA_PAUSE_ASYM)
  1001. cap = TG3_FLOW_CTRL_RX;
  1002. } else {
  1003. if (rmtadv & LPA_PAUSE_CAP)
  1004. cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
  1005. }
  1006. } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
  1007. if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
  1008. cap = TG3_FLOW_CTRL_TX;
  1009. }
  1010. return cap;
  1011. }
  1012. static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
  1013. {
  1014. u8 cap = 0;
  1015. if (lcladv & ADVERTISE_1000XPAUSE) {
  1016. if (lcladv & ADVERTISE_1000XPSE_ASYM) {
  1017. if (rmtadv & LPA_1000XPAUSE)
  1018. cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
  1019. else if (rmtadv & LPA_1000XPAUSE_ASYM)
  1020. cap = TG3_FLOW_CTRL_RX;
  1021. } else {
  1022. if (rmtadv & LPA_1000XPAUSE)
  1023. cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
  1024. }
  1025. } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
  1026. if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
  1027. cap = TG3_FLOW_CTRL_TX;
  1028. }
  1029. return cap;
  1030. }
  1031. static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
  1032. {
  1033. u8 autoneg;
  1034. u8 flowctrl = 0;
  1035. u32 old_rx_mode = tp->rx_mode;
  1036. u32 old_tx_mode = tp->tx_mode;
  1037. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
  1038. autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
  1039. else
  1040. autoneg = tp->link_config.autoneg;
  1041. if (autoneg == AUTONEG_ENABLE &&
  1042. (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
  1043. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  1044. flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
  1045. else
  1046. flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
  1047. } else
  1048. flowctrl = tp->link_config.flowctrl;
  1049. tp->link_config.active_flowctrl = flowctrl;
  1050. if (flowctrl & TG3_FLOW_CTRL_RX)
  1051. tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
  1052. else
  1053. tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
  1054. if (old_rx_mode != tp->rx_mode)
  1055. tw32_f(MAC_RX_MODE, tp->rx_mode);
  1056. if (flowctrl & TG3_FLOW_CTRL_TX)
  1057. tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
  1058. else
  1059. tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
  1060. if (old_tx_mode != tp->tx_mode)
  1061. tw32_f(MAC_TX_MODE, tp->tx_mode);
  1062. }
  1063. static void tg3_adjust_link(struct net_device *dev)
  1064. {
  1065. u8 oldflowctrl, linkmesg = 0;
  1066. u32 mac_mode, lcl_adv, rmt_adv;
  1067. struct tg3 *tp = netdev_priv(dev);
  1068. struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
  1069. spin_lock(&tp->lock);
  1070. mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
  1071. MAC_MODE_HALF_DUPLEX);
  1072. oldflowctrl = tp->link_config.active_flowctrl;
  1073. if (phydev->link) {
  1074. lcl_adv = 0;
  1075. rmt_adv = 0;
  1076. if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
  1077. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1078. else
  1079. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1080. if (phydev->duplex == DUPLEX_HALF)
  1081. mac_mode |= MAC_MODE_HALF_DUPLEX;
  1082. else {
  1083. lcl_adv = tg3_advert_flowctrl_1000T(
  1084. tp->link_config.flowctrl);
  1085. if (phydev->pause)
  1086. rmt_adv = LPA_PAUSE_CAP;
  1087. if (phydev->asym_pause)
  1088. rmt_adv |= LPA_PAUSE_ASYM;
  1089. }
  1090. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  1091. } else
  1092. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1093. if (mac_mode != tp->mac_mode) {
  1094. tp->mac_mode = mac_mode;
  1095. tw32_f(MAC_MODE, tp->mac_mode);
  1096. udelay(40);
  1097. }
  1098. if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
  1099. tw32(MAC_TX_LENGTHS,
  1100. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1101. (6 << TX_LENGTHS_IPG_SHIFT) |
  1102. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1103. else
  1104. tw32(MAC_TX_LENGTHS,
  1105. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1106. (6 << TX_LENGTHS_IPG_SHIFT) |
  1107. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1108. if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
  1109. (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
  1110. phydev->speed != tp->link_config.active_speed ||
  1111. phydev->duplex != tp->link_config.active_duplex ||
  1112. oldflowctrl != tp->link_config.active_flowctrl)
  1113. linkmesg = 1;
  1114. tp->link_config.active_speed = phydev->speed;
  1115. tp->link_config.active_duplex = phydev->duplex;
  1116. spin_unlock(&tp->lock);
  1117. if (linkmesg)
  1118. tg3_link_report(tp);
  1119. }
  1120. static int tg3_phy_init(struct tg3 *tp)
  1121. {
  1122. struct phy_device *phydev;
  1123. if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
  1124. return 0;
  1125. /* Bring the PHY back to a known state. */
  1126. tg3_bmcr_reset(tp);
  1127. phydev = tp->mdio_bus.phy_map[PHY_ADDR];
  1128. /* Attach the MAC to the PHY. */
  1129. phydev = phy_connect(tp->dev, phydev->dev.bus_id, tg3_adjust_link,
  1130. phydev->dev_flags, phydev->interface);
  1131. if (IS_ERR(phydev)) {
  1132. printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
  1133. return PTR_ERR(phydev);
  1134. }
  1135. tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
  1136. /* Mask with MAC supported features. */
  1137. phydev->supported &= (PHY_GBIT_FEATURES |
  1138. SUPPORTED_Pause |
  1139. SUPPORTED_Asym_Pause);
  1140. phydev->advertising = phydev->supported;
  1141. printk(KERN_INFO
  1142. "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
  1143. tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
  1144. return 0;
  1145. }
  1146. static void tg3_phy_start(struct tg3 *tp)
  1147. {
  1148. struct phy_device *phydev;
  1149. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  1150. return;
  1151. phydev = tp->mdio_bus.phy_map[PHY_ADDR];
  1152. if (tp->link_config.phy_is_low_power) {
  1153. tp->link_config.phy_is_low_power = 0;
  1154. phydev->speed = tp->link_config.orig_speed;
  1155. phydev->duplex = tp->link_config.orig_duplex;
  1156. phydev->autoneg = tp->link_config.orig_autoneg;
  1157. phydev->advertising = tp->link_config.orig_advertising;
  1158. }
  1159. phy_start(phydev);
  1160. phy_start_aneg(phydev);
  1161. }
  1162. static void tg3_phy_stop(struct tg3 *tp)
  1163. {
  1164. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  1165. return;
  1166. phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
  1167. }
  1168. static void tg3_phy_fini(struct tg3 *tp)
  1169. {
  1170. if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
  1171. phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
  1172. tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
  1173. }
  1174. }
  1175. static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
  1176. {
  1177. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  1178. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
  1179. }
  1180. static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
  1181. {
  1182. u32 phy;
  1183. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  1184. (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  1185. return;
  1186. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1187. u32 ephy;
  1188. if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
  1189. tg3_writephy(tp, MII_TG3_EPHY_TEST,
  1190. ephy | MII_TG3_EPHY_SHADOW_EN);
  1191. if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
  1192. if (enable)
  1193. phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
  1194. else
  1195. phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
  1196. tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
  1197. }
  1198. tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
  1199. }
  1200. } else {
  1201. phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
  1202. MII_TG3_AUXCTL_SHDWSEL_MISC;
  1203. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
  1204. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
  1205. if (enable)
  1206. phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1207. else
  1208. phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1209. phy |= MII_TG3_AUXCTL_MISC_WREN;
  1210. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  1211. }
  1212. }
  1213. }
  1214. static void tg3_phy_set_wirespeed(struct tg3 *tp)
  1215. {
  1216. u32 val;
  1217. if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
  1218. return;
  1219. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
  1220. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
  1221. tg3_writephy(tp, MII_TG3_AUX_CTRL,
  1222. (val | (1 << 15) | (1 << 4)));
  1223. }
  1224. static void tg3_phy_apply_otp(struct tg3 *tp)
  1225. {
  1226. u32 otp, phy;
  1227. if (!tp->phy_otp)
  1228. return;
  1229. otp = tp->phy_otp;
  1230. /* Enable SM_DSP clock and tx 6dB coding. */
  1231. phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
  1232. MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
  1233. MII_TG3_AUXCTL_ACTL_TX_6DB;
  1234. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  1235. phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
  1236. phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
  1237. tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
  1238. phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
  1239. ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
  1240. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
  1241. phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
  1242. phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
  1243. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
  1244. phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
  1245. tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
  1246. phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
  1247. tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
  1248. phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
  1249. ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
  1250. tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
  1251. /* Turn off SM_DSP clock. */
  1252. phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
  1253. MII_TG3_AUXCTL_ACTL_TX_6DB;
  1254. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  1255. }
  1256. static int tg3_wait_macro_done(struct tg3 *tp)
  1257. {
  1258. int limit = 100;
  1259. while (limit--) {
  1260. u32 tmp32;
  1261. if (!tg3_readphy(tp, 0x16, &tmp32)) {
  1262. if ((tmp32 & 0x1000) == 0)
  1263. break;
  1264. }
  1265. }
  1266. if (limit <= 0)
  1267. return -EBUSY;
  1268. return 0;
  1269. }
  1270. static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
  1271. {
  1272. static const u32 test_pat[4][6] = {
  1273. { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
  1274. { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
  1275. { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
  1276. { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
  1277. };
  1278. int chan;
  1279. for (chan = 0; chan < 4; chan++) {
  1280. int i;
  1281. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1282. (chan * 0x2000) | 0x0200);
  1283. tg3_writephy(tp, 0x16, 0x0002);
  1284. for (i = 0; i < 6; i++)
  1285. tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
  1286. test_pat[chan][i]);
  1287. tg3_writephy(tp, 0x16, 0x0202);
  1288. if (tg3_wait_macro_done(tp)) {
  1289. *resetp = 1;
  1290. return -EBUSY;
  1291. }
  1292. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1293. (chan * 0x2000) | 0x0200);
  1294. tg3_writephy(tp, 0x16, 0x0082);
  1295. if (tg3_wait_macro_done(tp)) {
  1296. *resetp = 1;
  1297. return -EBUSY;
  1298. }
  1299. tg3_writephy(tp, 0x16, 0x0802);
  1300. if (tg3_wait_macro_done(tp)) {
  1301. *resetp = 1;
  1302. return -EBUSY;
  1303. }
  1304. for (i = 0; i < 6; i += 2) {
  1305. u32 low, high;
  1306. if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
  1307. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
  1308. tg3_wait_macro_done(tp)) {
  1309. *resetp = 1;
  1310. return -EBUSY;
  1311. }
  1312. low &= 0x7fff;
  1313. high &= 0x000f;
  1314. if (low != test_pat[chan][i] ||
  1315. high != test_pat[chan][i+1]) {
  1316. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
  1317. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
  1318. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
  1319. return -EBUSY;
  1320. }
  1321. }
  1322. }
  1323. return 0;
  1324. }
  1325. static int tg3_phy_reset_chanpat(struct tg3 *tp)
  1326. {
  1327. int chan;
  1328. for (chan = 0; chan < 4; chan++) {
  1329. int i;
  1330. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1331. (chan * 0x2000) | 0x0200);
  1332. tg3_writephy(tp, 0x16, 0x0002);
  1333. for (i = 0; i < 6; i++)
  1334. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
  1335. tg3_writephy(tp, 0x16, 0x0202);
  1336. if (tg3_wait_macro_done(tp))
  1337. return -EBUSY;
  1338. }
  1339. return 0;
  1340. }
  1341. static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
  1342. {
  1343. u32 reg32, phy9_orig;
  1344. int retries, do_phy_reset, err;
  1345. retries = 10;
  1346. do_phy_reset = 1;
  1347. do {
  1348. if (do_phy_reset) {
  1349. err = tg3_bmcr_reset(tp);
  1350. if (err)
  1351. return err;
  1352. do_phy_reset = 0;
  1353. }
  1354. /* Disable transmitter and interrupt. */
  1355. if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
  1356. continue;
  1357. reg32 |= 0x3000;
  1358. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  1359. /* Set full-duplex, 1000 mbps. */
  1360. tg3_writephy(tp, MII_BMCR,
  1361. BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
  1362. /* Set to master mode. */
  1363. if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
  1364. continue;
  1365. tg3_writephy(tp, MII_TG3_CTRL,
  1366. (MII_TG3_CTRL_AS_MASTER |
  1367. MII_TG3_CTRL_ENABLE_AS_MASTER));
  1368. /* Enable SM_DSP_CLOCK and 6dB. */
  1369. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1370. /* Block the PHY control access. */
  1371. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  1372. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
  1373. err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
  1374. if (!err)
  1375. break;
  1376. } while (--retries);
  1377. err = tg3_phy_reset_chanpat(tp);
  1378. if (err)
  1379. return err;
  1380. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  1381. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
  1382. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
  1383. tg3_writephy(tp, 0x16, 0x0000);
  1384. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  1385. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  1386. /* Set Extended packet length bit for jumbo frames */
  1387. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
  1388. }
  1389. else {
  1390. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1391. }
  1392. tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
  1393. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
  1394. reg32 &= ~0x3000;
  1395. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  1396. } else if (!err)
  1397. err = -EBUSY;
  1398. return err;
  1399. }
  1400. /* This will reset the tigon3 PHY if there is no valid
  1401. * link unless the FORCE argument is non-zero.
  1402. */
  1403. static int tg3_phy_reset(struct tg3 *tp)
  1404. {
  1405. u32 cpmuctrl;
  1406. u32 phy_status;
  1407. int err;
  1408. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1409. u32 val;
  1410. val = tr32(GRC_MISC_CFG);
  1411. tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
  1412. udelay(40);
  1413. }
  1414. err = tg3_readphy(tp, MII_BMSR, &phy_status);
  1415. err |= tg3_readphy(tp, MII_BMSR, &phy_status);
  1416. if (err != 0)
  1417. return -EBUSY;
  1418. if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
  1419. netif_carrier_off(tp->dev);
  1420. tg3_link_report(tp);
  1421. }
  1422. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  1423. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1424. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  1425. err = tg3_phy_reset_5703_4_5(tp);
  1426. if (err)
  1427. return err;
  1428. goto out;
  1429. }
  1430. cpmuctrl = 0;
  1431. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  1432. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
  1433. cpmuctrl = tr32(TG3_CPMU_CTRL);
  1434. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
  1435. tw32(TG3_CPMU_CTRL,
  1436. cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
  1437. }
  1438. err = tg3_bmcr_reset(tp);
  1439. if (err)
  1440. return err;
  1441. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
  1442. u32 phy;
  1443. phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
  1444. tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
  1445. tw32(TG3_CPMU_CTRL, cpmuctrl);
  1446. }
  1447. if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
  1448. u32 val;
  1449. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  1450. if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
  1451. CPMU_LSPD_1000MB_MACCLK_12_5) {
  1452. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  1453. udelay(40);
  1454. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  1455. }
  1456. /* Disable GPHY autopowerdown. */
  1457. tg3_writephy(tp, MII_TG3_MISC_SHDW,
  1458. MII_TG3_MISC_SHDW_WREN |
  1459. MII_TG3_MISC_SHDW_APD_SEL |
  1460. MII_TG3_MISC_SHDW_APD_WKTM_84MS);
  1461. }
  1462. tg3_phy_apply_otp(tp);
  1463. out:
  1464. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
  1465. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1466. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  1467. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
  1468. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  1469. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
  1470. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1471. }
  1472. if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
  1473. tg3_writephy(tp, 0x1c, 0x8d68);
  1474. tg3_writephy(tp, 0x1c, 0x8d68);
  1475. }
  1476. if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
  1477. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1478. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  1479. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
  1480. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  1481. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
  1482. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
  1483. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
  1484. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1485. }
  1486. else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
  1487. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1488. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  1489. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
  1490. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
  1491. tg3_writephy(tp, MII_TG3_TEST1,
  1492. MII_TG3_TEST1_TRIM_EN | 0x4);
  1493. } else
  1494. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
  1495. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1496. }
  1497. /* Set Extended packet length bit (bit 14) on all chips that */
  1498. /* support jumbo frames */
  1499. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  1500. /* Cannot do read-modify-write on 5401 */
  1501. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  1502. } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
  1503. u32 phy_reg;
  1504. /* Set bit 14 with read-modify-write to preserve other bits */
  1505. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
  1506. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
  1507. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
  1508. }
  1509. /* Set phy register 0x10 bit 0 to high fifo elasticity to support
  1510. * jumbo frames transmission.
  1511. */
  1512. if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
  1513. u32 phy_reg;
  1514. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
  1515. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1516. phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
  1517. }
  1518. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1519. /* adjust output voltage */
  1520. tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
  1521. }
  1522. tg3_phy_toggle_automdix(tp, 1);
  1523. tg3_phy_set_wirespeed(tp);
  1524. return 0;
  1525. }
  1526. static void tg3_frob_aux_power(struct tg3 *tp)
  1527. {
  1528. struct tg3 *tp_peer = tp;
  1529. if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
  1530. return;
  1531. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  1532. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  1533. struct net_device *dev_peer;
  1534. dev_peer = pci_get_drvdata(tp->pdev_peer);
  1535. /* remove_one() may have been run on the peer. */
  1536. if (!dev_peer)
  1537. tp_peer = tp;
  1538. else
  1539. tp_peer = netdev_priv(dev_peer);
  1540. }
  1541. if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  1542. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
  1543. (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  1544. (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  1545. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1546. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1547. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1548. (GRC_LCLCTRL_GPIO_OE0 |
  1549. GRC_LCLCTRL_GPIO_OE1 |
  1550. GRC_LCLCTRL_GPIO_OE2 |
  1551. GRC_LCLCTRL_GPIO_OUTPUT0 |
  1552. GRC_LCLCTRL_GPIO_OUTPUT1),
  1553. 100);
  1554. } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
  1555. /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
  1556. u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
  1557. GRC_LCLCTRL_GPIO_OE1 |
  1558. GRC_LCLCTRL_GPIO_OE2 |
  1559. GRC_LCLCTRL_GPIO_OUTPUT0 |
  1560. GRC_LCLCTRL_GPIO_OUTPUT1 |
  1561. tp->grc_local_ctrl;
  1562. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
  1563. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
  1564. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
  1565. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
  1566. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
  1567. } else {
  1568. u32 no_gpio2;
  1569. u32 grc_local_ctrl = 0;
  1570. if (tp_peer != tp &&
  1571. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  1572. return;
  1573. /* Workaround to prevent overdrawing Amps. */
  1574. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  1575. ASIC_REV_5714) {
  1576. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  1577. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1578. grc_local_ctrl, 100);
  1579. }
  1580. /* On 5753 and variants, GPIO2 cannot be used. */
  1581. no_gpio2 = tp->nic_sram_data_cfg &
  1582. NIC_SRAM_DATA_CFG_NO_GPIO2;
  1583. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  1584. GRC_LCLCTRL_GPIO_OE1 |
  1585. GRC_LCLCTRL_GPIO_OE2 |
  1586. GRC_LCLCTRL_GPIO_OUTPUT1 |
  1587. GRC_LCLCTRL_GPIO_OUTPUT2;
  1588. if (no_gpio2) {
  1589. grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
  1590. GRC_LCLCTRL_GPIO_OUTPUT2);
  1591. }
  1592. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1593. grc_local_ctrl, 100);
  1594. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
  1595. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1596. grc_local_ctrl, 100);
  1597. if (!no_gpio2) {
  1598. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
  1599. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1600. grc_local_ctrl, 100);
  1601. }
  1602. }
  1603. } else {
  1604. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  1605. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  1606. if (tp_peer != tp &&
  1607. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  1608. return;
  1609. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1610. (GRC_LCLCTRL_GPIO_OE1 |
  1611. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1612. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1613. GRC_LCLCTRL_GPIO_OE1, 100);
  1614. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1615. (GRC_LCLCTRL_GPIO_OE1 |
  1616. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1617. }
  1618. }
  1619. }
  1620. static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
  1621. {
  1622. if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
  1623. return 1;
  1624. else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
  1625. if (speed != SPEED_10)
  1626. return 1;
  1627. } else if (speed == SPEED_10)
  1628. return 1;
  1629. return 0;
  1630. }
  1631. static int tg3_setup_phy(struct tg3 *, int);
  1632. #define RESET_KIND_SHUTDOWN 0
  1633. #define RESET_KIND_INIT 1
  1634. #define RESET_KIND_SUSPEND 2
  1635. static void tg3_write_sig_post_reset(struct tg3 *, int);
  1636. static int tg3_halt_cpu(struct tg3 *, u32);
  1637. static int tg3_nvram_lock(struct tg3 *);
  1638. static void tg3_nvram_unlock(struct tg3 *);
  1639. static void tg3_power_down_phy(struct tg3 *tp)
  1640. {
  1641. u32 val;
  1642. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  1643. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  1644. u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
  1645. u32 serdes_cfg = tr32(MAC_SERDES_CFG);
  1646. sg_dig_ctrl |=
  1647. SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
  1648. tw32(SG_DIG_CTRL, sg_dig_ctrl);
  1649. tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
  1650. }
  1651. return;
  1652. }
  1653. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1654. tg3_bmcr_reset(tp);
  1655. val = tr32(GRC_MISC_CFG);
  1656. tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
  1657. udelay(40);
  1658. return;
  1659. } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
  1660. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1661. MII_TG3_EXT_CTRL_FORCE_LED_OFF);
  1662. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
  1663. }
  1664. /* The PHY should not be powered down on some chips because
  1665. * of bugs.
  1666. */
  1667. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1668. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1669. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
  1670. (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
  1671. return;
  1672. if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
  1673. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  1674. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  1675. val |= CPMU_LSPD_1000MB_MACCLK_12_5;
  1676. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  1677. }
  1678. tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
  1679. }
  1680. static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
  1681. {
  1682. u32 misc_host_ctrl;
  1683. /* Make sure register accesses (indirect or otherwise)
  1684. * will function correctly.
  1685. */
  1686. pci_write_config_dword(tp->pdev,
  1687. TG3PCI_MISC_HOST_CTRL,
  1688. tp->misc_host_ctrl);
  1689. switch (state) {
  1690. case PCI_D0:
  1691. pci_enable_wake(tp->pdev, state, false);
  1692. pci_set_power_state(tp->pdev, PCI_D0);
  1693. /* Switch out of Vaux if it is a NIC */
  1694. if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
  1695. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
  1696. return 0;
  1697. case PCI_D1:
  1698. case PCI_D2:
  1699. case PCI_D3hot:
  1700. break;
  1701. default:
  1702. printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
  1703. tp->dev->name, state);
  1704. return -EINVAL;
  1705. }
  1706. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  1707. tw32(TG3PCI_MISC_HOST_CTRL,
  1708. misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
  1709. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  1710. if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
  1711. !tp->link_config.phy_is_low_power) {
  1712. struct phy_device *phydev;
  1713. u32 advertising;
  1714. phydev = tp->mdio_bus.phy_map[PHY_ADDR];
  1715. tp->link_config.phy_is_low_power = 1;
  1716. tp->link_config.orig_speed = phydev->speed;
  1717. tp->link_config.orig_duplex = phydev->duplex;
  1718. tp->link_config.orig_autoneg = phydev->autoneg;
  1719. tp->link_config.orig_advertising = phydev->advertising;
  1720. advertising = ADVERTISED_TP |
  1721. ADVERTISED_Pause |
  1722. ADVERTISED_Autoneg |
  1723. ADVERTISED_10baseT_Half;
  1724. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  1725. (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
  1726. if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
  1727. advertising |=
  1728. ADVERTISED_100baseT_Half |
  1729. ADVERTISED_100baseT_Full |
  1730. ADVERTISED_10baseT_Full;
  1731. else
  1732. advertising |= ADVERTISED_10baseT_Full;
  1733. }
  1734. phydev->advertising = advertising;
  1735. phy_start_aneg(phydev);
  1736. }
  1737. } else {
  1738. if (tp->link_config.phy_is_low_power == 0) {
  1739. tp->link_config.phy_is_low_power = 1;
  1740. tp->link_config.orig_speed = tp->link_config.speed;
  1741. tp->link_config.orig_duplex = tp->link_config.duplex;
  1742. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  1743. }
  1744. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  1745. tp->link_config.speed = SPEED_10;
  1746. tp->link_config.duplex = DUPLEX_HALF;
  1747. tp->link_config.autoneg = AUTONEG_ENABLE;
  1748. tg3_setup_phy(tp, 0);
  1749. }
  1750. }
  1751. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1752. u32 val;
  1753. val = tr32(GRC_VCPU_EXT_CTRL);
  1754. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
  1755. } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  1756. int i;
  1757. u32 val;
  1758. for (i = 0; i < 200; i++) {
  1759. tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
  1760. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  1761. break;
  1762. msleep(1);
  1763. }
  1764. }
  1765. if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
  1766. tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
  1767. WOL_DRV_STATE_SHUTDOWN |
  1768. WOL_DRV_WOL |
  1769. WOL_SET_MAGIC_PKT);
  1770. if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
  1771. u32 mac_mode;
  1772. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  1773. if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
  1774. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
  1775. udelay(40);
  1776. }
  1777. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  1778. mac_mode = MAC_MODE_PORT_MODE_GMII;
  1779. else
  1780. mac_mode = MAC_MODE_PORT_MODE_MII;
  1781. mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
  1782. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  1783. ASIC_REV_5700) {
  1784. u32 speed = (tp->tg3_flags &
  1785. TG3_FLAG_WOL_SPEED_100MB) ?
  1786. SPEED_100 : SPEED_10;
  1787. if (tg3_5700_link_polarity(tp, speed))
  1788. mac_mode |= MAC_MODE_LINK_POLARITY;
  1789. else
  1790. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  1791. }
  1792. } else {
  1793. mac_mode = MAC_MODE_PORT_MODE_TBI;
  1794. }
  1795. if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  1796. tw32(MAC_LED_CTRL, tp->led_ctrl);
  1797. if (pci_pme_capable(tp->pdev, state) &&
  1798. (tp->tg3_flags & TG3_FLAG_WOL_ENABLE))
  1799. mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
  1800. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  1801. mac_mode |= tp->mac_mode &
  1802. (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
  1803. if (mac_mode & MAC_MODE_APE_TX_EN)
  1804. mac_mode |= MAC_MODE_TDE_ENABLE;
  1805. }
  1806. tw32_f(MAC_MODE, mac_mode);
  1807. udelay(100);
  1808. tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
  1809. udelay(10);
  1810. }
  1811. if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
  1812. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1813. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  1814. u32 base_val;
  1815. base_val = tp->pci_clock_ctrl;
  1816. base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
  1817. CLOCK_CTRL_TXCLK_DISABLE);
  1818. tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
  1819. CLOCK_CTRL_PWRDOWN_PLL133, 40);
  1820. } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  1821. (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
  1822. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
  1823. /* do nothing */
  1824. } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  1825. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
  1826. u32 newbits1, newbits2;
  1827. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1828. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1829. newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
  1830. CLOCK_CTRL_TXCLK_DISABLE |
  1831. CLOCK_CTRL_ALTCLK);
  1832. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  1833. } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  1834. newbits1 = CLOCK_CTRL_625_CORE;
  1835. newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
  1836. } else {
  1837. newbits1 = CLOCK_CTRL_ALTCLK;
  1838. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  1839. }
  1840. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
  1841. 40);
  1842. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
  1843. 40);
  1844. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  1845. u32 newbits3;
  1846. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1847. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1848. newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
  1849. CLOCK_CTRL_TXCLK_DISABLE |
  1850. CLOCK_CTRL_44MHZ_CORE);
  1851. } else {
  1852. newbits3 = CLOCK_CTRL_44MHZ_CORE;
  1853. }
  1854. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  1855. tp->pci_clock_ctrl | newbits3, 40);
  1856. }
  1857. }
  1858. if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
  1859. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
  1860. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  1861. tg3_power_down_phy(tp);
  1862. tg3_frob_aux_power(tp);
  1863. /* Workaround for unstable PLL clock */
  1864. if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  1865. (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
  1866. u32 val = tr32(0x7d00);
  1867. val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  1868. tw32(0x7d00, val);
  1869. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  1870. int err;
  1871. err = tg3_nvram_lock(tp);
  1872. tg3_halt_cpu(tp, RX_CPU_BASE);
  1873. if (!err)
  1874. tg3_nvram_unlock(tp);
  1875. }
  1876. }
  1877. tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
  1878. if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
  1879. pci_enable_wake(tp->pdev, state, true);
  1880. /* Finally, set the new power state. */
  1881. pci_set_power_state(tp->pdev, state);
  1882. return 0;
  1883. }
  1884. static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
  1885. {
  1886. switch (val & MII_TG3_AUX_STAT_SPDMASK) {
  1887. case MII_TG3_AUX_STAT_10HALF:
  1888. *speed = SPEED_10;
  1889. *duplex = DUPLEX_HALF;
  1890. break;
  1891. case MII_TG3_AUX_STAT_10FULL:
  1892. *speed = SPEED_10;
  1893. *duplex = DUPLEX_FULL;
  1894. break;
  1895. case MII_TG3_AUX_STAT_100HALF:
  1896. *speed = SPEED_100;
  1897. *duplex = DUPLEX_HALF;
  1898. break;
  1899. case MII_TG3_AUX_STAT_100FULL:
  1900. *speed = SPEED_100;
  1901. *duplex = DUPLEX_FULL;
  1902. break;
  1903. case MII_TG3_AUX_STAT_1000HALF:
  1904. *speed = SPEED_1000;
  1905. *duplex = DUPLEX_HALF;
  1906. break;
  1907. case MII_TG3_AUX_STAT_1000FULL:
  1908. *speed = SPEED_1000;
  1909. *duplex = DUPLEX_FULL;
  1910. break;
  1911. default:
  1912. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1913. *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
  1914. SPEED_10;
  1915. *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
  1916. DUPLEX_HALF;
  1917. break;
  1918. }
  1919. *speed = SPEED_INVALID;
  1920. *duplex = DUPLEX_INVALID;
  1921. break;
  1922. }
  1923. }
  1924. static void tg3_phy_copper_begin(struct tg3 *tp)
  1925. {
  1926. u32 new_adv;
  1927. int i;
  1928. if (tp->link_config.phy_is_low_power) {
  1929. /* Entering low power mode. Disable gigabit and
  1930. * 100baseT advertisements.
  1931. */
  1932. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1933. new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  1934. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  1935. if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
  1936. new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
  1937. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1938. } else if (tp->link_config.speed == SPEED_INVALID) {
  1939. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  1940. tp->link_config.advertising &=
  1941. ~(ADVERTISED_1000baseT_Half |
  1942. ADVERTISED_1000baseT_Full);
  1943. new_adv = ADVERTISE_CSMA;
  1944. if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
  1945. new_adv |= ADVERTISE_10HALF;
  1946. if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
  1947. new_adv |= ADVERTISE_10FULL;
  1948. if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
  1949. new_adv |= ADVERTISE_100HALF;
  1950. if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
  1951. new_adv |= ADVERTISE_100FULL;
  1952. new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  1953. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1954. if (tp->link_config.advertising &
  1955. (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
  1956. new_adv = 0;
  1957. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  1958. new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
  1959. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  1960. new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
  1961. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
  1962. (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1963. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
  1964. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  1965. MII_TG3_CTRL_ENABLE_AS_MASTER);
  1966. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  1967. } else {
  1968. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1969. }
  1970. } else {
  1971. new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  1972. new_adv |= ADVERTISE_CSMA;
  1973. /* Asking for a specific link mode. */
  1974. if (tp->link_config.speed == SPEED_1000) {
  1975. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1976. if (tp->link_config.duplex == DUPLEX_FULL)
  1977. new_adv = MII_TG3_CTRL_ADV_1000_FULL;
  1978. else
  1979. new_adv = MII_TG3_CTRL_ADV_1000_HALF;
  1980. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1981. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  1982. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  1983. MII_TG3_CTRL_ENABLE_AS_MASTER);
  1984. } else {
  1985. if (tp->link_config.speed == SPEED_100) {
  1986. if (tp->link_config.duplex == DUPLEX_FULL)
  1987. new_adv |= ADVERTISE_100FULL;
  1988. else
  1989. new_adv |= ADVERTISE_100HALF;
  1990. } else {
  1991. if (tp->link_config.duplex == DUPLEX_FULL)
  1992. new_adv |= ADVERTISE_10FULL;
  1993. else
  1994. new_adv |= ADVERTISE_10HALF;
  1995. }
  1996. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1997. new_adv = 0;
  1998. }
  1999. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  2000. }
  2001. if (tp->link_config.autoneg == AUTONEG_DISABLE &&
  2002. tp->link_config.speed != SPEED_INVALID) {
  2003. u32 bmcr, orig_bmcr;
  2004. tp->link_config.active_speed = tp->link_config.speed;
  2005. tp->link_config.active_duplex = tp->link_config.duplex;
  2006. bmcr = 0;
  2007. switch (tp->link_config.speed) {
  2008. default:
  2009. case SPEED_10:
  2010. break;
  2011. case SPEED_100:
  2012. bmcr |= BMCR_SPEED100;
  2013. break;
  2014. case SPEED_1000:
  2015. bmcr |= TG3_BMCR_SPEED1000;
  2016. break;
  2017. }
  2018. if (tp->link_config.duplex == DUPLEX_FULL)
  2019. bmcr |= BMCR_FULLDPLX;
  2020. if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
  2021. (bmcr != orig_bmcr)) {
  2022. tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
  2023. for (i = 0; i < 1500; i++) {
  2024. u32 tmp;
  2025. udelay(10);
  2026. if (tg3_readphy(tp, MII_BMSR, &tmp) ||
  2027. tg3_readphy(tp, MII_BMSR, &tmp))
  2028. continue;
  2029. if (!(tmp & BMSR_LSTATUS)) {
  2030. udelay(40);
  2031. break;
  2032. }
  2033. }
  2034. tg3_writephy(tp, MII_BMCR, bmcr);
  2035. udelay(40);
  2036. }
  2037. } else {
  2038. tg3_writephy(tp, MII_BMCR,
  2039. BMCR_ANENABLE | BMCR_ANRESTART);
  2040. }
  2041. }
  2042. static int tg3_init_5401phy_dsp(struct tg3 *tp)
  2043. {
  2044. int err;
  2045. /* Turn off tap power management. */
  2046. /* Set Extended packet length bit */
  2047. err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  2048. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
  2049. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
  2050. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
  2051. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
  2052. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  2053. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
  2054. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  2055. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
  2056. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  2057. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
  2058. udelay(40);
  2059. return err;
  2060. }
  2061. static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
  2062. {
  2063. u32 adv_reg, all_mask = 0;
  2064. if (mask & ADVERTISED_10baseT_Half)
  2065. all_mask |= ADVERTISE_10HALF;
  2066. if (mask & ADVERTISED_10baseT_Full)
  2067. all_mask |= ADVERTISE_10FULL;
  2068. if (mask & ADVERTISED_100baseT_Half)
  2069. all_mask |= ADVERTISE_100HALF;
  2070. if (mask & ADVERTISED_100baseT_Full)
  2071. all_mask |= ADVERTISE_100FULL;
  2072. if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
  2073. return 0;
  2074. if ((adv_reg & all_mask) != all_mask)
  2075. return 0;
  2076. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  2077. u32 tg3_ctrl;
  2078. all_mask = 0;
  2079. if (mask & ADVERTISED_1000baseT_Half)
  2080. all_mask |= ADVERTISE_1000HALF;
  2081. if (mask & ADVERTISED_1000baseT_Full)
  2082. all_mask |= ADVERTISE_1000FULL;
  2083. if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
  2084. return 0;
  2085. if ((tg3_ctrl & all_mask) != all_mask)
  2086. return 0;
  2087. }
  2088. return 1;
  2089. }
  2090. static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
  2091. {
  2092. u32 curadv, reqadv;
  2093. if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
  2094. return 1;
  2095. curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  2096. reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  2097. if (tp->link_config.active_duplex == DUPLEX_FULL) {
  2098. if (curadv != reqadv)
  2099. return 0;
  2100. if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
  2101. tg3_readphy(tp, MII_LPA, rmtadv);
  2102. } else {
  2103. /* Reprogram the advertisement register, even if it
  2104. * does not affect the current link. If the link
  2105. * gets renegotiated in the future, we can save an
  2106. * additional renegotiation cycle by advertising
  2107. * it correctly in the first place.
  2108. */
  2109. if (curadv != reqadv) {
  2110. *lcladv &= ~(ADVERTISE_PAUSE_CAP |
  2111. ADVERTISE_PAUSE_ASYM);
  2112. tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
  2113. }
  2114. }
  2115. return 1;
  2116. }
  2117. static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
  2118. {
  2119. int current_link_up;
  2120. u32 bmsr, dummy;
  2121. u32 lcl_adv, rmt_adv;
  2122. u16 current_speed;
  2123. u8 current_duplex;
  2124. int i, err;
  2125. tw32(MAC_EVENT, 0);
  2126. tw32_f(MAC_STATUS,
  2127. (MAC_STATUS_SYNC_CHANGED |
  2128. MAC_STATUS_CFG_CHANGED |
  2129. MAC_STATUS_MI_COMPLETION |
  2130. MAC_STATUS_LNKSTATE_CHANGED));
  2131. udelay(40);
  2132. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  2133. tw32_f(MAC_MI_MODE,
  2134. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  2135. udelay(80);
  2136. }
  2137. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
  2138. /* Some third-party PHYs need to be reset on link going
  2139. * down.
  2140. */
  2141. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  2142. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  2143. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  2144. netif_carrier_ok(tp->dev)) {
  2145. tg3_readphy(tp, MII_BMSR, &bmsr);
  2146. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  2147. !(bmsr & BMSR_LSTATUS))
  2148. force_reset = 1;
  2149. }
  2150. if (force_reset)
  2151. tg3_phy_reset(tp);
  2152. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  2153. tg3_readphy(tp, MII_BMSR, &bmsr);
  2154. if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
  2155. !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
  2156. bmsr = 0;
  2157. if (!(bmsr & BMSR_LSTATUS)) {
  2158. err = tg3_init_5401phy_dsp(tp);
  2159. if (err)
  2160. return err;
  2161. tg3_readphy(tp, MII_BMSR, &bmsr);
  2162. for (i = 0; i < 1000; i++) {
  2163. udelay(10);
  2164. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  2165. (bmsr & BMSR_LSTATUS)) {
  2166. udelay(40);
  2167. break;
  2168. }
  2169. }
  2170. if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
  2171. !(bmsr & BMSR_LSTATUS) &&
  2172. tp->link_config.active_speed == SPEED_1000) {
  2173. err = tg3_phy_reset(tp);
  2174. if (!err)
  2175. err = tg3_init_5401phy_dsp(tp);
  2176. if (err)
  2177. return err;
  2178. }
  2179. }
  2180. } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  2181. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
  2182. /* 5701 {A0,B0} CRC bug workaround */
  2183. tg3_writephy(tp, 0x15, 0x0a75);
  2184. tg3_writephy(tp, 0x1c, 0x8c68);
  2185. tg3_writephy(tp, 0x1c, 0x8d68);
  2186. tg3_writephy(tp, 0x1c, 0x8c68);
  2187. }
  2188. /* Clear pending interrupts... */
  2189. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  2190. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  2191. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
  2192. tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
  2193. else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  2194. tg3_writephy(tp, MII_TG3_IMASK, ~0);
  2195. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2196. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  2197. if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
  2198. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  2199. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  2200. else
  2201. tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
  2202. }
  2203. current_link_up = 0;
  2204. current_speed = SPEED_INVALID;
  2205. current_duplex = DUPLEX_INVALID;
  2206. if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
  2207. u32 val;
  2208. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
  2209. tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
  2210. if (!(val & (1 << 10))) {
  2211. val |= (1 << 10);
  2212. tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
  2213. goto relink;
  2214. }
  2215. }
  2216. bmsr = 0;
  2217. for (i = 0; i < 100; i++) {
  2218. tg3_readphy(tp, MII_BMSR, &bmsr);
  2219. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  2220. (bmsr & BMSR_LSTATUS))
  2221. break;
  2222. udelay(40);
  2223. }
  2224. if (bmsr & BMSR_LSTATUS) {
  2225. u32 aux_stat, bmcr;
  2226. tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
  2227. for (i = 0; i < 2000; i++) {
  2228. udelay(10);
  2229. if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
  2230. aux_stat)
  2231. break;
  2232. }
  2233. tg3_aux_stat_to_speed_duplex(tp, aux_stat,
  2234. &current_speed,
  2235. &current_duplex);
  2236. bmcr = 0;
  2237. for (i = 0; i < 200; i++) {
  2238. tg3_readphy(tp, MII_BMCR, &bmcr);
  2239. if (tg3_readphy(tp, MII_BMCR, &bmcr))
  2240. continue;
  2241. if (bmcr && bmcr != 0x7fff)
  2242. break;
  2243. udelay(10);
  2244. }
  2245. lcl_adv = 0;
  2246. rmt_adv = 0;
  2247. tp->link_config.active_speed = current_speed;
  2248. tp->link_config.active_duplex = current_duplex;
  2249. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2250. if ((bmcr & BMCR_ANENABLE) &&
  2251. tg3_copper_is_advertising_all(tp,
  2252. tp->link_config.advertising)) {
  2253. if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
  2254. &rmt_adv))
  2255. current_link_up = 1;
  2256. }
  2257. } else {
  2258. if (!(bmcr & BMCR_ANENABLE) &&
  2259. tp->link_config.speed == current_speed &&
  2260. tp->link_config.duplex == current_duplex &&
  2261. tp->link_config.flowctrl ==
  2262. tp->link_config.active_flowctrl) {
  2263. current_link_up = 1;
  2264. }
  2265. }
  2266. if (current_link_up == 1 &&
  2267. tp->link_config.active_duplex == DUPLEX_FULL)
  2268. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  2269. }
  2270. relink:
  2271. if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
  2272. u32 tmp;
  2273. tg3_phy_copper_begin(tp);
  2274. tg3_readphy(tp, MII_BMSR, &tmp);
  2275. if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
  2276. (tmp & BMSR_LSTATUS))
  2277. current_link_up = 1;
  2278. }
  2279. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  2280. if (current_link_up == 1) {
  2281. if (tp->link_config.active_speed == SPEED_100 ||
  2282. tp->link_config.active_speed == SPEED_10)
  2283. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  2284. else
  2285. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2286. } else
  2287. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2288. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  2289. if (tp->link_config.active_duplex == DUPLEX_HALF)
  2290. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  2291. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  2292. if (current_link_up == 1 &&
  2293. tg3_5700_link_polarity(tp, tp->link_config.active_speed))
  2294. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  2295. else
  2296. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  2297. }
  2298. /* ??? Without this setting Netgear GA302T PHY does not
  2299. * ??? send/receive packets...
  2300. */
  2301. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
  2302. tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
  2303. tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  2304. tw32_f(MAC_MI_MODE, tp->mi_mode);
  2305. udelay(80);
  2306. }
  2307. tw32_f(MAC_MODE, tp->mac_mode);
  2308. udelay(40);
  2309. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  2310. /* Polled via timer. */
  2311. tw32_f(MAC_EVENT, 0);
  2312. } else {
  2313. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2314. }
  2315. udelay(40);
  2316. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
  2317. current_link_up == 1 &&
  2318. tp->link_config.active_speed == SPEED_1000 &&
  2319. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
  2320. (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
  2321. udelay(120);
  2322. tw32_f(MAC_STATUS,
  2323. (MAC_STATUS_SYNC_CHANGED |
  2324. MAC_STATUS_CFG_CHANGED));
  2325. udelay(40);
  2326. tg3_write_mem(tp,
  2327. NIC_SRAM_FIRMWARE_MBOX,
  2328. NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  2329. }
  2330. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2331. if (current_link_up)
  2332. netif_carrier_on(tp->dev);
  2333. else
  2334. netif_carrier_off(tp->dev);
  2335. tg3_link_report(tp);
  2336. }
  2337. return 0;
  2338. }
  2339. struct tg3_fiber_aneginfo {
  2340. int state;
  2341. #define ANEG_STATE_UNKNOWN 0
  2342. #define ANEG_STATE_AN_ENABLE 1
  2343. #define ANEG_STATE_RESTART_INIT 2
  2344. #define ANEG_STATE_RESTART 3
  2345. #define ANEG_STATE_DISABLE_LINK_OK 4
  2346. #define ANEG_STATE_ABILITY_DETECT_INIT 5
  2347. #define ANEG_STATE_ABILITY_DETECT 6
  2348. #define ANEG_STATE_ACK_DETECT_INIT 7
  2349. #define ANEG_STATE_ACK_DETECT 8
  2350. #define ANEG_STATE_COMPLETE_ACK_INIT 9
  2351. #define ANEG_STATE_COMPLETE_ACK 10
  2352. #define ANEG_STATE_IDLE_DETECT_INIT 11
  2353. #define ANEG_STATE_IDLE_DETECT 12
  2354. #define ANEG_STATE_LINK_OK 13
  2355. #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
  2356. #define ANEG_STATE_NEXT_PAGE_WAIT 15
  2357. u32 flags;
  2358. #define MR_AN_ENABLE 0x00000001
  2359. #define MR_RESTART_AN 0x00000002
  2360. #define MR_AN_COMPLETE 0x00000004
  2361. #define MR_PAGE_RX 0x00000008
  2362. #define MR_NP_LOADED 0x00000010
  2363. #define MR_TOGGLE_TX 0x00000020
  2364. #define MR_LP_ADV_FULL_DUPLEX 0x00000040
  2365. #define MR_LP_ADV_HALF_DUPLEX 0x00000080
  2366. #define MR_LP_ADV_SYM_PAUSE 0x00000100
  2367. #define MR_LP_ADV_ASYM_PAUSE 0x00000200
  2368. #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
  2369. #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
  2370. #define MR_LP_ADV_NEXT_PAGE 0x00001000
  2371. #define MR_TOGGLE_RX 0x00002000
  2372. #define MR_NP_RX 0x00004000
  2373. #define MR_LINK_OK 0x80000000
  2374. unsigned long link_time, cur_time;
  2375. u32 ability_match_cfg;
  2376. int ability_match_count;
  2377. char ability_match, idle_match, ack_match;
  2378. u32 txconfig, rxconfig;
  2379. #define ANEG_CFG_NP 0x00000080
  2380. #define ANEG_CFG_ACK 0x00000040
  2381. #define ANEG_CFG_RF2 0x00000020
  2382. #define ANEG_CFG_RF1 0x00000010
  2383. #define ANEG_CFG_PS2 0x00000001
  2384. #define ANEG_CFG_PS1 0x00008000
  2385. #define ANEG_CFG_HD 0x00004000
  2386. #define ANEG_CFG_FD 0x00002000
  2387. #define ANEG_CFG_INVAL 0x00001f06
  2388. };
  2389. #define ANEG_OK 0
  2390. #define ANEG_DONE 1
  2391. #define ANEG_TIMER_ENAB 2
  2392. #define ANEG_FAILED -1
  2393. #define ANEG_STATE_SETTLE_TIME 10000
  2394. static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  2395. struct tg3_fiber_aneginfo *ap)
  2396. {
  2397. u16 flowctrl;
  2398. unsigned long delta;
  2399. u32 rx_cfg_reg;
  2400. int ret;
  2401. if (ap->state == ANEG_STATE_UNKNOWN) {
  2402. ap->rxconfig = 0;
  2403. ap->link_time = 0;
  2404. ap->cur_time = 0;
  2405. ap->ability_match_cfg = 0;
  2406. ap->ability_match_count = 0;
  2407. ap->ability_match = 0;
  2408. ap->idle_match = 0;
  2409. ap->ack_match = 0;
  2410. }
  2411. ap->cur_time++;
  2412. if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  2413. rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  2414. if (rx_cfg_reg != ap->ability_match_cfg) {
  2415. ap->ability_match_cfg = rx_cfg_reg;
  2416. ap->ability_match = 0;
  2417. ap->ability_match_count = 0;
  2418. } else {
  2419. if (++ap->ability_match_count > 1) {
  2420. ap->ability_match = 1;
  2421. ap->ability_match_cfg = rx_cfg_reg;
  2422. }
  2423. }
  2424. if (rx_cfg_reg & ANEG_CFG_ACK)
  2425. ap->ack_match = 1;
  2426. else
  2427. ap->ack_match = 0;
  2428. ap->idle_match = 0;
  2429. } else {
  2430. ap->idle_match = 1;
  2431. ap->ability_match_cfg = 0;
  2432. ap->ability_match_count = 0;
  2433. ap->ability_match = 0;
  2434. ap->ack_match = 0;
  2435. rx_cfg_reg = 0;
  2436. }
  2437. ap->rxconfig = rx_cfg_reg;
  2438. ret = ANEG_OK;
  2439. switch(ap->state) {
  2440. case ANEG_STATE_UNKNOWN:
  2441. if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  2442. ap->state = ANEG_STATE_AN_ENABLE;
  2443. /* fallthru */
  2444. case ANEG_STATE_AN_ENABLE:
  2445. ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  2446. if (ap->flags & MR_AN_ENABLE) {
  2447. ap->link_time = 0;
  2448. ap->cur_time = 0;
  2449. ap->ability_match_cfg = 0;
  2450. ap->ability_match_count = 0;
  2451. ap->ability_match = 0;
  2452. ap->idle_match = 0;
  2453. ap->ack_match = 0;
  2454. ap->state = ANEG_STATE_RESTART_INIT;
  2455. } else {
  2456. ap->state = ANEG_STATE_DISABLE_LINK_OK;
  2457. }
  2458. break;
  2459. case ANEG_STATE_RESTART_INIT:
  2460. ap->link_time = ap->cur_time;
  2461. ap->flags &= ~(MR_NP_LOADED);
  2462. ap->txconfig = 0;
  2463. tw32(MAC_TX_AUTO_NEG, 0);
  2464. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2465. tw32_f(MAC_MODE, tp->mac_mode);
  2466. udelay(40);
  2467. ret = ANEG_TIMER_ENAB;
  2468. ap->state = ANEG_STATE_RESTART;
  2469. /* fallthru */
  2470. case ANEG_STATE_RESTART:
  2471. delta = ap->cur_time - ap->link_time;
  2472. if (delta > ANEG_STATE_SETTLE_TIME) {
  2473. ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  2474. } else {
  2475. ret = ANEG_TIMER_ENAB;
  2476. }
  2477. break;
  2478. case ANEG_STATE_DISABLE_LINK_OK:
  2479. ret = ANEG_DONE;
  2480. break;
  2481. case ANEG_STATE_ABILITY_DETECT_INIT:
  2482. ap->flags &= ~(MR_TOGGLE_TX);
  2483. ap->txconfig = ANEG_CFG_FD;
  2484. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  2485. if (flowctrl & ADVERTISE_1000XPAUSE)
  2486. ap->txconfig |= ANEG_CFG_PS1;
  2487. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  2488. ap->txconfig |= ANEG_CFG_PS2;
  2489. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  2490. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2491. tw32_f(MAC_MODE, tp->mac_mode);
  2492. udelay(40);
  2493. ap->state = ANEG_STATE_ABILITY_DETECT;
  2494. break;
  2495. case ANEG_STATE_ABILITY_DETECT:
  2496. if (ap->ability_match != 0 && ap->rxconfig != 0) {
  2497. ap->state = ANEG_STATE_ACK_DETECT_INIT;
  2498. }
  2499. break;
  2500. case ANEG_STATE_ACK_DETECT_INIT:
  2501. ap->txconfig |= ANEG_CFG_ACK;
  2502. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  2503. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2504. tw32_f(MAC_MODE, tp->mac_mode);
  2505. udelay(40);
  2506. ap->state = ANEG_STATE_ACK_DETECT;
  2507. /* fallthru */
  2508. case ANEG_STATE_ACK_DETECT:
  2509. if (ap->ack_match != 0) {
  2510. if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  2511. (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  2512. ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  2513. } else {
  2514. ap->state = ANEG_STATE_AN_ENABLE;
  2515. }
  2516. } else if (ap->ability_match != 0 &&
  2517. ap->rxconfig == 0) {
  2518. ap->state = ANEG_STATE_AN_ENABLE;
  2519. }
  2520. break;
  2521. case ANEG_STATE_COMPLETE_ACK_INIT:
  2522. if (ap->rxconfig & ANEG_CFG_INVAL) {
  2523. ret = ANEG_FAILED;
  2524. break;
  2525. }
  2526. ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  2527. MR_LP_ADV_HALF_DUPLEX |
  2528. MR_LP_ADV_SYM_PAUSE |
  2529. MR_LP_ADV_ASYM_PAUSE |
  2530. MR_LP_ADV_REMOTE_FAULT1 |
  2531. MR_LP_ADV_REMOTE_FAULT2 |
  2532. MR_LP_ADV_NEXT_PAGE |
  2533. MR_TOGGLE_RX |
  2534. MR_NP_RX);
  2535. if (ap->rxconfig & ANEG_CFG_FD)
  2536. ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  2537. if (ap->rxconfig & ANEG_CFG_HD)
  2538. ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  2539. if (ap->rxconfig & ANEG_CFG_PS1)
  2540. ap->flags |= MR_LP_ADV_SYM_PAUSE;
  2541. if (ap->rxconfig & ANEG_CFG_PS2)
  2542. ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  2543. if (ap->rxconfig & ANEG_CFG_RF1)
  2544. ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  2545. if (ap->rxconfig & ANEG_CFG_RF2)
  2546. ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  2547. if (ap->rxconfig & ANEG_CFG_NP)
  2548. ap->flags |= MR_LP_ADV_NEXT_PAGE;
  2549. ap->link_time = ap->cur_time;
  2550. ap->flags ^= (MR_TOGGLE_TX);
  2551. if (ap->rxconfig & 0x0008)
  2552. ap->flags |= MR_TOGGLE_RX;
  2553. if (ap->rxconfig & ANEG_CFG_NP)
  2554. ap->flags |= MR_NP_RX;
  2555. ap->flags |= MR_PAGE_RX;
  2556. ap->state = ANEG_STATE_COMPLETE_ACK;
  2557. ret = ANEG_TIMER_ENAB;
  2558. break;
  2559. case ANEG_STATE_COMPLETE_ACK:
  2560. if (ap->ability_match != 0 &&
  2561. ap->rxconfig == 0) {
  2562. ap->state = ANEG_STATE_AN_ENABLE;
  2563. break;
  2564. }
  2565. delta = ap->cur_time - ap->link_time;
  2566. if (delta > ANEG_STATE_SETTLE_TIME) {
  2567. if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  2568. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2569. } else {
  2570. if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  2571. !(ap->flags & MR_NP_RX)) {
  2572. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2573. } else {
  2574. ret = ANEG_FAILED;
  2575. }
  2576. }
  2577. }
  2578. break;
  2579. case ANEG_STATE_IDLE_DETECT_INIT:
  2580. ap->link_time = ap->cur_time;
  2581. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  2582. tw32_f(MAC_MODE, tp->mac_mode);
  2583. udelay(40);
  2584. ap->state = ANEG_STATE_IDLE_DETECT;
  2585. ret = ANEG_TIMER_ENAB;
  2586. break;
  2587. case ANEG_STATE_IDLE_DETECT:
  2588. if (ap->ability_match != 0 &&
  2589. ap->rxconfig == 0) {
  2590. ap->state = ANEG_STATE_AN_ENABLE;
  2591. break;
  2592. }
  2593. delta = ap->cur_time - ap->link_time;
  2594. if (delta > ANEG_STATE_SETTLE_TIME) {
  2595. /* XXX another gem from the Broadcom driver :( */
  2596. ap->state = ANEG_STATE_LINK_OK;
  2597. }
  2598. break;
  2599. case ANEG_STATE_LINK_OK:
  2600. ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  2601. ret = ANEG_DONE;
  2602. break;
  2603. case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  2604. /* ??? unimplemented */
  2605. break;
  2606. case ANEG_STATE_NEXT_PAGE_WAIT:
  2607. /* ??? unimplemented */
  2608. break;
  2609. default:
  2610. ret = ANEG_FAILED;
  2611. break;
  2612. }
  2613. return ret;
  2614. }
  2615. static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
  2616. {
  2617. int res = 0;
  2618. struct tg3_fiber_aneginfo aninfo;
  2619. int status = ANEG_FAILED;
  2620. unsigned int tick;
  2621. u32 tmp;
  2622. tw32_f(MAC_TX_AUTO_NEG, 0);
  2623. tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  2624. tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  2625. udelay(40);
  2626. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  2627. udelay(40);
  2628. memset(&aninfo, 0, sizeof(aninfo));
  2629. aninfo.flags |= MR_AN_ENABLE;
  2630. aninfo.state = ANEG_STATE_UNKNOWN;
  2631. aninfo.cur_time = 0;
  2632. tick = 0;
  2633. while (++tick < 195000) {
  2634. status = tg3_fiber_aneg_smachine(tp, &aninfo);
  2635. if (status == ANEG_DONE || status == ANEG_FAILED)
  2636. break;
  2637. udelay(1);
  2638. }
  2639. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  2640. tw32_f(MAC_MODE, tp->mac_mode);
  2641. udelay(40);
  2642. *txflags = aninfo.txconfig;
  2643. *rxflags = aninfo.flags;
  2644. if (status == ANEG_DONE &&
  2645. (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
  2646. MR_LP_ADV_FULL_DUPLEX)))
  2647. res = 1;
  2648. return res;
  2649. }
  2650. static void tg3_init_bcm8002(struct tg3 *tp)
  2651. {
  2652. u32 mac_status = tr32(MAC_STATUS);
  2653. int i;
  2654. /* Reset when initting first time or we have a link. */
  2655. if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
  2656. !(mac_status & MAC_STATUS_PCS_SYNCED))
  2657. return;
  2658. /* Set PLL lock range. */
  2659. tg3_writephy(tp, 0x16, 0x8007);
  2660. /* SW reset */
  2661. tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  2662. /* Wait for reset to complete. */
  2663. /* XXX schedule_timeout() ... */
  2664. for (i = 0; i < 500; i++)
  2665. udelay(10);
  2666. /* Config mode; select PMA/Ch 1 regs. */
  2667. tg3_writephy(tp, 0x10, 0x8411);
  2668. /* Enable auto-lock and comdet, select txclk for tx. */
  2669. tg3_writephy(tp, 0x11, 0x0a10);
  2670. tg3_writephy(tp, 0x18, 0x00a0);
  2671. tg3_writephy(tp, 0x16, 0x41ff);
  2672. /* Assert and deassert POR. */
  2673. tg3_writephy(tp, 0x13, 0x0400);
  2674. udelay(40);
  2675. tg3_writephy(tp, 0x13, 0x0000);
  2676. tg3_writephy(tp, 0x11, 0x0a50);
  2677. udelay(40);
  2678. tg3_writephy(tp, 0x11, 0x0a10);
  2679. /* Wait for signal to stabilize */
  2680. /* XXX schedule_timeout() ... */
  2681. for (i = 0; i < 15000; i++)
  2682. udelay(10);
  2683. /* Deselect the channel register so we can read the PHYID
  2684. * later.
  2685. */
  2686. tg3_writephy(tp, 0x10, 0x8011);
  2687. }
  2688. static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
  2689. {
  2690. u16 flowctrl;
  2691. u32 sg_dig_ctrl, sg_dig_status;
  2692. u32 serdes_cfg, expected_sg_dig_ctrl;
  2693. int workaround, port_a;
  2694. int current_link_up;
  2695. serdes_cfg = 0;
  2696. expected_sg_dig_ctrl = 0;
  2697. workaround = 0;
  2698. port_a = 1;
  2699. current_link_up = 0;
  2700. if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
  2701. tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
  2702. workaround = 1;
  2703. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  2704. port_a = 0;
  2705. /* preserve bits 0-11,13,14 for signal pre-emphasis */
  2706. /* preserve bits 20-23 for voltage regulator */
  2707. serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
  2708. }
  2709. sg_dig_ctrl = tr32(SG_DIG_CTRL);
  2710. if (tp->link_config.autoneg != AUTONEG_ENABLE) {
  2711. if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
  2712. if (workaround) {
  2713. u32 val = serdes_cfg;
  2714. if (port_a)
  2715. val |= 0xc010000;
  2716. else
  2717. val |= 0x4010000;
  2718. tw32_f(MAC_SERDES_CFG, val);
  2719. }
  2720. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  2721. }
  2722. if (mac_status & MAC_STATUS_PCS_SYNCED) {
  2723. tg3_setup_flow_control(tp, 0, 0);
  2724. current_link_up = 1;
  2725. }
  2726. goto out;
  2727. }
  2728. /* Want auto-negotiation. */
  2729. expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
  2730. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  2731. if (flowctrl & ADVERTISE_1000XPAUSE)
  2732. expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
  2733. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  2734. expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
  2735. if (sg_dig_ctrl != expected_sg_dig_ctrl) {
  2736. if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
  2737. tp->serdes_counter &&
  2738. ((mac_status & (MAC_STATUS_PCS_SYNCED |
  2739. MAC_STATUS_RCVD_CFG)) ==
  2740. MAC_STATUS_PCS_SYNCED)) {
  2741. tp->serdes_counter--;
  2742. current_link_up = 1;
  2743. goto out;
  2744. }
  2745. restart_autoneg:
  2746. if (workaround)
  2747. tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
  2748. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
  2749. udelay(5);
  2750. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
  2751. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  2752. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2753. } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
  2754. MAC_STATUS_SIGNAL_DET)) {
  2755. sg_dig_status = tr32(SG_DIG_STATUS);
  2756. mac_status = tr32(MAC_STATUS);
  2757. if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
  2758. (mac_status & MAC_STATUS_PCS_SYNCED)) {
  2759. u32 local_adv = 0, remote_adv = 0;
  2760. if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
  2761. local_adv |= ADVERTISE_1000XPAUSE;
  2762. if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
  2763. local_adv |= ADVERTISE_1000XPSE_ASYM;
  2764. if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
  2765. remote_adv |= LPA_1000XPAUSE;
  2766. if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
  2767. remote_adv |= LPA_1000XPAUSE_ASYM;
  2768. tg3_setup_flow_control(tp, local_adv, remote_adv);
  2769. current_link_up = 1;
  2770. tp->serdes_counter = 0;
  2771. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2772. } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
  2773. if (tp->serdes_counter)
  2774. tp->serdes_counter--;
  2775. else {
  2776. if (workaround) {
  2777. u32 val = serdes_cfg;
  2778. if (port_a)
  2779. val |= 0xc010000;
  2780. else
  2781. val |= 0x4010000;
  2782. tw32_f(MAC_SERDES_CFG, val);
  2783. }
  2784. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  2785. udelay(40);
  2786. /* Link parallel detection - link is up */
  2787. /* only if we have PCS_SYNC and not */
  2788. /* receiving config code words */
  2789. mac_status = tr32(MAC_STATUS);
  2790. if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
  2791. !(mac_status & MAC_STATUS_RCVD_CFG)) {
  2792. tg3_setup_flow_control(tp, 0, 0);
  2793. current_link_up = 1;
  2794. tp->tg3_flags2 |=
  2795. TG3_FLG2_PARALLEL_DETECT;
  2796. tp->serdes_counter =
  2797. SERDES_PARALLEL_DET_TIMEOUT;
  2798. } else
  2799. goto restart_autoneg;
  2800. }
  2801. }
  2802. } else {
  2803. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  2804. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2805. }
  2806. out:
  2807. return current_link_up;
  2808. }
  2809. static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
  2810. {
  2811. int current_link_up = 0;
  2812. if (!(mac_status & MAC_STATUS_PCS_SYNCED))
  2813. goto out;
  2814. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2815. u32 txflags, rxflags;
  2816. int i;
  2817. if (fiber_autoneg(tp, &txflags, &rxflags)) {
  2818. u32 local_adv = 0, remote_adv = 0;
  2819. if (txflags & ANEG_CFG_PS1)
  2820. local_adv |= ADVERTISE_1000XPAUSE;
  2821. if (txflags & ANEG_CFG_PS2)
  2822. local_adv |= ADVERTISE_1000XPSE_ASYM;
  2823. if (rxflags & MR_LP_ADV_SYM_PAUSE)
  2824. remote_adv |= LPA_1000XPAUSE;
  2825. if (rxflags & MR_LP_ADV_ASYM_PAUSE)
  2826. remote_adv |= LPA_1000XPAUSE_ASYM;
  2827. tg3_setup_flow_control(tp, local_adv, remote_adv);
  2828. current_link_up = 1;
  2829. }
  2830. for (i = 0; i < 30; i++) {
  2831. udelay(20);
  2832. tw32_f(MAC_STATUS,
  2833. (MAC_STATUS_SYNC_CHANGED |
  2834. MAC_STATUS_CFG_CHANGED));
  2835. udelay(40);
  2836. if ((tr32(MAC_STATUS) &
  2837. (MAC_STATUS_SYNC_CHANGED |
  2838. MAC_STATUS_CFG_CHANGED)) == 0)
  2839. break;
  2840. }
  2841. mac_status = tr32(MAC_STATUS);
  2842. if (current_link_up == 0 &&
  2843. (mac_status & MAC_STATUS_PCS_SYNCED) &&
  2844. !(mac_status & MAC_STATUS_RCVD_CFG))
  2845. current_link_up = 1;
  2846. } else {
  2847. tg3_setup_flow_control(tp, 0, 0);
  2848. /* Forcing 1000FD link up. */
  2849. current_link_up = 1;
  2850. tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
  2851. udelay(40);
  2852. tw32_f(MAC_MODE, tp->mac_mode);
  2853. udelay(40);
  2854. }
  2855. out:
  2856. return current_link_up;
  2857. }
  2858. static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
  2859. {
  2860. u32 orig_pause_cfg;
  2861. u16 orig_active_speed;
  2862. u8 orig_active_duplex;
  2863. u32 mac_status;
  2864. int current_link_up;
  2865. int i;
  2866. orig_pause_cfg = tp->link_config.active_flowctrl;
  2867. orig_active_speed = tp->link_config.active_speed;
  2868. orig_active_duplex = tp->link_config.active_duplex;
  2869. if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
  2870. netif_carrier_ok(tp->dev) &&
  2871. (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
  2872. mac_status = tr32(MAC_STATUS);
  2873. mac_status &= (MAC_STATUS_PCS_SYNCED |
  2874. MAC_STATUS_SIGNAL_DET |
  2875. MAC_STATUS_CFG_CHANGED |
  2876. MAC_STATUS_RCVD_CFG);
  2877. if (mac_status == (MAC_STATUS_PCS_SYNCED |
  2878. MAC_STATUS_SIGNAL_DET)) {
  2879. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  2880. MAC_STATUS_CFG_CHANGED));
  2881. return 0;
  2882. }
  2883. }
  2884. tw32_f(MAC_TX_AUTO_NEG, 0);
  2885. tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  2886. tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  2887. tw32_f(MAC_MODE, tp->mac_mode);
  2888. udelay(40);
  2889. if (tp->phy_id == PHY_ID_BCM8002)
  2890. tg3_init_bcm8002(tp);
  2891. /* Enable link change event even when serdes polling. */
  2892. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2893. udelay(40);
  2894. current_link_up = 0;
  2895. mac_status = tr32(MAC_STATUS);
  2896. if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
  2897. current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
  2898. else
  2899. current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
  2900. tp->hw_status->status =
  2901. (SD_STATUS_UPDATED |
  2902. (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
  2903. for (i = 0; i < 100; i++) {
  2904. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  2905. MAC_STATUS_CFG_CHANGED));
  2906. udelay(5);
  2907. if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
  2908. MAC_STATUS_CFG_CHANGED |
  2909. MAC_STATUS_LNKSTATE_CHANGED)) == 0)
  2910. break;
  2911. }
  2912. mac_status = tr32(MAC_STATUS);
  2913. if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
  2914. current_link_up = 0;
  2915. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  2916. tp->serdes_counter == 0) {
  2917. tw32_f(MAC_MODE, (tp->mac_mode |
  2918. MAC_MODE_SEND_CONFIGS));
  2919. udelay(1);
  2920. tw32_f(MAC_MODE, tp->mac_mode);
  2921. }
  2922. }
  2923. if (current_link_up == 1) {
  2924. tp->link_config.active_speed = SPEED_1000;
  2925. tp->link_config.active_duplex = DUPLEX_FULL;
  2926. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  2927. LED_CTRL_LNKLED_OVERRIDE |
  2928. LED_CTRL_1000MBPS_ON));
  2929. } else {
  2930. tp->link_config.active_speed = SPEED_INVALID;
  2931. tp->link_config.active_duplex = DUPLEX_INVALID;
  2932. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  2933. LED_CTRL_LNKLED_OVERRIDE |
  2934. LED_CTRL_TRAFFIC_OVERRIDE));
  2935. }
  2936. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2937. if (current_link_up)
  2938. netif_carrier_on(tp->dev);
  2939. else
  2940. netif_carrier_off(tp->dev);
  2941. tg3_link_report(tp);
  2942. } else {
  2943. u32 now_pause_cfg = tp->link_config.active_flowctrl;
  2944. if (orig_pause_cfg != now_pause_cfg ||
  2945. orig_active_speed != tp->link_config.active_speed ||
  2946. orig_active_duplex != tp->link_config.active_duplex)
  2947. tg3_link_report(tp);
  2948. }
  2949. return 0;
  2950. }
  2951. static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
  2952. {
  2953. int current_link_up, err = 0;
  2954. u32 bmsr, bmcr;
  2955. u16 current_speed;
  2956. u8 current_duplex;
  2957. u32 local_adv, remote_adv;
  2958. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2959. tw32_f(MAC_MODE, tp->mac_mode);
  2960. udelay(40);
  2961. tw32(MAC_EVENT, 0);
  2962. tw32_f(MAC_STATUS,
  2963. (MAC_STATUS_SYNC_CHANGED |
  2964. MAC_STATUS_CFG_CHANGED |
  2965. MAC_STATUS_MI_COMPLETION |
  2966. MAC_STATUS_LNKSTATE_CHANGED));
  2967. udelay(40);
  2968. if (force_reset)
  2969. tg3_phy_reset(tp);
  2970. current_link_up = 0;
  2971. current_speed = SPEED_INVALID;
  2972. current_duplex = DUPLEX_INVALID;
  2973. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2974. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2975. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  2976. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  2977. bmsr |= BMSR_LSTATUS;
  2978. else
  2979. bmsr &= ~BMSR_LSTATUS;
  2980. }
  2981. err |= tg3_readphy(tp, MII_BMCR, &bmcr);
  2982. if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
  2983. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
  2984. /* do nothing, just check for link up at the end */
  2985. } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2986. u32 adv, new_adv;
  2987. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  2988. new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
  2989. ADVERTISE_1000XPAUSE |
  2990. ADVERTISE_1000XPSE_ASYM |
  2991. ADVERTISE_SLCT);
  2992. new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  2993. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  2994. new_adv |= ADVERTISE_1000XHALF;
  2995. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  2996. new_adv |= ADVERTISE_1000XFULL;
  2997. if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
  2998. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2999. bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
  3000. tg3_writephy(tp, MII_BMCR, bmcr);
  3001. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  3002. tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
  3003. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  3004. return err;
  3005. }
  3006. } else {
  3007. u32 new_bmcr;
  3008. bmcr &= ~BMCR_SPEED1000;
  3009. new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
  3010. if (tp->link_config.duplex == DUPLEX_FULL)
  3011. new_bmcr |= BMCR_FULLDPLX;
  3012. if (new_bmcr != bmcr) {
  3013. /* BMCR_SPEED1000 is a reserved bit that needs
  3014. * to be set on write.
  3015. */
  3016. new_bmcr |= BMCR_SPEED1000;
  3017. /* Force a linkdown */
  3018. if (netif_carrier_ok(tp->dev)) {
  3019. u32 adv;
  3020. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  3021. adv &= ~(ADVERTISE_1000XFULL |
  3022. ADVERTISE_1000XHALF |
  3023. ADVERTISE_SLCT);
  3024. tg3_writephy(tp, MII_ADVERTISE, adv);
  3025. tg3_writephy(tp, MII_BMCR, bmcr |
  3026. BMCR_ANRESTART |
  3027. BMCR_ANENABLE);
  3028. udelay(10);
  3029. netif_carrier_off(tp->dev);
  3030. }
  3031. tg3_writephy(tp, MII_BMCR, new_bmcr);
  3032. bmcr = new_bmcr;
  3033. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  3034. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  3035. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  3036. ASIC_REV_5714) {
  3037. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  3038. bmsr |= BMSR_LSTATUS;
  3039. else
  3040. bmsr &= ~BMSR_LSTATUS;
  3041. }
  3042. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  3043. }
  3044. }
  3045. if (bmsr & BMSR_LSTATUS) {
  3046. current_speed = SPEED_1000;
  3047. current_link_up = 1;
  3048. if (bmcr & BMCR_FULLDPLX)
  3049. current_duplex = DUPLEX_FULL;
  3050. else
  3051. current_duplex = DUPLEX_HALF;
  3052. local_adv = 0;
  3053. remote_adv = 0;
  3054. if (bmcr & BMCR_ANENABLE) {
  3055. u32 common;
  3056. err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  3057. err |= tg3_readphy(tp, MII_LPA, &remote_adv);
  3058. common = local_adv & remote_adv;
  3059. if (common & (ADVERTISE_1000XHALF |
  3060. ADVERTISE_1000XFULL)) {
  3061. if (common & ADVERTISE_1000XFULL)
  3062. current_duplex = DUPLEX_FULL;
  3063. else
  3064. current_duplex = DUPLEX_HALF;
  3065. }
  3066. else
  3067. current_link_up = 0;
  3068. }
  3069. }
  3070. if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
  3071. tg3_setup_flow_control(tp, local_adv, remote_adv);
  3072. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  3073. if (tp->link_config.active_duplex == DUPLEX_HALF)
  3074. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  3075. tw32_f(MAC_MODE, tp->mac_mode);
  3076. udelay(40);
  3077. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  3078. tp->link_config.active_speed = current_speed;
  3079. tp->link_config.active_duplex = current_duplex;
  3080. if (current_link_up != netif_carrier_ok(tp->dev)) {
  3081. if (current_link_up)
  3082. netif_carrier_on(tp->dev);
  3083. else {
  3084. netif_carrier_off(tp->dev);
  3085. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  3086. }
  3087. tg3_link_report(tp);
  3088. }
  3089. return err;
  3090. }
  3091. static void tg3_serdes_parallel_detect(struct tg3 *tp)
  3092. {
  3093. if (tp->serdes_counter) {
  3094. /* Give autoneg time to complete. */
  3095. tp->serdes_counter--;
  3096. return;
  3097. }
  3098. if (!netif_carrier_ok(tp->dev) &&
  3099. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  3100. u32 bmcr;
  3101. tg3_readphy(tp, MII_BMCR, &bmcr);
  3102. if (bmcr & BMCR_ANENABLE) {
  3103. u32 phy1, phy2;
  3104. /* Select shadow register 0x1f */
  3105. tg3_writephy(tp, 0x1c, 0x7c00);
  3106. tg3_readphy(tp, 0x1c, &phy1);
  3107. /* Select expansion interrupt status register */
  3108. tg3_writephy(tp, 0x17, 0x0f01);
  3109. tg3_readphy(tp, 0x15, &phy2);
  3110. tg3_readphy(tp, 0x15, &phy2);
  3111. if ((phy1 & 0x10) && !(phy2 & 0x20)) {
  3112. /* We have signal detect and not receiving
  3113. * config code words, link is up by parallel
  3114. * detection.
  3115. */
  3116. bmcr &= ~BMCR_ANENABLE;
  3117. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  3118. tg3_writephy(tp, MII_BMCR, bmcr);
  3119. tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
  3120. }
  3121. }
  3122. }
  3123. else if (netif_carrier_ok(tp->dev) &&
  3124. (tp->link_config.autoneg == AUTONEG_ENABLE) &&
  3125. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
  3126. u32 phy2;
  3127. /* Select expansion interrupt status register */
  3128. tg3_writephy(tp, 0x17, 0x0f01);
  3129. tg3_readphy(tp, 0x15, &phy2);
  3130. if (phy2 & 0x20) {
  3131. u32 bmcr;
  3132. /* Config code words received, turn on autoneg. */
  3133. tg3_readphy(tp, MII_BMCR, &bmcr);
  3134. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
  3135. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  3136. }
  3137. }
  3138. }
  3139. static int tg3_setup_phy(struct tg3 *tp, int force_reset)
  3140. {
  3141. int err;
  3142. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  3143. err = tg3_setup_fiber_phy(tp, force_reset);
  3144. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  3145. err = tg3_setup_fiber_mii_phy(tp, force_reset);
  3146. } else {
  3147. err = tg3_setup_copper_phy(tp, force_reset);
  3148. }
  3149. if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
  3150. tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
  3151. u32 val, scale;
  3152. val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
  3153. if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
  3154. scale = 65;
  3155. else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
  3156. scale = 6;
  3157. else
  3158. scale = 12;
  3159. val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
  3160. val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
  3161. tw32(GRC_MISC_CFG, val);
  3162. }
  3163. if (tp->link_config.active_speed == SPEED_1000 &&
  3164. tp->link_config.active_duplex == DUPLEX_HALF)
  3165. tw32(MAC_TX_LENGTHS,
  3166. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  3167. (6 << TX_LENGTHS_IPG_SHIFT) |
  3168. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  3169. else
  3170. tw32(MAC_TX_LENGTHS,
  3171. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  3172. (6 << TX_LENGTHS_IPG_SHIFT) |
  3173. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  3174. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  3175. if (netif_carrier_ok(tp->dev)) {
  3176. tw32(HOSTCC_STAT_COAL_TICKS,
  3177. tp->coal.stats_block_coalesce_usecs);
  3178. } else {
  3179. tw32(HOSTCC_STAT_COAL_TICKS, 0);
  3180. }
  3181. }
  3182. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
  3183. u32 val = tr32(PCIE_PWR_MGMT_THRESH);
  3184. if (!netif_carrier_ok(tp->dev))
  3185. val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
  3186. tp->pwrmgmt_thresh;
  3187. else
  3188. val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
  3189. tw32(PCIE_PWR_MGMT_THRESH, val);
  3190. }
  3191. return err;
  3192. }
  3193. /* This is called whenever we suspect that the system chipset is re-
  3194. * ordering the sequence of MMIO to the tx send mailbox. The symptom
  3195. * is bogus tx completions. We try to recover by setting the
  3196. * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
  3197. * in the workqueue.
  3198. */
  3199. static void tg3_tx_recover(struct tg3 *tp)
  3200. {
  3201. BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
  3202. tp->write32_tx_mbox == tg3_write_indirect_mbox);
  3203. printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
  3204. "mapped I/O cycles to the network device, attempting to "
  3205. "recover. Please report the problem to the driver maintainer "
  3206. "and include system chipset information.\n", tp->dev->name);
  3207. spin_lock(&tp->lock);
  3208. tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
  3209. spin_unlock(&tp->lock);
  3210. }
  3211. static inline u32 tg3_tx_avail(struct tg3 *tp)
  3212. {
  3213. smp_mb();
  3214. return (tp->tx_pending -
  3215. ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
  3216. }
  3217. /* Tigon3 never reports partial packet sends. So we do not
  3218. * need special logic to handle SKBs that have not had all
  3219. * of their frags sent yet, like SunGEM does.
  3220. */
  3221. static void tg3_tx(struct tg3 *tp)
  3222. {
  3223. u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
  3224. u32 sw_idx = tp->tx_cons;
  3225. while (sw_idx != hw_idx) {
  3226. struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
  3227. struct sk_buff *skb = ri->skb;
  3228. int i, tx_bug = 0;
  3229. if (unlikely(skb == NULL)) {
  3230. tg3_tx_recover(tp);
  3231. return;
  3232. }
  3233. pci_unmap_single(tp->pdev,
  3234. pci_unmap_addr(ri, mapping),
  3235. skb_headlen(skb),
  3236. PCI_DMA_TODEVICE);
  3237. ri->skb = NULL;
  3238. sw_idx = NEXT_TX(sw_idx);
  3239. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  3240. ri = &tp->tx_buffers[sw_idx];
  3241. if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
  3242. tx_bug = 1;
  3243. pci_unmap_page(tp->pdev,
  3244. pci_unmap_addr(ri, mapping),
  3245. skb_shinfo(skb)->frags[i].size,
  3246. PCI_DMA_TODEVICE);
  3247. sw_idx = NEXT_TX(sw_idx);
  3248. }
  3249. dev_kfree_skb(skb);
  3250. if (unlikely(tx_bug)) {
  3251. tg3_tx_recover(tp);
  3252. return;
  3253. }
  3254. }
  3255. tp->tx_cons = sw_idx;
  3256. /* Need to make the tx_cons update visible to tg3_start_xmit()
  3257. * before checking for netif_queue_stopped(). Without the
  3258. * memory barrier, there is a small possibility that tg3_start_xmit()
  3259. * will miss it and cause the queue to be stopped forever.
  3260. */
  3261. smp_mb();
  3262. if (unlikely(netif_queue_stopped(tp->dev) &&
  3263. (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
  3264. netif_tx_lock(tp->dev);
  3265. if (netif_queue_stopped(tp->dev) &&
  3266. (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
  3267. netif_wake_queue(tp->dev);
  3268. netif_tx_unlock(tp->dev);
  3269. }
  3270. }
  3271. /* Returns size of skb allocated or < 0 on error.
  3272. *
  3273. * We only need to fill in the address because the other members
  3274. * of the RX descriptor are invariant, see tg3_init_rings.
  3275. *
  3276. * Note the purposeful assymetry of cpu vs. chip accesses. For
  3277. * posting buffers we only dirty the first cache line of the RX
  3278. * descriptor (containing the address). Whereas for the RX status
  3279. * buffers the cpu only reads the last cacheline of the RX descriptor
  3280. * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  3281. */
  3282. static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
  3283. int src_idx, u32 dest_idx_unmasked)
  3284. {
  3285. struct tg3_rx_buffer_desc *desc;
  3286. struct ring_info *map, *src_map;
  3287. struct sk_buff *skb;
  3288. dma_addr_t mapping;
  3289. int skb_size, dest_idx;
  3290. src_map = NULL;
  3291. switch (opaque_key) {
  3292. case RXD_OPAQUE_RING_STD:
  3293. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  3294. desc = &tp->rx_std[dest_idx];
  3295. map = &tp->rx_std_buffers[dest_idx];
  3296. if (src_idx >= 0)
  3297. src_map = &tp->rx_std_buffers[src_idx];
  3298. skb_size = tp->rx_pkt_buf_sz;
  3299. break;
  3300. case RXD_OPAQUE_RING_JUMBO:
  3301. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  3302. desc = &tp->rx_jumbo[dest_idx];
  3303. map = &tp->rx_jumbo_buffers[dest_idx];
  3304. if (src_idx >= 0)
  3305. src_map = &tp->rx_jumbo_buffers[src_idx];
  3306. skb_size = RX_JUMBO_PKT_BUF_SZ;
  3307. break;
  3308. default:
  3309. return -EINVAL;
  3310. }
  3311. /* Do not overwrite any of the map or rp information
  3312. * until we are sure we can commit to a new buffer.
  3313. *
  3314. * Callers depend upon this behavior and assume that
  3315. * we leave everything unchanged if we fail.
  3316. */
  3317. skb = netdev_alloc_skb(tp->dev, skb_size);
  3318. if (skb == NULL)
  3319. return -ENOMEM;
  3320. skb_reserve(skb, tp->rx_offset);
  3321. mapping = pci_map_single(tp->pdev, skb->data,
  3322. skb_size - tp->rx_offset,
  3323. PCI_DMA_FROMDEVICE);
  3324. map->skb = skb;
  3325. pci_unmap_addr_set(map, mapping, mapping);
  3326. if (src_map != NULL)
  3327. src_map->skb = NULL;
  3328. desc->addr_hi = ((u64)mapping >> 32);
  3329. desc->addr_lo = ((u64)mapping & 0xffffffff);
  3330. return skb_size;
  3331. }
  3332. /* We only need to move over in the address because the other
  3333. * members of the RX descriptor are invariant. See notes above
  3334. * tg3_alloc_rx_skb for full details.
  3335. */
  3336. static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
  3337. int src_idx, u32 dest_idx_unmasked)
  3338. {
  3339. struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  3340. struct ring_info *src_map, *dest_map;
  3341. int dest_idx;
  3342. switch (opaque_key) {
  3343. case RXD_OPAQUE_RING_STD:
  3344. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  3345. dest_desc = &tp->rx_std[dest_idx];
  3346. dest_map = &tp->rx_std_buffers[dest_idx];
  3347. src_desc = &tp->rx_std[src_idx];
  3348. src_map = &tp->rx_std_buffers[src_idx];
  3349. break;
  3350. case RXD_OPAQUE_RING_JUMBO:
  3351. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  3352. dest_desc = &tp->rx_jumbo[dest_idx];
  3353. dest_map = &tp->rx_jumbo_buffers[dest_idx];
  3354. src_desc = &tp->rx_jumbo[src_idx];
  3355. src_map = &tp->rx_jumbo_buffers[src_idx];
  3356. break;
  3357. default:
  3358. return;
  3359. }
  3360. dest_map->skb = src_map->skb;
  3361. pci_unmap_addr_set(dest_map, mapping,
  3362. pci_unmap_addr(src_map, mapping));
  3363. dest_desc->addr_hi = src_desc->addr_hi;
  3364. dest_desc->addr_lo = src_desc->addr_lo;
  3365. src_map->skb = NULL;
  3366. }
  3367. #if TG3_VLAN_TAG_USED
  3368. static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
  3369. {
  3370. return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
  3371. }
  3372. #endif
  3373. /* The RX ring scheme is composed of multiple rings which post fresh
  3374. * buffers to the chip, and one special ring the chip uses to report
  3375. * status back to the host.
  3376. *
  3377. * The special ring reports the status of received packets to the
  3378. * host. The chip does not write into the original descriptor the
  3379. * RX buffer was obtained from. The chip simply takes the original
  3380. * descriptor as provided by the host, updates the status and length
  3381. * field, then writes this into the next status ring entry.
  3382. *
  3383. * Each ring the host uses to post buffers to the chip is described
  3384. * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
  3385. * it is first placed into the on-chip ram. When the packet's length
  3386. * is known, it walks down the TG3_BDINFO entries to select the ring.
  3387. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  3388. * which is within the range of the new packet's length is chosen.
  3389. *
  3390. * The "separate ring for rx status" scheme may sound queer, but it makes
  3391. * sense from a cache coherency perspective. If only the host writes
  3392. * to the buffer post rings, and only the chip writes to the rx status
  3393. * rings, then cache lines never move beyond shared-modified state.
  3394. * If both the host and chip were to write into the same ring, cache line
  3395. * eviction could occur since both entities want it in an exclusive state.
  3396. */
  3397. static int tg3_rx(struct tg3 *tp, int budget)
  3398. {
  3399. u32 work_mask, rx_std_posted = 0;
  3400. u32 sw_idx = tp->rx_rcb_ptr;
  3401. u16 hw_idx;
  3402. int received;
  3403. hw_idx = tp->hw_status->idx[0].rx_producer;
  3404. /*
  3405. * We need to order the read of hw_idx and the read of
  3406. * the opaque cookie.
  3407. */
  3408. rmb();
  3409. work_mask = 0;
  3410. received = 0;
  3411. while (sw_idx != hw_idx && budget > 0) {
  3412. struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
  3413. unsigned int len;
  3414. struct sk_buff *skb;
  3415. dma_addr_t dma_addr;
  3416. u32 opaque_key, desc_idx, *post_ptr;
  3417. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  3418. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  3419. if (opaque_key == RXD_OPAQUE_RING_STD) {
  3420. dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
  3421. mapping);
  3422. skb = tp->rx_std_buffers[desc_idx].skb;
  3423. post_ptr = &tp->rx_std_ptr;
  3424. rx_std_posted++;
  3425. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  3426. dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
  3427. mapping);
  3428. skb = tp->rx_jumbo_buffers[desc_idx].skb;
  3429. post_ptr = &tp->rx_jumbo_ptr;
  3430. }
  3431. else {
  3432. goto next_pkt_nopost;
  3433. }
  3434. work_mask |= opaque_key;
  3435. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  3436. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  3437. drop_it:
  3438. tg3_recycle_rx(tp, opaque_key,
  3439. desc_idx, *post_ptr);
  3440. drop_it_no_recycle:
  3441. /* Other statistics kept track of by card. */
  3442. tp->net_stats.rx_dropped++;
  3443. goto next_pkt;
  3444. }
  3445. len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
  3446. if (len > RX_COPY_THRESHOLD
  3447. && tp->rx_offset == 2
  3448. /* rx_offset != 2 iff this is a 5701 card running
  3449. * in PCI-X mode [see tg3_get_invariants()] */
  3450. ) {
  3451. int skb_size;
  3452. skb_size = tg3_alloc_rx_skb(tp, opaque_key,
  3453. desc_idx, *post_ptr);
  3454. if (skb_size < 0)
  3455. goto drop_it;
  3456. pci_unmap_single(tp->pdev, dma_addr,
  3457. skb_size - tp->rx_offset,
  3458. PCI_DMA_FROMDEVICE);
  3459. skb_put(skb, len);
  3460. } else {
  3461. struct sk_buff *copy_skb;
  3462. tg3_recycle_rx(tp, opaque_key,
  3463. desc_idx, *post_ptr);
  3464. copy_skb = netdev_alloc_skb(tp->dev, len + 2);
  3465. if (copy_skb == NULL)
  3466. goto drop_it_no_recycle;
  3467. skb_reserve(copy_skb, 2);
  3468. skb_put(copy_skb, len);
  3469. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  3470. skb_copy_from_linear_data(skb, copy_skb->data, len);
  3471. pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  3472. /* We'll reuse the original ring buffer. */
  3473. skb = copy_skb;
  3474. }
  3475. if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
  3476. (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  3477. (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  3478. >> RXD_TCPCSUM_SHIFT) == 0xffff))
  3479. skb->ip_summed = CHECKSUM_UNNECESSARY;
  3480. else
  3481. skb->ip_summed = CHECKSUM_NONE;
  3482. skb->protocol = eth_type_trans(skb, tp->dev);
  3483. #if TG3_VLAN_TAG_USED
  3484. if (tp->vlgrp != NULL &&
  3485. desc->type_flags & RXD_FLAG_VLAN) {
  3486. tg3_vlan_rx(tp, skb,
  3487. desc->err_vlan & RXD_VLAN_MASK);
  3488. } else
  3489. #endif
  3490. netif_receive_skb(skb);
  3491. tp->dev->last_rx = jiffies;
  3492. received++;
  3493. budget--;
  3494. next_pkt:
  3495. (*post_ptr)++;
  3496. if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
  3497. u32 idx = *post_ptr % TG3_RX_RING_SIZE;
  3498. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
  3499. TG3_64BIT_REG_LOW, idx);
  3500. work_mask &= ~RXD_OPAQUE_RING_STD;
  3501. rx_std_posted = 0;
  3502. }
  3503. next_pkt_nopost:
  3504. sw_idx++;
  3505. sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
  3506. /* Refresh hw_idx to see if there is new work */
  3507. if (sw_idx == hw_idx) {
  3508. hw_idx = tp->hw_status->idx[0].rx_producer;
  3509. rmb();
  3510. }
  3511. }
  3512. /* ACK the status ring. */
  3513. tp->rx_rcb_ptr = sw_idx;
  3514. tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
  3515. /* Refill RX ring(s). */
  3516. if (work_mask & RXD_OPAQUE_RING_STD) {
  3517. sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
  3518. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  3519. sw_idx);
  3520. }
  3521. if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  3522. sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
  3523. tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  3524. sw_idx);
  3525. }
  3526. mmiowb();
  3527. return received;
  3528. }
  3529. static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
  3530. {
  3531. struct tg3_hw_status *sblk = tp->hw_status;
  3532. /* handle link change and other phy events */
  3533. if (!(tp->tg3_flags &
  3534. (TG3_FLAG_USE_LINKCHG_REG |
  3535. TG3_FLAG_POLL_SERDES))) {
  3536. if (sblk->status & SD_STATUS_LINK_CHG) {
  3537. sblk->status = SD_STATUS_UPDATED |
  3538. (sblk->status & ~SD_STATUS_LINK_CHG);
  3539. spin_lock(&tp->lock);
  3540. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  3541. tw32_f(MAC_STATUS,
  3542. (MAC_STATUS_SYNC_CHANGED |
  3543. MAC_STATUS_CFG_CHANGED |
  3544. MAC_STATUS_MI_COMPLETION |
  3545. MAC_STATUS_LNKSTATE_CHANGED));
  3546. udelay(40);
  3547. } else
  3548. tg3_setup_phy(tp, 0);
  3549. spin_unlock(&tp->lock);
  3550. }
  3551. }
  3552. /* run TX completion thread */
  3553. if (sblk->idx[0].tx_consumer != tp->tx_cons) {
  3554. tg3_tx(tp);
  3555. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
  3556. return work_done;
  3557. }
  3558. /* run RX thread, within the bounds set by NAPI.
  3559. * All RX "locking" is done by ensuring outside
  3560. * code synchronizes with tg3->napi.poll()
  3561. */
  3562. if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
  3563. work_done += tg3_rx(tp, budget - work_done);
  3564. return work_done;
  3565. }
  3566. static int tg3_poll(struct napi_struct *napi, int budget)
  3567. {
  3568. struct tg3 *tp = container_of(napi, struct tg3, napi);
  3569. int work_done = 0;
  3570. struct tg3_hw_status *sblk = tp->hw_status;
  3571. while (1) {
  3572. work_done = tg3_poll_work(tp, work_done, budget);
  3573. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
  3574. goto tx_recovery;
  3575. if (unlikely(work_done >= budget))
  3576. break;
  3577. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  3578. /* tp->last_tag is used in tg3_restart_ints() below
  3579. * to tell the hw how much work has been processed,
  3580. * so we must read it before checking for more work.
  3581. */
  3582. tp->last_tag = sblk->status_tag;
  3583. rmb();
  3584. } else
  3585. sblk->status &= ~SD_STATUS_UPDATED;
  3586. if (likely(!tg3_has_work(tp))) {
  3587. netif_rx_complete(tp->dev, napi);
  3588. tg3_restart_ints(tp);
  3589. break;
  3590. }
  3591. }
  3592. return work_done;
  3593. tx_recovery:
  3594. /* work_done is guaranteed to be less than budget. */
  3595. netif_rx_complete(tp->dev, napi);
  3596. schedule_work(&tp->reset_task);
  3597. return work_done;
  3598. }
  3599. static void tg3_irq_quiesce(struct tg3 *tp)
  3600. {
  3601. BUG_ON(tp->irq_sync);
  3602. tp->irq_sync = 1;
  3603. smp_mb();
  3604. synchronize_irq(tp->pdev->irq);
  3605. }
  3606. static inline int tg3_irq_sync(struct tg3 *tp)
  3607. {
  3608. return tp->irq_sync;
  3609. }
  3610. /* Fully shutdown all tg3 driver activity elsewhere in the system.
  3611. * If irq_sync is non-zero, then the IRQ handler must be synchronized
  3612. * with as well. Most of the time, this is not necessary except when
  3613. * shutting down the device.
  3614. */
  3615. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
  3616. {
  3617. spin_lock_bh(&tp->lock);
  3618. if (irq_sync)
  3619. tg3_irq_quiesce(tp);
  3620. }
  3621. static inline void tg3_full_unlock(struct tg3 *tp)
  3622. {
  3623. spin_unlock_bh(&tp->lock);
  3624. }
  3625. /* One-shot MSI handler - Chip automatically disables interrupt
  3626. * after sending MSI so driver doesn't have to do it.
  3627. */
  3628. static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
  3629. {
  3630. struct net_device *dev = dev_id;
  3631. struct tg3 *tp = netdev_priv(dev);
  3632. prefetch(tp->hw_status);
  3633. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3634. if (likely(!tg3_irq_sync(tp)))
  3635. netif_rx_schedule(dev, &tp->napi);
  3636. return IRQ_HANDLED;
  3637. }
  3638. /* MSI ISR - No need to check for interrupt sharing and no need to
  3639. * flush status block and interrupt mailbox. PCI ordering rules
  3640. * guarantee that MSI will arrive after the status block.
  3641. */
  3642. static irqreturn_t tg3_msi(int irq, void *dev_id)
  3643. {
  3644. struct net_device *dev = dev_id;
  3645. struct tg3 *tp = netdev_priv(dev);
  3646. prefetch(tp->hw_status);
  3647. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3648. /*
  3649. * Writing any value to intr-mbox-0 clears PCI INTA# and
  3650. * chip-internal interrupt pending events.
  3651. * Writing non-zero to intr-mbox-0 additional tells the
  3652. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3653. * event coalescing.
  3654. */
  3655. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3656. if (likely(!tg3_irq_sync(tp)))
  3657. netif_rx_schedule(dev, &tp->napi);
  3658. return IRQ_RETVAL(1);
  3659. }
  3660. static irqreturn_t tg3_interrupt(int irq, void *dev_id)
  3661. {
  3662. struct net_device *dev = dev_id;
  3663. struct tg3 *tp = netdev_priv(dev);
  3664. struct tg3_hw_status *sblk = tp->hw_status;
  3665. unsigned int handled = 1;
  3666. /* In INTx mode, it is possible for the interrupt to arrive at
  3667. * the CPU before the status block posted prior to the interrupt.
  3668. * Reading the PCI State register will confirm whether the
  3669. * interrupt is ours and will flush the status block.
  3670. */
  3671. if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
  3672. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  3673. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3674. handled = 0;
  3675. goto out;
  3676. }
  3677. }
  3678. /*
  3679. * Writing any value to intr-mbox-0 clears PCI INTA# and
  3680. * chip-internal interrupt pending events.
  3681. * Writing non-zero to intr-mbox-0 additional tells the
  3682. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3683. * event coalescing.
  3684. *
  3685. * Flush the mailbox to de-assert the IRQ immediately to prevent
  3686. * spurious interrupts. The flush impacts performance but
  3687. * excessive spurious interrupts can be worse in some cases.
  3688. */
  3689. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3690. if (tg3_irq_sync(tp))
  3691. goto out;
  3692. sblk->status &= ~SD_STATUS_UPDATED;
  3693. if (likely(tg3_has_work(tp))) {
  3694. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3695. netif_rx_schedule(dev, &tp->napi);
  3696. } else {
  3697. /* No work, shared interrupt perhaps? re-enable
  3698. * interrupts, and flush that PCI write
  3699. */
  3700. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  3701. 0x00000000);
  3702. }
  3703. out:
  3704. return IRQ_RETVAL(handled);
  3705. }
  3706. static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
  3707. {
  3708. struct net_device *dev = dev_id;
  3709. struct tg3 *tp = netdev_priv(dev);
  3710. struct tg3_hw_status *sblk = tp->hw_status;
  3711. unsigned int handled = 1;
  3712. /* In INTx mode, it is possible for the interrupt to arrive at
  3713. * the CPU before the status block posted prior to the interrupt.
  3714. * Reading the PCI State register will confirm whether the
  3715. * interrupt is ours and will flush the status block.
  3716. */
  3717. if (unlikely(sblk->status_tag == tp->last_tag)) {
  3718. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  3719. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3720. handled = 0;
  3721. goto out;
  3722. }
  3723. }
  3724. /*
  3725. * writing any value to intr-mbox-0 clears PCI INTA# and
  3726. * chip-internal interrupt pending events.
  3727. * writing non-zero to intr-mbox-0 additional tells the
  3728. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3729. * event coalescing.
  3730. *
  3731. * Flush the mailbox to de-assert the IRQ immediately to prevent
  3732. * spurious interrupts. The flush impacts performance but
  3733. * excessive spurious interrupts can be worse in some cases.
  3734. */
  3735. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3736. if (tg3_irq_sync(tp))
  3737. goto out;
  3738. if (netif_rx_schedule_prep(dev, &tp->napi)) {
  3739. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3740. /* Update last_tag to mark that this status has been
  3741. * seen. Because interrupt may be shared, we may be
  3742. * racing with tg3_poll(), so only update last_tag
  3743. * if tg3_poll() is not scheduled.
  3744. */
  3745. tp->last_tag = sblk->status_tag;
  3746. __netif_rx_schedule(dev, &tp->napi);
  3747. }
  3748. out:
  3749. return IRQ_RETVAL(handled);
  3750. }
  3751. /* ISR for interrupt test */
  3752. static irqreturn_t tg3_test_isr(int irq, void *dev_id)
  3753. {
  3754. struct net_device *dev = dev_id;
  3755. struct tg3 *tp = netdev_priv(dev);
  3756. struct tg3_hw_status *sblk = tp->hw_status;
  3757. if ((sblk->status & SD_STATUS_UPDATED) ||
  3758. !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3759. tg3_disable_ints(tp);
  3760. return IRQ_RETVAL(1);
  3761. }
  3762. return IRQ_RETVAL(0);
  3763. }
  3764. static int tg3_init_hw(struct tg3 *, int);
  3765. static int tg3_halt(struct tg3 *, int, int);
  3766. /* Restart hardware after configuration changes, self-test, etc.
  3767. * Invoked with tp->lock held.
  3768. */
  3769. static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
  3770. __releases(tp->lock)
  3771. __acquires(tp->lock)
  3772. {
  3773. int err;
  3774. err = tg3_init_hw(tp, reset_phy);
  3775. if (err) {
  3776. printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
  3777. "aborting.\n", tp->dev->name);
  3778. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  3779. tg3_full_unlock(tp);
  3780. del_timer_sync(&tp->timer);
  3781. tp->irq_sync = 0;
  3782. napi_enable(&tp->napi);
  3783. dev_close(tp->dev);
  3784. tg3_full_lock(tp, 0);
  3785. }
  3786. return err;
  3787. }
  3788. #ifdef CONFIG_NET_POLL_CONTROLLER
  3789. static void tg3_poll_controller(struct net_device *dev)
  3790. {
  3791. struct tg3 *tp = netdev_priv(dev);
  3792. tg3_interrupt(tp->pdev->irq, dev);
  3793. }
  3794. #endif
  3795. static void tg3_reset_task(struct work_struct *work)
  3796. {
  3797. struct tg3 *tp = container_of(work, struct tg3, reset_task);
  3798. int err;
  3799. unsigned int restart_timer;
  3800. tg3_full_lock(tp, 0);
  3801. if (!netif_running(tp->dev)) {
  3802. tg3_full_unlock(tp);
  3803. return;
  3804. }
  3805. tg3_full_unlock(tp);
  3806. tg3_phy_stop(tp);
  3807. tg3_netif_stop(tp);
  3808. tg3_full_lock(tp, 1);
  3809. restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
  3810. tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
  3811. if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
  3812. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  3813. tp->write32_rx_mbox = tg3_write_flush_reg32;
  3814. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  3815. tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
  3816. }
  3817. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  3818. err = tg3_init_hw(tp, 1);
  3819. if (err)
  3820. goto out;
  3821. tg3_netif_start(tp);
  3822. if (restart_timer)
  3823. mod_timer(&tp->timer, jiffies + 1);
  3824. out:
  3825. tg3_full_unlock(tp);
  3826. if (!err)
  3827. tg3_phy_start(tp);
  3828. }
  3829. static void tg3_dump_short_state(struct tg3 *tp)
  3830. {
  3831. printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
  3832. tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
  3833. printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
  3834. tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
  3835. }
  3836. static void tg3_tx_timeout(struct net_device *dev)
  3837. {
  3838. struct tg3 *tp = netdev_priv(dev);
  3839. if (netif_msg_tx_err(tp)) {
  3840. printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
  3841. dev->name);
  3842. tg3_dump_short_state(tp);
  3843. }
  3844. schedule_work(&tp->reset_task);
  3845. }
  3846. /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
  3847. static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  3848. {
  3849. u32 base = (u32) mapping & 0xffffffff;
  3850. return ((base > 0xffffdcc0) &&
  3851. (base + len + 8 < base));
  3852. }
  3853. /* Test for DMA addresses > 40-bit */
  3854. static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  3855. int len)
  3856. {
  3857. #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
  3858. if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
  3859. return (((u64) mapping + len) > DMA_40BIT_MASK);
  3860. return 0;
  3861. #else
  3862. return 0;
  3863. #endif
  3864. }
  3865. static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
  3866. /* Workaround 4GB and 40-bit hardware DMA bugs. */
  3867. static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
  3868. u32 last_plus_one, u32 *start,
  3869. u32 base_flags, u32 mss)
  3870. {
  3871. struct sk_buff *new_skb;
  3872. dma_addr_t new_addr = 0;
  3873. u32 entry = *start;
  3874. int i, ret = 0;
  3875. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  3876. new_skb = skb_copy(skb, GFP_ATOMIC);
  3877. else {
  3878. int more_headroom = 4 - ((unsigned long)skb->data & 3);
  3879. new_skb = skb_copy_expand(skb,
  3880. skb_headroom(skb) + more_headroom,
  3881. skb_tailroom(skb), GFP_ATOMIC);
  3882. }
  3883. if (!new_skb) {
  3884. ret = -1;
  3885. } else {
  3886. /* New SKB is guaranteed to be linear. */
  3887. entry = *start;
  3888. new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  3889. PCI_DMA_TODEVICE);
  3890. /* Make sure new skb does not cross any 4G boundaries.
  3891. * Drop the packet if it does.
  3892. */
  3893. if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
  3894. ret = -1;
  3895. dev_kfree_skb(new_skb);
  3896. new_skb = NULL;
  3897. } else {
  3898. tg3_set_txd(tp, entry, new_addr, new_skb->len,
  3899. base_flags, 1 | (mss << 1));
  3900. *start = NEXT_TX(entry);
  3901. }
  3902. }
  3903. /* Now clean up the sw ring entries. */
  3904. i = 0;
  3905. while (entry != last_plus_one) {
  3906. int len;
  3907. if (i == 0)
  3908. len = skb_headlen(skb);
  3909. else
  3910. len = skb_shinfo(skb)->frags[i-1].size;
  3911. pci_unmap_single(tp->pdev,
  3912. pci_unmap_addr(&tp->tx_buffers[entry], mapping),
  3913. len, PCI_DMA_TODEVICE);
  3914. if (i == 0) {
  3915. tp->tx_buffers[entry].skb = new_skb;
  3916. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
  3917. } else {
  3918. tp->tx_buffers[entry].skb = NULL;
  3919. }
  3920. entry = NEXT_TX(entry);
  3921. i++;
  3922. }
  3923. dev_kfree_skb(skb);
  3924. return ret;
  3925. }
  3926. static void tg3_set_txd(struct tg3 *tp, int entry,
  3927. dma_addr_t mapping, int len, u32 flags,
  3928. u32 mss_and_is_end)
  3929. {
  3930. struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
  3931. int is_end = (mss_and_is_end & 0x1);
  3932. u32 mss = (mss_and_is_end >> 1);
  3933. u32 vlan_tag = 0;
  3934. if (is_end)
  3935. flags |= TXD_FLAG_END;
  3936. if (flags & TXD_FLAG_VLAN) {
  3937. vlan_tag = flags >> 16;
  3938. flags &= 0xffff;
  3939. }
  3940. vlan_tag |= (mss << TXD_MSS_SHIFT);
  3941. txd->addr_hi = ((u64) mapping >> 32);
  3942. txd->addr_lo = ((u64) mapping & 0xffffffff);
  3943. txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
  3944. txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
  3945. }
  3946. /* hard_start_xmit for devices that don't have any bugs and
  3947. * support TG3_FLG2_HW_TSO_2 only.
  3948. */
  3949. static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  3950. {
  3951. struct tg3 *tp = netdev_priv(dev);
  3952. dma_addr_t mapping;
  3953. u32 len, entry, base_flags, mss;
  3954. len = skb_headlen(skb);
  3955. /* We are running in BH disabled context with netif_tx_lock
  3956. * and TX reclaim runs via tp->napi.poll inside of a software
  3957. * interrupt. Furthermore, IRQ processing runs lockless so we have
  3958. * no IRQ context deadlocks to worry about either. Rejoice!
  3959. */
  3960. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  3961. if (!netif_queue_stopped(dev)) {
  3962. netif_stop_queue(dev);
  3963. /* This is a hard error, log it. */
  3964. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  3965. "queue awake!\n", dev->name);
  3966. }
  3967. return NETDEV_TX_BUSY;
  3968. }
  3969. entry = tp->tx_prod;
  3970. base_flags = 0;
  3971. mss = 0;
  3972. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  3973. int tcp_opt_len, ip_tcp_len;
  3974. if (skb_header_cloned(skb) &&
  3975. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  3976. dev_kfree_skb(skb);
  3977. goto out_unlock;
  3978. }
  3979. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  3980. mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
  3981. else {
  3982. struct iphdr *iph = ip_hdr(skb);
  3983. tcp_opt_len = tcp_optlen(skb);
  3984. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  3985. iph->check = 0;
  3986. iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
  3987. mss |= (ip_tcp_len + tcp_opt_len) << 9;
  3988. }
  3989. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  3990. TXD_FLAG_CPU_POST_DMA);
  3991. tcp_hdr(skb)->check = 0;
  3992. }
  3993. else if (skb->ip_summed == CHECKSUM_PARTIAL)
  3994. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  3995. #if TG3_VLAN_TAG_USED
  3996. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  3997. base_flags |= (TXD_FLAG_VLAN |
  3998. (vlan_tx_tag_get(skb) << 16));
  3999. #endif
  4000. /* Queue skb data, a.k.a. the main skb fragment. */
  4001. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  4002. tp->tx_buffers[entry].skb = skb;
  4003. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  4004. tg3_set_txd(tp, entry, mapping, len, base_flags,
  4005. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  4006. entry = NEXT_TX(entry);
  4007. /* Now loop through additional data fragments, and queue them. */
  4008. if (skb_shinfo(skb)->nr_frags > 0) {
  4009. unsigned int i, last;
  4010. last = skb_shinfo(skb)->nr_frags - 1;
  4011. for (i = 0; i <= last; i++) {
  4012. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  4013. len = frag->size;
  4014. mapping = pci_map_page(tp->pdev,
  4015. frag->page,
  4016. frag->page_offset,
  4017. len, PCI_DMA_TODEVICE);
  4018. tp->tx_buffers[entry].skb = NULL;
  4019. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  4020. tg3_set_txd(tp, entry, mapping, len,
  4021. base_flags, (i == last) | (mss << 1));
  4022. entry = NEXT_TX(entry);
  4023. }
  4024. }
  4025. /* Packets are ready, update Tx producer idx local and on card. */
  4026. tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
  4027. tp->tx_prod = entry;
  4028. if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
  4029. netif_stop_queue(dev);
  4030. if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
  4031. netif_wake_queue(tp->dev);
  4032. }
  4033. out_unlock:
  4034. mmiowb();
  4035. dev->trans_start = jiffies;
  4036. return NETDEV_TX_OK;
  4037. }
  4038. static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
  4039. /* Use GSO to workaround a rare TSO bug that may be triggered when the
  4040. * TSO header is greater than 80 bytes.
  4041. */
  4042. static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
  4043. {
  4044. struct sk_buff *segs, *nskb;
  4045. /* Estimate the number of fragments in the worst case */
  4046. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
  4047. netif_stop_queue(tp->dev);
  4048. if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
  4049. return NETDEV_TX_BUSY;
  4050. netif_wake_queue(tp->dev);
  4051. }
  4052. segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
  4053. if (IS_ERR(segs))
  4054. goto tg3_tso_bug_end;
  4055. do {
  4056. nskb = segs;
  4057. segs = segs->next;
  4058. nskb->next = NULL;
  4059. tg3_start_xmit_dma_bug(nskb, tp->dev);
  4060. } while (segs);
  4061. tg3_tso_bug_end:
  4062. dev_kfree_skb(skb);
  4063. return NETDEV_TX_OK;
  4064. }
  4065. /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
  4066. * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
  4067. */
  4068. static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
  4069. {
  4070. struct tg3 *tp = netdev_priv(dev);
  4071. dma_addr_t mapping;
  4072. u32 len, entry, base_flags, mss;
  4073. int would_hit_hwbug;
  4074. len = skb_headlen(skb);
  4075. /* We are running in BH disabled context with netif_tx_lock
  4076. * and TX reclaim runs via tp->napi.poll inside of a software
  4077. * interrupt. Furthermore, IRQ processing runs lockless so we have
  4078. * no IRQ context deadlocks to worry about either. Rejoice!
  4079. */
  4080. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  4081. if (!netif_queue_stopped(dev)) {
  4082. netif_stop_queue(dev);
  4083. /* This is a hard error, log it. */
  4084. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  4085. "queue awake!\n", dev->name);
  4086. }
  4087. return NETDEV_TX_BUSY;
  4088. }
  4089. entry = tp->tx_prod;
  4090. base_flags = 0;
  4091. if (skb->ip_summed == CHECKSUM_PARTIAL)
  4092. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  4093. mss = 0;
  4094. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  4095. struct iphdr *iph;
  4096. int tcp_opt_len, ip_tcp_len, hdr_len;
  4097. if (skb_header_cloned(skb) &&
  4098. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  4099. dev_kfree_skb(skb);
  4100. goto out_unlock;
  4101. }
  4102. tcp_opt_len = tcp_optlen(skb);
  4103. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  4104. hdr_len = ip_tcp_len + tcp_opt_len;
  4105. if (unlikely((ETH_HLEN + hdr_len) > 80) &&
  4106. (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
  4107. return (tg3_tso_bug(tp, skb));
  4108. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  4109. TXD_FLAG_CPU_POST_DMA);
  4110. iph = ip_hdr(skb);
  4111. iph->check = 0;
  4112. iph->tot_len = htons(mss + hdr_len);
  4113. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  4114. tcp_hdr(skb)->check = 0;
  4115. base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
  4116. } else
  4117. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  4118. iph->daddr, 0,
  4119. IPPROTO_TCP,
  4120. 0);
  4121. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
  4122. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
  4123. if (tcp_opt_len || iph->ihl > 5) {
  4124. int tsflags;
  4125. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  4126. mss |= (tsflags << 11);
  4127. }
  4128. } else {
  4129. if (tcp_opt_len || iph->ihl > 5) {
  4130. int tsflags;
  4131. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  4132. base_flags |= tsflags << 12;
  4133. }
  4134. }
  4135. }
  4136. #if TG3_VLAN_TAG_USED
  4137. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  4138. base_flags |= (TXD_FLAG_VLAN |
  4139. (vlan_tx_tag_get(skb) << 16));
  4140. #endif
  4141. /* Queue skb data, a.k.a. the main skb fragment. */
  4142. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  4143. tp->tx_buffers[entry].skb = skb;
  4144. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  4145. would_hit_hwbug = 0;
  4146. if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
  4147. would_hit_hwbug = 1;
  4148. else if (tg3_4g_overflow_test(mapping, len))
  4149. would_hit_hwbug = 1;
  4150. tg3_set_txd(tp, entry, mapping, len, base_flags,
  4151. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  4152. entry = NEXT_TX(entry);
  4153. /* Now loop through additional data fragments, and queue them. */
  4154. if (skb_shinfo(skb)->nr_frags > 0) {
  4155. unsigned int i, last;
  4156. last = skb_shinfo(skb)->nr_frags - 1;
  4157. for (i = 0; i <= last; i++) {
  4158. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  4159. len = frag->size;
  4160. mapping = pci_map_page(tp->pdev,
  4161. frag->page,
  4162. frag->page_offset,
  4163. len, PCI_DMA_TODEVICE);
  4164. tp->tx_buffers[entry].skb = NULL;
  4165. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  4166. if (tg3_4g_overflow_test(mapping, len))
  4167. would_hit_hwbug = 1;
  4168. if (tg3_40bit_overflow_test(tp, mapping, len))
  4169. would_hit_hwbug = 1;
  4170. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  4171. tg3_set_txd(tp, entry, mapping, len,
  4172. base_flags, (i == last)|(mss << 1));
  4173. else
  4174. tg3_set_txd(tp, entry, mapping, len,
  4175. base_flags, (i == last));
  4176. entry = NEXT_TX(entry);
  4177. }
  4178. }
  4179. if (would_hit_hwbug) {
  4180. u32 last_plus_one = entry;
  4181. u32 start;
  4182. start = entry - 1 - skb_shinfo(skb)->nr_frags;
  4183. start &= (TG3_TX_RING_SIZE - 1);
  4184. /* If the workaround fails due to memory/mapping
  4185. * failure, silently drop this packet.
  4186. */
  4187. if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
  4188. &start, base_flags, mss))
  4189. goto out_unlock;
  4190. entry = start;
  4191. }
  4192. /* Packets are ready, update Tx producer idx local and on card. */
  4193. tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
  4194. tp->tx_prod = entry;
  4195. if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
  4196. netif_stop_queue(dev);
  4197. if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
  4198. netif_wake_queue(tp->dev);
  4199. }
  4200. out_unlock:
  4201. mmiowb();
  4202. dev->trans_start = jiffies;
  4203. return NETDEV_TX_OK;
  4204. }
  4205. static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  4206. int new_mtu)
  4207. {
  4208. dev->mtu = new_mtu;
  4209. if (new_mtu > ETH_DATA_LEN) {
  4210. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  4211. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  4212. ethtool_op_set_tso(dev, 0);
  4213. }
  4214. else
  4215. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  4216. } else {
  4217. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  4218. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  4219. tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
  4220. }
  4221. }
  4222. static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  4223. {
  4224. struct tg3 *tp = netdev_priv(dev);
  4225. int err;
  4226. if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  4227. return -EINVAL;
  4228. if (!netif_running(dev)) {
  4229. /* We'll just catch it later when the
  4230. * device is up'd.
  4231. */
  4232. tg3_set_mtu(dev, tp, new_mtu);
  4233. return 0;
  4234. }
  4235. tg3_phy_stop(tp);
  4236. tg3_netif_stop(tp);
  4237. tg3_full_lock(tp, 1);
  4238. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  4239. tg3_set_mtu(dev, tp, new_mtu);
  4240. err = tg3_restart_hw(tp, 0);
  4241. if (!err)
  4242. tg3_netif_start(tp);
  4243. tg3_full_unlock(tp);
  4244. if (!err)
  4245. tg3_phy_start(tp);
  4246. return err;
  4247. }
  4248. /* Free up pending packets in all rx/tx rings.
  4249. *
  4250. * The chip has been shut down and the driver detached from
  4251. * the networking, so no interrupts or new tx packets will
  4252. * end up in the driver. tp->{tx,}lock is not held and we are not
  4253. * in an interrupt context and thus may sleep.
  4254. */
  4255. static void tg3_free_rings(struct tg3 *tp)
  4256. {
  4257. struct ring_info *rxp;
  4258. int i;
  4259. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  4260. rxp = &tp->rx_std_buffers[i];
  4261. if (rxp->skb == NULL)
  4262. continue;
  4263. pci_unmap_single(tp->pdev,
  4264. pci_unmap_addr(rxp, mapping),
  4265. tp->rx_pkt_buf_sz - tp->rx_offset,
  4266. PCI_DMA_FROMDEVICE);
  4267. dev_kfree_skb_any(rxp->skb);
  4268. rxp->skb = NULL;
  4269. }
  4270. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  4271. rxp = &tp->rx_jumbo_buffers[i];
  4272. if (rxp->skb == NULL)
  4273. continue;
  4274. pci_unmap_single(tp->pdev,
  4275. pci_unmap_addr(rxp, mapping),
  4276. RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
  4277. PCI_DMA_FROMDEVICE);
  4278. dev_kfree_skb_any(rxp->skb);
  4279. rxp->skb = NULL;
  4280. }
  4281. for (i = 0; i < TG3_TX_RING_SIZE; ) {
  4282. struct tx_ring_info *txp;
  4283. struct sk_buff *skb;
  4284. int j;
  4285. txp = &tp->tx_buffers[i];
  4286. skb = txp->skb;
  4287. if (skb == NULL) {
  4288. i++;
  4289. continue;
  4290. }
  4291. pci_unmap_single(tp->pdev,
  4292. pci_unmap_addr(txp, mapping),
  4293. skb_headlen(skb),
  4294. PCI_DMA_TODEVICE);
  4295. txp->skb = NULL;
  4296. i++;
  4297. for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
  4298. txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
  4299. pci_unmap_page(tp->pdev,
  4300. pci_unmap_addr(txp, mapping),
  4301. skb_shinfo(skb)->frags[j].size,
  4302. PCI_DMA_TODEVICE);
  4303. i++;
  4304. }
  4305. dev_kfree_skb_any(skb);
  4306. }
  4307. }
  4308. /* Initialize tx/rx rings for packet processing.
  4309. *
  4310. * The chip has been shut down and the driver detached from
  4311. * the networking, so no interrupts or new tx packets will
  4312. * end up in the driver. tp->{tx,}lock are held and thus
  4313. * we may not sleep.
  4314. */
  4315. static int tg3_init_rings(struct tg3 *tp)
  4316. {
  4317. u32 i;
  4318. /* Free up all the SKBs. */
  4319. tg3_free_rings(tp);
  4320. /* Zero out all descriptors. */
  4321. memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
  4322. memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
  4323. memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  4324. memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
  4325. tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
  4326. if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
  4327. (tp->dev->mtu > ETH_DATA_LEN))
  4328. tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
  4329. /* Initialize invariants of the rings, we only set this
  4330. * stuff once. This works because the card does not
  4331. * write into the rx buffer posting rings.
  4332. */
  4333. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  4334. struct tg3_rx_buffer_desc *rxd;
  4335. rxd = &tp->rx_std[i];
  4336. rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
  4337. << RXD_LEN_SHIFT;
  4338. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  4339. rxd->opaque = (RXD_OPAQUE_RING_STD |
  4340. (i << RXD_OPAQUE_INDEX_SHIFT));
  4341. }
  4342. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  4343. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  4344. struct tg3_rx_buffer_desc *rxd;
  4345. rxd = &tp->rx_jumbo[i];
  4346. rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
  4347. << RXD_LEN_SHIFT;
  4348. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  4349. RXD_FLAG_JUMBO;
  4350. rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  4351. (i << RXD_OPAQUE_INDEX_SHIFT));
  4352. }
  4353. }
  4354. /* Now allocate fresh SKBs for each rx ring. */
  4355. for (i = 0; i < tp->rx_pending; i++) {
  4356. if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
  4357. printk(KERN_WARNING PFX
  4358. "%s: Using a smaller RX standard ring, "
  4359. "only %d out of %d buffers were allocated "
  4360. "successfully.\n",
  4361. tp->dev->name, i, tp->rx_pending);
  4362. if (i == 0)
  4363. return -ENOMEM;
  4364. tp->rx_pending = i;
  4365. break;
  4366. }
  4367. }
  4368. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  4369. for (i = 0; i < tp->rx_jumbo_pending; i++) {
  4370. if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
  4371. -1, i) < 0) {
  4372. printk(KERN_WARNING PFX
  4373. "%s: Using a smaller RX jumbo ring, "
  4374. "only %d out of %d buffers were "
  4375. "allocated successfully.\n",
  4376. tp->dev->name, i, tp->rx_jumbo_pending);
  4377. if (i == 0) {
  4378. tg3_free_rings(tp);
  4379. return -ENOMEM;
  4380. }
  4381. tp->rx_jumbo_pending = i;
  4382. break;
  4383. }
  4384. }
  4385. }
  4386. return 0;
  4387. }
  4388. /*
  4389. * Must not be invoked with interrupt sources disabled and
  4390. * the hardware shutdown down.
  4391. */
  4392. static void tg3_free_consistent(struct tg3 *tp)
  4393. {
  4394. kfree(tp->rx_std_buffers);
  4395. tp->rx_std_buffers = NULL;
  4396. if (tp->rx_std) {
  4397. pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
  4398. tp->rx_std, tp->rx_std_mapping);
  4399. tp->rx_std = NULL;
  4400. }
  4401. if (tp->rx_jumbo) {
  4402. pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  4403. tp->rx_jumbo, tp->rx_jumbo_mapping);
  4404. tp->rx_jumbo = NULL;
  4405. }
  4406. if (tp->rx_rcb) {
  4407. pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  4408. tp->rx_rcb, tp->rx_rcb_mapping);
  4409. tp->rx_rcb = NULL;
  4410. }
  4411. if (tp->tx_ring) {
  4412. pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
  4413. tp->tx_ring, tp->tx_desc_mapping);
  4414. tp->tx_ring = NULL;
  4415. }
  4416. if (tp->hw_status) {
  4417. pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
  4418. tp->hw_status, tp->status_mapping);
  4419. tp->hw_status = NULL;
  4420. }
  4421. if (tp->hw_stats) {
  4422. pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
  4423. tp->hw_stats, tp->stats_mapping);
  4424. tp->hw_stats = NULL;
  4425. }
  4426. }
  4427. /*
  4428. * Must not be invoked with interrupt sources disabled and
  4429. * the hardware shutdown down. Can sleep.
  4430. */
  4431. static int tg3_alloc_consistent(struct tg3 *tp)
  4432. {
  4433. tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
  4434. (TG3_RX_RING_SIZE +
  4435. TG3_RX_JUMBO_RING_SIZE)) +
  4436. (sizeof(struct tx_ring_info) *
  4437. TG3_TX_RING_SIZE),
  4438. GFP_KERNEL);
  4439. if (!tp->rx_std_buffers)
  4440. return -ENOMEM;
  4441. tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
  4442. tp->tx_buffers = (struct tx_ring_info *)
  4443. &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
  4444. tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
  4445. &tp->rx_std_mapping);
  4446. if (!tp->rx_std)
  4447. goto err_out;
  4448. tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  4449. &tp->rx_jumbo_mapping);
  4450. if (!tp->rx_jumbo)
  4451. goto err_out;
  4452. tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  4453. &tp->rx_rcb_mapping);
  4454. if (!tp->rx_rcb)
  4455. goto err_out;
  4456. tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
  4457. &tp->tx_desc_mapping);
  4458. if (!tp->tx_ring)
  4459. goto err_out;
  4460. tp->hw_status = pci_alloc_consistent(tp->pdev,
  4461. TG3_HW_STATUS_SIZE,
  4462. &tp->status_mapping);
  4463. if (!tp->hw_status)
  4464. goto err_out;
  4465. tp->hw_stats = pci_alloc_consistent(tp->pdev,
  4466. sizeof(struct tg3_hw_stats),
  4467. &tp->stats_mapping);
  4468. if (!tp->hw_stats)
  4469. goto err_out;
  4470. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  4471. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  4472. return 0;
  4473. err_out:
  4474. tg3_free_consistent(tp);
  4475. return -ENOMEM;
  4476. }
  4477. #define MAX_WAIT_CNT 1000
  4478. /* To stop a block, clear the enable bit and poll till it
  4479. * clears. tp->lock is held.
  4480. */
  4481. static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
  4482. {
  4483. unsigned int i;
  4484. u32 val;
  4485. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  4486. switch (ofs) {
  4487. case RCVLSC_MODE:
  4488. case DMAC_MODE:
  4489. case MBFREE_MODE:
  4490. case BUFMGR_MODE:
  4491. case MEMARB_MODE:
  4492. /* We can't enable/disable these bits of the
  4493. * 5705/5750, just say success.
  4494. */
  4495. return 0;
  4496. default:
  4497. break;
  4498. }
  4499. }
  4500. val = tr32(ofs);
  4501. val &= ~enable_bit;
  4502. tw32_f(ofs, val);
  4503. for (i = 0; i < MAX_WAIT_CNT; i++) {
  4504. udelay(100);
  4505. val = tr32(ofs);
  4506. if ((val & enable_bit) == 0)
  4507. break;
  4508. }
  4509. if (i == MAX_WAIT_CNT && !silent) {
  4510. printk(KERN_ERR PFX "tg3_stop_block timed out, "
  4511. "ofs=%lx enable_bit=%x\n",
  4512. ofs, enable_bit);
  4513. return -ENODEV;
  4514. }
  4515. return 0;
  4516. }
  4517. /* tp->lock is held. */
  4518. static int tg3_abort_hw(struct tg3 *tp, int silent)
  4519. {
  4520. int i, err;
  4521. tg3_disable_ints(tp);
  4522. tp->rx_mode &= ~RX_MODE_ENABLE;
  4523. tw32_f(MAC_RX_MODE, tp->rx_mode);
  4524. udelay(10);
  4525. err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
  4526. err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
  4527. err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
  4528. err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
  4529. err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
  4530. err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
  4531. err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
  4532. err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
  4533. err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
  4534. err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
  4535. err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
  4536. err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
  4537. err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
  4538. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  4539. tw32_f(MAC_MODE, tp->mac_mode);
  4540. udelay(40);
  4541. tp->tx_mode &= ~TX_MODE_ENABLE;
  4542. tw32_f(MAC_TX_MODE, tp->tx_mode);
  4543. for (i = 0; i < MAX_WAIT_CNT; i++) {
  4544. udelay(100);
  4545. if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  4546. break;
  4547. }
  4548. if (i >= MAX_WAIT_CNT) {
  4549. printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
  4550. "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
  4551. tp->dev->name, tr32(MAC_TX_MODE));
  4552. err |= -ENODEV;
  4553. }
  4554. err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
  4555. err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
  4556. err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
  4557. tw32(FTQ_RESET, 0xffffffff);
  4558. tw32(FTQ_RESET, 0x00000000);
  4559. err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
  4560. err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
  4561. if (tp->hw_status)
  4562. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  4563. if (tp->hw_stats)
  4564. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  4565. return err;
  4566. }
  4567. /* tp->lock is held. */
  4568. static int tg3_nvram_lock(struct tg3 *tp)
  4569. {
  4570. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  4571. int i;
  4572. if (tp->nvram_lock_cnt == 0) {
  4573. tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  4574. for (i = 0; i < 8000; i++) {
  4575. if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  4576. break;
  4577. udelay(20);
  4578. }
  4579. if (i == 8000) {
  4580. tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  4581. return -ENODEV;
  4582. }
  4583. }
  4584. tp->nvram_lock_cnt++;
  4585. }
  4586. return 0;
  4587. }
  4588. /* tp->lock is held. */
  4589. static void tg3_nvram_unlock(struct tg3 *tp)
  4590. {
  4591. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  4592. if (tp->nvram_lock_cnt > 0)
  4593. tp->nvram_lock_cnt--;
  4594. if (tp->nvram_lock_cnt == 0)
  4595. tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
  4596. }
  4597. }
  4598. /* tp->lock is held. */
  4599. static void tg3_enable_nvram_access(struct tg3 *tp)
  4600. {
  4601. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  4602. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
  4603. u32 nvaccess = tr32(NVRAM_ACCESS);
  4604. tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
  4605. }
  4606. }
  4607. /* tp->lock is held. */
  4608. static void tg3_disable_nvram_access(struct tg3 *tp)
  4609. {
  4610. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  4611. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
  4612. u32 nvaccess = tr32(NVRAM_ACCESS);
  4613. tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
  4614. }
  4615. }
  4616. static void tg3_ape_send_event(struct tg3 *tp, u32 event)
  4617. {
  4618. int i;
  4619. u32 apedata;
  4620. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  4621. if (apedata != APE_SEG_SIG_MAGIC)
  4622. return;
  4623. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  4624. if (!(apedata & APE_FW_STATUS_READY))
  4625. return;
  4626. /* Wait for up to 1 millisecond for APE to service previous event. */
  4627. for (i = 0; i < 10; i++) {
  4628. if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
  4629. return;
  4630. apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
  4631. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  4632. tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
  4633. event | APE_EVENT_STATUS_EVENT_PENDING);
  4634. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  4635. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  4636. break;
  4637. udelay(100);
  4638. }
  4639. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  4640. tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
  4641. }
  4642. static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
  4643. {
  4644. u32 event;
  4645. u32 apedata;
  4646. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  4647. return;
  4648. switch (kind) {
  4649. case RESET_KIND_INIT:
  4650. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
  4651. APE_HOST_SEG_SIG_MAGIC);
  4652. tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
  4653. APE_HOST_SEG_LEN_MAGIC);
  4654. apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
  4655. tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
  4656. tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
  4657. APE_HOST_DRIVER_ID_MAGIC);
  4658. tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
  4659. APE_HOST_BEHAV_NO_PHYLOCK);
  4660. event = APE_EVENT_STATUS_STATE_START;
  4661. break;
  4662. case RESET_KIND_SHUTDOWN:
  4663. event = APE_EVENT_STATUS_STATE_UNLOAD;
  4664. break;
  4665. case RESET_KIND_SUSPEND:
  4666. event = APE_EVENT_STATUS_STATE_SUSPEND;
  4667. break;
  4668. default:
  4669. return;
  4670. }
  4671. event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
  4672. tg3_ape_send_event(tp, event);
  4673. }
  4674. /* tp->lock is held. */
  4675. static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
  4676. {
  4677. tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
  4678. NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  4679. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  4680. switch (kind) {
  4681. case RESET_KIND_INIT:
  4682. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4683. DRV_STATE_START);
  4684. break;
  4685. case RESET_KIND_SHUTDOWN:
  4686. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4687. DRV_STATE_UNLOAD);
  4688. break;
  4689. case RESET_KIND_SUSPEND:
  4690. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4691. DRV_STATE_SUSPEND);
  4692. break;
  4693. default:
  4694. break;
  4695. }
  4696. }
  4697. if (kind == RESET_KIND_INIT ||
  4698. kind == RESET_KIND_SUSPEND)
  4699. tg3_ape_driver_state_change(tp, kind);
  4700. }
  4701. /* tp->lock is held. */
  4702. static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
  4703. {
  4704. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  4705. switch (kind) {
  4706. case RESET_KIND_INIT:
  4707. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4708. DRV_STATE_START_DONE);
  4709. break;
  4710. case RESET_KIND_SHUTDOWN:
  4711. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4712. DRV_STATE_UNLOAD_DONE);
  4713. break;
  4714. default:
  4715. break;
  4716. }
  4717. }
  4718. if (kind == RESET_KIND_SHUTDOWN)
  4719. tg3_ape_driver_state_change(tp, kind);
  4720. }
  4721. /* tp->lock is held. */
  4722. static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
  4723. {
  4724. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  4725. switch (kind) {
  4726. case RESET_KIND_INIT:
  4727. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4728. DRV_STATE_START);
  4729. break;
  4730. case RESET_KIND_SHUTDOWN:
  4731. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4732. DRV_STATE_UNLOAD);
  4733. break;
  4734. case RESET_KIND_SUSPEND:
  4735. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4736. DRV_STATE_SUSPEND);
  4737. break;
  4738. default:
  4739. break;
  4740. }
  4741. }
  4742. }
  4743. static int tg3_poll_fw(struct tg3 *tp)
  4744. {
  4745. int i;
  4746. u32 val;
  4747. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4748. /* Wait up to 20ms for init done. */
  4749. for (i = 0; i < 200; i++) {
  4750. if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
  4751. return 0;
  4752. udelay(100);
  4753. }
  4754. return -ENODEV;
  4755. }
  4756. /* Wait for firmware initialization to complete. */
  4757. for (i = 0; i < 100000; i++) {
  4758. tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  4759. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  4760. break;
  4761. udelay(10);
  4762. }
  4763. /* Chip might not be fitted with firmware. Some Sun onboard
  4764. * parts are configured like that. So don't signal the timeout
  4765. * of the above loop as an error, but do report the lack of
  4766. * running firmware once.
  4767. */
  4768. if (i >= 100000 &&
  4769. !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
  4770. tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
  4771. printk(KERN_INFO PFX "%s: No firmware running.\n",
  4772. tp->dev->name);
  4773. }
  4774. return 0;
  4775. }
  4776. /* Save PCI command register before chip reset */
  4777. static void tg3_save_pci_state(struct tg3 *tp)
  4778. {
  4779. pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
  4780. }
  4781. /* Restore PCI state after chip reset */
  4782. static void tg3_restore_pci_state(struct tg3 *tp)
  4783. {
  4784. u32 val;
  4785. /* Re-enable indirect register accesses. */
  4786. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  4787. tp->misc_host_ctrl);
  4788. /* Set MAX PCI retry to zero. */
  4789. val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  4790. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  4791. (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
  4792. val |= PCISTATE_RETRY_SAME_DMA;
  4793. /* Allow reads and writes to the APE register and memory space. */
  4794. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  4795. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  4796. PCISTATE_ALLOW_APE_SHMEM_WR;
  4797. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  4798. pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
  4799. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
  4800. pcie_set_readrq(tp->pdev, 4096);
  4801. else {
  4802. pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  4803. tp->pci_cacheline_sz);
  4804. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  4805. tp->pci_lat_timer);
  4806. }
  4807. /* Make sure PCI-X relaxed ordering bit is clear. */
  4808. if (tp->pcix_cap) {
  4809. u16 pcix_cmd;
  4810. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  4811. &pcix_cmd);
  4812. pcix_cmd &= ~PCI_X_CMD_ERO;
  4813. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  4814. pcix_cmd);
  4815. }
  4816. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  4817. /* Chip reset on 5780 will reset MSI enable bit,
  4818. * so need to restore it.
  4819. */
  4820. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  4821. u16 ctrl;
  4822. pci_read_config_word(tp->pdev,
  4823. tp->msi_cap + PCI_MSI_FLAGS,
  4824. &ctrl);
  4825. pci_write_config_word(tp->pdev,
  4826. tp->msi_cap + PCI_MSI_FLAGS,
  4827. ctrl | PCI_MSI_FLAGS_ENABLE);
  4828. val = tr32(MSGINT_MODE);
  4829. tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
  4830. }
  4831. }
  4832. }
  4833. static void tg3_stop_fw(struct tg3 *);
  4834. /* tp->lock is held. */
  4835. static int tg3_chip_reset(struct tg3 *tp)
  4836. {
  4837. u32 val;
  4838. void (*write_op)(struct tg3 *, u32, u32);
  4839. int err;
  4840. tg3_nvram_lock(tp);
  4841. tg3_mdio_stop(tp);
  4842. tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
  4843. /* No matching tg3_nvram_unlock() after this because
  4844. * chip reset below will undo the nvram lock.
  4845. */
  4846. tp->nvram_lock_cnt = 0;
  4847. /* GRC_MISC_CFG core clock reset will clear the memory
  4848. * enable bit in PCI register 4 and the MSI enable bit
  4849. * on some chips, so we save relevant registers here.
  4850. */
  4851. tg3_save_pci_state(tp);
  4852. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  4853. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  4854. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  4855. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  4856. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  4857. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  4858. tw32(GRC_FASTBOOT_PC, 0);
  4859. /*
  4860. * We must avoid the readl() that normally takes place.
  4861. * It locks machines, causes machine checks, and other
  4862. * fun things. So, temporarily disable the 5701
  4863. * hardware workaround, while we do the reset.
  4864. */
  4865. write_op = tp->write32;
  4866. if (write_op == tg3_write_flush_reg32)
  4867. tp->write32 = tg3_write32;
  4868. /* Prevent the irq handler from reading or writing PCI registers
  4869. * during chip reset when the memory enable bit in the PCI command
  4870. * register may be cleared. The chip does not generate interrupt
  4871. * at this time, but the irq handler may still be called due to irq
  4872. * sharing or irqpoll.
  4873. */
  4874. tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
  4875. if (tp->hw_status) {
  4876. tp->hw_status->status = 0;
  4877. tp->hw_status->status_tag = 0;
  4878. }
  4879. tp->last_tag = 0;
  4880. smp_mb();
  4881. synchronize_irq(tp->pdev->irq);
  4882. /* do the reset */
  4883. val = GRC_MISC_CFG_CORECLK_RESET;
  4884. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  4885. if (tr32(0x7e2c) == 0x60) {
  4886. tw32(0x7e2c, 0x20);
  4887. }
  4888. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  4889. tw32(GRC_MISC_CFG, (1 << 29));
  4890. val |= (1 << 29);
  4891. }
  4892. }
  4893. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4894. tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
  4895. tw32(GRC_VCPU_EXT_CTRL,
  4896. tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
  4897. }
  4898. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  4899. val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  4900. tw32(GRC_MISC_CFG, val);
  4901. /* restore 5701 hardware bug workaround write method */
  4902. tp->write32 = write_op;
  4903. /* Unfortunately, we have to delay before the PCI read back.
  4904. * Some 575X chips even will not respond to a PCI cfg access
  4905. * when the reset command is given to the chip.
  4906. *
  4907. * How do these hardware designers expect things to work
  4908. * properly if the PCI write is posted for a long period
  4909. * of time? It is always necessary to have some method by
  4910. * which a register read back can occur to push the write
  4911. * out which does the reset.
  4912. *
  4913. * For most tg3 variants the trick below was working.
  4914. * Ho hum...
  4915. */
  4916. udelay(120);
  4917. /* Flush PCI posted writes. The normal MMIO registers
  4918. * are inaccessible at this time so this is the only
  4919. * way to make this reliably (actually, this is no longer
  4920. * the case, see above). I tried to use indirect
  4921. * register read/write but this upset some 5701 variants.
  4922. */
  4923. pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  4924. udelay(120);
  4925. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  4926. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
  4927. int i;
  4928. u32 cfg_val;
  4929. /* Wait for link training to complete. */
  4930. for (i = 0; i < 5000; i++)
  4931. udelay(100);
  4932. pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
  4933. pci_write_config_dword(tp->pdev, 0xc4,
  4934. cfg_val | (1 << 15));
  4935. }
  4936. /* Set PCIE max payload size and clear error status. */
  4937. pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
  4938. }
  4939. tg3_restore_pci_state(tp);
  4940. tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
  4941. val = 0;
  4942. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  4943. val = tr32(MEMARB_MODE);
  4944. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  4945. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
  4946. tg3_stop_fw(tp);
  4947. tw32(0x5000, 0x400);
  4948. }
  4949. tw32(GRC_MODE, tp->grc_mode);
  4950. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
  4951. val = tr32(0xc4);
  4952. tw32(0xc4, val | (1 << 15));
  4953. }
  4954. if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  4955. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  4956. tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
  4957. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
  4958. tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
  4959. tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  4960. }
  4961. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  4962. tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  4963. tw32_f(MAC_MODE, tp->mac_mode);
  4964. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  4965. tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
  4966. tw32_f(MAC_MODE, tp->mac_mode);
  4967. } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  4968. tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
  4969. if (tp->mac_mode & MAC_MODE_APE_TX_EN)
  4970. tp->mac_mode |= MAC_MODE_TDE_ENABLE;
  4971. tw32_f(MAC_MODE, tp->mac_mode);
  4972. } else
  4973. tw32_f(MAC_MODE, 0);
  4974. udelay(40);
  4975. tg3_mdio_start(tp);
  4976. tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
  4977. err = tg3_poll_fw(tp);
  4978. if (err)
  4979. return err;
  4980. if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  4981. tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  4982. val = tr32(0x7c00);
  4983. tw32(0x7c00, val | (1 << 25));
  4984. }
  4985. /* Reprobe ASF enable state. */
  4986. tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
  4987. tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
  4988. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  4989. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  4990. u32 nic_cfg;
  4991. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  4992. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  4993. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  4994. tp->last_event_jiffies = jiffies;
  4995. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  4996. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  4997. }
  4998. }
  4999. return 0;
  5000. }
  5001. /* tp->lock is held. */
  5002. static void tg3_stop_fw(struct tg3 *tp)
  5003. {
  5004. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
  5005. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
  5006. /* Wait for RX cpu to ACK the previous event. */
  5007. tg3_wait_for_event_ack(tp);
  5008. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  5009. tg3_generate_fw_event(tp);
  5010. /* Wait for RX cpu to ACK this event. */
  5011. tg3_wait_for_event_ack(tp);
  5012. }
  5013. }
  5014. /* tp->lock is held. */
  5015. static int tg3_halt(struct tg3 *tp, int kind, int silent)
  5016. {
  5017. int err;
  5018. tg3_stop_fw(tp);
  5019. tg3_write_sig_pre_reset(tp, kind);
  5020. tg3_abort_hw(tp, silent);
  5021. err = tg3_chip_reset(tp);
  5022. tg3_write_sig_legacy(tp, kind);
  5023. tg3_write_sig_post_reset(tp, kind);
  5024. if (err)
  5025. return err;
  5026. return 0;
  5027. }
  5028. #define TG3_FW_RELEASE_MAJOR 0x0
  5029. #define TG3_FW_RELASE_MINOR 0x0
  5030. #define TG3_FW_RELEASE_FIX 0x0
  5031. #define TG3_FW_START_ADDR 0x08000000
  5032. #define TG3_FW_TEXT_ADDR 0x08000000
  5033. #define TG3_FW_TEXT_LEN 0x9c0
  5034. #define TG3_FW_RODATA_ADDR 0x080009c0
  5035. #define TG3_FW_RODATA_LEN 0x60
  5036. #define TG3_FW_DATA_ADDR 0x08000a40
  5037. #define TG3_FW_DATA_LEN 0x20
  5038. #define TG3_FW_SBSS_ADDR 0x08000a60
  5039. #define TG3_FW_SBSS_LEN 0xc
  5040. #define TG3_FW_BSS_ADDR 0x08000a70
  5041. #define TG3_FW_BSS_LEN 0x10
  5042. static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
  5043. 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
  5044. 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
  5045. 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
  5046. 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
  5047. 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
  5048. 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
  5049. 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
  5050. 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
  5051. 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
  5052. 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
  5053. 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
  5054. 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
  5055. 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
  5056. 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
  5057. 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
  5058. 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  5059. 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
  5060. 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
  5061. 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
  5062. 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  5063. 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
  5064. 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
  5065. 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  5066. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5067. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5068. 0, 0, 0, 0, 0, 0,
  5069. 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
  5070. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  5071. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  5072. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  5073. 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
  5074. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
  5075. 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
  5076. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
  5077. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  5078. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  5079. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
  5080. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5081. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5082. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5083. 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
  5084. 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
  5085. 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
  5086. 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
  5087. 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
  5088. 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
  5089. 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
  5090. 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
  5091. 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
  5092. 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
  5093. 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
  5094. 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
  5095. 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
  5096. 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
  5097. 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
  5098. 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
  5099. 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
  5100. 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
  5101. 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
  5102. 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
  5103. 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
  5104. 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
  5105. 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
  5106. 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
  5107. 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
  5108. 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
  5109. 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
  5110. 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
  5111. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
  5112. 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
  5113. 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
  5114. 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
  5115. 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
  5116. 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
  5117. 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
  5118. 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
  5119. 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
  5120. 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
  5121. 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
  5122. 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
  5123. 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
  5124. 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
  5125. 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
  5126. 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
  5127. 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
  5128. 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
  5129. 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
  5130. 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
  5131. 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
  5132. 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
  5133. 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
  5134. };
  5135. static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
  5136. 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
  5137. 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
  5138. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  5139. 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
  5140. 0x00000000
  5141. };
  5142. #if 0 /* All zeros, don't eat up space with it. */
  5143. u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
  5144. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  5145. 0x00000000, 0x00000000, 0x00000000, 0x00000000
  5146. };
  5147. #endif
  5148. #define RX_CPU_SCRATCH_BASE 0x30000
  5149. #define RX_CPU_SCRATCH_SIZE 0x04000
  5150. #define TX_CPU_SCRATCH_BASE 0x34000
  5151. #define TX_CPU_SCRATCH_SIZE 0x04000
  5152. /* tp->lock is held. */
  5153. static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
  5154. {
  5155. int i;
  5156. BUG_ON(offset == TX_CPU_BASE &&
  5157. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
  5158. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  5159. u32 val = tr32(GRC_VCPU_EXT_CTRL);
  5160. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
  5161. return 0;
  5162. }
  5163. if (offset == RX_CPU_BASE) {
  5164. for (i = 0; i < 10000; i++) {
  5165. tw32(offset + CPU_STATE, 0xffffffff);
  5166. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  5167. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  5168. break;
  5169. }
  5170. tw32(offset + CPU_STATE, 0xffffffff);
  5171. tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
  5172. udelay(10);
  5173. } else {
  5174. for (i = 0; i < 10000; i++) {
  5175. tw32(offset + CPU_STATE, 0xffffffff);
  5176. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  5177. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  5178. break;
  5179. }
  5180. }
  5181. if (i >= 10000) {
  5182. printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
  5183. "and %s CPU\n",
  5184. tp->dev->name,
  5185. (offset == RX_CPU_BASE ? "RX" : "TX"));
  5186. return -ENODEV;
  5187. }
  5188. /* Clear firmware's nvram arbitration. */
  5189. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  5190. tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
  5191. return 0;
  5192. }
  5193. struct fw_info {
  5194. unsigned int text_base;
  5195. unsigned int text_len;
  5196. const u32 *text_data;
  5197. unsigned int rodata_base;
  5198. unsigned int rodata_len;
  5199. const u32 *rodata_data;
  5200. unsigned int data_base;
  5201. unsigned int data_len;
  5202. const u32 *data_data;
  5203. };
  5204. /* tp->lock is held. */
  5205. static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
  5206. int cpu_scratch_size, struct fw_info *info)
  5207. {
  5208. int err, lock_err, i;
  5209. void (*write_op)(struct tg3 *, u32, u32);
  5210. if (cpu_base == TX_CPU_BASE &&
  5211. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5212. printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
  5213. "TX cpu firmware on %s which is 5705.\n",
  5214. tp->dev->name);
  5215. return -EINVAL;
  5216. }
  5217. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  5218. write_op = tg3_write_mem;
  5219. else
  5220. write_op = tg3_write_indirect_reg32;
  5221. /* It is possible that bootcode is still loading at this point.
  5222. * Get the nvram lock first before halting the cpu.
  5223. */
  5224. lock_err = tg3_nvram_lock(tp);
  5225. err = tg3_halt_cpu(tp, cpu_base);
  5226. if (!lock_err)
  5227. tg3_nvram_unlock(tp);
  5228. if (err)
  5229. goto out;
  5230. for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  5231. write_op(tp, cpu_scratch_base + i, 0);
  5232. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5233. tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
  5234. for (i = 0; i < (info->text_len / sizeof(u32)); i++)
  5235. write_op(tp, (cpu_scratch_base +
  5236. (info->text_base & 0xffff) +
  5237. (i * sizeof(u32))),
  5238. (info->text_data ?
  5239. info->text_data[i] : 0));
  5240. for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
  5241. write_op(tp, (cpu_scratch_base +
  5242. (info->rodata_base & 0xffff) +
  5243. (i * sizeof(u32))),
  5244. (info->rodata_data ?
  5245. info->rodata_data[i] : 0));
  5246. for (i = 0; i < (info->data_len / sizeof(u32)); i++)
  5247. write_op(tp, (cpu_scratch_base +
  5248. (info->data_base & 0xffff) +
  5249. (i * sizeof(u32))),
  5250. (info->data_data ?
  5251. info->data_data[i] : 0));
  5252. err = 0;
  5253. out:
  5254. return err;
  5255. }
  5256. /* tp->lock is held. */
  5257. static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  5258. {
  5259. struct fw_info info;
  5260. int err, i;
  5261. info.text_base = TG3_FW_TEXT_ADDR;
  5262. info.text_len = TG3_FW_TEXT_LEN;
  5263. info.text_data = &tg3FwText[0];
  5264. info.rodata_base = TG3_FW_RODATA_ADDR;
  5265. info.rodata_len = TG3_FW_RODATA_LEN;
  5266. info.rodata_data = &tg3FwRodata[0];
  5267. info.data_base = TG3_FW_DATA_ADDR;
  5268. info.data_len = TG3_FW_DATA_LEN;
  5269. info.data_data = NULL;
  5270. err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  5271. RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  5272. &info);
  5273. if (err)
  5274. return err;
  5275. err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  5276. TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  5277. &info);
  5278. if (err)
  5279. return err;
  5280. /* Now startup only the RX cpu. */
  5281. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  5282. tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
  5283. for (i = 0; i < 5; i++) {
  5284. if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
  5285. break;
  5286. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  5287. tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
  5288. tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
  5289. udelay(1000);
  5290. }
  5291. if (i >= 5) {
  5292. printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
  5293. "to set RX CPU PC, is %08x should be %08x\n",
  5294. tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
  5295. TG3_FW_TEXT_ADDR);
  5296. return -ENODEV;
  5297. }
  5298. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  5299. tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
  5300. return 0;
  5301. }
  5302. #define TG3_TSO_FW_RELEASE_MAJOR 0x1
  5303. #define TG3_TSO_FW_RELASE_MINOR 0x6
  5304. #define TG3_TSO_FW_RELEASE_FIX 0x0
  5305. #define TG3_TSO_FW_START_ADDR 0x08000000
  5306. #define TG3_TSO_FW_TEXT_ADDR 0x08000000
  5307. #define TG3_TSO_FW_TEXT_LEN 0x1aa0
  5308. #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
  5309. #define TG3_TSO_FW_RODATA_LEN 0x60
  5310. #define TG3_TSO_FW_DATA_ADDR 0x08001b20
  5311. #define TG3_TSO_FW_DATA_LEN 0x30
  5312. #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
  5313. #define TG3_TSO_FW_SBSS_LEN 0x2c
  5314. #define TG3_TSO_FW_BSS_ADDR 0x08001b80
  5315. #define TG3_TSO_FW_BSS_LEN 0x894
  5316. static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
  5317. 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
  5318. 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
  5319. 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
  5320. 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
  5321. 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
  5322. 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
  5323. 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
  5324. 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
  5325. 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
  5326. 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
  5327. 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
  5328. 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
  5329. 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
  5330. 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
  5331. 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
  5332. 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
  5333. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
  5334. 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
  5335. 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
  5336. 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
  5337. 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
  5338. 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
  5339. 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
  5340. 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
  5341. 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
  5342. 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
  5343. 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
  5344. 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
  5345. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
  5346. 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  5347. 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
  5348. 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
  5349. 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
  5350. 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
  5351. 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
  5352. 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
  5353. 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
  5354. 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
  5355. 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
  5356. 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
  5357. 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
  5358. 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
  5359. 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
  5360. 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
  5361. 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
  5362. 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
  5363. 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
  5364. 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
  5365. 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
  5366. 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
  5367. 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
  5368. 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
  5369. 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
  5370. 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
  5371. 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
  5372. 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
  5373. 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
  5374. 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
  5375. 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
  5376. 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
  5377. 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
  5378. 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
  5379. 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
  5380. 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
  5381. 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
  5382. 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
  5383. 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
  5384. 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
  5385. 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
  5386. 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
  5387. 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
  5388. 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
  5389. 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
  5390. 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
  5391. 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
  5392. 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
  5393. 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
  5394. 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
  5395. 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
  5396. 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
  5397. 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
  5398. 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
  5399. 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
  5400. 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
  5401. 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
  5402. 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
  5403. 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
  5404. 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
  5405. 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
  5406. 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
  5407. 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
  5408. 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
  5409. 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
  5410. 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
  5411. 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
  5412. 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
  5413. 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
  5414. 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
  5415. 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
  5416. 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
  5417. 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
  5418. 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
  5419. 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
  5420. 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
  5421. 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
  5422. 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
  5423. 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
  5424. 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
  5425. 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
  5426. 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
  5427. 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
  5428. 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
  5429. 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
  5430. 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
  5431. 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
  5432. 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
  5433. 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
  5434. 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
  5435. 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
  5436. 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
  5437. 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
  5438. 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
  5439. 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
  5440. 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
  5441. 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
  5442. 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
  5443. 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
  5444. 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
  5445. 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
  5446. 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
  5447. 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
  5448. 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
  5449. 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
  5450. 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
  5451. 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
  5452. 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
  5453. 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
  5454. 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
  5455. 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
  5456. 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
  5457. 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
  5458. 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
  5459. 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
  5460. 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
  5461. 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
  5462. 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
  5463. 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
  5464. 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
  5465. 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
  5466. 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
  5467. 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
  5468. 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
  5469. 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
  5470. 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
  5471. 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
  5472. 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
  5473. 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
  5474. 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
  5475. 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
  5476. 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
  5477. 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
  5478. 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
  5479. 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
  5480. 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
  5481. 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
  5482. 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
  5483. 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
  5484. 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
  5485. 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
  5486. 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
  5487. 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
  5488. 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
  5489. 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
  5490. 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
  5491. 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
  5492. 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
  5493. 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
  5494. 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
  5495. 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
  5496. 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
  5497. 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
  5498. 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
  5499. 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
  5500. 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
  5501. 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
  5502. 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
  5503. 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
  5504. 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
  5505. 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
  5506. 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
  5507. 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
  5508. 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
  5509. 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
  5510. 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
  5511. 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
  5512. 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
  5513. 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
  5514. 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
  5515. 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
  5516. 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
  5517. 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
  5518. 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
  5519. 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
  5520. 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
  5521. 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
  5522. 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
  5523. 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
  5524. 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
  5525. 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
  5526. 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
  5527. 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
  5528. 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
  5529. 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
  5530. 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
  5531. 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
  5532. 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
  5533. 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
  5534. 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
  5535. 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
  5536. 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
  5537. 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
  5538. 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
  5539. 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
  5540. 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
  5541. 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
  5542. 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
  5543. 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
  5544. 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
  5545. 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
  5546. 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
  5547. 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
  5548. 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
  5549. 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
  5550. 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
  5551. 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
  5552. 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
  5553. 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
  5554. 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
  5555. 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
  5556. 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
  5557. 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
  5558. 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
  5559. 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
  5560. 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
  5561. 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
  5562. 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
  5563. 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
  5564. 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
  5565. 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
  5566. 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
  5567. 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
  5568. 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
  5569. 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
  5570. 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
  5571. 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
  5572. 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
  5573. 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
  5574. 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
  5575. 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
  5576. 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
  5577. 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
  5578. 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
  5579. 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
  5580. 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
  5581. 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
  5582. 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
  5583. 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
  5584. 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
  5585. 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
  5586. 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
  5587. 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
  5588. 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
  5589. 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
  5590. 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
  5591. 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
  5592. 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
  5593. 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
  5594. 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
  5595. 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
  5596. 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
  5597. 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
  5598. 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
  5599. 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
  5600. 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
  5601. };
  5602. static const u32 tg3TsoFwRodata[] = {
  5603. 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
  5604. 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
  5605. 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
  5606. 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
  5607. 0x00000000,
  5608. };
  5609. static const u32 tg3TsoFwData[] = {
  5610. 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
  5611. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  5612. 0x00000000,
  5613. };
  5614. /* 5705 needs a special version of the TSO firmware. */
  5615. #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
  5616. #define TG3_TSO5_FW_RELASE_MINOR 0x2
  5617. #define TG3_TSO5_FW_RELEASE_FIX 0x0
  5618. #define TG3_TSO5_FW_START_ADDR 0x00010000
  5619. #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
  5620. #define TG3_TSO5_FW_TEXT_LEN 0xe90
  5621. #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
  5622. #define TG3_TSO5_FW_RODATA_LEN 0x50
  5623. #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
  5624. #define TG3_TSO5_FW_DATA_LEN 0x20
  5625. #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
  5626. #define TG3_TSO5_FW_SBSS_LEN 0x28
  5627. #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
  5628. #define TG3_TSO5_FW_BSS_LEN 0x88
  5629. static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
  5630. 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
  5631. 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
  5632. 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
  5633. 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
  5634. 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
  5635. 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
  5636. 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  5637. 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
  5638. 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
  5639. 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
  5640. 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
  5641. 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
  5642. 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
  5643. 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
  5644. 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
  5645. 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
  5646. 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
  5647. 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
  5648. 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
  5649. 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
  5650. 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
  5651. 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
  5652. 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
  5653. 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
  5654. 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
  5655. 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
  5656. 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
  5657. 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
  5658. 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
  5659. 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
  5660. 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  5661. 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
  5662. 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
  5663. 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
  5664. 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
  5665. 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
  5666. 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
  5667. 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
  5668. 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
  5669. 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
  5670. 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
  5671. 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
  5672. 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
  5673. 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
  5674. 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
  5675. 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
  5676. 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
  5677. 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
  5678. 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
  5679. 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
  5680. 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
  5681. 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
  5682. 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
  5683. 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
  5684. 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
  5685. 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
  5686. 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
  5687. 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
  5688. 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
  5689. 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
  5690. 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
  5691. 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
  5692. 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
  5693. 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
  5694. 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
  5695. 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
  5696. 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  5697. 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
  5698. 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
  5699. 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
  5700. 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
  5701. 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
  5702. 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
  5703. 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
  5704. 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
  5705. 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
  5706. 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
  5707. 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
  5708. 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
  5709. 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
  5710. 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
  5711. 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
  5712. 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
  5713. 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
  5714. 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
  5715. 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
  5716. 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
  5717. 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
  5718. 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
  5719. 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
  5720. 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
  5721. 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
  5722. 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
  5723. 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
  5724. 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
  5725. 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
  5726. 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
  5727. 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
  5728. 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
  5729. 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
  5730. 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
  5731. 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
  5732. 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
  5733. 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
  5734. 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
  5735. 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
  5736. 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  5737. 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  5738. 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
  5739. 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
  5740. 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
  5741. 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
  5742. 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
  5743. 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
  5744. 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
  5745. 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
  5746. 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
  5747. 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  5748. 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  5749. 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
  5750. 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
  5751. 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
  5752. 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
  5753. 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  5754. 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
  5755. 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
  5756. 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
  5757. 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
  5758. 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
  5759. 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
  5760. 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
  5761. 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
  5762. 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
  5763. 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
  5764. 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
  5765. 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
  5766. 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
  5767. 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
  5768. 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
  5769. 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
  5770. 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
  5771. 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
  5772. 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
  5773. 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
  5774. 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
  5775. 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
  5776. 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
  5777. 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  5778. 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
  5779. 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
  5780. 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
  5781. 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  5782. 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
  5783. 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
  5784. 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  5785. 0x00000000, 0x00000000, 0x00000000,
  5786. };
  5787. static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
  5788. 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
  5789. 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
  5790. 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  5791. 0x00000000, 0x00000000, 0x00000000,
  5792. };
  5793. static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
  5794. 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
  5795. 0x00000000, 0x00000000, 0x00000000,
  5796. };
  5797. /* tp->lock is held. */
  5798. static int tg3_load_tso_firmware(struct tg3 *tp)
  5799. {
  5800. struct fw_info info;
  5801. unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  5802. int err, i;
  5803. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5804. return 0;
  5805. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5806. info.text_base = TG3_TSO5_FW_TEXT_ADDR;
  5807. info.text_len = TG3_TSO5_FW_TEXT_LEN;
  5808. info.text_data = &tg3Tso5FwText[0];
  5809. info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
  5810. info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
  5811. info.rodata_data = &tg3Tso5FwRodata[0];
  5812. info.data_base = TG3_TSO5_FW_DATA_ADDR;
  5813. info.data_len = TG3_TSO5_FW_DATA_LEN;
  5814. info.data_data = &tg3Tso5FwData[0];
  5815. cpu_base = RX_CPU_BASE;
  5816. cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  5817. cpu_scratch_size = (info.text_len +
  5818. info.rodata_len +
  5819. info.data_len +
  5820. TG3_TSO5_FW_SBSS_LEN +
  5821. TG3_TSO5_FW_BSS_LEN);
  5822. } else {
  5823. info.text_base = TG3_TSO_FW_TEXT_ADDR;
  5824. info.text_len = TG3_TSO_FW_TEXT_LEN;
  5825. info.text_data = &tg3TsoFwText[0];
  5826. info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
  5827. info.rodata_len = TG3_TSO_FW_RODATA_LEN;
  5828. info.rodata_data = &tg3TsoFwRodata[0];
  5829. info.data_base = TG3_TSO_FW_DATA_ADDR;
  5830. info.data_len = TG3_TSO_FW_DATA_LEN;
  5831. info.data_data = &tg3TsoFwData[0];
  5832. cpu_base = TX_CPU_BASE;
  5833. cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  5834. cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  5835. }
  5836. err = tg3_load_firmware_cpu(tp, cpu_base,
  5837. cpu_scratch_base, cpu_scratch_size,
  5838. &info);
  5839. if (err)
  5840. return err;
  5841. /* Now startup the cpu. */
  5842. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5843. tw32_f(cpu_base + CPU_PC, info.text_base);
  5844. for (i = 0; i < 5; i++) {
  5845. if (tr32(cpu_base + CPU_PC) == info.text_base)
  5846. break;
  5847. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5848. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  5849. tw32_f(cpu_base + CPU_PC, info.text_base);
  5850. udelay(1000);
  5851. }
  5852. if (i >= 5) {
  5853. printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
  5854. "to set CPU PC, is %08x should be %08x\n",
  5855. tp->dev->name, tr32(cpu_base + CPU_PC),
  5856. info.text_base);
  5857. return -ENODEV;
  5858. }
  5859. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5860. tw32_f(cpu_base + CPU_MODE, 0x00000000);
  5861. return 0;
  5862. }
  5863. /* tp->lock is held. */
  5864. static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
  5865. {
  5866. u32 addr_high, addr_low;
  5867. int i;
  5868. addr_high = ((tp->dev->dev_addr[0] << 8) |
  5869. tp->dev->dev_addr[1]);
  5870. addr_low = ((tp->dev->dev_addr[2] << 24) |
  5871. (tp->dev->dev_addr[3] << 16) |
  5872. (tp->dev->dev_addr[4] << 8) |
  5873. (tp->dev->dev_addr[5] << 0));
  5874. for (i = 0; i < 4; i++) {
  5875. if (i == 1 && skip_mac_1)
  5876. continue;
  5877. tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  5878. tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  5879. }
  5880. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  5881. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  5882. for (i = 0; i < 12; i++) {
  5883. tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  5884. tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  5885. }
  5886. }
  5887. addr_high = (tp->dev->dev_addr[0] +
  5888. tp->dev->dev_addr[1] +
  5889. tp->dev->dev_addr[2] +
  5890. tp->dev->dev_addr[3] +
  5891. tp->dev->dev_addr[4] +
  5892. tp->dev->dev_addr[5]) &
  5893. TX_BACKOFF_SEED_MASK;
  5894. tw32(MAC_TX_BACKOFF_SEED, addr_high);
  5895. }
  5896. static int tg3_set_mac_addr(struct net_device *dev, void *p)
  5897. {
  5898. struct tg3 *tp = netdev_priv(dev);
  5899. struct sockaddr *addr = p;
  5900. int err = 0, skip_mac_1 = 0;
  5901. if (!is_valid_ether_addr(addr->sa_data))
  5902. return -EINVAL;
  5903. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  5904. if (!netif_running(dev))
  5905. return 0;
  5906. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  5907. u32 addr0_high, addr0_low, addr1_high, addr1_low;
  5908. addr0_high = tr32(MAC_ADDR_0_HIGH);
  5909. addr0_low = tr32(MAC_ADDR_0_LOW);
  5910. addr1_high = tr32(MAC_ADDR_1_HIGH);
  5911. addr1_low = tr32(MAC_ADDR_1_LOW);
  5912. /* Skip MAC addr 1 if ASF is using it. */
  5913. if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
  5914. !(addr1_high == 0 && addr1_low == 0))
  5915. skip_mac_1 = 1;
  5916. }
  5917. spin_lock_bh(&tp->lock);
  5918. __tg3_set_mac_addr(tp, skip_mac_1);
  5919. spin_unlock_bh(&tp->lock);
  5920. return err;
  5921. }
  5922. /* tp->lock is held. */
  5923. static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  5924. dma_addr_t mapping, u32 maxlen_flags,
  5925. u32 nic_addr)
  5926. {
  5927. tg3_write_mem(tp,
  5928. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  5929. ((u64) mapping >> 32));
  5930. tg3_write_mem(tp,
  5931. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  5932. ((u64) mapping & 0xffffffff));
  5933. tg3_write_mem(tp,
  5934. (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  5935. maxlen_flags);
  5936. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5937. tg3_write_mem(tp,
  5938. (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  5939. nic_addr);
  5940. }
  5941. static void __tg3_set_rx_mode(struct net_device *);
  5942. static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
  5943. {
  5944. tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
  5945. tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
  5946. tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
  5947. tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
  5948. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5949. tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
  5950. tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
  5951. }
  5952. tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
  5953. tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
  5954. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5955. u32 val = ec->stats_block_coalesce_usecs;
  5956. if (!netif_carrier_ok(tp->dev))
  5957. val = 0;
  5958. tw32(HOSTCC_STAT_COAL_TICKS, val);
  5959. }
  5960. }
  5961. /* tp->lock is held. */
  5962. static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
  5963. {
  5964. u32 val, rdmac_mode;
  5965. int i, err, limit;
  5966. tg3_disable_ints(tp);
  5967. tg3_stop_fw(tp);
  5968. tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
  5969. if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
  5970. tg3_abort_hw(tp, 1);
  5971. }
  5972. if (reset_phy &&
  5973. !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
  5974. tg3_phy_reset(tp);
  5975. err = tg3_chip_reset(tp);
  5976. if (err)
  5977. return err;
  5978. tg3_write_sig_legacy(tp, RESET_KIND_INIT);
  5979. if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
  5980. tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
  5981. val = tr32(TG3_CPMU_CTRL);
  5982. val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
  5983. tw32(TG3_CPMU_CTRL, val);
  5984. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  5985. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  5986. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  5987. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  5988. val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
  5989. val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
  5990. val |= CPMU_LNK_AWARE_MACCLK_6_25;
  5991. tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
  5992. val = tr32(TG3_CPMU_HST_ACC);
  5993. val &= ~CPMU_HST_ACC_MACCLK_MASK;
  5994. val |= CPMU_HST_ACC_MACCLK_6_25;
  5995. tw32(TG3_CPMU_HST_ACC, val);
  5996. }
  5997. /* This works around an issue with Athlon chipsets on
  5998. * B3 tigon3 silicon. This bit has no effect on any
  5999. * other revision. But do not set this on PCI Express
  6000. * chips and don't even touch the clocks if the CPMU is present.
  6001. */
  6002. if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
  6003. if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  6004. tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  6005. tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  6006. }
  6007. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  6008. (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  6009. val = tr32(TG3PCI_PCISTATE);
  6010. val |= PCISTATE_RETRY_SAME_DMA;
  6011. tw32(TG3PCI_PCISTATE, val);
  6012. }
  6013. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  6014. /* Allow reads and writes to the
  6015. * APE register and memory space.
  6016. */
  6017. val = tr32(TG3PCI_PCISTATE);
  6018. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  6019. PCISTATE_ALLOW_APE_SHMEM_WR;
  6020. tw32(TG3PCI_PCISTATE, val);
  6021. }
  6022. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
  6023. /* Enable some hw fixes. */
  6024. val = tr32(TG3PCI_MSI_DATA);
  6025. val |= (1 << 26) | (1 << 28) | (1 << 29);
  6026. tw32(TG3PCI_MSI_DATA, val);
  6027. }
  6028. /* Descriptor ring init may make accesses to the
  6029. * NIC SRAM area to setup the TX descriptors, so we
  6030. * can only do this after the hardware has been
  6031. * successfully reset.
  6032. */
  6033. err = tg3_init_rings(tp);
  6034. if (err)
  6035. return err;
  6036. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
  6037. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
  6038. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
  6039. /* This value is determined during the probe time DMA
  6040. * engine test, tg3_test_dma.
  6041. */
  6042. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  6043. }
  6044. tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  6045. GRC_MODE_4X_NIC_SEND_RINGS |
  6046. GRC_MODE_NO_TX_PHDR_CSUM |
  6047. GRC_MODE_NO_RX_PHDR_CSUM);
  6048. tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  6049. /* Pseudo-header checksum is done by hardware logic and not
  6050. * the offload processers, so make the chip do the pseudo-
  6051. * header checksums on receive. For transmit it is more
  6052. * convenient to do the pseudo-header checksum in software
  6053. * as Linux does that on transmit for us in all cases.
  6054. */
  6055. tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  6056. tw32(GRC_MODE,
  6057. tp->grc_mode |
  6058. (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
  6059. /* Setup the timer prescalar register. Clock is always 66Mhz. */
  6060. val = tr32(GRC_MISC_CFG);
  6061. val &= ~0xff;
  6062. val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
  6063. tw32(GRC_MISC_CFG, val);
  6064. /* Initialize MBUF/DESC pool. */
  6065. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  6066. /* Do nothing. */
  6067. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  6068. tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  6069. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  6070. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  6071. else
  6072. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  6073. tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  6074. tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  6075. }
  6076. else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  6077. int fw_len;
  6078. fw_len = (TG3_TSO5_FW_TEXT_LEN +
  6079. TG3_TSO5_FW_RODATA_LEN +
  6080. TG3_TSO5_FW_DATA_LEN +
  6081. TG3_TSO5_FW_SBSS_LEN +
  6082. TG3_TSO5_FW_BSS_LEN);
  6083. fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  6084. tw32(BUFMGR_MB_POOL_ADDR,
  6085. NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  6086. tw32(BUFMGR_MB_POOL_SIZE,
  6087. NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  6088. }
  6089. if (tp->dev->mtu <= ETH_DATA_LEN) {
  6090. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  6091. tp->bufmgr_config.mbuf_read_dma_low_water);
  6092. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  6093. tp->bufmgr_config.mbuf_mac_rx_low_water);
  6094. tw32(BUFMGR_MB_HIGH_WATER,
  6095. tp->bufmgr_config.mbuf_high_water);
  6096. } else {
  6097. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  6098. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  6099. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  6100. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  6101. tw32(BUFMGR_MB_HIGH_WATER,
  6102. tp->bufmgr_config.mbuf_high_water_jumbo);
  6103. }
  6104. tw32(BUFMGR_DMA_LOW_WATER,
  6105. tp->bufmgr_config.dma_low_water);
  6106. tw32(BUFMGR_DMA_HIGH_WATER,
  6107. tp->bufmgr_config.dma_high_water);
  6108. tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
  6109. for (i = 0; i < 2000; i++) {
  6110. if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  6111. break;
  6112. udelay(10);
  6113. }
  6114. if (i >= 2000) {
  6115. printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
  6116. tp->dev->name);
  6117. return -ENODEV;
  6118. }
  6119. /* Setup replenish threshold. */
  6120. val = tp->rx_pending / 8;
  6121. if (val == 0)
  6122. val = 1;
  6123. else if (val > tp->rx_std_max_post)
  6124. val = tp->rx_std_max_post;
  6125. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  6126. if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
  6127. tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
  6128. if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
  6129. val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
  6130. }
  6131. tw32(RCVBDI_STD_THRESH, val);
  6132. /* Initialize TG3_BDINFO's at:
  6133. * RCVDBDI_STD_BD: standard eth size rx ring
  6134. * RCVDBDI_JUMBO_BD: jumbo frame rx ring
  6135. * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
  6136. *
  6137. * like so:
  6138. * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
  6139. * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
  6140. * ring attribute flags
  6141. * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
  6142. *
  6143. * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  6144. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  6145. *
  6146. * The size of each ring is fixed in the firmware, but the location is
  6147. * configurable.
  6148. */
  6149. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6150. ((u64) tp->rx_std_mapping >> 32));
  6151. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  6152. ((u64) tp->rx_std_mapping & 0xffffffff));
  6153. tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  6154. NIC_SRAM_RX_BUFFER_DESC);
  6155. /* Don't even try to program the JUMBO/MINI buffer descriptor
  6156. * configs on 5705.
  6157. */
  6158. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  6159. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  6160. RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
  6161. } else {
  6162. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  6163. RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  6164. tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  6165. BDINFO_FLAGS_DISABLED);
  6166. /* Setup replenish threshold. */
  6167. tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
  6168. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  6169. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6170. ((u64) tp->rx_jumbo_mapping >> 32));
  6171. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  6172. ((u64) tp->rx_jumbo_mapping & 0xffffffff));
  6173. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  6174. RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  6175. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  6176. NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  6177. } else {
  6178. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  6179. BDINFO_FLAGS_DISABLED);
  6180. }
  6181. }
  6182. /* There is only one send ring on 5705/5750, no need to explicitly
  6183. * disable the others.
  6184. */
  6185. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6186. /* Clear out send RCB ring in SRAM. */
  6187. for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
  6188. tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  6189. BDINFO_FLAGS_DISABLED);
  6190. }
  6191. tp->tx_prod = 0;
  6192. tp->tx_cons = 0;
  6193. tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  6194. tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  6195. tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
  6196. tp->tx_desc_mapping,
  6197. (TG3_TX_RING_SIZE <<
  6198. BDINFO_FLAGS_MAXLEN_SHIFT),
  6199. NIC_SRAM_TX_BUFFER_DESC);
  6200. /* There is only one receive return ring on 5705/5750, no need
  6201. * to explicitly disable the others.
  6202. */
  6203. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6204. for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
  6205. i += TG3_BDINFO_SIZE) {
  6206. tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  6207. BDINFO_FLAGS_DISABLED);
  6208. }
  6209. }
  6210. tp->rx_rcb_ptr = 0;
  6211. tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
  6212. tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
  6213. tp->rx_rcb_mapping,
  6214. (TG3_RX_RCB_RING_SIZE(tp) <<
  6215. BDINFO_FLAGS_MAXLEN_SHIFT),
  6216. 0);
  6217. tp->rx_std_ptr = tp->rx_pending;
  6218. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  6219. tp->rx_std_ptr);
  6220. tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
  6221. tp->rx_jumbo_pending : 0;
  6222. tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  6223. tp->rx_jumbo_ptr);
  6224. /* Initialize MAC address and backoff seed. */
  6225. __tg3_set_mac_addr(tp, 0);
  6226. /* MTU + ethernet header + FCS + optional VLAN tag */
  6227. tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
  6228. /* The slot time is changed by tg3_setup_phy if we
  6229. * run at gigabit with half duplex.
  6230. */
  6231. tw32(MAC_TX_LENGTHS,
  6232. (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  6233. (6 << TX_LENGTHS_IPG_SHIFT) |
  6234. (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  6235. /* Receive rules. */
  6236. tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  6237. tw32(RCVLPC_CONFIG, 0x0181);
  6238. /* Calculate RDMAC_MODE setting early, we need it to determine
  6239. * the RCVLPC_STATE_ENABLE mask.
  6240. */
  6241. rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  6242. RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  6243. RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  6244. RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  6245. RDMAC_MODE_LNGREAD_ENAB);
  6246. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  6247. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  6248. rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
  6249. RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
  6250. RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
  6251. /* If statement applies to 5705 and 5750 PCI devices only */
  6252. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  6253. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  6254. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
  6255. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
  6256. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  6257. rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  6258. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  6259. !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
  6260. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  6261. }
  6262. }
  6263. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
  6264. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  6265. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  6266. rdmac_mode |= (1 << 27);
  6267. /* Receive/send statistics. */
  6268. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  6269. val = tr32(RCVLPC_STATS_ENABLE);
  6270. val &= ~RCVLPC_STATSENAB_DACK_FIX;
  6271. tw32(RCVLPC_STATS_ENABLE, val);
  6272. } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  6273. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  6274. val = tr32(RCVLPC_STATS_ENABLE);
  6275. val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  6276. tw32(RCVLPC_STATS_ENABLE, val);
  6277. } else {
  6278. tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  6279. }
  6280. tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  6281. tw32(SNDDATAI_STATSENAB, 0xffffff);
  6282. tw32(SNDDATAI_STATSCTRL,
  6283. (SNDDATAI_SCTRL_ENABLE |
  6284. SNDDATAI_SCTRL_FASTUPD));
  6285. /* Setup host coalescing engine. */
  6286. tw32(HOSTCC_MODE, 0);
  6287. for (i = 0; i < 2000; i++) {
  6288. if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  6289. break;
  6290. udelay(10);
  6291. }
  6292. __tg3_set_coalesce(tp, &tp->coal);
  6293. /* set status block DMA address */
  6294. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6295. ((u64) tp->status_mapping >> 32));
  6296. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  6297. ((u64) tp->status_mapping & 0xffffffff));
  6298. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6299. /* Status/statistics block address. See tg3_timer,
  6300. * the tg3_periodic_fetch_stats call there, and
  6301. * tg3_get_stats to see how this works for 5705/5750 chips.
  6302. */
  6303. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6304. ((u64) tp->stats_mapping >> 32));
  6305. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  6306. ((u64) tp->stats_mapping & 0xffffffff));
  6307. tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  6308. tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  6309. }
  6310. tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  6311. tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  6312. tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  6313. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6314. tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  6315. /* Clear statistics/status block in chip, and status block in ram. */
  6316. for (i = NIC_SRAM_STATS_BLK;
  6317. i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  6318. i += sizeof(u32)) {
  6319. tg3_write_mem(tp, i, 0);
  6320. udelay(40);
  6321. }
  6322. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  6323. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  6324. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  6325. /* reset to prevent losing 1st rx packet intermittently */
  6326. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  6327. udelay(10);
  6328. }
  6329. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  6330. tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  6331. else
  6332. tp->mac_mode = 0;
  6333. tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  6334. MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
  6335. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  6336. !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  6337. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
  6338. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  6339. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  6340. udelay(40);
  6341. /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
  6342. * If TG3_FLG2_IS_NIC is zero, we should read the
  6343. * register to preserve the GPIO settings for LOMs. The GPIOs,
  6344. * whether used as inputs or outputs, are set by boot code after
  6345. * reset.
  6346. */
  6347. if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
  6348. u32 gpio_mask;
  6349. gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
  6350. GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
  6351. GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
  6352. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  6353. gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
  6354. GRC_LCLCTRL_GPIO_OUTPUT3;
  6355. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  6356. gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
  6357. tp->grc_local_ctrl &= ~gpio_mask;
  6358. tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
  6359. /* GPIO1 must be driven high for eeprom write protect */
  6360. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
  6361. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  6362. GRC_LCLCTRL_GPIO_OUTPUT1);
  6363. }
  6364. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  6365. udelay(100);
  6366. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
  6367. tp->last_tag = 0;
  6368. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6369. tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
  6370. udelay(40);
  6371. }
  6372. val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  6373. WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  6374. WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  6375. WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  6376. WDMAC_MODE_LNGREAD_ENAB);
  6377. /* If statement applies to 5705 and 5750 PCI devices only */
  6378. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  6379. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  6380. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
  6381. if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
  6382. (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
  6383. tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
  6384. /* nothing */
  6385. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  6386. !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  6387. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  6388. val |= WDMAC_MODE_RX_ACCEL;
  6389. }
  6390. }
  6391. /* Enable host coalescing bug fix */
  6392. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
  6393. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
  6394. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
  6395. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) ||
  6396. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785))
  6397. val |= WDMAC_MODE_STATUS_TAG_FIX;
  6398. tw32_f(WDMAC_MODE, val);
  6399. udelay(40);
  6400. if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  6401. u16 pcix_cmd;
  6402. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6403. &pcix_cmd);
  6404. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
  6405. pcix_cmd &= ~PCI_X_CMD_MAX_READ;
  6406. pcix_cmd |= PCI_X_CMD_READ_2K;
  6407. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  6408. pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
  6409. pcix_cmd |= PCI_X_CMD_READ_2K;
  6410. }
  6411. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6412. pcix_cmd);
  6413. }
  6414. tw32_f(RDMAC_MODE, rdmac_mode);
  6415. udelay(40);
  6416. tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  6417. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6418. tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  6419. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  6420. tw32(SNDDATAC_MODE,
  6421. SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
  6422. else
  6423. tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  6424. tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  6425. tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  6426. tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
  6427. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  6428. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  6429. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
  6430. tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
  6431. tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  6432. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  6433. err = tg3_load_5701_a0_firmware_fix(tp);
  6434. if (err)
  6435. return err;
  6436. }
  6437. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  6438. err = tg3_load_tso_firmware(tp);
  6439. if (err)
  6440. return err;
  6441. }
  6442. tp->tx_mode = TX_MODE_ENABLE;
  6443. tw32_f(MAC_TX_MODE, tp->tx_mode);
  6444. udelay(100);
  6445. tp->rx_mode = RX_MODE_ENABLE;
  6446. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  6447. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  6448. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  6449. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  6450. tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
  6451. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6452. udelay(10);
  6453. tw32(MAC_LED_CTRL, tp->led_ctrl);
  6454. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  6455. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  6456. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  6457. udelay(10);
  6458. }
  6459. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6460. udelay(10);
  6461. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  6462. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
  6463. !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
  6464. /* Set drive transmission level to 1.2V */
  6465. /* only if the signal pre-emphasis bit is not set */
  6466. val = tr32(MAC_SERDES_CFG);
  6467. val &= 0xfffff000;
  6468. val |= 0x880;
  6469. tw32(MAC_SERDES_CFG, val);
  6470. }
  6471. if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
  6472. tw32(MAC_SERDES_CFG, 0x616000);
  6473. }
  6474. /* Prevent chip from dropping frames when flow control
  6475. * is enabled.
  6476. */
  6477. tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
  6478. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
  6479. (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  6480. /* Use hardware link auto-negotiation */
  6481. tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
  6482. }
  6483. if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
  6484. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  6485. u32 tmp;
  6486. tmp = tr32(SERDES_RX_CTRL);
  6487. tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
  6488. tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
  6489. tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
  6490. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  6491. }
  6492. if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
  6493. if (tp->link_config.phy_is_low_power) {
  6494. tp->link_config.phy_is_low_power = 0;
  6495. tp->link_config.speed = tp->link_config.orig_speed;
  6496. tp->link_config.duplex = tp->link_config.orig_duplex;
  6497. tp->link_config.autoneg = tp->link_config.orig_autoneg;
  6498. }
  6499. err = tg3_setup_phy(tp, 0);
  6500. if (err)
  6501. return err;
  6502. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  6503. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
  6504. u32 tmp;
  6505. /* Clear CRC stats. */
  6506. if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
  6507. tg3_writephy(tp, MII_TG3_TEST1,
  6508. tmp | MII_TG3_TEST1_CRC_EN);
  6509. tg3_readphy(tp, 0x14, &tmp);
  6510. }
  6511. }
  6512. }
  6513. __tg3_set_rx_mode(tp->dev);
  6514. /* Initialize receive rules. */
  6515. tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
  6516. tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  6517. tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
  6518. tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  6519. if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  6520. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  6521. limit = 8;
  6522. else
  6523. limit = 16;
  6524. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
  6525. limit -= 4;
  6526. switch (limit) {
  6527. case 16:
  6528. tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
  6529. case 15:
  6530. tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
  6531. case 14:
  6532. tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
  6533. case 13:
  6534. tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
  6535. case 12:
  6536. tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
  6537. case 11:
  6538. tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
  6539. case 10:
  6540. tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
  6541. case 9:
  6542. tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
  6543. case 8:
  6544. tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
  6545. case 7:
  6546. tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
  6547. case 6:
  6548. tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
  6549. case 5:
  6550. tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
  6551. case 4:
  6552. /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
  6553. case 3:
  6554. /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
  6555. case 2:
  6556. case 1:
  6557. default:
  6558. break;
  6559. }
  6560. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  6561. /* Write our heartbeat update interval to APE. */
  6562. tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
  6563. APE_HOST_HEARTBEAT_INT_DISABLE);
  6564. tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
  6565. return 0;
  6566. }
  6567. /* Called at device open time to get the chip ready for
  6568. * packet processing. Invoked with tp->lock held.
  6569. */
  6570. static int tg3_init_hw(struct tg3 *tp, int reset_phy)
  6571. {
  6572. tg3_switch_clocks(tp);
  6573. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  6574. return tg3_reset_hw(tp, reset_phy);
  6575. }
  6576. #define TG3_STAT_ADD32(PSTAT, REG) \
  6577. do { u32 __val = tr32(REG); \
  6578. (PSTAT)->low += __val; \
  6579. if ((PSTAT)->low < __val) \
  6580. (PSTAT)->high += 1; \
  6581. } while (0)
  6582. static void tg3_periodic_fetch_stats(struct tg3 *tp)
  6583. {
  6584. struct tg3_hw_stats *sp = tp->hw_stats;
  6585. if (!netif_carrier_ok(tp->dev))
  6586. return;
  6587. TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  6588. TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  6589. TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  6590. TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  6591. TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  6592. TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  6593. TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  6594. TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  6595. TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  6596. TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  6597. TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  6598. TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  6599. TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  6600. TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  6601. TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  6602. TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  6603. TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  6604. TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  6605. TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  6606. TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  6607. TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  6608. TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  6609. TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  6610. TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  6611. TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  6612. TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  6613. TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  6614. TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
  6615. TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
  6616. TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
  6617. }
  6618. static void tg3_timer(unsigned long __opaque)
  6619. {
  6620. struct tg3 *tp = (struct tg3 *) __opaque;
  6621. if (tp->irq_sync)
  6622. goto restart_timer;
  6623. spin_lock(&tp->lock);
  6624. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  6625. /* All of this garbage is because when using non-tagged
  6626. * IRQ status the mailbox/status_block protocol the chip
  6627. * uses with the cpu is race prone.
  6628. */
  6629. if (tp->hw_status->status & SD_STATUS_UPDATED) {
  6630. tw32(GRC_LOCAL_CTRL,
  6631. tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  6632. } else {
  6633. tw32(HOSTCC_MODE, tp->coalesce_mode |
  6634. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  6635. }
  6636. if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  6637. tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
  6638. spin_unlock(&tp->lock);
  6639. schedule_work(&tp->reset_task);
  6640. return;
  6641. }
  6642. }
  6643. /* This part only runs once per second. */
  6644. if (!--tp->timer_counter) {
  6645. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  6646. tg3_periodic_fetch_stats(tp);
  6647. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  6648. u32 mac_stat;
  6649. int phy_event;
  6650. mac_stat = tr32(MAC_STATUS);
  6651. phy_event = 0;
  6652. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
  6653. if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  6654. phy_event = 1;
  6655. } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  6656. phy_event = 1;
  6657. if (phy_event)
  6658. tg3_setup_phy(tp, 0);
  6659. } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
  6660. u32 mac_stat = tr32(MAC_STATUS);
  6661. int need_setup = 0;
  6662. if (netif_carrier_ok(tp->dev) &&
  6663. (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  6664. need_setup = 1;
  6665. }
  6666. if (! netif_carrier_ok(tp->dev) &&
  6667. (mac_stat & (MAC_STATUS_PCS_SYNCED |
  6668. MAC_STATUS_SIGNAL_DET))) {
  6669. need_setup = 1;
  6670. }
  6671. if (need_setup) {
  6672. if (!tp->serdes_counter) {
  6673. tw32_f(MAC_MODE,
  6674. (tp->mac_mode &
  6675. ~MAC_MODE_PORT_MODE_MASK));
  6676. udelay(40);
  6677. tw32_f(MAC_MODE, tp->mac_mode);
  6678. udelay(40);
  6679. }
  6680. tg3_setup_phy(tp, 0);
  6681. }
  6682. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  6683. tg3_serdes_parallel_detect(tp);
  6684. tp->timer_counter = tp->timer_multiplier;
  6685. }
  6686. /* Heartbeat is only sent once every 2 seconds.
  6687. *
  6688. * The heartbeat is to tell the ASF firmware that the host
  6689. * driver is still alive. In the event that the OS crashes,
  6690. * ASF needs to reset the hardware to free up the FIFO space
  6691. * that may be filled with rx packets destined for the host.
  6692. * If the FIFO is full, ASF will no longer function properly.
  6693. *
  6694. * Unintended resets have been reported on real time kernels
  6695. * where the timer doesn't run on time. Netpoll will also have
  6696. * same problem.
  6697. *
  6698. * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
  6699. * to check the ring condition when the heartbeat is expiring
  6700. * before doing the reset. This will prevent most unintended
  6701. * resets.
  6702. */
  6703. if (!--tp->asf_counter) {
  6704. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
  6705. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
  6706. tg3_wait_for_event_ack(tp);
  6707. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
  6708. FWCMD_NICDRV_ALIVE3);
  6709. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  6710. /* 5 seconds timeout */
  6711. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
  6712. tg3_generate_fw_event(tp);
  6713. }
  6714. tp->asf_counter = tp->asf_multiplier;
  6715. }
  6716. spin_unlock(&tp->lock);
  6717. restart_timer:
  6718. tp->timer.expires = jiffies + tp->timer_offset;
  6719. add_timer(&tp->timer);
  6720. }
  6721. static int tg3_request_irq(struct tg3 *tp)
  6722. {
  6723. irq_handler_t fn;
  6724. unsigned long flags;
  6725. struct net_device *dev = tp->dev;
  6726. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6727. fn = tg3_msi;
  6728. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  6729. fn = tg3_msi_1shot;
  6730. flags = IRQF_SAMPLE_RANDOM;
  6731. } else {
  6732. fn = tg3_interrupt;
  6733. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  6734. fn = tg3_interrupt_tagged;
  6735. flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
  6736. }
  6737. return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
  6738. }
  6739. static int tg3_test_interrupt(struct tg3 *tp)
  6740. {
  6741. struct net_device *dev = tp->dev;
  6742. int err, i, intr_ok = 0;
  6743. if (!netif_running(dev))
  6744. return -ENODEV;
  6745. tg3_disable_ints(tp);
  6746. free_irq(tp->pdev->irq, dev);
  6747. err = request_irq(tp->pdev->irq, tg3_test_isr,
  6748. IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
  6749. if (err)
  6750. return err;
  6751. tp->hw_status->status &= ~SD_STATUS_UPDATED;
  6752. tg3_enable_ints(tp);
  6753. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  6754. HOSTCC_MODE_NOW);
  6755. for (i = 0; i < 5; i++) {
  6756. u32 int_mbox, misc_host_ctrl;
  6757. int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
  6758. TG3_64BIT_REG_LOW);
  6759. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  6760. if ((int_mbox != 0) ||
  6761. (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
  6762. intr_ok = 1;
  6763. break;
  6764. }
  6765. msleep(10);
  6766. }
  6767. tg3_disable_ints(tp);
  6768. free_irq(tp->pdev->irq, dev);
  6769. err = tg3_request_irq(tp);
  6770. if (err)
  6771. return err;
  6772. if (intr_ok)
  6773. return 0;
  6774. return -EIO;
  6775. }
  6776. /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
  6777. * successfully restored
  6778. */
  6779. static int tg3_test_msi(struct tg3 *tp)
  6780. {
  6781. struct net_device *dev = tp->dev;
  6782. int err;
  6783. u16 pci_cmd;
  6784. if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
  6785. return 0;
  6786. /* Turn off SERR reporting in case MSI terminates with Master
  6787. * Abort.
  6788. */
  6789. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  6790. pci_write_config_word(tp->pdev, PCI_COMMAND,
  6791. pci_cmd & ~PCI_COMMAND_SERR);
  6792. err = tg3_test_interrupt(tp);
  6793. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  6794. if (!err)
  6795. return 0;
  6796. /* other failures */
  6797. if (err != -EIO)
  6798. return err;
  6799. /* MSI test failed, go back to INTx mode */
  6800. printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
  6801. "switching to INTx mode. Please report this failure to "
  6802. "the PCI maintainer and include system chipset information.\n",
  6803. tp->dev->name);
  6804. free_irq(tp->pdev->irq, dev);
  6805. pci_disable_msi(tp->pdev);
  6806. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6807. err = tg3_request_irq(tp);
  6808. if (err)
  6809. return err;
  6810. /* Need to reset the chip because the MSI cycle may have terminated
  6811. * with Master Abort.
  6812. */
  6813. tg3_full_lock(tp, 1);
  6814. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6815. err = tg3_init_hw(tp, 1);
  6816. tg3_full_unlock(tp);
  6817. if (err)
  6818. free_irq(tp->pdev->irq, dev);
  6819. return err;
  6820. }
  6821. static int tg3_open(struct net_device *dev)
  6822. {
  6823. struct tg3 *tp = netdev_priv(dev);
  6824. int err;
  6825. netif_carrier_off(tp->dev);
  6826. err = tg3_set_power_state(tp, PCI_D0);
  6827. if (err)
  6828. return err;
  6829. tg3_full_lock(tp, 0);
  6830. tg3_disable_ints(tp);
  6831. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  6832. tg3_full_unlock(tp);
  6833. /* The placement of this call is tied
  6834. * to the setup and use of Host TX descriptors.
  6835. */
  6836. err = tg3_alloc_consistent(tp);
  6837. if (err)
  6838. return err;
  6839. if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
  6840. /* All MSI supporting chips should support tagged
  6841. * status. Assert that this is the case.
  6842. */
  6843. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  6844. printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
  6845. "Not using MSI.\n", tp->dev->name);
  6846. } else if (pci_enable_msi(tp->pdev) == 0) {
  6847. u32 msi_mode;
  6848. msi_mode = tr32(MSGINT_MODE);
  6849. tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
  6850. tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
  6851. }
  6852. }
  6853. err = tg3_request_irq(tp);
  6854. if (err) {
  6855. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6856. pci_disable_msi(tp->pdev);
  6857. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6858. }
  6859. tg3_free_consistent(tp);
  6860. return err;
  6861. }
  6862. napi_enable(&tp->napi);
  6863. tg3_full_lock(tp, 0);
  6864. err = tg3_init_hw(tp, 1);
  6865. if (err) {
  6866. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6867. tg3_free_rings(tp);
  6868. } else {
  6869. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  6870. tp->timer_offset = HZ;
  6871. else
  6872. tp->timer_offset = HZ / 10;
  6873. BUG_ON(tp->timer_offset > HZ);
  6874. tp->timer_counter = tp->timer_multiplier =
  6875. (HZ / tp->timer_offset);
  6876. tp->asf_counter = tp->asf_multiplier =
  6877. ((HZ / tp->timer_offset) * 2);
  6878. init_timer(&tp->timer);
  6879. tp->timer.expires = jiffies + tp->timer_offset;
  6880. tp->timer.data = (unsigned long) tp;
  6881. tp->timer.function = tg3_timer;
  6882. }
  6883. tg3_full_unlock(tp);
  6884. if (err) {
  6885. napi_disable(&tp->napi);
  6886. free_irq(tp->pdev->irq, dev);
  6887. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6888. pci_disable_msi(tp->pdev);
  6889. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6890. }
  6891. tg3_free_consistent(tp);
  6892. return err;
  6893. }
  6894. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6895. err = tg3_test_msi(tp);
  6896. if (err) {
  6897. tg3_full_lock(tp, 0);
  6898. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6899. pci_disable_msi(tp->pdev);
  6900. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6901. }
  6902. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6903. tg3_free_rings(tp);
  6904. tg3_free_consistent(tp);
  6905. tg3_full_unlock(tp);
  6906. napi_disable(&tp->napi);
  6907. return err;
  6908. }
  6909. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6910. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
  6911. u32 val = tr32(PCIE_TRANSACTION_CFG);
  6912. tw32(PCIE_TRANSACTION_CFG,
  6913. val | PCIE_TRANS_CFG_1SHOT_MSI);
  6914. }
  6915. }
  6916. }
  6917. tg3_phy_start(tp);
  6918. tg3_full_lock(tp, 0);
  6919. add_timer(&tp->timer);
  6920. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  6921. tg3_enable_ints(tp);
  6922. tg3_full_unlock(tp);
  6923. netif_start_queue(dev);
  6924. return 0;
  6925. }
  6926. #if 0
  6927. /*static*/ void tg3_dump_state(struct tg3 *tp)
  6928. {
  6929. u32 val32, val32_2, val32_3, val32_4, val32_5;
  6930. u16 val16;
  6931. int i;
  6932. pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
  6933. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
  6934. printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
  6935. val16, val32);
  6936. /* MAC block */
  6937. printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
  6938. tr32(MAC_MODE), tr32(MAC_STATUS));
  6939. printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
  6940. tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
  6941. printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
  6942. tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
  6943. printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
  6944. tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
  6945. /* Send data initiator control block */
  6946. printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
  6947. tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
  6948. printk(" SNDDATAI_STATSCTRL[%08x]\n",
  6949. tr32(SNDDATAI_STATSCTRL));
  6950. /* Send data completion control block */
  6951. printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
  6952. /* Send BD ring selector block */
  6953. printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
  6954. tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
  6955. /* Send BD initiator control block */
  6956. printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
  6957. tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
  6958. /* Send BD completion control block */
  6959. printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
  6960. /* Receive list placement control block */
  6961. printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
  6962. tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
  6963. printk(" RCVLPC_STATSCTRL[%08x]\n",
  6964. tr32(RCVLPC_STATSCTRL));
  6965. /* Receive data and receive BD initiator control block */
  6966. printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
  6967. tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
  6968. /* Receive data completion control block */
  6969. printk("DEBUG: RCVDCC_MODE[%08x]\n",
  6970. tr32(RCVDCC_MODE));
  6971. /* Receive BD initiator control block */
  6972. printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
  6973. tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
  6974. /* Receive BD completion control block */
  6975. printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
  6976. tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
  6977. /* Receive list selector control block */
  6978. printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
  6979. tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
  6980. /* Mbuf cluster free block */
  6981. printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
  6982. tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
  6983. /* Host coalescing control block */
  6984. printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
  6985. tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
  6986. printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
  6987. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6988. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  6989. printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
  6990. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6991. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  6992. printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
  6993. tr32(HOSTCC_STATS_BLK_NIC_ADDR));
  6994. printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
  6995. tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
  6996. /* Memory arbiter control block */
  6997. printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
  6998. tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
  6999. /* Buffer manager control block */
  7000. printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
  7001. tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
  7002. printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
  7003. tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
  7004. printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
  7005. "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
  7006. tr32(BUFMGR_DMA_DESC_POOL_ADDR),
  7007. tr32(BUFMGR_DMA_DESC_POOL_SIZE));
  7008. /* Read DMA control block */
  7009. printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
  7010. tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
  7011. /* Write DMA control block */
  7012. printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
  7013. tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
  7014. /* DMA completion block */
  7015. printk("DEBUG: DMAC_MODE[%08x]\n",
  7016. tr32(DMAC_MODE));
  7017. /* GRC block */
  7018. printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
  7019. tr32(GRC_MODE), tr32(GRC_MISC_CFG));
  7020. printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
  7021. tr32(GRC_LOCAL_CTRL));
  7022. /* TG3_BDINFOs */
  7023. printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
  7024. tr32(RCVDBDI_JUMBO_BD + 0x0),
  7025. tr32(RCVDBDI_JUMBO_BD + 0x4),
  7026. tr32(RCVDBDI_JUMBO_BD + 0x8),
  7027. tr32(RCVDBDI_JUMBO_BD + 0xc));
  7028. printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
  7029. tr32(RCVDBDI_STD_BD + 0x0),
  7030. tr32(RCVDBDI_STD_BD + 0x4),
  7031. tr32(RCVDBDI_STD_BD + 0x8),
  7032. tr32(RCVDBDI_STD_BD + 0xc));
  7033. printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
  7034. tr32(RCVDBDI_MINI_BD + 0x0),
  7035. tr32(RCVDBDI_MINI_BD + 0x4),
  7036. tr32(RCVDBDI_MINI_BD + 0x8),
  7037. tr32(RCVDBDI_MINI_BD + 0xc));
  7038. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
  7039. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
  7040. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
  7041. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
  7042. printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
  7043. val32, val32_2, val32_3, val32_4);
  7044. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
  7045. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
  7046. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
  7047. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
  7048. printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
  7049. val32, val32_2, val32_3, val32_4);
  7050. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
  7051. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
  7052. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
  7053. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
  7054. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
  7055. printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
  7056. val32, val32_2, val32_3, val32_4, val32_5);
  7057. /* SW status block */
  7058. printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
  7059. tp->hw_status->status,
  7060. tp->hw_status->status_tag,
  7061. tp->hw_status->rx_jumbo_consumer,
  7062. tp->hw_status->rx_consumer,
  7063. tp->hw_status->rx_mini_consumer,
  7064. tp->hw_status->idx[0].rx_producer,
  7065. tp->hw_status->idx[0].tx_consumer);
  7066. /* SW statistics block */
  7067. printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
  7068. ((u32 *)tp->hw_stats)[0],
  7069. ((u32 *)tp->hw_stats)[1],
  7070. ((u32 *)tp->hw_stats)[2],
  7071. ((u32 *)tp->hw_stats)[3]);
  7072. /* Mailboxes */
  7073. printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
  7074. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
  7075. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
  7076. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
  7077. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
  7078. /* NIC side send descriptors. */
  7079. for (i = 0; i < 6; i++) {
  7080. unsigned long txd;
  7081. txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
  7082. + (i * sizeof(struct tg3_tx_buffer_desc));
  7083. printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
  7084. i,
  7085. readl(txd + 0x0), readl(txd + 0x4),
  7086. readl(txd + 0x8), readl(txd + 0xc));
  7087. }
  7088. /* NIC side RX descriptors. */
  7089. for (i = 0; i < 6; i++) {
  7090. unsigned long rxd;
  7091. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
  7092. + (i * sizeof(struct tg3_rx_buffer_desc));
  7093. printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
  7094. i,
  7095. readl(rxd + 0x0), readl(rxd + 0x4),
  7096. readl(rxd + 0x8), readl(rxd + 0xc));
  7097. rxd += (4 * sizeof(u32));
  7098. printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
  7099. i,
  7100. readl(rxd + 0x0), readl(rxd + 0x4),
  7101. readl(rxd + 0x8), readl(rxd + 0xc));
  7102. }
  7103. for (i = 0; i < 6; i++) {
  7104. unsigned long rxd;
  7105. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
  7106. + (i * sizeof(struct tg3_rx_buffer_desc));
  7107. printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
  7108. i,
  7109. readl(rxd + 0x0), readl(rxd + 0x4),
  7110. readl(rxd + 0x8), readl(rxd + 0xc));
  7111. rxd += (4 * sizeof(u32));
  7112. printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
  7113. i,
  7114. readl(rxd + 0x0), readl(rxd + 0x4),
  7115. readl(rxd + 0x8), readl(rxd + 0xc));
  7116. }
  7117. }
  7118. #endif
  7119. static struct net_device_stats *tg3_get_stats(struct net_device *);
  7120. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
  7121. static int tg3_close(struct net_device *dev)
  7122. {
  7123. struct tg3 *tp = netdev_priv(dev);
  7124. napi_disable(&tp->napi);
  7125. cancel_work_sync(&tp->reset_task);
  7126. netif_stop_queue(dev);
  7127. del_timer_sync(&tp->timer);
  7128. tg3_full_lock(tp, 1);
  7129. #if 0
  7130. tg3_dump_state(tp);
  7131. #endif
  7132. tg3_disable_ints(tp);
  7133. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7134. tg3_free_rings(tp);
  7135. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  7136. tg3_full_unlock(tp);
  7137. free_irq(tp->pdev->irq, dev);
  7138. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  7139. pci_disable_msi(tp->pdev);
  7140. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  7141. }
  7142. memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
  7143. sizeof(tp->net_stats_prev));
  7144. memcpy(&tp->estats_prev, tg3_get_estats(tp),
  7145. sizeof(tp->estats_prev));
  7146. tg3_free_consistent(tp);
  7147. tg3_set_power_state(tp, PCI_D3hot);
  7148. netif_carrier_off(tp->dev);
  7149. return 0;
  7150. }
  7151. static inline unsigned long get_stat64(tg3_stat64_t *val)
  7152. {
  7153. unsigned long ret;
  7154. #if (BITS_PER_LONG == 32)
  7155. ret = val->low;
  7156. #else
  7157. ret = ((u64)val->high << 32) | ((u64)val->low);
  7158. #endif
  7159. return ret;
  7160. }
  7161. static inline u64 get_estat64(tg3_stat64_t *val)
  7162. {
  7163. return ((u64)val->high << 32) | ((u64)val->low);
  7164. }
  7165. static unsigned long calc_crc_errors(struct tg3 *tp)
  7166. {
  7167. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  7168. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  7169. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  7170. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  7171. u32 val;
  7172. spin_lock_bh(&tp->lock);
  7173. if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
  7174. tg3_writephy(tp, MII_TG3_TEST1,
  7175. val | MII_TG3_TEST1_CRC_EN);
  7176. tg3_readphy(tp, 0x14, &val);
  7177. } else
  7178. val = 0;
  7179. spin_unlock_bh(&tp->lock);
  7180. tp->phy_crc_errors += val;
  7181. return tp->phy_crc_errors;
  7182. }
  7183. return get_stat64(&hw_stats->rx_fcs_errors);
  7184. }
  7185. #define ESTAT_ADD(member) \
  7186. estats->member = old_estats->member + \
  7187. get_estat64(&hw_stats->member)
  7188. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
  7189. {
  7190. struct tg3_ethtool_stats *estats = &tp->estats;
  7191. struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
  7192. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  7193. if (!hw_stats)
  7194. return old_estats;
  7195. ESTAT_ADD(rx_octets);
  7196. ESTAT_ADD(rx_fragments);
  7197. ESTAT_ADD(rx_ucast_packets);
  7198. ESTAT_ADD(rx_mcast_packets);
  7199. ESTAT_ADD(rx_bcast_packets);
  7200. ESTAT_ADD(rx_fcs_errors);
  7201. ESTAT_ADD(rx_align_errors);
  7202. ESTAT_ADD(rx_xon_pause_rcvd);
  7203. ESTAT_ADD(rx_xoff_pause_rcvd);
  7204. ESTAT_ADD(rx_mac_ctrl_rcvd);
  7205. ESTAT_ADD(rx_xoff_entered);
  7206. ESTAT_ADD(rx_frame_too_long_errors);
  7207. ESTAT_ADD(rx_jabbers);
  7208. ESTAT_ADD(rx_undersize_packets);
  7209. ESTAT_ADD(rx_in_length_errors);
  7210. ESTAT_ADD(rx_out_length_errors);
  7211. ESTAT_ADD(rx_64_or_less_octet_packets);
  7212. ESTAT_ADD(rx_65_to_127_octet_packets);
  7213. ESTAT_ADD(rx_128_to_255_octet_packets);
  7214. ESTAT_ADD(rx_256_to_511_octet_packets);
  7215. ESTAT_ADD(rx_512_to_1023_octet_packets);
  7216. ESTAT_ADD(rx_1024_to_1522_octet_packets);
  7217. ESTAT_ADD(rx_1523_to_2047_octet_packets);
  7218. ESTAT_ADD(rx_2048_to_4095_octet_packets);
  7219. ESTAT_ADD(rx_4096_to_8191_octet_packets);
  7220. ESTAT_ADD(rx_8192_to_9022_octet_packets);
  7221. ESTAT_ADD(tx_octets);
  7222. ESTAT_ADD(tx_collisions);
  7223. ESTAT_ADD(tx_xon_sent);
  7224. ESTAT_ADD(tx_xoff_sent);
  7225. ESTAT_ADD(tx_flow_control);
  7226. ESTAT_ADD(tx_mac_errors);
  7227. ESTAT_ADD(tx_single_collisions);
  7228. ESTAT_ADD(tx_mult_collisions);
  7229. ESTAT_ADD(tx_deferred);
  7230. ESTAT_ADD(tx_excessive_collisions);
  7231. ESTAT_ADD(tx_late_collisions);
  7232. ESTAT_ADD(tx_collide_2times);
  7233. ESTAT_ADD(tx_collide_3times);
  7234. ESTAT_ADD(tx_collide_4times);
  7235. ESTAT_ADD(tx_collide_5times);
  7236. ESTAT_ADD(tx_collide_6times);
  7237. ESTAT_ADD(tx_collide_7times);
  7238. ESTAT_ADD(tx_collide_8times);
  7239. ESTAT_ADD(tx_collide_9times);
  7240. ESTAT_ADD(tx_collide_10times);
  7241. ESTAT_ADD(tx_collide_11times);
  7242. ESTAT_ADD(tx_collide_12times);
  7243. ESTAT_ADD(tx_collide_13times);
  7244. ESTAT_ADD(tx_collide_14times);
  7245. ESTAT_ADD(tx_collide_15times);
  7246. ESTAT_ADD(tx_ucast_packets);
  7247. ESTAT_ADD(tx_mcast_packets);
  7248. ESTAT_ADD(tx_bcast_packets);
  7249. ESTAT_ADD(tx_carrier_sense_errors);
  7250. ESTAT_ADD(tx_discards);
  7251. ESTAT_ADD(tx_errors);
  7252. ESTAT_ADD(dma_writeq_full);
  7253. ESTAT_ADD(dma_write_prioq_full);
  7254. ESTAT_ADD(rxbds_empty);
  7255. ESTAT_ADD(rx_discards);
  7256. ESTAT_ADD(rx_errors);
  7257. ESTAT_ADD(rx_threshold_hit);
  7258. ESTAT_ADD(dma_readq_full);
  7259. ESTAT_ADD(dma_read_prioq_full);
  7260. ESTAT_ADD(tx_comp_queue_full);
  7261. ESTAT_ADD(ring_set_send_prod_index);
  7262. ESTAT_ADD(ring_status_update);
  7263. ESTAT_ADD(nic_irqs);
  7264. ESTAT_ADD(nic_avoided_irqs);
  7265. ESTAT_ADD(nic_tx_threshold_hit);
  7266. return estats;
  7267. }
  7268. static struct net_device_stats *tg3_get_stats(struct net_device *dev)
  7269. {
  7270. struct tg3 *tp = netdev_priv(dev);
  7271. struct net_device_stats *stats = &tp->net_stats;
  7272. struct net_device_stats *old_stats = &tp->net_stats_prev;
  7273. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  7274. if (!hw_stats)
  7275. return old_stats;
  7276. stats->rx_packets = old_stats->rx_packets +
  7277. get_stat64(&hw_stats->rx_ucast_packets) +
  7278. get_stat64(&hw_stats->rx_mcast_packets) +
  7279. get_stat64(&hw_stats->rx_bcast_packets);
  7280. stats->tx_packets = old_stats->tx_packets +
  7281. get_stat64(&hw_stats->tx_ucast_packets) +
  7282. get_stat64(&hw_stats->tx_mcast_packets) +
  7283. get_stat64(&hw_stats->tx_bcast_packets);
  7284. stats->rx_bytes = old_stats->rx_bytes +
  7285. get_stat64(&hw_stats->rx_octets);
  7286. stats->tx_bytes = old_stats->tx_bytes +
  7287. get_stat64(&hw_stats->tx_octets);
  7288. stats->rx_errors = old_stats->rx_errors +
  7289. get_stat64(&hw_stats->rx_errors);
  7290. stats->tx_errors = old_stats->tx_errors +
  7291. get_stat64(&hw_stats->tx_errors) +
  7292. get_stat64(&hw_stats->tx_mac_errors) +
  7293. get_stat64(&hw_stats->tx_carrier_sense_errors) +
  7294. get_stat64(&hw_stats->tx_discards);
  7295. stats->multicast = old_stats->multicast +
  7296. get_stat64(&hw_stats->rx_mcast_packets);
  7297. stats->collisions = old_stats->collisions +
  7298. get_stat64(&hw_stats->tx_collisions);
  7299. stats->rx_length_errors = old_stats->rx_length_errors +
  7300. get_stat64(&hw_stats->rx_frame_too_long_errors) +
  7301. get_stat64(&hw_stats->rx_undersize_packets);
  7302. stats->rx_over_errors = old_stats->rx_over_errors +
  7303. get_stat64(&hw_stats->rxbds_empty);
  7304. stats->rx_frame_errors = old_stats->rx_frame_errors +
  7305. get_stat64(&hw_stats->rx_align_errors);
  7306. stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  7307. get_stat64(&hw_stats->tx_discards);
  7308. stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  7309. get_stat64(&hw_stats->tx_carrier_sense_errors);
  7310. stats->rx_crc_errors = old_stats->rx_crc_errors +
  7311. calc_crc_errors(tp);
  7312. stats->rx_missed_errors = old_stats->rx_missed_errors +
  7313. get_stat64(&hw_stats->rx_discards);
  7314. return stats;
  7315. }
  7316. static inline u32 calc_crc(unsigned char *buf, int len)
  7317. {
  7318. u32 reg;
  7319. u32 tmp;
  7320. int j, k;
  7321. reg = 0xffffffff;
  7322. for (j = 0; j < len; j++) {
  7323. reg ^= buf[j];
  7324. for (k = 0; k < 8; k++) {
  7325. tmp = reg & 0x01;
  7326. reg >>= 1;
  7327. if (tmp) {
  7328. reg ^= 0xedb88320;
  7329. }
  7330. }
  7331. }
  7332. return ~reg;
  7333. }
  7334. static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  7335. {
  7336. /* accept or reject all multicast frames */
  7337. tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  7338. tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  7339. tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  7340. tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  7341. }
  7342. static void __tg3_set_rx_mode(struct net_device *dev)
  7343. {
  7344. struct tg3 *tp = netdev_priv(dev);
  7345. u32 rx_mode;
  7346. rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  7347. RX_MODE_KEEP_VLAN_TAG);
  7348. /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
  7349. * flag clear.
  7350. */
  7351. #if TG3_VLAN_TAG_USED
  7352. if (!tp->vlgrp &&
  7353. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  7354. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  7355. #else
  7356. /* By definition, VLAN is disabled always in this
  7357. * case.
  7358. */
  7359. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  7360. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  7361. #endif
  7362. if (dev->flags & IFF_PROMISC) {
  7363. /* Promiscuous mode. */
  7364. rx_mode |= RX_MODE_PROMISC;
  7365. } else if (dev->flags & IFF_ALLMULTI) {
  7366. /* Accept all multicast. */
  7367. tg3_set_multi (tp, 1);
  7368. } else if (dev->mc_count < 1) {
  7369. /* Reject all multicast. */
  7370. tg3_set_multi (tp, 0);
  7371. } else {
  7372. /* Accept one or more multicast(s). */
  7373. struct dev_mc_list *mclist;
  7374. unsigned int i;
  7375. u32 mc_filter[4] = { 0, };
  7376. u32 regidx;
  7377. u32 bit;
  7378. u32 crc;
  7379. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  7380. i++, mclist = mclist->next) {
  7381. crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
  7382. bit = ~crc & 0x7f;
  7383. regidx = (bit & 0x60) >> 5;
  7384. bit &= 0x1f;
  7385. mc_filter[regidx] |= (1 << bit);
  7386. }
  7387. tw32(MAC_HASH_REG_0, mc_filter[0]);
  7388. tw32(MAC_HASH_REG_1, mc_filter[1]);
  7389. tw32(MAC_HASH_REG_2, mc_filter[2]);
  7390. tw32(MAC_HASH_REG_3, mc_filter[3]);
  7391. }
  7392. if (rx_mode != tp->rx_mode) {
  7393. tp->rx_mode = rx_mode;
  7394. tw32_f(MAC_RX_MODE, rx_mode);
  7395. udelay(10);
  7396. }
  7397. }
  7398. static void tg3_set_rx_mode(struct net_device *dev)
  7399. {
  7400. struct tg3 *tp = netdev_priv(dev);
  7401. if (!netif_running(dev))
  7402. return;
  7403. tg3_full_lock(tp, 0);
  7404. __tg3_set_rx_mode(dev);
  7405. tg3_full_unlock(tp);
  7406. }
  7407. #define TG3_REGDUMP_LEN (32 * 1024)
  7408. static int tg3_get_regs_len(struct net_device *dev)
  7409. {
  7410. return TG3_REGDUMP_LEN;
  7411. }
  7412. static void tg3_get_regs(struct net_device *dev,
  7413. struct ethtool_regs *regs, void *_p)
  7414. {
  7415. u32 *p = _p;
  7416. struct tg3 *tp = netdev_priv(dev);
  7417. u8 *orig_p = _p;
  7418. int i;
  7419. regs->version = 0;
  7420. memset(p, 0, TG3_REGDUMP_LEN);
  7421. if (tp->link_config.phy_is_low_power)
  7422. return;
  7423. tg3_full_lock(tp, 0);
  7424. #define __GET_REG32(reg) (*(p)++ = tr32(reg))
  7425. #define GET_REG32_LOOP(base,len) \
  7426. do { p = (u32 *)(orig_p + (base)); \
  7427. for (i = 0; i < len; i += 4) \
  7428. __GET_REG32((base) + i); \
  7429. } while (0)
  7430. #define GET_REG32_1(reg) \
  7431. do { p = (u32 *)(orig_p + (reg)); \
  7432. __GET_REG32((reg)); \
  7433. } while (0)
  7434. GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
  7435. GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
  7436. GET_REG32_LOOP(MAC_MODE, 0x4f0);
  7437. GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
  7438. GET_REG32_1(SNDDATAC_MODE);
  7439. GET_REG32_LOOP(SNDBDS_MODE, 0x80);
  7440. GET_REG32_LOOP(SNDBDI_MODE, 0x48);
  7441. GET_REG32_1(SNDBDC_MODE);
  7442. GET_REG32_LOOP(RCVLPC_MODE, 0x20);
  7443. GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
  7444. GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
  7445. GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
  7446. GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
  7447. GET_REG32_1(RCVDCC_MODE);
  7448. GET_REG32_LOOP(RCVBDI_MODE, 0x20);
  7449. GET_REG32_LOOP(RCVCC_MODE, 0x14);
  7450. GET_REG32_LOOP(RCVLSC_MODE, 0x08);
  7451. GET_REG32_1(MBFREE_MODE);
  7452. GET_REG32_LOOP(HOSTCC_MODE, 0x100);
  7453. GET_REG32_LOOP(MEMARB_MODE, 0x10);
  7454. GET_REG32_LOOP(BUFMGR_MODE, 0x58);
  7455. GET_REG32_LOOP(RDMAC_MODE, 0x08);
  7456. GET_REG32_LOOP(WDMAC_MODE, 0x08);
  7457. GET_REG32_1(RX_CPU_MODE);
  7458. GET_REG32_1(RX_CPU_STATE);
  7459. GET_REG32_1(RX_CPU_PGMCTR);
  7460. GET_REG32_1(RX_CPU_HWBKPT);
  7461. GET_REG32_1(TX_CPU_MODE);
  7462. GET_REG32_1(TX_CPU_STATE);
  7463. GET_REG32_1(TX_CPU_PGMCTR);
  7464. GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
  7465. GET_REG32_LOOP(FTQ_RESET, 0x120);
  7466. GET_REG32_LOOP(MSGINT_MODE, 0x0c);
  7467. GET_REG32_1(DMAC_MODE);
  7468. GET_REG32_LOOP(GRC_MODE, 0x4c);
  7469. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  7470. GET_REG32_LOOP(NVRAM_CMD, 0x24);
  7471. #undef __GET_REG32
  7472. #undef GET_REG32_LOOP
  7473. #undef GET_REG32_1
  7474. tg3_full_unlock(tp);
  7475. }
  7476. static int tg3_get_eeprom_len(struct net_device *dev)
  7477. {
  7478. struct tg3 *tp = netdev_priv(dev);
  7479. return tp->nvram_size;
  7480. }
  7481. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
  7482. static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
  7483. static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
  7484. static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  7485. {
  7486. struct tg3 *tp = netdev_priv(dev);
  7487. int ret;
  7488. u8 *pd;
  7489. u32 i, offset, len, b_offset, b_count;
  7490. __le32 val;
  7491. if (tp->link_config.phy_is_low_power)
  7492. return -EAGAIN;
  7493. offset = eeprom->offset;
  7494. len = eeprom->len;
  7495. eeprom->len = 0;
  7496. eeprom->magic = TG3_EEPROM_MAGIC;
  7497. if (offset & 3) {
  7498. /* adjustments to start on required 4 byte boundary */
  7499. b_offset = offset & 3;
  7500. b_count = 4 - b_offset;
  7501. if (b_count > len) {
  7502. /* i.e. offset=1 len=2 */
  7503. b_count = len;
  7504. }
  7505. ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
  7506. if (ret)
  7507. return ret;
  7508. memcpy(data, ((char*)&val) + b_offset, b_count);
  7509. len -= b_count;
  7510. offset += b_count;
  7511. eeprom->len += b_count;
  7512. }
  7513. /* read bytes upto the last 4 byte boundary */
  7514. pd = &data[eeprom->len];
  7515. for (i = 0; i < (len - (len & 3)); i += 4) {
  7516. ret = tg3_nvram_read_le(tp, offset + i, &val);
  7517. if (ret) {
  7518. eeprom->len += i;
  7519. return ret;
  7520. }
  7521. memcpy(pd + i, &val, 4);
  7522. }
  7523. eeprom->len += i;
  7524. if (len & 3) {
  7525. /* read last bytes not ending on 4 byte boundary */
  7526. pd = &data[eeprom->len];
  7527. b_count = len & 3;
  7528. b_offset = offset + len - b_count;
  7529. ret = tg3_nvram_read_le(tp, b_offset, &val);
  7530. if (ret)
  7531. return ret;
  7532. memcpy(pd, &val, b_count);
  7533. eeprom->len += b_count;
  7534. }
  7535. return 0;
  7536. }
  7537. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
  7538. static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  7539. {
  7540. struct tg3 *tp = netdev_priv(dev);
  7541. int ret;
  7542. u32 offset, len, b_offset, odd_len;
  7543. u8 *buf;
  7544. __le32 start, end;
  7545. if (tp->link_config.phy_is_low_power)
  7546. return -EAGAIN;
  7547. if (eeprom->magic != TG3_EEPROM_MAGIC)
  7548. return -EINVAL;
  7549. offset = eeprom->offset;
  7550. len = eeprom->len;
  7551. if ((b_offset = (offset & 3))) {
  7552. /* adjustments to start on required 4 byte boundary */
  7553. ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
  7554. if (ret)
  7555. return ret;
  7556. len += b_offset;
  7557. offset &= ~3;
  7558. if (len < 4)
  7559. len = 4;
  7560. }
  7561. odd_len = 0;
  7562. if (len & 3) {
  7563. /* adjustments to end on required 4 byte boundary */
  7564. odd_len = 1;
  7565. len = (len + 3) & ~3;
  7566. ret = tg3_nvram_read_le(tp, offset+len-4, &end);
  7567. if (ret)
  7568. return ret;
  7569. }
  7570. buf = data;
  7571. if (b_offset || odd_len) {
  7572. buf = kmalloc(len, GFP_KERNEL);
  7573. if (!buf)
  7574. return -ENOMEM;
  7575. if (b_offset)
  7576. memcpy(buf, &start, 4);
  7577. if (odd_len)
  7578. memcpy(buf+len-4, &end, 4);
  7579. memcpy(buf + b_offset, data, eeprom->len);
  7580. }
  7581. ret = tg3_nvram_write_block(tp, offset, len, buf);
  7582. if (buf != data)
  7583. kfree(buf);
  7584. return ret;
  7585. }
  7586. static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  7587. {
  7588. struct tg3 *tp = netdev_priv(dev);
  7589. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  7590. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  7591. return -EAGAIN;
  7592. return phy_ethtool_gset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
  7593. }
  7594. cmd->supported = (SUPPORTED_Autoneg);
  7595. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  7596. cmd->supported |= (SUPPORTED_1000baseT_Half |
  7597. SUPPORTED_1000baseT_Full);
  7598. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  7599. cmd->supported |= (SUPPORTED_100baseT_Half |
  7600. SUPPORTED_100baseT_Full |
  7601. SUPPORTED_10baseT_Half |
  7602. SUPPORTED_10baseT_Full |
  7603. SUPPORTED_TP);
  7604. cmd->port = PORT_TP;
  7605. } else {
  7606. cmd->supported |= SUPPORTED_FIBRE;
  7607. cmd->port = PORT_FIBRE;
  7608. }
  7609. cmd->advertising = tp->link_config.advertising;
  7610. if (netif_running(dev)) {
  7611. cmd->speed = tp->link_config.active_speed;
  7612. cmd->duplex = tp->link_config.active_duplex;
  7613. }
  7614. cmd->phy_address = PHY_ADDR;
  7615. cmd->transceiver = 0;
  7616. cmd->autoneg = tp->link_config.autoneg;
  7617. cmd->maxtxpkt = 0;
  7618. cmd->maxrxpkt = 0;
  7619. return 0;
  7620. }
  7621. static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  7622. {
  7623. struct tg3 *tp = netdev_priv(dev);
  7624. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  7625. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  7626. return -EAGAIN;
  7627. return phy_ethtool_sset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
  7628. }
  7629. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
  7630. /* These are the only valid advertisement bits allowed. */
  7631. if (cmd->autoneg == AUTONEG_ENABLE &&
  7632. (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
  7633. ADVERTISED_1000baseT_Full |
  7634. ADVERTISED_Autoneg |
  7635. ADVERTISED_FIBRE)))
  7636. return -EINVAL;
  7637. /* Fiber can only do SPEED_1000. */
  7638. else if ((cmd->autoneg != AUTONEG_ENABLE) &&
  7639. (cmd->speed != SPEED_1000))
  7640. return -EINVAL;
  7641. /* Copper cannot force SPEED_1000. */
  7642. } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
  7643. (cmd->speed == SPEED_1000))
  7644. return -EINVAL;
  7645. else if ((cmd->speed == SPEED_1000) &&
  7646. (tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  7647. return -EINVAL;
  7648. tg3_full_lock(tp, 0);
  7649. tp->link_config.autoneg = cmd->autoneg;
  7650. if (cmd->autoneg == AUTONEG_ENABLE) {
  7651. tp->link_config.advertising = (cmd->advertising |
  7652. ADVERTISED_Autoneg);
  7653. tp->link_config.speed = SPEED_INVALID;
  7654. tp->link_config.duplex = DUPLEX_INVALID;
  7655. } else {
  7656. tp->link_config.advertising = 0;
  7657. tp->link_config.speed = cmd->speed;
  7658. tp->link_config.duplex = cmd->duplex;
  7659. }
  7660. tp->link_config.orig_speed = tp->link_config.speed;
  7661. tp->link_config.orig_duplex = tp->link_config.duplex;
  7662. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  7663. if (netif_running(dev))
  7664. tg3_setup_phy(tp, 1);
  7665. tg3_full_unlock(tp);
  7666. return 0;
  7667. }
  7668. static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  7669. {
  7670. struct tg3 *tp = netdev_priv(dev);
  7671. strcpy(info->driver, DRV_MODULE_NAME);
  7672. strcpy(info->version, DRV_MODULE_VERSION);
  7673. strcpy(info->fw_version, tp->fw_ver);
  7674. strcpy(info->bus_info, pci_name(tp->pdev));
  7675. }
  7676. static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  7677. {
  7678. struct tg3 *tp = netdev_priv(dev);
  7679. if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
  7680. device_can_wakeup(&tp->pdev->dev))
  7681. wol->supported = WAKE_MAGIC;
  7682. else
  7683. wol->supported = 0;
  7684. wol->wolopts = 0;
  7685. if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
  7686. wol->wolopts = WAKE_MAGIC;
  7687. memset(&wol->sopass, 0, sizeof(wol->sopass));
  7688. }
  7689. static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  7690. {
  7691. struct tg3 *tp = netdev_priv(dev);
  7692. struct device *dp = &tp->pdev->dev;
  7693. if (wol->wolopts & ~WAKE_MAGIC)
  7694. return -EINVAL;
  7695. if ((wol->wolopts & WAKE_MAGIC) &&
  7696. !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
  7697. return -EINVAL;
  7698. spin_lock_bh(&tp->lock);
  7699. if (wol->wolopts & WAKE_MAGIC) {
  7700. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  7701. device_set_wakeup_enable(dp, true);
  7702. } else {
  7703. tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  7704. device_set_wakeup_enable(dp, false);
  7705. }
  7706. spin_unlock_bh(&tp->lock);
  7707. return 0;
  7708. }
  7709. static u32 tg3_get_msglevel(struct net_device *dev)
  7710. {
  7711. struct tg3 *tp = netdev_priv(dev);
  7712. return tp->msg_enable;
  7713. }
  7714. static void tg3_set_msglevel(struct net_device *dev, u32 value)
  7715. {
  7716. struct tg3 *tp = netdev_priv(dev);
  7717. tp->msg_enable = value;
  7718. }
  7719. static int tg3_set_tso(struct net_device *dev, u32 value)
  7720. {
  7721. struct tg3 *tp = netdev_priv(dev);
  7722. if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  7723. if (value)
  7724. return -EINVAL;
  7725. return 0;
  7726. }
  7727. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
  7728. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
  7729. if (value) {
  7730. dev->features |= NETIF_F_TSO6;
  7731. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  7732. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  7733. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
  7734. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  7735. dev->features |= NETIF_F_TSO_ECN;
  7736. } else
  7737. dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
  7738. }
  7739. return ethtool_op_set_tso(dev, value);
  7740. }
  7741. static int tg3_nway_reset(struct net_device *dev)
  7742. {
  7743. struct tg3 *tp = netdev_priv(dev);
  7744. int r;
  7745. if (!netif_running(dev))
  7746. return -EAGAIN;
  7747. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  7748. return -EINVAL;
  7749. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  7750. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  7751. return -EAGAIN;
  7752. r = phy_start_aneg(tp->mdio_bus.phy_map[PHY_ADDR]);
  7753. } else {
  7754. u32 bmcr;
  7755. spin_lock_bh(&tp->lock);
  7756. r = -EINVAL;
  7757. tg3_readphy(tp, MII_BMCR, &bmcr);
  7758. if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
  7759. ((bmcr & BMCR_ANENABLE) ||
  7760. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
  7761. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
  7762. BMCR_ANENABLE);
  7763. r = 0;
  7764. }
  7765. spin_unlock_bh(&tp->lock);
  7766. }
  7767. return r;
  7768. }
  7769. static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  7770. {
  7771. struct tg3 *tp = netdev_priv(dev);
  7772. ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
  7773. ering->rx_mini_max_pending = 0;
  7774. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  7775. ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
  7776. else
  7777. ering->rx_jumbo_max_pending = 0;
  7778. ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
  7779. ering->rx_pending = tp->rx_pending;
  7780. ering->rx_mini_pending = 0;
  7781. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  7782. ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  7783. else
  7784. ering->rx_jumbo_pending = 0;
  7785. ering->tx_pending = tp->tx_pending;
  7786. }
  7787. static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  7788. {
  7789. struct tg3 *tp = netdev_priv(dev);
  7790. int irq_sync = 0, err = 0;
  7791. if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
  7792. (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
  7793. (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
  7794. (ering->tx_pending <= MAX_SKB_FRAGS) ||
  7795. ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
  7796. (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
  7797. return -EINVAL;
  7798. if (netif_running(dev)) {
  7799. tg3_phy_stop(tp);
  7800. tg3_netif_stop(tp);
  7801. irq_sync = 1;
  7802. }
  7803. tg3_full_lock(tp, irq_sync);
  7804. tp->rx_pending = ering->rx_pending;
  7805. if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
  7806. tp->rx_pending > 63)
  7807. tp->rx_pending = 63;
  7808. tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  7809. tp->tx_pending = ering->tx_pending;
  7810. if (netif_running(dev)) {
  7811. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7812. err = tg3_restart_hw(tp, 1);
  7813. if (!err)
  7814. tg3_netif_start(tp);
  7815. }
  7816. tg3_full_unlock(tp);
  7817. if (irq_sync && !err)
  7818. tg3_phy_start(tp);
  7819. return err;
  7820. }
  7821. static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  7822. {
  7823. struct tg3 *tp = netdev_priv(dev);
  7824. epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
  7825. if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
  7826. epause->rx_pause = 1;
  7827. else
  7828. epause->rx_pause = 0;
  7829. if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
  7830. epause->tx_pause = 1;
  7831. else
  7832. epause->tx_pause = 0;
  7833. }
  7834. static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  7835. {
  7836. struct tg3 *tp = netdev_priv(dev);
  7837. int err = 0;
  7838. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  7839. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  7840. return -EAGAIN;
  7841. if (epause->autoneg) {
  7842. u32 newadv;
  7843. struct phy_device *phydev;
  7844. phydev = tp->mdio_bus.phy_map[PHY_ADDR];
  7845. if (epause->rx_pause) {
  7846. if (epause->tx_pause)
  7847. newadv = ADVERTISED_Pause;
  7848. else
  7849. newadv = ADVERTISED_Pause |
  7850. ADVERTISED_Asym_Pause;
  7851. } else if (epause->tx_pause) {
  7852. newadv = ADVERTISED_Asym_Pause;
  7853. } else
  7854. newadv = 0;
  7855. if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
  7856. u32 oldadv = phydev->advertising &
  7857. (ADVERTISED_Pause |
  7858. ADVERTISED_Asym_Pause);
  7859. if (oldadv != newadv) {
  7860. phydev->advertising &=
  7861. ~(ADVERTISED_Pause |
  7862. ADVERTISED_Asym_Pause);
  7863. phydev->advertising |= newadv;
  7864. err = phy_start_aneg(phydev);
  7865. }
  7866. } else {
  7867. tp->link_config.advertising &=
  7868. ~(ADVERTISED_Pause |
  7869. ADVERTISED_Asym_Pause);
  7870. tp->link_config.advertising |= newadv;
  7871. }
  7872. } else {
  7873. if (epause->rx_pause)
  7874. tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
  7875. else
  7876. tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
  7877. if (epause->tx_pause)
  7878. tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
  7879. else
  7880. tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
  7881. if (netif_running(dev))
  7882. tg3_setup_flow_control(tp, 0, 0);
  7883. }
  7884. } else {
  7885. int irq_sync = 0;
  7886. if (netif_running(dev)) {
  7887. tg3_netif_stop(tp);
  7888. irq_sync = 1;
  7889. }
  7890. tg3_full_lock(tp, irq_sync);
  7891. if (epause->autoneg)
  7892. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  7893. else
  7894. tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
  7895. if (epause->rx_pause)
  7896. tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
  7897. else
  7898. tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
  7899. if (epause->tx_pause)
  7900. tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
  7901. else
  7902. tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
  7903. if (netif_running(dev)) {
  7904. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7905. err = tg3_restart_hw(tp, 1);
  7906. if (!err)
  7907. tg3_netif_start(tp);
  7908. }
  7909. tg3_full_unlock(tp);
  7910. }
  7911. return err;
  7912. }
  7913. static u32 tg3_get_rx_csum(struct net_device *dev)
  7914. {
  7915. struct tg3 *tp = netdev_priv(dev);
  7916. return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
  7917. }
  7918. static int tg3_set_rx_csum(struct net_device *dev, u32 data)
  7919. {
  7920. struct tg3 *tp = netdev_priv(dev);
  7921. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  7922. if (data != 0)
  7923. return -EINVAL;
  7924. return 0;
  7925. }
  7926. spin_lock_bh(&tp->lock);
  7927. if (data)
  7928. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  7929. else
  7930. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  7931. spin_unlock_bh(&tp->lock);
  7932. return 0;
  7933. }
  7934. static int tg3_set_tx_csum(struct net_device *dev, u32 data)
  7935. {
  7936. struct tg3 *tp = netdev_priv(dev);
  7937. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  7938. if (data != 0)
  7939. return -EINVAL;
  7940. return 0;
  7941. }
  7942. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  7943. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  7944. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  7945. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  7946. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  7947. ethtool_op_set_tx_ipv6_csum(dev, data);
  7948. else
  7949. ethtool_op_set_tx_csum(dev, data);
  7950. return 0;
  7951. }
  7952. static int tg3_get_sset_count (struct net_device *dev, int sset)
  7953. {
  7954. switch (sset) {
  7955. case ETH_SS_TEST:
  7956. return TG3_NUM_TEST;
  7957. case ETH_SS_STATS:
  7958. return TG3_NUM_STATS;
  7959. default:
  7960. return -EOPNOTSUPP;
  7961. }
  7962. }
  7963. static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
  7964. {
  7965. switch (stringset) {
  7966. case ETH_SS_STATS:
  7967. memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
  7968. break;
  7969. case ETH_SS_TEST:
  7970. memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
  7971. break;
  7972. default:
  7973. WARN_ON(1); /* we need a WARN() */
  7974. break;
  7975. }
  7976. }
  7977. static int tg3_phys_id(struct net_device *dev, u32 data)
  7978. {
  7979. struct tg3 *tp = netdev_priv(dev);
  7980. int i;
  7981. if (!netif_running(tp->dev))
  7982. return -EAGAIN;
  7983. if (data == 0)
  7984. data = UINT_MAX / 2;
  7985. for (i = 0; i < (data * 2); i++) {
  7986. if ((i % 2) == 0)
  7987. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  7988. LED_CTRL_1000MBPS_ON |
  7989. LED_CTRL_100MBPS_ON |
  7990. LED_CTRL_10MBPS_ON |
  7991. LED_CTRL_TRAFFIC_OVERRIDE |
  7992. LED_CTRL_TRAFFIC_BLINK |
  7993. LED_CTRL_TRAFFIC_LED);
  7994. else
  7995. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  7996. LED_CTRL_TRAFFIC_OVERRIDE);
  7997. if (msleep_interruptible(500))
  7998. break;
  7999. }
  8000. tw32(MAC_LED_CTRL, tp->led_ctrl);
  8001. return 0;
  8002. }
  8003. static void tg3_get_ethtool_stats (struct net_device *dev,
  8004. struct ethtool_stats *estats, u64 *tmp_stats)
  8005. {
  8006. struct tg3 *tp = netdev_priv(dev);
  8007. memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
  8008. }
  8009. #define NVRAM_TEST_SIZE 0x100
  8010. #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
  8011. #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
  8012. #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
  8013. #define NVRAM_SELFBOOT_HW_SIZE 0x20
  8014. #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
  8015. static int tg3_test_nvram(struct tg3 *tp)
  8016. {
  8017. u32 csum, magic;
  8018. __le32 *buf;
  8019. int i, j, k, err = 0, size;
  8020. if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
  8021. return -EIO;
  8022. if (magic == TG3_EEPROM_MAGIC)
  8023. size = NVRAM_TEST_SIZE;
  8024. else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
  8025. if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
  8026. TG3_EEPROM_SB_FORMAT_1) {
  8027. switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
  8028. case TG3_EEPROM_SB_REVISION_0:
  8029. size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
  8030. break;
  8031. case TG3_EEPROM_SB_REVISION_2:
  8032. size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
  8033. break;
  8034. case TG3_EEPROM_SB_REVISION_3:
  8035. size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
  8036. break;
  8037. default:
  8038. return 0;
  8039. }
  8040. } else
  8041. return 0;
  8042. } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  8043. size = NVRAM_SELFBOOT_HW_SIZE;
  8044. else
  8045. return -EIO;
  8046. buf = kmalloc(size, GFP_KERNEL);
  8047. if (buf == NULL)
  8048. return -ENOMEM;
  8049. err = -EIO;
  8050. for (i = 0, j = 0; i < size; i += 4, j++) {
  8051. if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
  8052. break;
  8053. }
  8054. if (i < size)
  8055. goto out;
  8056. /* Selfboot format */
  8057. magic = swab32(le32_to_cpu(buf[0]));
  8058. if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
  8059. TG3_EEPROM_MAGIC_FW) {
  8060. u8 *buf8 = (u8 *) buf, csum8 = 0;
  8061. if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
  8062. TG3_EEPROM_SB_REVISION_2) {
  8063. /* For rev 2, the csum doesn't include the MBA. */
  8064. for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
  8065. csum8 += buf8[i];
  8066. for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
  8067. csum8 += buf8[i];
  8068. } else {
  8069. for (i = 0; i < size; i++)
  8070. csum8 += buf8[i];
  8071. }
  8072. if (csum8 == 0) {
  8073. err = 0;
  8074. goto out;
  8075. }
  8076. err = -EIO;
  8077. goto out;
  8078. }
  8079. if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
  8080. TG3_EEPROM_MAGIC_HW) {
  8081. u8 data[NVRAM_SELFBOOT_DATA_SIZE];
  8082. u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
  8083. u8 *buf8 = (u8 *) buf;
  8084. /* Separate the parity bits and the data bytes. */
  8085. for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
  8086. if ((i == 0) || (i == 8)) {
  8087. int l;
  8088. u8 msk;
  8089. for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
  8090. parity[k++] = buf8[i] & msk;
  8091. i++;
  8092. }
  8093. else if (i == 16) {
  8094. int l;
  8095. u8 msk;
  8096. for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
  8097. parity[k++] = buf8[i] & msk;
  8098. i++;
  8099. for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
  8100. parity[k++] = buf8[i] & msk;
  8101. i++;
  8102. }
  8103. data[j++] = buf8[i];
  8104. }
  8105. err = -EIO;
  8106. for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
  8107. u8 hw8 = hweight8(data[i]);
  8108. if ((hw8 & 0x1) && parity[i])
  8109. goto out;
  8110. else if (!(hw8 & 0x1) && !parity[i])
  8111. goto out;
  8112. }
  8113. err = 0;
  8114. goto out;
  8115. }
  8116. /* Bootstrap checksum at offset 0x10 */
  8117. csum = calc_crc((unsigned char *) buf, 0x10);
  8118. if(csum != le32_to_cpu(buf[0x10/4]))
  8119. goto out;
  8120. /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
  8121. csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
  8122. if (csum != le32_to_cpu(buf[0xfc/4]))
  8123. goto out;
  8124. err = 0;
  8125. out:
  8126. kfree(buf);
  8127. return err;
  8128. }
  8129. #define TG3_SERDES_TIMEOUT_SEC 2
  8130. #define TG3_COPPER_TIMEOUT_SEC 6
  8131. static int tg3_test_link(struct tg3 *tp)
  8132. {
  8133. int i, max;
  8134. if (!netif_running(tp->dev))
  8135. return -ENODEV;
  8136. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  8137. max = TG3_SERDES_TIMEOUT_SEC;
  8138. else
  8139. max = TG3_COPPER_TIMEOUT_SEC;
  8140. for (i = 0; i < max; i++) {
  8141. if (netif_carrier_ok(tp->dev))
  8142. return 0;
  8143. if (msleep_interruptible(1000))
  8144. break;
  8145. }
  8146. return -EIO;
  8147. }
  8148. /* Only test the commonly used registers */
  8149. static int tg3_test_registers(struct tg3 *tp)
  8150. {
  8151. int i, is_5705, is_5750;
  8152. u32 offset, read_mask, write_mask, val, save_val, read_val;
  8153. static struct {
  8154. u16 offset;
  8155. u16 flags;
  8156. #define TG3_FL_5705 0x1
  8157. #define TG3_FL_NOT_5705 0x2
  8158. #define TG3_FL_NOT_5788 0x4
  8159. #define TG3_FL_NOT_5750 0x8
  8160. u32 read_mask;
  8161. u32 write_mask;
  8162. } reg_tbl[] = {
  8163. /* MAC Control Registers */
  8164. { MAC_MODE, TG3_FL_NOT_5705,
  8165. 0x00000000, 0x00ef6f8c },
  8166. { MAC_MODE, TG3_FL_5705,
  8167. 0x00000000, 0x01ef6b8c },
  8168. { MAC_STATUS, TG3_FL_NOT_5705,
  8169. 0x03800107, 0x00000000 },
  8170. { MAC_STATUS, TG3_FL_5705,
  8171. 0x03800100, 0x00000000 },
  8172. { MAC_ADDR_0_HIGH, 0x0000,
  8173. 0x00000000, 0x0000ffff },
  8174. { MAC_ADDR_0_LOW, 0x0000,
  8175. 0x00000000, 0xffffffff },
  8176. { MAC_RX_MTU_SIZE, 0x0000,
  8177. 0x00000000, 0x0000ffff },
  8178. { MAC_TX_MODE, 0x0000,
  8179. 0x00000000, 0x00000070 },
  8180. { MAC_TX_LENGTHS, 0x0000,
  8181. 0x00000000, 0x00003fff },
  8182. { MAC_RX_MODE, TG3_FL_NOT_5705,
  8183. 0x00000000, 0x000007fc },
  8184. { MAC_RX_MODE, TG3_FL_5705,
  8185. 0x00000000, 0x000007dc },
  8186. { MAC_HASH_REG_0, 0x0000,
  8187. 0x00000000, 0xffffffff },
  8188. { MAC_HASH_REG_1, 0x0000,
  8189. 0x00000000, 0xffffffff },
  8190. { MAC_HASH_REG_2, 0x0000,
  8191. 0x00000000, 0xffffffff },
  8192. { MAC_HASH_REG_3, 0x0000,
  8193. 0x00000000, 0xffffffff },
  8194. /* Receive Data and Receive BD Initiator Control Registers. */
  8195. { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
  8196. 0x00000000, 0xffffffff },
  8197. { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
  8198. 0x00000000, 0xffffffff },
  8199. { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
  8200. 0x00000000, 0x00000003 },
  8201. { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
  8202. 0x00000000, 0xffffffff },
  8203. { RCVDBDI_STD_BD+0, 0x0000,
  8204. 0x00000000, 0xffffffff },
  8205. { RCVDBDI_STD_BD+4, 0x0000,
  8206. 0x00000000, 0xffffffff },
  8207. { RCVDBDI_STD_BD+8, 0x0000,
  8208. 0x00000000, 0xffff0002 },
  8209. { RCVDBDI_STD_BD+0xc, 0x0000,
  8210. 0x00000000, 0xffffffff },
  8211. /* Receive BD Initiator Control Registers. */
  8212. { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
  8213. 0x00000000, 0xffffffff },
  8214. { RCVBDI_STD_THRESH, TG3_FL_5705,
  8215. 0x00000000, 0x000003ff },
  8216. { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
  8217. 0x00000000, 0xffffffff },
  8218. /* Host Coalescing Control Registers. */
  8219. { HOSTCC_MODE, TG3_FL_NOT_5705,
  8220. 0x00000000, 0x00000004 },
  8221. { HOSTCC_MODE, TG3_FL_5705,
  8222. 0x00000000, 0x000000f6 },
  8223. { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
  8224. 0x00000000, 0xffffffff },
  8225. { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
  8226. 0x00000000, 0x000003ff },
  8227. { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
  8228. 0x00000000, 0xffffffff },
  8229. { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
  8230. 0x00000000, 0x000003ff },
  8231. { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
  8232. 0x00000000, 0xffffffff },
  8233. { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  8234. 0x00000000, 0x000000ff },
  8235. { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
  8236. 0x00000000, 0xffffffff },
  8237. { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  8238. 0x00000000, 0x000000ff },
  8239. { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
  8240. 0x00000000, 0xffffffff },
  8241. { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
  8242. 0x00000000, 0xffffffff },
  8243. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  8244. 0x00000000, 0xffffffff },
  8245. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  8246. 0x00000000, 0x000000ff },
  8247. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  8248. 0x00000000, 0xffffffff },
  8249. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  8250. 0x00000000, 0x000000ff },
  8251. { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
  8252. 0x00000000, 0xffffffff },
  8253. { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
  8254. 0x00000000, 0xffffffff },
  8255. { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
  8256. 0x00000000, 0xffffffff },
  8257. { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
  8258. 0x00000000, 0xffffffff },
  8259. { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
  8260. 0x00000000, 0xffffffff },
  8261. { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
  8262. 0xffffffff, 0x00000000 },
  8263. { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
  8264. 0xffffffff, 0x00000000 },
  8265. /* Buffer Manager Control Registers. */
  8266. { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
  8267. 0x00000000, 0x007fff80 },
  8268. { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
  8269. 0x00000000, 0x007fffff },
  8270. { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
  8271. 0x00000000, 0x0000003f },
  8272. { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
  8273. 0x00000000, 0x000001ff },
  8274. { BUFMGR_MB_HIGH_WATER, 0x0000,
  8275. 0x00000000, 0x000001ff },
  8276. { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
  8277. 0xffffffff, 0x00000000 },
  8278. { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
  8279. 0xffffffff, 0x00000000 },
  8280. /* Mailbox Registers */
  8281. { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
  8282. 0x00000000, 0x000001ff },
  8283. { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
  8284. 0x00000000, 0x000001ff },
  8285. { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
  8286. 0x00000000, 0x000007ff },
  8287. { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
  8288. 0x00000000, 0x000001ff },
  8289. { 0xffff, 0x0000, 0x00000000, 0x00000000 },
  8290. };
  8291. is_5705 = is_5750 = 0;
  8292. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  8293. is_5705 = 1;
  8294. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  8295. is_5750 = 1;
  8296. }
  8297. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  8298. if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
  8299. continue;
  8300. if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
  8301. continue;
  8302. if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  8303. (reg_tbl[i].flags & TG3_FL_NOT_5788))
  8304. continue;
  8305. if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
  8306. continue;
  8307. offset = (u32) reg_tbl[i].offset;
  8308. read_mask = reg_tbl[i].read_mask;
  8309. write_mask = reg_tbl[i].write_mask;
  8310. /* Save the original register content */
  8311. save_val = tr32(offset);
  8312. /* Determine the read-only value. */
  8313. read_val = save_val & read_mask;
  8314. /* Write zero to the register, then make sure the read-only bits
  8315. * are not changed and the read/write bits are all zeros.
  8316. */
  8317. tw32(offset, 0);
  8318. val = tr32(offset);
  8319. /* Test the read-only and read/write bits. */
  8320. if (((val & read_mask) != read_val) || (val & write_mask))
  8321. goto out;
  8322. /* Write ones to all the bits defined by RdMask and WrMask, then
  8323. * make sure the read-only bits are not changed and the
  8324. * read/write bits are all ones.
  8325. */
  8326. tw32(offset, read_mask | write_mask);
  8327. val = tr32(offset);
  8328. /* Test the read-only bits. */
  8329. if ((val & read_mask) != read_val)
  8330. goto out;
  8331. /* Test the read/write bits. */
  8332. if ((val & write_mask) != write_mask)
  8333. goto out;
  8334. tw32(offset, save_val);
  8335. }
  8336. return 0;
  8337. out:
  8338. if (netif_msg_hw(tp))
  8339. printk(KERN_ERR PFX "Register test failed at offset %x\n",
  8340. offset);
  8341. tw32(offset, save_val);
  8342. return -EIO;
  8343. }
  8344. static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
  8345. {
  8346. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
  8347. int i;
  8348. u32 j;
  8349. for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
  8350. for (j = 0; j < len; j += 4) {
  8351. u32 val;
  8352. tg3_write_mem(tp, offset + j, test_pattern[i]);
  8353. tg3_read_mem(tp, offset + j, &val);
  8354. if (val != test_pattern[i])
  8355. return -EIO;
  8356. }
  8357. }
  8358. return 0;
  8359. }
  8360. static int tg3_test_memory(struct tg3 *tp)
  8361. {
  8362. static struct mem_entry {
  8363. u32 offset;
  8364. u32 len;
  8365. } mem_tbl_570x[] = {
  8366. { 0x00000000, 0x00b50},
  8367. { 0x00002000, 0x1c000},
  8368. { 0xffffffff, 0x00000}
  8369. }, mem_tbl_5705[] = {
  8370. { 0x00000100, 0x0000c},
  8371. { 0x00000200, 0x00008},
  8372. { 0x00004000, 0x00800},
  8373. { 0x00006000, 0x01000},
  8374. { 0x00008000, 0x02000},
  8375. { 0x00010000, 0x0e000},
  8376. { 0xffffffff, 0x00000}
  8377. }, mem_tbl_5755[] = {
  8378. { 0x00000200, 0x00008},
  8379. { 0x00004000, 0x00800},
  8380. { 0x00006000, 0x00800},
  8381. { 0x00008000, 0x02000},
  8382. { 0x00010000, 0x0c000},
  8383. { 0xffffffff, 0x00000}
  8384. }, mem_tbl_5906[] = {
  8385. { 0x00000200, 0x00008},
  8386. { 0x00004000, 0x00400},
  8387. { 0x00006000, 0x00400},
  8388. { 0x00008000, 0x01000},
  8389. { 0x00010000, 0x01000},
  8390. { 0xffffffff, 0x00000}
  8391. };
  8392. struct mem_entry *mem_tbl;
  8393. int err = 0;
  8394. int i;
  8395. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  8396. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  8397. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  8398. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  8399. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  8400. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  8401. mem_tbl = mem_tbl_5755;
  8402. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  8403. mem_tbl = mem_tbl_5906;
  8404. else
  8405. mem_tbl = mem_tbl_5705;
  8406. } else
  8407. mem_tbl = mem_tbl_570x;
  8408. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  8409. if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
  8410. mem_tbl[i].len)) != 0)
  8411. break;
  8412. }
  8413. return err;
  8414. }
  8415. #define TG3_MAC_LOOPBACK 0
  8416. #define TG3_PHY_LOOPBACK 1
  8417. static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
  8418. {
  8419. u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
  8420. u32 desc_idx;
  8421. struct sk_buff *skb, *rx_skb;
  8422. u8 *tx_data;
  8423. dma_addr_t map;
  8424. int num_pkts, tx_len, rx_len, i, err;
  8425. struct tg3_rx_buffer_desc *desc;
  8426. if (loopback_mode == TG3_MAC_LOOPBACK) {
  8427. /* HW errata - mac loopback fails in some cases on 5780.
  8428. * Normal traffic and PHY loopback are not affected by
  8429. * errata.
  8430. */
  8431. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
  8432. return 0;
  8433. mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
  8434. MAC_MODE_PORT_INT_LPBACK;
  8435. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  8436. mac_mode |= MAC_MODE_LINK_POLARITY;
  8437. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  8438. mac_mode |= MAC_MODE_PORT_MODE_MII;
  8439. else
  8440. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  8441. tw32(MAC_MODE, mac_mode);
  8442. } else if (loopback_mode == TG3_PHY_LOOPBACK) {
  8443. u32 val;
  8444. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  8445. u32 phytest;
  8446. if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
  8447. u32 phy;
  8448. tg3_writephy(tp, MII_TG3_EPHY_TEST,
  8449. phytest | MII_TG3_EPHY_SHADOW_EN);
  8450. if (!tg3_readphy(tp, 0x1b, &phy))
  8451. tg3_writephy(tp, 0x1b, phy & ~0x20);
  8452. tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
  8453. }
  8454. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
  8455. } else
  8456. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
  8457. tg3_phy_toggle_automdix(tp, 0);
  8458. tg3_writephy(tp, MII_BMCR, val);
  8459. udelay(40);
  8460. mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  8461. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  8462. tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
  8463. mac_mode |= MAC_MODE_PORT_MODE_MII;
  8464. } else
  8465. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  8466. /* reset to prevent losing 1st rx packet intermittently */
  8467. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  8468. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  8469. udelay(10);
  8470. tw32_f(MAC_RX_MODE, tp->rx_mode);
  8471. }
  8472. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  8473. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
  8474. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  8475. else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
  8476. mac_mode |= MAC_MODE_LINK_POLARITY;
  8477. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  8478. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  8479. }
  8480. tw32(MAC_MODE, mac_mode);
  8481. }
  8482. else
  8483. return -EINVAL;
  8484. err = -EIO;
  8485. tx_len = 1514;
  8486. skb = netdev_alloc_skb(tp->dev, tx_len);
  8487. if (!skb)
  8488. return -ENOMEM;
  8489. tx_data = skb_put(skb, tx_len);
  8490. memcpy(tx_data, tp->dev->dev_addr, 6);
  8491. memset(tx_data + 6, 0x0, 8);
  8492. tw32(MAC_RX_MTU_SIZE, tx_len + 4);
  8493. for (i = 14; i < tx_len; i++)
  8494. tx_data[i] = (u8) (i & 0xff);
  8495. map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
  8496. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  8497. HOSTCC_MODE_NOW);
  8498. udelay(10);
  8499. rx_start_idx = tp->hw_status->idx[0].rx_producer;
  8500. num_pkts = 0;
  8501. tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
  8502. tp->tx_prod++;
  8503. num_pkts++;
  8504. tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
  8505. tp->tx_prod);
  8506. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
  8507. udelay(10);
  8508. /* 250 usec to allow enough time on some 10/100 Mbps devices. */
  8509. for (i = 0; i < 25; i++) {
  8510. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  8511. HOSTCC_MODE_NOW);
  8512. udelay(10);
  8513. tx_idx = tp->hw_status->idx[0].tx_consumer;
  8514. rx_idx = tp->hw_status->idx[0].rx_producer;
  8515. if ((tx_idx == tp->tx_prod) &&
  8516. (rx_idx == (rx_start_idx + num_pkts)))
  8517. break;
  8518. }
  8519. pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
  8520. dev_kfree_skb(skb);
  8521. if (tx_idx != tp->tx_prod)
  8522. goto out;
  8523. if (rx_idx != rx_start_idx + num_pkts)
  8524. goto out;
  8525. desc = &tp->rx_rcb[rx_start_idx];
  8526. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  8527. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  8528. if (opaque_key != RXD_OPAQUE_RING_STD)
  8529. goto out;
  8530. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  8531. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
  8532. goto out;
  8533. rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
  8534. if (rx_len != tx_len)
  8535. goto out;
  8536. rx_skb = tp->rx_std_buffers[desc_idx].skb;
  8537. map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
  8538. pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
  8539. for (i = 14; i < tx_len; i++) {
  8540. if (*(rx_skb->data + i) != (u8) (i & 0xff))
  8541. goto out;
  8542. }
  8543. err = 0;
  8544. /* tg3_free_rings will unmap and free the rx_skb */
  8545. out:
  8546. return err;
  8547. }
  8548. #define TG3_MAC_LOOPBACK_FAILED 1
  8549. #define TG3_PHY_LOOPBACK_FAILED 2
  8550. #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
  8551. TG3_PHY_LOOPBACK_FAILED)
  8552. static int tg3_test_loopback(struct tg3 *tp)
  8553. {
  8554. int err = 0;
  8555. u32 cpmuctrl = 0;
  8556. if (!netif_running(tp->dev))
  8557. return TG3_LOOPBACK_FAILED;
  8558. err = tg3_reset_hw(tp, 1);
  8559. if (err)
  8560. return TG3_LOOPBACK_FAILED;
  8561. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  8562. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  8563. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
  8564. int i;
  8565. u32 status;
  8566. tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
  8567. /* Wait for up to 40 microseconds to acquire lock. */
  8568. for (i = 0; i < 4; i++) {
  8569. status = tr32(TG3_CPMU_MUTEX_GNT);
  8570. if (status == CPMU_MUTEX_GNT_DRIVER)
  8571. break;
  8572. udelay(10);
  8573. }
  8574. if (status != CPMU_MUTEX_GNT_DRIVER)
  8575. return TG3_LOOPBACK_FAILED;
  8576. /* Turn off link-based power management. */
  8577. cpmuctrl = tr32(TG3_CPMU_CTRL);
  8578. tw32(TG3_CPMU_CTRL,
  8579. cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
  8580. CPMU_CTRL_LINK_AWARE_MODE));
  8581. }
  8582. if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
  8583. err |= TG3_MAC_LOOPBACK_FAILED;
  8584. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  8585. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  8586. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
  8587. tw32(TG3_CPMU_CTRL, cpmuctrl);
  8588. /* Release the mutex */
  8589. tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
  8590. }
  8591. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  8592. !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
  8593. if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
  8594. err |= TG3_PHY_LOOPBACK_FAILED;
  8595. }
  8596. return err;
  8597. }
  8598. static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
  8599. u64 *data)
  8600. {
  8601. struct tg3 *tp = netdev_priv(dev);
  8602. if (tp->link_config.phy_is_low_power)
  8603. tg3_set_power_state(tp, PCI_D0);
  8604. memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
  8605. if (tg3_test_nvram(tp) != 0) {
  8606. etest->flags |= ETH_TEST_FL_FAILED;
  8607. data[0] = 1;
  8608. }
  8609. if (tg3_test_link(tp) != 0) {
  8610. etest->flags |= ETH_TEST_FL_FAILED;
  8611. data[1] = 1;
  8612. }
  8613. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  8614. int err, err2 = 0, irq_sync = 0;
  8615. if (netif_running(dev)) {
  8616. tg3_phy_stop(tp);
  8617. tg3_netif_stop(tp);
  8618. irq_sync = 1;
  8619. }
  8620. tg3_full_lock(tp, irq_sync);
  8621. tg3_halt(tp, RESET_KIND_SUSPEND, 1);
  8622. err = tg3_nvram_lock(tp);
  8623. tg3_halt_cpu(tp, RX_CPU_BASE);
  8624. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  8625. tg3_halt_cpu(tp, TX_CPU_BASE);
  8626. if (!err)
  8627. tg3_nvram_unlock(tp);
  8628. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  8629. tg3_phy_reset(tp);
  8630. if (tg3_test_registers(tp) != 0) {
  8631. etest->flags |= ETH_TEST_FL_FAILED;
  8632. data[2] = 1;
  8633. }
  8634. if (tg3_test_memory(tp) != 0) {
  8635. etest->flags |= ETH_TEST_FL_FAILED;
  8636. data[3] = 1;
  8637. }
  8638. if ((data[4] = tg3_test_loopback(tp)) != 0)
  8639. etest->flags |= ETH_TEST_FL_FAILED;
  8640. tg3_full_unlock(tp);
  8641. if (tg3_test_interrupt(tp) != 0) {
  8642. etest->flags |= ETH_TEST_FL_FAILED;
  8643. data[5] = 1;
  8644. }
  8645. tg3_full_lock(tp, 0);
  8646. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8647. if (netif_running(dev)) {
  8648. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  8649. err2 = tg3_restart_hw(tp, 1);
  8650. if (!err2)
  8651. tg3_netif_start(tp);
  8652. }
  8653. tg3_full_unlock(tp);
  8654. if (irq_sync && !err2)
  8655. tg3_phy_start(tp);
  8656. }
  8657. if (tp->link_config.phy_is_low_power)
  8658. tg3_set_power_state(tp, PCI_D3hot);
  8659. }
  8660. static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  8661. {
  8662. struct mii_ioctl_data *data = if_mii(ifr);
  8663. struct tg3 *tp = netdev_priv(dev);
  8664. int err;
  8665. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  8666. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  8667. return -EAGAIN;
  8668. return phy_mii_ioctl(tp->mdio_bus.phy_map[PHY_ADDR], data, cmd);
  8669. }
  8670. switch(cmd) {
  8671. case SIOCGMIIPHY:
  8672. data->phy_id = PHY_ADDR;
  8673. /* fallthru */
  8674. case SIOCGMIIREG: {
  8675. u32 mii_regval;
  8676. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  8677. break; /* We have no PHY */
  8678. if (tp->link_config.phy_is_low_power)
  8679. return -EAGAIN;
  8680. spin_lock_bh(&tp->lock);
  8681. err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
  8682. spin_unlock_bh(&tp->lock);
  8683. data->val_out = mii_regval;
  8684. return err;
  8685. }
  8686. case SIOCSMIIREG:
  8687. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  8688. break; /* We have no PHY */
  8689. if (!capable(CAP_NET_ADMIN))
  8690. return -EPERM;
  8691. if (tp->link_config.phy_is_low_power)
  8692. return -EAGAIN;
  8693. spin_lock_bh(&tp->lock);
  8694. err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
  8695. spin_unlock_bh(&tp->lock);
  8696. return err;
  8697. default:
  8698. /* do nothing */
  8699. break;
  8700. }
  8701. return -EOPNOTSUPP;
  8702. }
  8703. #if TG3_VLAN_TAG_USED
  8704. static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  8705. {
  8706. struct tg3 *tp = netdev_priv(dev);
  8707. if (netif_running(dev))
  8708. tg3_netif_stop(tp);
  8709. tg3_full_lock(tp, 0);
  8710. tp->vlgrp = grp;
  8711. /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
  8712. __tg3_set_rx_mode(dev);
  8713. if (netif_running(dev))
  8714. tg3_netif_start(tp);
  8715. tg3_full_unlock(tp);
  8716. }
  8717. #endif
  8718. static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  8719. {
  8720. struct tg3 *tp = netdev_priv(dev);
  8721. memcpy(ec, &tp->coal, sizeof(*ec));
  8722. return 0;
  8723. }
  8724. static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  8725. {
  8726. struct tg3 *tp = netdev_priv(dev);
  8727. u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
  8728. u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
  8729. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  8730. max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
  8731. max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
  8732. max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
  8733. min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
  8734. }
  8735. if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
  8736. (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
  8737. (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
  8738. (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
  8739. (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
  8740. (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
  8741. (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
  8742. (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
  8743. (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
  8744. (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
  8745. return -EINVAL;
  8746. /* No rx interrupts will be generated if both are zero */
  8747. if ((ec->rx_coalesce_usecs == 0) &&
  8748. (ec->rx_max_coalesced_frames == 0))
  8749. return -EINVAL;
  8750. /* No tx interrupts will be generated if both are zero */
  8751. if ((ec->tx_coalesce_usecs == 0) &&
  8752. (ec->tx_max_coalesced_frames == 0))
  8753. return -EINVAL;
  8754. /* Only copy relevant parameters, ignore all others. */
  8755. tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
  8756. tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
  8757. tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  8758. tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
  8759. tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
  8760. tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
  8761. tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
  8762. tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
  8763. tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
  8764. if (netif_running(dev)) {
  8765. tg3_full_lock(tp, 0);
  8766. __tg3_set_coalesce(tp, &tp->coal);
  8767. tg3_full_unlock(tp);
  8768. }
  8769. return 0;
  8770. }
  8771. static const struct ethtool_ops tg3_ethtool_ops = {
  8772. .get_settings = tg3_get_settings,
  8773. .set_settings = tg3_set_settings,
  8774. .get_drvinfo = tg3_get_drvinfo,
  8775. .get_regs_len = tg3_get_regs_len,
  8776. .get_regs = tg3_get_regs,
  8777. .get_wol = tg3_get_wol,
  8778. .set_wol = tg3_set_wol,
  8779. .get_msglevel = tg3_get_msglevel,
  8780. .set_msglevel = tg3_set_msglevel,
  8781. .nway_reset = tg3_nway_reset,
  8782. .get_link = ethtool_op_get_link,
  8783. .get_eeprom_len = tg3_get_eeprom_len,
  8784. .get_eeprom = tg3_get_eeprom,
  8785. .set_eeprom = tg3_set_eeprom,
  8786. .get_ringparam = tg3_get_ringparam,
  8787. .set_ringparam = tg3_set_ringparam,
  8788. .get_pauseparam = tg3_get_pauseparam,
  8789. .set_pauseparam = tg3_set_pauseparam,
  8790. .get_rx_csum = tg3_get_rx_csum,
  8791. .set_rx_csum = tg3_set_rx_csum,
  8792. .set_tx_csum = tg3_set_tx_csum,
  8793. .set_sg = ethtool_op_set_sg,
  8794. .set_tso = tg3_set_tso,
  8795. .self_test = tg3_self_test,
  8796. .get_strings = tg3_get_strings,
  8797. .phys_id = tg3_phys_id,
  8798. .get_ethtool_stats = tg3_get_ethtool_stats,
  8799. .get_coalesce = tg3_get_coalesce,
  8800. .set_coalesce = tg3_set_coalesce,
  8801. .get_sset_count = tg3_get_sset_count,
  8802. };
  8803. static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
  8804. {
  8805. u32 cursize, val, magic;
  8806. tp->nvram_size = EEPROM_CHIP_SIZE;
  8807. if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
  8808. return;
  8809. if ((magic != TG3_EEPROM_MAGIC) &&
  8810. ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
  8811. ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
  8812. return;
  8813. /*
  8814. * Size the chip by reading offsets at increasing powers of two.
  8815. * When we encounter our validation signature, we know the addressing
  8816. * has wrapped around, and thus have our chip size.
  8817. */
  8818. cursize = 0x10;
  8819. while (cursize < tp->nvram_size) {
  8820. if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
  8821. return;
  8822. if (val == magic)
  8823. break;
  8824. cursize <<= 1;
  8825. }
  8826. tp->nvram_size = cursize;
  8827. }
  8828. static void __devinit tg3_get_nvram_size(struct tg3 *tp)
  8829. {
  8830. u32 val;
  8831. if (tg3_nvram_read_swab(tp, 0, &val) != 0)
  8832. return;
  8833. /* Selfboot format */
  8834. if (val != TG3_EEPROM_MAGIC) {
  8835. tg3_get_eeprom_size(tp);
  8836. return;
  8837. }
  8838. if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
  8839. if (val != 0) {
  8840. tp->nvram_size = (val >> 16) * 1024;
  8841. return;
  8842. }
  8843. }
  8844. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  8845. }
  8846. static void __devinit tg3_get_nvram_info(struct tg3 *tp)
  8847. {
  8848. u32 nvcfg1;
  8849. nvcfg1 = tr32(NVRAM_CFG1);
  8850. if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  8851. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8852. }
  8853. else {
  8854. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  8855. tw32(NVRAM_CFG1, nvcfg1);
  8856. }
  8857. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
  8858. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  8859. switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
  8860. case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
  8861. tp->nvram_jedecnum = JEDEC_ATMEL;
  8862. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  8863. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8864. break;
  8865. case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
  8866. tp->nvram_jedecnum = JEDEC_ATMEL;
  8867. tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
  8868. break;
  8869. case FLASH_VENDOR_ATMEL_EEPROM:
  8870. tp->nvram_jedecnum = JEDEC_ATMEL;
  8871. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8872. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8873. break;
  8874. case FLASH_VENDOR_ST:
  8875. tp->nvram_jedecnum = JEDEC_ST;
  8876. tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
  8877. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8878. break;
  8879. case FLASH_VENDOR_SAIFUN:
  8880. tp->nvram_jedecnum = JEDEC_SAIFUN;
  8881. tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
  8882. break;
  8883. case FLASH_VENDOR_SST_SMALL:
  8884. case FLASH_VENDOR_SST_LARGE:
  8885. tp->nvram_jedecnum = JEDEC_SST;
  8886. tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
  8887. break;
  8888. }
  8889. }
  8890. else {
  8891. tp->nvram_jedecnum = JEDEC_ATMEL;
  8892. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  8893. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8894. }
  8895. }
  8896. static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
  8897. {
  8898. u32 nvcfg1;
  8899. nvcfg1 = tr32(NVRAM_CFG1);
  8900. /* NVRAM protection for TPM */
  8901. if (nvcfg1 & (1 << 27))
  8902. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  8903. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  8904. case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
  8905. case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
  8906. tp->nvram_jedecnum = JEDEC_ATMEL;
  8907. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8908. break;
  8909. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  8910. tp->nvram_jedecnum = JEDEC_ATMEL;
  8911. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8912. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8913. break;
  8914. case FLASH_5752VENDOR_ST_M45PE10:
  8915. case FLASH_5752VENDOR_ST_M45PE20:
  8916. case FLASH_5752VENDOR_ST_M45PE40:
  8917. tp->nvram_jedecnum = JEDEC_ST;
  8918. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8919. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8920. break;
  8921. }
  8922. if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
  8923. switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
  8924. case FLASH_5752PAGE_SIZE_256:
  8925. tp->nvram_pagesize = 256;
  8926. break;
  8927. case FLASH_5752PAGE_SIZE_512:
  8928. tp->nvram_pagesize = 512;
  8929. break;
  8930. case FLASH_5752PAGE_SIZE_1K:
  8931. tp->nvram_pagesize = 1024;
  8932. break;
  8933. case FLASH_5752PAGE_SIZE_2K:
  8934. tp->nvram_pagesize = 2048;
  8935. break;
  8936. case FLASH_5752PAGE_SIZE_4K:
  8937. tp->nvram_pagesize = 4096;
  8938. break;
  8939. case FLASH_5752PAGE_SIZE_264:
  8940. tp->nvram_pagesize = 264;
  8941. break;
  8942. }
  8943. }
  8944. else {
  8945. /* For eeprom, set pagesize to maximum eeprom size */
  8946. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8947. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  8948. tw32(NVRAM_CFG1, nvcfg1);
  8949. }
  8950. }
  8951. static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
  8952. {
  8953. u32 nvcfg1, protect = 0;
  8954. nvcfg1 = tr32(NVRAM_CFG1);
  8955. /* NVRAM protection for TPM */
  8956. if (nvcfg1 & (1 << 27)) {
  8957. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  8958. protect = 1;
  8959. }
  8960. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  8961. switch (nvcfg1) {
  8962. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  8963. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  8964. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  8965. case FLASH_5755VENDOR_ATMEL_FLASH_5:
  8966. tp->nvram_jedecnum = JEDEC_ATMEL;
  8967. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8968. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8969. tp->nvram_pagesize = 264;
  8970. if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
  8971. nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
  8972. tp->nvram_size = (protect ? 0x3e200 :
  8973. TG3_NVRAM_SIZE_512KB);
  8974. else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
  8975. tp->nvram_size = (protect ? 0x1f200 :
  8976. TG3_NVRAM_SIZE_256KB);
  8977. else
  8978. tp->nvram_size = (protect ? 0x1f200 :
  8979. TG3_NVRAM_SIZE_128KB);
  8980. break;
  8981. case FLASH_5752VENDOR_ST_M45PE10:
  8982. case FLASH_5752VENDOR_ST_M45PE20:
  8983. case FLASH_5752VENDOR_ST_M45PE40:
  8984. tp->nvram_jedecnum = JEDEC_ST;
  8985. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8986. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8987. tp->nvram_pagesize = 256;
  8988. if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
  8989. tp->nvram_size = (protect ?
  8990. TG3_NVRAM_SIZE_64KB :
  8991. TG3_NVRAM_SIZE_128KB);
  8992. else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
  8993. tp->nvram_size = (protect ?
  8994. TG3_NVRAM_SIZE_64KB :
  8995. TG3_NVRAM_SIZE_256KB);
  8996. else
  8997. tp->nvram_size = (protect ?
  8998. TG3_NVRAM_SIZE_128KB :
  8999. TG3_NVRAM_SIZE_512KB);
  9000. break;
  9001. }
  9002. }
  9003. static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
  9004. {
  9005. u32 nvcfg1;
  9006. nvcfg1 = tr32(NVRAM_CFG1);
  9007. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9008. case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
  9009. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  9010. case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
  9011. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  9012. tp->nvram_jedecnum = JEDEC_ATMEL;
  9013. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9014. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9015. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9016. tw32(NVRAM_CFG1, nvcfg1);
  9017. break;
  9018. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  9019. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  9020. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  9021. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  9022. tp->nvram_jedecnum = JEDEC_ATMEL;
  9023. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9024. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9025. tp->nvram_pagesize = 264;
  9026. break;
  9027. case FLASH_5752VENDOR_ST_M45PE10:
  9028. case FLASH_5752VENDOR_ST_M45PE20:
  9029. case FLASH_5752VENDOR_ST_M45PE40:
  9030. tp->nvram_jedecnum = JEDEC_ST;
  9031. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9032. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9033. tp->nvram_pagesize = 256;
  9034. break;
  9035. }
  9036. }
  9037. static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
  9038. {
  9039. u32 nvcfg1, protect = 0;
  9040. nvcfg1 = tr32(NVRAM_CFG1);
  9041. /* NVRAM protection for TPM */
  9042. if (nvcfg1 & (1 << 27)) {
  9043. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  9044. protect = 1;
  9045. }
  9046. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  9047. switch (nvcfg1) {
  9048. case FLASH_5761VENDOR_ATMEL_ADB021D:
  9049. case FLASH_5761VENDOR_ATMEL_ADB041D:
  9050. case FLASH_5761VENDOR_ATMEL_ADB081D:
  9051. case FLASH_5761VENDOR_ATMEL_ADB161D:
  9052. case FLASH_5761VENDOR_ATMEL_MDB021D:
  9053. case FLASH_5761VENDOR_ATMEL_MDB041D:
  9054. case FLASH_5761VENDOR_ATMEL_MDB081D:
  9055. case FLASH_5761VENDOR_ATMEL_MDB161D:
  9056. tp->nvram_jedecnum = JEDEC_ATMEL;
  9057. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9058. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9059. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
  9060. tp->nvram_pagesize = 256;
  9061. break;
  9062. case FLASH_5761VENDOR_ST_A_M45PE20:
  9063. case FLASH_5761VENDOR_ST_A_M45PE40:
  9064. case FLASH_5761VENDOR_ST_A_M45PE80:
  9065. case FLASH_5761VENDOR_ST_A_M45PE16:
  9066. case FLASH_5761VENDOR_ST_M_M45PE20:
  9067. case FLASH_5761VENDOR_ST_M_M45PE40:
  9068. case FLASH_5761VENDOR_ST_M_M45PE80:
  9069. case FLASH_5761VENDOR_ST_M_M45PE16:
  9070. tp->nvram_jedecnum = JEDEC_ST;
  9071. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9072. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9073. tp->nvram_pagesize = 256;
  9074. break;
  9075. }
  9076. if (protect) {
  9077. tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
  9078. } else {
  9079. switch (nvcfg1) {
  9080. case FLASH_5761VENDOR_ATMEL_ADB161D:
  9081. case FLASH_5761VENDOR_ATMEL_MDB161D:
  9082. case FLASH_5761VENDOR_ST_A_M45PE16:
  9083. case FLASH_5761VENDOR_ST_M_M45PE16:
  9084. tp->nvram_size = TG3_NVRAM_SIZE_2MB;
  9085. break;
  9086. case FLASH_5761VENDOR_ATMEL_ADB081D:
  9087. case FLASH_5761VENDOR_ATMEL_MDB081D:
  9088. case FLASH_5761VENDOR_ST_A_M45PE80:
  9089. case FLASH_5761VENDOR_ST_M_M45PE80:
  9090. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  9091. break;
  9092. case FLASH_5761VENDOR_ATMEL_ADB041D:
  9093. case FLASH_5761VENDOR_ATMEL_MDB041D:
  9094. case FLASH_5761VENDOR_ST_A_M45PE40:
  9095. case FLASH_5761VENDOR_ST_M_M45PE40:
  9096. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  9097. break;
  9098. case FLASH_5761VENDOR_ATMEL_ADB021D:
  9099. case FLASH_5761VENDOR_ATMEL_MDB021D:
  9100. case FLASH_5761VENDOR_ST_A_M45PE20:
  9101. case FLASH_5761VENDOR_ST_M_M45PE20:
  9102. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  9103. break;
  9104. }
  9105. }
  9106. }
  9107. static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
  9108. {
  9109. tp->nvram_jedecnum = JEDEC_ATMEL;
  9110. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9111. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9112. }
  9113. /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  9114. static void __devinit tg3_nvram_init(struct tg3 *tp)
  9115. {
  9116. tw32_f(GRC_EEPROM_ADDR,
  9117. (EEPROM_ADDR_FSM_RESET |
  9118. (EEPROM_DEFAULT_CLOCK_PERIOD <<
  9119. EEPROM_ADDR_CLKPERD_SHIFT)));
  9120. msleep(1);
  9121. /* Enable seeprom accesses. */
  9122. tw32_f(GRC_LOCAL_CTRL,
  9123. tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  9124. udelay(100);
  9125. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  9126. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  9127. tp->tg3_flags |= TG3_FLAG_NVRAM;
  9128. if (tg3_nvram_lock(tp)) {
  9129. printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
  9130. "tg3_nvram_init failed.\n", tp->dev->name);
  9131. return;
  9132. }
  9133. tg3_enable_nvram_access(tp);
  9134. tp->nvram_size = 0;
  9135. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  9136. tg3_get_5752_nvram_info(tp);
  9137. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  9138. tg3_get_5755_nvram_info(tp);
  9139. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9140. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  9141. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  9142. tg3_get_5787_nvram_info(tp);
  9143. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  9144. tg3_get_5761_nvram_info(tp);
  9145. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9146. tg3_get_5906_nvram_info(tp);
  9147. else
  9148. tg3_get_nvram_info(tp);
  9149. if (tp->nvram_size == 0)
  9150. tg3_get_nvram_size(tp);
  9151. tg3_disable_nvram_access(tp);
  9152. tg3_nvram_unlock(tp);
  9153. } else {
  9154. tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
  9155. tg3_get_eeprom_size(tp);
  9156. }
  9157. }
  9158. static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
  9159. u32 offset, u32 *val)
  9160. {
  9161. u32 tmp;
  9162. int i;
  9163. if (offset > EEPROM_ADDR_ADDR_MASK ||
  9164. (offset % 4) != 0)
  9165. return -EINVAL;
  9166. tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  9167. EEPROM_ADDR_DEVID_MASK |
  9168. EEPROM_ADDR_READ);
  9169. tw32(GRC_EEPROM_ADDR,
  9170. tmp |
  9171. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  9172. ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  9173. EEPROM_ADDR_ADDR_MASK) |
  9174. EEPROM_ADDR_READ | EEPROM_ADDR_START);
  9175. for (i = 0; i < 1000; i++) {
  9176. tmp = tr32(GRC_EEPROM_ADDR);
  9177. if (tmp & EEPROM_ADDR_COMPLETE)
  9178. break;
  9179. msleep(1);
  9180. }
  9181. if (!(tmp & EEPROM_ADDR_COMPLETE))
  9182. return -EBUSY;
  9183. *val = tr32(GRC_EEPROM_DATA);
  9184. return 0;
  9185. }
  9186. #define NVRAM_CMD_TIMEOUT 10000
  9187. static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
  9188. {
  9189. int i;
  9190. tw32(NVRAM_CMD, nvram_cmd);
  9191. for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
  9192. udelay(10);
  9193. if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
  9194. udelay(10);
  9195. break;
  9196. }
  9197. }
  9198. if (i == NVRAM_CMD_TIMEOUT) {
  9199. return -EBUSY;
  9200. }
  9201. return 0;
  9202. }
  9203. static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
  9204. {
  9205. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  9206. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  9207. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  9208. !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
  9209. (tp->nvram_jedecnum == JEDEC_ATMEL))
  9210. addr = ((addr / tp->nvram_pagesize) <<
  9211. ATMEL_AT45DB0X1B_PAGE_POS) +
  9212. (addr % tp->nvram_pagesize);
  9213. return addr;
  9214. }
  9215. static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
  9216. {
  9217. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  9218. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  9219. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  9220. !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
  9221. (tp->nvram_jedecnum == JEDEC_ATMEL))
  9222. addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
  9223. tp->nvram_pagesize) +
  9224. (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
  9225. return addr;
  9226. }
  9227. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
  9228. {
  9229. int ret;
  9230. if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
  9231. return tg3_nvram_read_using_eeprom(tp, offset, val);
  9232. offset = tg3_nvram_phys_addr(tp, offset);
  9233. if (offset > NVRAM_ADDR_MSK)
  9234. return -EINVAL;
  9235. ret = tg3_nvram_lock(tp);
  9236. if (ret)
  9237. return ret;
  9238. tg3_enable_nvram_access(tp);
  9239. tw32(NVRAM_ADDR, offset);
  9240. ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
  9241. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  9242. if (ret == 0)
  9243. *val = swab32(tr32(NVRAM_RDDATA));
  9244. tg3_disable_nvram_access(tp);
  9245. tg3_nvram_unlock(tp);
  9246. return ret;
  9247. }
  9248. static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
  9249. {
  9250. u32 v;
  9251. int res = tg3_nvram_read(tp, offset, &v);
  9252. if (!res)
  9253. *val = cpu_to_le32(v);
  9254. return res;
  9255. }
  9256. static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
  9257. {
  9258. int err;
  9259. u32 tmp;
  9260. err = tg3_nvram_read(tp, offset, &tmp);
  9261. *val = swab32(tmp);
  9262. return err;
  9263. }
  9264. static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
  9265. u32 offset, u32 len, u8 *buf)
  9266. {
  9267. int i, j, rc = 0;
  9268. u32 val;
  9269. for (i = 0; i < len; i += 4) {
  9270. u32 addr;
  9271. __le32 data;
  9272. addr = offset + i;
  9273. memcpy(&data, buf + i, 4);
  9274. tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
  9275. val = tr32(GRC_EEPROM_ADDR);
  9276. tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
  9277. val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
  9278. EEPROM_ADDR_READ);
  9279. tw32(GRC_EEPROM_ADDR, val |
  9280. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  9281. (addr & EEPROM_ADDR_ADDR_MASK) |
  9282. EEPROM_ADDR_START |
  9283. EEPROM_ADDR_WRITE);
  9284. for (j = 0; j < 1000; j++) {
  9285. val = tr32(GRC_EEPROM_ADDR);
  9286. if (val & EEPROM_ADDR_COMPLETE)
  9287. break;
  9288. msleep(1);
  9289. }
  9290. if (!(val & EEPROM_ADDR_COMPLETE)) {
  9291. rc = -EBUSY;
  9292. break;
  9293. }
  9294. }
  9295. return rc;
  9296. }
  9297. /* offset and length are dword aligned */
  9298. static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
  9299. u8 *buf)
  9300. {
  9301. int ret = 0;
  9302. u32 pagesize = tp->nvram_pagesize;
  9303. u32 pagemask = pagesize - 1;
  9304. u32 nvram_cmd;
  9305. u8 *tmp;
  9306. tmp = kmalloc(pagesize, GFP_KERNEL);
  9307. if (tmp == NULL)
  9308. return -ENOMEM;
  9309. while (len) {
  9310. int j;
  9311. u32 phy_addr, page_off, size;
  9312. phy_addr = offset & ~pagemask;
  9313. for (j = 0; j < pagesize; j += 4) {
  9314. if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
  9315. (__le32 *) (tmp + j))))
  9316. break;
  9317. }
  9318. if (ret)
  9319. break;
  9320. page_off = offset & pagemask;
  9321. size = pagesize;
  9322. if (len < size)
  9323. size = len;
  9324. len -= size;
  9325. memcpy(tmp + page_off, buf, size);
  9326. offset = offset + (pagesize - page_off);
  9327. tg3_enable_nvram_access(tp);
  9328. /*
  9329. * Before we can erase the flash page, we need
  9330. * to issue a special "write enable" command.
  9331. */
  9332. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  9333. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  9334. break;
  9335. /* Erase the target page */
  9336. tw32(NVRAM_ADDR, phy_addr);
  9337. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
  9338. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
  9339. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  9340. break;
  9341. /* Issue another write enable to start the write. */
  9342. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  9343. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  9344. break;
  9345. for (j = 0; j < pagesize; j += 4) {
  9346. __be32 data;
  9347. data = *((__be32 *) (tmp + j));
  9348. /* swab32(le32_to_cpu(data)), actually */
  9349. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  9350. tw32(NVRAM_ADDR, phy_addr + j);
  9351. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
  9352. NVRAM_CMD_WR;
  9353. if (j == 0)
  9354. nvram_cmd |= NVRAM_CMD_FIRST;
  9355. else if (j == (pagesize - 4))
  9356. nvram_cmd |= NVRAM_CMD_LAST;
  9357. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  9358. break;
  9359. }
  9360. if (ret)
  9361. break;
  9362. }
  9363. nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  9364. tg3_nvram_exec_cmd(tp, nvram_cmd);
  9365. kfree(tmp);
  9366. return ret;
  9367. }
  9368. /* offset and length are dword aligned */
  9369. static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
  9370. u8 *buf)
  9371. {
  9372. int i, ret = 0;
  9373. for (i = 0; i < len; i += 4, offset += 4) {
  9374. u32 page_off, phy_addr, nvram_cmd;
  9375. __be32 data;
  9376. memcpy(&data, buf + i, 4);
  9377. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  9378. page_off = offset % tp->nvram_pagesize;
  9379. phy_addr = tg3_nvram_phys_addr(tp, offset);
  9380. tw32(NVRAM_ADDR, phy_addr);
  9381. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
  9382. if ((page_off == 0) || (i == 0))
  9383. nvram_cmd |= NVRAM_CMD_FIRST;
  9384. if (page_off == (tp->nvram_pagesize - 4))
  9385. nvram_cmd |= NVRAM_CMD_LAST;
  9386. if (i == (len - 4))
  9387. nvram_cmd |= NVRAM_CMD_LAST;
  9388. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
  9389. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
  9390. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
  9391. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
  9392. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
  9393. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) &&
  9394. (tp->nvram_jedecnum == JEDEC_ST) &&
  9395. (nvram_cmd & NVRAM_CMD_FIRST)) {
  9396. if ((ret = tg3_nvram_exec_cmd(tp,
  9397. NVRAM_CMD_WREN | NVRAM_CMD_GO |
  9398. NVRAM_CMD_DONE)))
  9399. break;
  9400. }
  9401. if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  9402. /* We always do complete word writes to eeprom. */
  9403. nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
  9404. }
  9405. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  9406. break;
  9407. }
  9408. return ret;
  9409. }
  9410. /* offset and length are dword aligned */
  9411. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
  9412. {
  9413. int ret;
  9414. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  9415. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  9416. ~GRC_LCLCTRL_GPIO_OUTPUT1);
  9417. udelay(40);
  9418. }
  9419. if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
  9420. ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
  9421. }
  9422. else {
  9423. u32 grc_mode;
  9424. ret = tg3_nvram_lock(tp);
  9425. if (ret)
  9426. return ret;
  9427. tg3_enable_nvram_access(tp);
  9428. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  9429. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
  9430. tw32(NVRAM_WRITE1, 0x406);
  9431. grc_mode = tr32(GRC_MODE);
  9432. tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
  9433. if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
  9434. !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  9435. ret = tg3_nvram_write_block_buffered(tp, offset, len,
  9436. buf);
  9437. }
  9438. else {
  9439. ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
  9440. buf);
  9441. }
  9442. grc_mode = tr32(GRC_MODE);
  9443. tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
  9444. tg3_disable_nvram_access(tp);
  9445. tg3_nvram_unlock(tp);
  9446. }
  9447. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  9448. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  9449. udelay(40);
  9450. }
  9451. return ret;
  9452. }
  9453. struct subsys_tbl_ent {
  9454. u16 subsys_vendor, subsys_devid;
  9455. u32 phy_id;
  9456. };
  9457. static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
  9458. /* Broadcom boards. */
  9459. { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
  9460. { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
  9461. { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
  9462. { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
  9463. { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
  9464. { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
  9465. { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
  9466. { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
  9467. { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
  9468. { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
  9469. { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
  9470. /* 3com boards. */
  9471. { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
  9472. { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
  9473. { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
  9474. { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
  9475. { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
  9476. /* DELL boards. */
  9477. { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
  9478. { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
  9479. { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
  9480. { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
  9481. /* Compaq boards. */
  9482. { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
  9483. { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
  9484. { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
  9485. { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
  9486. { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
  9487. /* IBM boards. */
  9488. { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
  9489. };
  9490. static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
  9491. {
  9492. int i;
  9493. for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  9494. if ((subsys_id_to_phy_id[i].subsys_vendor ==
  9495. tp->pdev->subsystem_vendor) &&
  9496. (subsys_id_to_phy_id[i].subsys_devid ==
  9497. tp->pdev->subsystem_device))
  9498. return &subsys_id_to_phy_id[i];
  9499. }
  9500. return NULL;
  9501. }
  9502. static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
  9503. {
  9504. u32 val;
  9505. u16 pmcsr;
  9506. /* On some early chips the SRAM cannot be accessed in D3hot state,
  9507. * so need make sure we're in D0.
  9508. */
  9509. pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
  9510. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  9511. pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
  9512. msleep(1);
  9513. /* Make sure register accesses (indirect or otherwise)
  9514. * will function correctly.
  9515. */
  9516. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  9517. tp->misc_host_ctrl);
  9518. /* The memory arbiter has to be enabled in order for SRAM accesses
  9519. * to succeed. Normally on powerup the tg3 chip firmware will make
  9520. * sure it is enabled, but other entities such as system netboot
  9521. * code might disable it.
  9522. */
  9523. val = tr32(MEMARB_MODE);
  9524. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  9525. tp->phy_id = PHY_ID_INVALID;
  9526. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  9527. /* Assume an onboard device and WOL capable by default. */
  9528. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
  9529. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9530. if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
  9531. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  9532. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  9533. }
  9534. val = tr32(VCPU_CFGSHDW);
  9535. if (val & VCPU_CFGSHDW_ASPM_DBNC)
  9536. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  9537. if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
  9538. (val & VCPU_CFGSHDW_WOL_MAGPKT) &&
  9539. device_may_wakeup(&tp->pdev->dev))
  9540. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  9541. return;
  9542. }
  9543. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  9544. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  9545. u32 nic_cfg, led_cfg;
  9546. u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
  9547. int eeprom_phy_serdes = 0;
  9548. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  9549. tp->nic_sram_data_cfg = nic_cfg;
  9550. tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
  9551. ver >>= NIC_SRAM_DATA_VER_SHIFT;
  9552. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
  9553. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
  9554. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
  9555. (ver > 0) && (ver < 0x100))
  9556. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
  9557. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  9558. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
  9559. if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  9560. NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
  9561. eeprom_phy_serdes = 1;
  9562. tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  9563. if (nic_phy_id != 0) {
  9564. u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  9565. u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  9566. eeprom_phy_id = (id1 >> 16) << 10;
  9567. eeprom_phy_id |= (id2 & 0xfc00) << 16;
  9568. eeprom_phy_id |= (id2 & 0x03ff) << 0;
  9569. } else
  9570. eeprom_phy_id = 0;
  9571. tp->phy_id = eeprom_phy_id;
  9572. if (eeprom_phy_serdes) {
  9573. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  9574. tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
  9575. else
  9576. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  9577. }
  9578. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  9579. led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
  9580. SHASTA_EXT_LED_MODE_MASK);
  9581. else
  9582. led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
  9583. switch (led_cfg) {
  9584. default:
  9585. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
  9586. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  9587. break;
  9588. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
  9589. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  9590. break;
  9591. case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
  9592. tp->led_ctrl = LED_CTRL_MODE_MAC;
  9593. /* Default to PHY_1_MODE if 0 (MAC_MODE) is
  9594. * read on some older 5700/5701 bootcode.
  9595. */
  9596. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  9597. ASIC_REV_5700 ||
  9598. GET_ASIC_REV(tp->pci_chip_rev_id) ==
  9599. ASIC_REV_5701)
  9600. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  9601. break;
  9602. case SHASTA_EXT_LED_SHARED:
  9603. tp->led_ctrl = LED_CTRL_MODE_SHARED;
  9604. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
  9605. tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
  9606. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  9607. LED_CTRL_MODE_PHY_2);
  9608. break;
  9609. case SHASTA_EXT_LED_MAC:
  9610. tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
  9611. break;
  9612. case SHASTA_EXT_LED_COMBO:
  9613. tp->led_ctrl = LED_CTRL_MODE_COMBO;
  9614. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
  9615. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  9616. LED_CTRL_MODE_PHY_2);
  9617. break;
  9618. }
  9619. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9620. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
  9621. tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  9622. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  9623. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
  9624. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  9625. if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
  9626. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
  9627. if ((tp->pdev->subsystem_vendor ==
  9628. PCI_VENDOR_ID_ARIMA) &&
  9629. (tp->pdev->subsystem_device == 0x205a ||
  9630. tp->pdev->subsystem_device == 0x2063))
  9631. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  9632. } else {
  9633. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  9634. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  9635. }
  9636. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  9637. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  9638. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  9639. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  9640. }
  9641. if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
  9642. tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
  9643. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
  9644. !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
  9645. tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
  9646. if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
  9647. (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE) &&
  9648. device_may_wakeup(&tp->pdev->dev))
  9649. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  9650. if (cfg2 & (1 << 17))
  9651. tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
  9652. /* serdes signal pre-emphasis in register 0x590 set by */
  9653. /* bootcode if bit 18 is set */
  9654. if (cfg2 & (1 << 18))
  9655. tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
  9656. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  9657. u32 cfg3;
  9658. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
  9659. if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
  9660. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  9661. }
  9662. if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
  9663. tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
  9664. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
  9665. tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
  9666. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
  9667. tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
  9668. }
  9669. }
  9670. static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
  9671. {
  9672. int i;
  9673. u32 val;
  9674. tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
  9675. tw32(OTP_CTRL, cmd);
  9676. /* Wait for up to 1 ms for command to execute. */
  9677. for (i = 0; i < 100; i++) {
  9678. val = tr32(OTP_STATUS);
  9679. if (val & OTP_STATUS_CMD_DONE)
  9680. break;
  9681. udelay(10);
  9682. }
  9683. return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
  9684. }
  9685. /* Read the gphy configuration from the OTP region of the chip. The gphy
  9686. * configuration is a 32-bit value that straddles the alignment boundary.
  9687. * We do two 32-bit reads and then shift and merge the results.
  9688. */
  9689. static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
  9690. {
  9691. u32 bhalf_otp, thalf_otp;
  9692. tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
  9693. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
  9694. return 0;
  9695. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
  9696. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  9697. return 0;
  9698. thalf_otp = tr32(OTP_READ_DATA);
  9699. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
  9700. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  9701. return 0;
  9702. bhalf_otp = tr32(OTP_READ_DATA);
  9703. return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
  9704. }
  9705. static int __devinit tg3_phy_probe(struct tg3 *tp)
  9706. {
  9707. u32 hw_phy_id_1, hw_phy_id_2;
  9708. u32 hw_phy_id, hw_phy_id_masked;
  9709. int err;
  9710. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
  9711. return tg3_phy_init(tp);
  9712. /* Reading the PHY ID register can conflict with ASF
  9713. * firwmare access to the PHY hardware.
  9714. */
  9715. err = 0;
  9716. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  9717. (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
  9718. hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
  9719. } else {
  9720. /* Now read the physical PHY_ID from the chip and verify
  9721. * that it is sane. If it doesn't look good, we fall back
  9722. * to either the hard-coded table based PHY_ID and failing
  9723. * that the value found in the eeprom area.
  9724. */
  9725. err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  9726. err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  9727. hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
  9728. hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  9729. hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
  9730. hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
  9731. }
  9732. if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
  9733. tp->phy_id = hw_phy_id;
  9734. if (hw_phy_id_masked == PHY_ID_BCM8002)
  9735. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  9736. else
  9737. tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
  9738. } else {
  9739. if (tp->phy_id != PHY_ID_INVALID) {
  9740. /* Do nothing, phy ID already set up in
  9741. * tg3_get_eeprom_hw_cfg().
  9742. */
  9743. } else {
  9744. struct subsys_tbl_ent *p;
  9745. /* No eeprom signature? Try the hardcoded
  9746. * subsys device table.
  9747. */
  9748. p = lookup_by_subsys(tp);
  9749. if (!p)
  9750. return -ENODEV;
  9751. tp->phy_id = p->phy_id;
  9752. if (!tp->phy_id ||
  9753. tp->phy_id == PHY_ID_BCM8002)
  9754. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  9755. }
  9756. }
  9757. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
  9758. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
  9759. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  9760. u32 bmsr, adv_reg, tg3_ctrl, mask;
  9761. tg3_readphy(tp, MII_BMSR, &bmsr);
  9762. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  9763. (bmsr & BMSR_LSTATUS))
  9764. goto skip_phy_reset;
  9765. err = tg3_phy_reset(tp);
  9766. if (err)
  9767. return err;
  9768. adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  9769. ADVERTISE_100HALF | ADVERTISE_100FULL |
  9770. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  9771. tg3_ctrl = 0;
  9772. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  9773. tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
  9774. MII_TG3_CTRL_ADV_1000_FULL);
  9775. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  9776. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  9777. tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
  9778. MII_TG3_CTRL_ENABLE_AS_MASTER);
  9779. }
  9780. mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  9781. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  9782. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
  9783. if (!tg3_copper_is_advertising_all(tp, mask)) {
  9784. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  9785. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  9786. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  9787. tg3_writephy(tp, MII_BMCR,
  9788. BMCR_ANENABLE | BMCR_ANRESTART);
  9789. }
  9790. tg3_phy_set_wirespeed(tp);
  9791. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  9792. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  9793. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  9794. }
  9795. skip_phy_reset:
  9796. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  9797. err = tg3_init_5401phy_dsp(tp);
  9798. if (err)
  9799. return err;
  9800. }
  9801. if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
  9802. err = tg3_init_5401phy_dsp(tp);
  9803. }
  9804. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  9805. tp->link_config.advertising =
  9806. (ADVERTISED_1000baseT_Half |
  9807. ADVERTISED_1000baseT_Full |
  9808. ADVERTISED_Autoneg |
  9809. ADVERTISED_FIBRE);
  9810. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  9811. tp->link_config.advertising &=
  9812. ~(ADVERTISED_1000baseT_Half |
  9813. ADVERTISED_1000baseT_Full);
  9814. return err;
  9815. }
  9816. static void __devinit tg3_read_partno(struct tg3 *tp)
  9817. {
  9818. unsigned char vpd_data[256];
  9819. unsigned int i;
  9820. u32 magic;
  9821. if (tg3_nvram_read_swab(tp, 0x0, &magic))
  9822. goto out_not_found;
  9823. if (magic == TG3_EEPROM_MAGIC) {
  9824. for (i = 0; i < 256; i += 4) {
  9825. u32 tmp;
  9826. if (tg3_nvram_read(tp, 0x100 + i, &tmp))
  9827. goto out_not_found;
  9828. vpd_data[i + 0] = ((tmp >> 0) & 0xff);
  9829. vpd_data[i + 1] = ((tmp >> 8) & 0xff);
  9830. vpd_data[i + 2] = ((tmp >> 16) & 0xff);
  9831. vpd_data[i + 3] = ((tmp >> 24) & 0xff);
  9832. }
  9833. } else {
  9834. int vpd_cap;
  9835. vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
  9836. for (i = 0; i < 256; i += 4) {
  9837. u32 tmp, j = 0;
  9838. __le32 v;
  9839. u16 tmp16;
  9840. pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
  9841. i);
  9842. while (j++ < 100) {
  9843. pci_read_config_word(tp->pdev, vpd_cap +
  9844. PCI_VPD_ADDR, &tmp16);
  9845. if (tmp16 & 0x8000)
  9846. break;
  9847. msleep(1);
  9848. }
  9849. if (!(tmp16 & 0x8000))
  9850. goto out_not_found;
  9851. pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
  9852. &tmp);
  9853. v = cpu_to_le32(tmp);
  9854. memcpy(&vpd_data[i], &v, 4);
  9855. }
  9856. }
  9857. /* Now parse and find the part number. */
  9858. for (i = 0; i < 254; ) {
  9859. unsigned char val = vpd_data[i];
  9860. unsigned int block_end;
  9861. if (val == 0x82 || val == 0x91) {
  9862. i = (i + 3 +
  9863. (vpd_data[i + 1] +
  9864. (vpd_data[i + 2] << 8)));
  9865. continue;
  9866. }
  9867. if (val != 0x90)
  9868. goto out_not_found;
  9869. block_end = (i + 3 +
  9870. (vpd_data[i + 1] +
  9871. (vpd_data[i + 2] << 8)));
  9872. i += 3;
  9873. if (block_end > 256)
  9874. goto out_not_found;
  9875. while (i < (block_end - 2)) {
  9876. if (vpd_data[i + 0] == 'P' &&
  9877. vpd_data[i + 1] == 'N') {
  9878. int partno_len = vpd_data[i + 2];
  9879. i += 3;
  9880. if (partno_len > 24 || (partno_len + i) > 256)
  9881. goto out_not_found;
  9882. memcpy(tp->board_part_number,
  9883. &vpd_data[i], partno_len);
  9884. /* Success. */
  9885. return;
  9886. }
  9887. i += 3 + vpd_data[i + 2];
  9888. }
  9889. /* Part number not found. */
  9890. goto out_not_found;
  9891. }
  9892. out_not_found:
  9893. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9894. strcpy(tp->board_part_number, "BCM95906");
  9895. else
  9896. strcpy(tp->board_part_number, "none");
  9897. }
  9898. static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
  9899. {
  9900. u32 val;
  9901. if (tg3_nvram_read_swab(tp, offset, &val) ||
  9902. (val & 0xfc000000) != 0x0c000000 ||
  9903. tg3_nvram_read_swab(tp, offset + 4, &val) ||
  9904. val != 0)
  9905. return 0;
  9906. return 1;
  9907. }
  9908. static void __devinit tg3_read_fw_ver(struct tg3 *tp)
  9909. {
  9910. u32 val, offset, start;
  9911. u32 ver_offset;
  9912. int i, bcnt;
  9913. if (tg3_nvram_read_swab(tp, 0, &val))
  9914. return;
  9915. if (val != TG3_EEPROM_MAGIC)
  9916. return;
  9917. if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
  9918. tg3_nvram_read_swab(tp, 0x4, &start))
  9919. return;
  9920. offset = tg3_nvram_logical_addr(tp, offset);
  9921. if (!tg3_fw_img_is_valid(tp, offset) ||
  9922. tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
  9923. return;
  9924. offset = offset + ver_offset - start;
  9925. for (i = 0; i < 16; i += 4) {
  9926. __le32 v;
  9927. if (tg3_nvram_read_le(tp, offset + i, &v))
  9928. return;
  9929. memcpy(tp->fw_ver + i, &v, 4);
  9930. }
  9931. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  9932. (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  9933. return;
  9934. for (offset = TG3_NVM_DIR_START;
  9935. offset < TG3_NVM_DIR_END;
  9936. offset += TG3_NVM_DIRENT_SIZE) {
  9937. if (tg3_nvram_read_swab(tp, offset, &val))
  9938. return;
  9939. if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
  9940. break;
  9941. }
  9942. if (offset == TG3_NVM_DIR_END)
  9943. return;
  9944. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  9945. start = 0x08000000;
  9946. else if (tg3_nvram_read_swab(tp, offset - 4, &start))
  9947. return;
  9948. if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
  9949. !tg3_fw_img_is_valid(tp, offset) ||
  9950. tg3_nvram_read_swab(tp, offset + 8, &val))
  9951. return;
  9952. offset += val - start;
  9953. bcnt = strlen(tp->fw_ver);
  9954. tp->fw_ver[bcnt++] = ',';
  9955. tp->fw_ver[bcnt++] = ' ';
  9956. for (i = 0; i < 4; i++) {
  9957. __le32 v;
  9958. if (tg3_nvram_read_le(tp, offset, &v))
  9959. return;
  9960. offset += sizeof(v);
  9961. if (bcnt > TG3_VER_SIZE - sizeof(v)) {
  9962. memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
  9963. break;
  9964. }
  9965. memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
  9966. bcnt += sizeof(v);
  9967. }
  9968. tp->fw_ver[TG3_VER_SIZE - 1] = 0;
  9969. }
  9970. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
  9971. static int __devinit tg3_get_invariants(struct tg3 *tp)
  9972. {
  9973. static struct pci_device_id write_reorder_chipsets[] = {
  9974. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  9975. PCI_DEVICE_ID_AMD_FE_GATE_700C) },
  9976. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  9977. PCI_DEVICE_ID_AMD_8131_BRIDGE) },
  9978. { PCI_DEVICE(PCI_VENDOR_ID_VIA,
  9979. PCI_DEVICE_ID_VIA_8385_0) },
  9980. { },
  9981. };
  9982. u32 misc_ctrl_reg;
  9983. u32 cacheline_sz_reg;
  9984. u32 pci_state_reg, grc_misc_cfg;
  9985. u32 val;
  9986. u16 pci_cmd;
  9987. int err, pcie_cap;
  9988. /* Force memory write invalidate off. If we leave it on,
  9989. * then on 5700_BX chips we have to enable a workaround.
  9990. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  9991. * to match the cacheline size. The Broadcom driver have this
  9992. * workaround but turns MWI off all the times so never uses
  9993. * it. This seems to suggest that the workaround is insufficient.
  9994. */
  9995. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9996. pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  9997. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9998. /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
  9999. * has the register indirect write enable bit set before
  10000. * we try to access any of the MMIO registers. It is also
  10001. * critical that the PCI-X hw workaround situation is decided
  10002. * before that as well.
  10003. */
  10004. pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  10005. &misc_ctrl_reg);
  10006. tp->pci_chip_rev_id = (misc_ctrl_reg >>
  10007. MISC_HOST_CTRL_CHIPREV_SHIFT);
  10008. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
  10009. u32 prod_id_asic_rev;
  10010. pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
  10011. &prod_id_asic_rev);
  10012. tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
  10013. }
  10014. /* Wrong chip ID in 5752 A0. This code can be removed later
  10015. * as A0 is not in production.
  10016. */
  10017. if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
  10018. tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
  10019. /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
  10020. * we need to disable memory and use config. cycles
  10021. * only to access all registers. The 5702/03 chips
  10022. * can mistakenly decode the special cycles from the
  10023. * ICH chipsets as memory write cycles, causing corruption
  10024. * of register and memory space. Only certain ICH bridges
  10025. * will drive special cycles with non-zero data during the
  10026. * address phase which can fall within the 5703's address
  10027. * range. This is not an ICH bug as the PCI spec allows
  10028. * non-zero address during special cycles. However, only
  10029. * these ICH bridges are known to drive non-zero addresses
  10030. * during special cycles.
  10031. *
  10032. * Since special cycles do not cross PCI bridges, we only
  10033. * enable this workaround if the 5703 is on the secondary
  10034. * bus of these ICH bridges.
  10035. */
  10036. if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
  10037. (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
  10038. static struct tg3_dev_id {
  10039. u32 vendor;
  10040. u32 device;
  10041. u32 rev;
  10042. } ich_chipsets[] = {
  10043. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
  10044. PCI_ANY_ID },
  10045. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
  10046. PCI_ANY_ID },
  10047. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
  10048. 0xa },
  10049. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
  10050. PCI_ANY_ID },
  10051. { },
  10052. };
  10053. struct tg3_dev_id *pci_id = &ich_chipsets[0];
  10054. struct pci_dev *bridge = NULL;
  10055. while (pci_id->vendor != 0) {
  10056. bridge = pci_get_device(pci_id->vendor, pci_id->device,
  10057. bridge);
  10058. if (!bridge) {
  10059. pci_id++;
  10060. continue;
  10061. }
  10062. if (pci_id->rev != PCI_ANY_ID) {
  10063. if (bridge->revision > pci_id->rev)
  10064. continue;
  10065. }
  10066. if (bridge->subordinate &&
  10067. (bridge->subordinate->number ==
  10068. tp->pdev->bus->number)) {
  10069. tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
  10070. pci_dev_put(bridge);
  10071. break;
  10072. }
  10073. }
  10074. }
  10075. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  10076. static struct tg3_dev_id {
  10077. u32 vendor;
  10078. u32 device;
  10079. } bridge_chipsets[] = {
  10080. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
  10081. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
  10082. { },
  10083. };
  10084. struct tg3_dev_id *pci_id = &bridge_chipsets[0];
  10085. struct pci_dev *bridge = NULL;
  10086. while (pci_id->vendor != 0) {
  10087. bridge = pci_get_device(pci_id->vendor,
  10088. pci_id->device,
  10089. bridge);
  10090. if (!bridge) {
  10091. pci_id++;
  10092. continue;
  10093. }
  10094. if (bridge->subordinate &&
  10095. (bridge->subordinate->number <=
  10096. tp->pdev->bus->number) &&
  10097. (bridge->subordinate->subordinate >=
  10098. tp->pdev->bus->number)) {
  10099. tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
  10100. pci_dev_put(bridge);
  10101. break;
  10102. }
  10103. }
  10104. }
  10105. /* The EPB bridge inside 5714, 5715, and 5780 cannot support
  10106. * DMA addresses > 40-bit. This bridge may have other additional
  10107. * 57xx devices behind it in some 4-port NIC designs for example.
  10108. * Any tg3 device found behind the bridge will also need the 40-bit
  10109. * DMA workaround.
  10110. */
  10111. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
  10112. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  10113. tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
  10114. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  10115. tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
  10116. }
  10117. else {
  10118. struct pci_dev *bridge = NULL;
  10119. do {
  10120. bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  10121. PCI_DEVICE_ID_SERVERWORKS_EPB,
  10122. bridge);
  10123. if (bridge && bridge->subordinate &&
  10124. (bridge->subordinate->number <=
  10125. tp->pdev->bus->number) &&
  10126. (bridge->subordinate->subordinate >=
  10127. tp->pdev->bus->number)) {
  10128. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  10129. pci_dev_put(bridge);
  10130. break;
  10131. }
  10132. } while (bridge);
  10133. }
  10134. /* Initialize misc host control in PCI block. */
  10135. tp->misc_host_ctrl |= (misc_ctrl_reg &
  10136. MISC_HOST_CTRL_CHIPREV);
  10137. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  10138. tp->misc_host_ctrl);
  10139. pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  10140. &cacheline_sz_reg);
  10141. tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
  10142. tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
  10143. tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
  10144. tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
  10145. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  10146. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
  10147. tp->pdev_peer = tg3_find_peer(tp);
  10148. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  10149. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  10150. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  10151. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  10152. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10153. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  10154. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  10155. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  10156. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  10157. tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
  10158. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
  10159. (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  10160. tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
  10161. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  10162. tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
  10163. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
  10164. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
  10165. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
  10166. tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
  10167. tp->pdev_peer == tp->pdev))
  10168. tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
  10169. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  10170. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  10171. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10172. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  10173. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  10174. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  10175. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
  10176. tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
  10177. } else {
  10178. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
  10179. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  10180. ASIC_REV_5750 &&
  10181. tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
  10182. tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
  10183. }
  10184. }
  10185. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  10186. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  10187. tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
  10188. pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
  10189. if (pcie_cap != 0) {
  10190. tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
  10191. pcie_set_readrq(tp->pdev, 4096);
  10192. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  10193. u16 lnkctl;
  10194. pci_read_config_word(tp->pdev,
  10195. pcie_cap + PCI_EXP_LNKCTL,
  10196. &lnkctl);
  10197. if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
  10198. tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
  10199. }
  10200. }
  10201. /* If we have an AMD 762 or VIA K8T800 chipset, write
  10202. * reordering to the mailbox registers done by the host
  10203. * controller can cause major troubles. We read back from
  10204. * every mailbox register write to force the writes to be
  10205. * posted to the chip in order.
  10206. */
  10207. if (pci_dev_present(write_reorder_chipsets) &&
  10208. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  10209. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  10210. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  10211. tp->pci_lat_timer < 64) {
  10212. tp->pci_lat_timer = 64;
  10213. cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
  10214. cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
  10215. cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
  10216. cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
  10217. pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  10218. cacheline_sz_reg);
  10219. }
  10220. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  10221. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  10222. tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
  10223. if (!tp->pcix_cap) {
  10224. printk(KERN_ERR PFX "Cannot find PCI-X "
  10225. "capability, aborting.\n");
  10226. return -EIO;
  10227. }
  10228. }
  10229. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  10230. &pci_state_reg);
  10231. if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
  10232. tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
  10233. /* If this is a 5700 BX chipset, and we are in PCI-X
  10234. * mode, enable register write workaround.
  10235. *
  10236. * The workaround is to use indirect register accesses
  10237. * for all chip writes not to mailbox registers.
  10238. */
  10239. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
  10240. u32 pm_reg;
  10241. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  10242. /* The chip can have it's power management PCI config
  10243. * space registers clobbered due to this bug.
  10244. * So explicitly force the chip into D0 here.
  10245. */
  10246. pci_read_config_dword(tp->pdev,
  10247. tp->pm_cap + PCI_PM_CTRL,
  10248. &pm_reg);
  10249. pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  10250. pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  10251. pci_write_config_dword(tp->pdev,
  10252. tp->pm_cap + PCI_PM_CTRL,
  10253. pm_reg);
  10254. /* Also, force SERR#/PERR# in PCI command. */
  10255. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  10256. pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  10257. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  10258. }
  10259. }
  10260. /* 5700 BX chips need to have their TX producer index mailboxes
  10261. * written twice to workaround a bug.
  10262. */
  10263. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
  10264. tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
  10265. if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  10266. tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
  10267. if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  10268. tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
  10269. /* Chip-specific fixup from Broadcom driver */
  10270. if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
  10271. (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  10272. pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  10273. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  10274. }
  10275. /* Default fast path register access methods */
  10276. tp->read32 = tg3_read32;
  10277. tp->write32 = tg3_write32;
  10278. tp->read32_mbox = tg3_read32;
  10279. tp->write32_mbox = tg3_write32;
  10280. tp->write32_tx_mbox = tg3_write32;
  10281. tp->write32_rx_mbox = tg3_write32;
  10282. /* Various workaround register access methods */
  10283. if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
  10284. tp->write32 = tg3_write_indirect_reg32;
  10285. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  10286. ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  10287. tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
  10288. /*
  10289. * Back to back register writes can cause problems on these
  10290. * chips, the workaround is to read back all reg writes
  10291. * except those to mailbox regs.
  10292. *
  10293. * See tg3_write_indirect_reg32().
  10294. */
  10295. tp->write32 = tg3_write_flush_reg32;
  10296. }
  10297. if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
  10298. (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
  10299. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  10300. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  10301. tp->write32_rx_mbox = tg3_write_flush_reg32;
  10302. }
  10303. if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
  10304. tp->read32 = tg3_read_indirect_reg32;
  10305. tp->write32 = tg3_write_indirect_reg32;
  10306. tp->read32_mbox = tg3_read_indirect_mbox;
  10307. tp->write32_mbox = tg3_write_indirect_mbox;
  10308. tp->write32_tx_mbox = tg3_write_indirect_mbox;
  10309. tp->write32_rx_mbox = tg3_write_indirect_mbox;
  10310. iounmap(tp->regs);
  10311. tp->regs = NULL;
  10312. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  10313. pci_cmd &= ~PCI_COMMAND_MEMORY;
  10314. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  10315. }
  10316. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  10317. tp->read32_mbox = tg3_read32_mbox_5906;
  10318. tp->write32_mbox = tg3_write32_mbox_5906;
  10319. tp->write32_tx_mbox = tg3_write32_mbox_5906;
  10320. tp->write32_rx_mbox = tg3_write32_mbox_5906;
  10321. }
  10322. if (tp->write32 == tg3_write_indirect_reg32 ||
  10323. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  10324. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  10325. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
  10326. tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
  10327. /* Get eeprom hw config before calling tg3_set_power_state().
  10328. * In particular, the TG3_FLG2_IS_NIC flag must be
  10329. * determined before calling tg3_set_power_state() so that
  10330. * we know whether or not to switch out of Vaux power.
  10331. * When the flag is set, it means that GPIO1 is used for eeprom
  10332. * write protect and also implies that it is a LOM where GPIOs
  10333. * are not used to switch power.
  10334. */
  10335. tg3_get_eeprom_hw_cfg(tp);
  10336. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  10337. /* Allow reads and writes to the
  10338. * APE register and memory space.
  10339. */
  10340. pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  10341. PCISTATE_ALLOW_APE_SHMEM_WR;
  10342. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
  10343. pci_state_reg);
  10344. }
  10345. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10346. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  10347. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
  10348. tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
  10349. if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
  10350. tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
  10351. tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
  10352. tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
  10353. tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
  10354. }
  10355. /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
  10356. * GPIO1 driven high will bring 5700's external PHY out of reset.
  10357. * It is also used as eeprom write protect on LOMs.
  10358. */
  10359. tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  10360. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  10361. (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
  10362. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  10363. GRC_LCLCTRL_GPIO_OUTPUT1);
  10364. /* Unused GPIO3 must be driven as output on 5752 because there
  10365. * are no pull-up resistors on unused GPIO pins.
  10366. */
  10367. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  10368. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  10369. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  10370. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  10371. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
  10372. /* Turn off the debug UART. */
  10373. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  10374. if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
  10375. /* Keep VMain power. */
  10376. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  10377. GRC_LCLCTRL_GPIO_OUTPUT0;
  10378. }
  10379. /* Force the chip into D0. */
  10380. err = tg3_set_power_state(tp, PCI_D0);
  10381. if (err) {
  10382. printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
  10383. pci_name(tp->pdev));
  10384. return err;
  10385. }
  10386. /* 5700 B0 chips do not support checksumming correctly due
  10387. * to hardware bugs.
  10388. */
  10389. if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
  10390. tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
  10391. /* Derive initial jumbo mode from MTU assigned in
  10392. * ether_setup() via the alloc_etherdev() call
  10393. */
  10394. if (tp->dev->mtu > ETH_DATA_LEN &&
  10395. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  10396. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  10397. /* Determine WakeOnLan speed to use. */
  10398. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  10399. tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  10400. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
  10401. tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
  10402. tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
  10403. } else {
  10404. tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
  10405. }
  10406. /* A few boards don't want Ethernet@WireSpeed phy feature */
  10407. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  10408. ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  10409. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
  10410. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
  10411. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
  10412. (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  10413. tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
  10414. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
  10415. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
  10416. tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
  10417. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
  10418. tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
  10419. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  10420. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  10421. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  10422. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10423. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
  10424. if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
  10425. tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
  10426. tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
  10427. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
  10428. tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
  10429. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
  10430. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
  10431. tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
  10432. }
  10433. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  10434. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
  10435. tp->phy_otp = tg3_read_otp_phycfg(tp);
  10436. if (tp->phy_otp == 0)
  10437. tp->phy_otp = TG3_OTP_DEFAULT;
  10438. }
  10439. if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
  10440. tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
  10441. else
  10442. tp->mi_mode = MAC_MI_MODE_BASE;
  10443. tp->coalesce_mode = 0;
  10444. if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
  10445. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
  10446. tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  10447. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  10448. tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
  10449. err = tg3_mdio_init(tp);
  10450. if (err)
  10451. return err;
  10452. /* Initialize data/descriptor byte/word swapping. */
  10453. val = tr32(GRC_MODE);
  10454. val &= GRC_MODE_HOST_STACKUP;
  10455. tw32(GRC_MODE, val | tp->grc_mode);
  10456. tg3_switch_clocks(tp);
  10457. /* Clear this out for sanity. */
  10458. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  10459. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  10460. &pci_state_reg);
  10461. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  10462. (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
  10463. u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
  10464. if (chiprevid == CHIPREV_ID_5701_A0 ||
  10465. chiprevid == CHIPREV_ID_5701_B0 ||
  10466. chiprevid == CHIPREV_ID_5701_B2 ||
  10467. chiprevid == CHIPREV_ID_5701_B5) {
  10468. void __iomem *sram_base;
  10469. /* Write some dummy words into the SRAM status block
  10470. * area, see if it reads back correctly. If the return
  10471. * value is bad, force enable the PCIX workaround.
  10472. */
  10473. sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  10474. writel(0x00000000, sram_base);
  10475. writel(0x00000000, sram_base + 4);
  10476. writel(0xffffffff, sram_base + 4);
  10477. if (readl(sram_base) != 0x00000000)
  10478. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  10479. }
  10480. }
  10481. udelay(50);
  10482. tg3_nvram_init(tp);
  10483. grc_misc_cfg = tr32(GRC_MISC_CFG);
  10484. grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  10485. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  10486. (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  10487. grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  10488. tp->tg3_flags2 |= TG3_FLG2_IS_5788;
  10489. if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  10490. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
  10491. tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
  10492. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  10493. tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
  10494. HOSTCC_MODE_CLRTICK_TXBD);
  10495. tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
  10496. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  10497. tp->misc_host_ctrl);
  10498. }
  10499. /* Preserve the APE MAC_MODE bits */
  10500. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  10501. tp->mac_mode = tr32(MAC_MODE) |
  10502. MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  10503. else
  10504. tp->mac_mode = TG3_DEF_MAC_MODE;
  10505. /* these are limited to 10/100 only */
  10506. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  10507. (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  10508. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  10509. tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  10510. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
  10511. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
  10512. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
  10513. (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  10514. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
  10515. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
  10516. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
  10517. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10518. tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
  10519. err = tg3_phy_probe(tp);
  10520. if (err) {
  10521. printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
  10522. pci_name(tp->pdev), err);
  10523. /* ... but do not return immediately ... */
  10524. tg3_mdio_fini(tp);
  10525. }
  10526. tg3_read_partno(tp);
  10527. tg3_read_fw_ver(tp);
  10528. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  10529. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  10530. } else {
  10531. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  10532. tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
  10533. else
  10534. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  10535. }
  10536. /* 5700 {AX,BX} chips have a broken status block link
  10537. * change bit implementation, so we must use the
  10538. * status register in those cases.
  10539. */
  10540. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  10541. tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
  10542. else
  10543. tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
  10544. /* The led_ctrl is set during tg3_phy_probe, here we might
  10545. * have to force the link status polling mechanism based
  10546. * upon subsystem IDs.
  10547. */
  10548. if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  10549. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  10550. !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  10551. tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
  10552. TG3_FLAG_USE_LINKCHG_REG);
  10553. }
  10554. /* For all SERDES we poll the MAC status register. */
  10555. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  10556. tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
  10557. else
  10558. tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
  10559. /* All chips before 5787 can get confused if TX buffers
  10560. * straddle the 4GB address boundary in some cases.
  10561. */
  10562. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  10563. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  10564. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10565. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  10566. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  10567. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10568. tp->dev->hard_start_xmit = tg3_start_xmit;
  10569. else
  10570. tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
  10571. tp->rx_offset = 2;
  10572. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  10573. (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
  10574. tp->rx_offset = 0;
  10575. tp->rx_std_max_post = TG3_RX_RING_SIZE;
  10576. /* Increment the rx prod index on the rx std ring by at most
  10577. * 8 for these chips to workaround hw errata.
  10578. */
  10579. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  10580. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  10581. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  10582. tp->rx_std_max_post = 8;
  10583. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
  10584. tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
  10585. PCIE_PWR_MGMT_L1_THRESH_MSK;
  10586. return err;
  10587. }
  10588. #ifdef CONFIG_SPARC
  10589. static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
  10590. {
  10591. struct net_device *dev = tp->dev;
  10592. struct pci_dev *pdev = tp->pdev;
  10593. struct device_node *dp = pci_device_to_OF_node(pdev);
  10594. const unsigned char *addr;
  10595. int len;
  10596. addr = of_get_property(dp, "local-mac-address", &len);
  10597. if (addr && len == 6) {
  10598. memcpy(dev->dev_addr, addr, 6);
  10599. memcpy(dev->perm_addr, dev->dev_addr, 6);
  10600. return 0;
  10601. }
  10602. return -ENODEV;
  10603. }
  10604. static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
  10605. {
  10606. struct net_device *dev = tp->dev;
  10607. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  10608. memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
  10609. return 0;
  10610. }
  10611. #endif
  10612. static int __devinit tg3_get_device_address(struct tg3 *tp)
  10613. {
  10614. struct net_device *dev = tp->dev;
  10615. u32 hi, lo, mac_offset;
  10616. int addr_ok = 0;
  10617. #ifdef CONFIG_SPARC
  10618. if (!tg3_get_macaddr_sparc(tp))
  10619. return 0;
  10620. #endif
  10621. mac_offset = 0x7c;
  10622. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  10623. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  10624. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  10625. mac_offset = 0xcc;
  10626. if (tg3_nvram_lock(tp))
  10627. tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
  10628. else
  10629. tg3_nvram_unlock(tp);
  10630. }
  10631. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10632. mac_offset = 0x10;
  10633. /* First try to get it from MAC address mailbox. */
  10634. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  10635. if ((hi >> 16) == 0x484b) {
  10636. dev->dev_addr[0] = (hi >> 8) & 0xff;
  10637. dev->dev_addr[1] = (hi >> 0) & 0xff;
  10638. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  10639. dev->dev_addr[2] = (lo >> 24) & 0xff;
  10640. dev->dev_addr[3] = (lo >> 16) & 0xff;
  10641. dev->dev_addr[4] = (lo >> 8) & 0xff;
  10642. dev->dev_addr[5] = (lo >> 0) & 0xff;
  10643. /* Some old bootcode may report a 0 MAC address in SRAM */
  10644. addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
  10645. }
  10646. if (!addr_ok) {
  10647. /* Next, try NVRAM. */
  10648. if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
  10649. !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
  10650. dev->dev_addr[0] = ((hi >> 16) & 0xff);
  10651. dev->dev_addr[1] = ((hi >> 24) & 0xff);
  10652. dev->dev_addr[2] = ((lo >> 0) & 0xff);
  10653. dev->dev_addr[3] = ((lo >> 8) & 0xff);
  10654. dev->dev_addr[4] = ((lo >> 16) & 0xff);
  10655. dev->dev_addr[5] = ((lo >> 24) & 0xff);
  10656. }
  10657. /* Finally just fetch it out of the MAC control regs. */
  10658. else {
  10659. hi = tr32(MAC_ADDR_0_HIGH);
  10660. lo = tr32(MAC_ADDR_0_LOW);
  10661. dev->dev_addr[5] = lo & 0xff;
  10662. dev->dev_addr[4] = (lo >> 8) & 0xff;
  10663. dev->dev_addr[3] = (lo >> 16) & 0xff;
  10664. dev->dev_addr[2] = (lo >> 24) & 0xff;
  10665. dev->dev_addr[1] = hi & 0xff;
  10666. dev->dev_addr[0] = (hi >> 8) & 0xff;
  10667. }
  10668. }
  10669. if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  10670. #ifdef CONFIG_SPARC
  10671. if (!tg3_get_default_macaddr_sparc(tp))
  10672. return 0;
  10673. #endif
  10674. return -EINVAL;
  10675. }
  10676. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  10677. return 0;
  10678. }
  10679. #define BOUNDARY_SINGLE_CACHELINE 1
  10680. #define BOUNDARY_MULTI_CACHELINE 2
  10681. static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
  10682. {
  10683. int cacheline_size;
  10684. u8 byte;
  10685. int goal;
  10686. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  10687. if (byte == 0)
  10688. cacheline_size = 1024;
  10689. else
  10690. cacheline_size = (int) byte * 4;
  10691. /* On 5703 and later chips, the boundary bits have no
  10692. * effect.
  10693. */
  10694. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  10695. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  10696. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  10697. goto out;
  10698. #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
  10699. goal = BOUNDARY_MULTI_CACHELINE;
  10700. #else
  10701. #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
  10702. goal = BOUNDARY_SINGLE_CACHELINE;
  10703. #else
  10704. goal = 0;
  10705. #endif
  10706. #endif
  10707. if (!goal)
  10708. goto out;
  10709. /* PCI controllers on most RISC systems tend to disconnect
  10710. * when a device tries to burst across a cache-line boundary.
  10711. * Therefore, letting tg3 do so just wastes PCI bandwidth.
  10712. *
  10713. * Unfortunately, for PCI-E there are only limited
  10714. * write-side controls for this, and thus for reads
  10715. * we will still get the disconnects. We'll also waste
  10716. * these PCI cycles for both read and write for chips
  10717. * other than 5700 and 5701 which do not implement the
  10718. * boundary bits.
  10719. */
  10720. if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  10721. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  10722. switch (cacheline_size) {
  10723. case 16:
  10724. case 32:
  10725. case 64:
  10726. case 128:
  10727. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10728. val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
  10729. DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
  10730. } else {
  10731. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  10732. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  10733. }
  10734. break;
  10735. case 256:
  10736. val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
  10737. DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
  10738. break;
  10739. default:
  10740. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  10741. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  10742. break;
  10743. }
  10744. } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  10745. switch (cacheline_size) {
  10746. case 16:
  10747. case 32:
  10748. case 64:
  10749. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10750. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  10751. val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
  10752. break;
  10753. }
  10754. /* fallthrough */
  10755. case 128:
  10756. default:
  10757. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  10758. val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
  10759. break;
  10760. }
  10761. } else {
  10762. switch (cacheline_size) {
  10763. case 16:
  10764. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10765. val |= (DMA_RWCTRL_READ_BNDRY_16 |
  10766. DMA_RWCTRL_WRITE_BNDRY_16);
  10767. break;
  10768. }
  10769. /* fallthrough */
  10770. case 32:
  10771. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10772. val |= (DMA_RWCTRL_READ_BNDRY_32 |
  10773. DMA_RWCTRL_WRITE_BNDRY_32);
  10774. break;
  10775. }
  10776. /* fallthrough */
  10777. case 64:
  10778. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10779. val |= (DMA_RWCTRL_READ_BNDRY_64 |
  10780. DMA_RWCTRL_WRITE_BNDRY_64);
  10781. break;
  10782. }
  10783. /* fallthrough */
  10784. case 128:
  10785. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10786. val |= (DMA_RWCTRL_READ_BNDRY_128 |
  10787. DMA_RWCTRL_WRITE_BNDRY_128);
  10788. break;
  10789. }
  10790. /* fallthrough */
  10791. case 256:
  10792. val |= (DMA_RWCTRL_READ_BNDRY_256 |
  10793. DMA_RWCTRL_WRITE_BNDRY_256);
  10794. break;
  10795. case 512:
  10796. val |= (DMA_RWCTRL_READ_BNDRY_512 |
  10797. DMA_RWCTRL_WRITE_BNDRY_512);
  10798. break;
  10799. case 1024:
  10800. default:
  10801. val |= (DMA_RWCTRL_READ_BNDRY_1024 |
  10802. DMA_RWCTRL_WRITE_BNDRY_1024);
  10803. break;
  10804. }
  10805. }
  10806. out:
  10807. return val;
  10808. }
  10809. static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
  10810. {
  10811. struct tg3_internal_buffer_desc test_desc;
  10812. u32 sram_dma_descs;
  10813. int i, ret;
  10814. sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  10815. tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  10816. tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  10817. tw32(RDMAC_STATUS, 0);
  10818. tw32(WDMAC_STATUS, 0);
  10819. tw32(BUFMGR_MODE, 0);
  10820. tw32(FTQ_RESET, 0);
  10821. test_desc.addr_hi = ((u64) buf_dma) >> 32;
  10822. test_desc.addr_lo = buf_dma & 0xffffffff;
  10823. test_desc.nic_mbuf = 0x00002100;
  10824. test_desc.len = size;
  10825. /*
  10826. * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
  10827. * the *second* time the tg3 driver was getting loaded after an
  10828. * initial scan.
  10829. *
  10830. * Broadcom tells me:
  10831. * ...the DMA engine is connected to the GRC block and a DMA
  10832. * reset may affect the GRC block in some unpredictable way...
  10833. * The behavior of resets to individual blocks has not been tested.
  10834. *
  10835. * Broadcom noted the GRC reset will also reset all sub-components.
  10836. */
  10837. if (to_device) {
  10838. test_desc.cqid_sqid = (13 << 8) | 2;
  10839. tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
  10840. udelay(40);
  10841. } else {
  10842. test_desc.cqid_sqid = (16 << 8) | 7;
  10843. tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
  10844. udelay(40);
  10845. }
  10846. test_desc.flags = 0x00000005;
  10847. for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  10848. u32 val;
  10849. val = *(((u32 *)&test_desc) + i);
  10850. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  10851. sram_dma_descs + (i * sizeof(u32)));
  10852. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  10853. }
  10854. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  10855. if (to_device) {
  10856. tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  10857. } else {
  10858. tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  10859. }
  10860. ret = -ENODEV;
  10861. for (i = 0; i < 40; i++) {
  10862. u32 val;
  10863. if (to_device)
  10864. val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  10865. else
  10866. val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  10867. if ((val & 0xffff) == sram_dma_descs) {
  10868. ret = 0;
  10869. break;
  10870. }
  10871. udelay(100);
  10872. }
  10873. return ret;
  10874. }
  10875. #define TEST_BUFFER_SIZE 0x2000
  10876. static int __devinit tg3_test_dma(struct tg3 *tp)
  10877. {
  10878. dma_addr_t buf_dma;
  10879. u32 *buf, saved_dma_rwctrl;
  10880. int ret;
  10881. buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
  10882. if (!buf) {
  10883. ret = -ENOMEM;
  10884. goto out_nofree;
  10885. }
  10886. tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  10887. (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
  10888. tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
  10889. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  10890. /* DMA read watermark not used on PCIE */
  10891. tp->dma_rwctrl |= 0x00180000;
  10892. } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  10893. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
  10894. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
  10895. tp->dma_rwctrl |= 0x003f0000;
  10896. else
  10897. tp->dma_rwctrl |= 0x003f000f;
  10898. } else {
  10899. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  10900. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  10901. u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
  10902. u32 read_water = 0x7;
  10903. /* If the 5704 is behind the EPB bridge, we can
  10904. * do the less restrictive ONE_DMA workaround for
  10905. * better performance.
  10906. */
  10907. if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
  10908. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  10909. tp->dma_rwctrl |= 0x8000;
  10910. else if (ccval == 0x6 || ccval == 0x7)
  10911. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  10912. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
  10913. read_water = 4;
  10914. /* Set bit 23 to enable PCIX hw bug fix */
  10915. tp->dma_rwctrl |=
  10916. (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
  10917. (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  10918. (1 << 23);
  10919. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
  10920. /* 5780 always in PCIX mode */
  10921. tp->dma_rwctrl |= 0x00144000;
  10922. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  10923. /* 5714 always in PCIX mode */
  10924. tp->dma_rwctrl |= 0x00148000;
  10925. } else {
  10926. tp->dma_rwctrl |= 0x001b000f;
  10927. }
  10928. }
  10929. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  10930. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  10931. tp->dma_rwctrl &= 0xfffffff0;
  10932. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  10933. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  10934. /* Remove this if it causes problems for some boards. */
  10935. tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  10936. /* On 5700/5701 chips, we need to set this bit.
  10937. * Otherwise the chip will issue cacheline transactions
  10938. * to streamable DMA memory with not all the byte
  10939. * enables turned on. This is an error on several
  10940. * RISC PCI controllers, in particular sparc64.
  10941. *
  10942. * On 5703/5704 chips, this bit has been reassigned
  10943. * a different meaning. In particular, it is used
  10944. * on those chips to enable a PCI-X workaround.
  10945. */
  10946. tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  10947. }
  10948. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  10949. #if 0
  10950. /* Unneeded, already done by tg3_get_invariants. */
  10951. tg3_switch_clocks(tp);
  10952. #endif
  10953. ret = 0;
  10954. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  10955. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  10956. goto out;
  10957. /* It is best to perform DMA test with maximum write burst size
  10958. * to expose the 5700/5701 write DMA bug.
  10959. */
  10960. saved_dma_rwctrl = tp->dma_rwctrl;
  10961. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  10962. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  10963. while (1) {
  10964. u32 *p = buf, i;
  10965. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  10966. p[i] = i;
  10967. /* Send the buffer to the chip. */
  10968. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
  10969. if (ret) {
  10970. printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
  10971. break;
  10972. }
  10973. #if 0
  10974. /* validate data reached card RAM correctly. */
  10975. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  10976. u32 val;
  10977. tg3_read_mem(tp, 0x2100 + (i*4), &val);
  10978. if (le32_to_cpu(val) != p[i]) {
  10979. printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
  10980. /* ret = -ENODEV here? */
  10981. }
  10982. p[i] = 0;
  10983. }
  10984. #endif
  10985. /* Now read it back. */
  10986. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
  10987. if (ret) {
  10988. printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
  10989. break;
  10990. }
  10991. /* Verify it. */
  10992. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  10993. if (p[i] == i)
  10994. continue;
  10995. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  10996. DMA_RWCTRL_WRITE_BNDRY_16) {
  10997. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  10998. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  10999. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  11000. break;
  11001. } else {
  11002. printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
  11003. ret = -ENODEV;
  11004. goto out;
  11005. }
  11006. }
  11007. if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  11008. /* Success. */
  11009. ret = 0;
  11010. break;
  11011. }
  11012. }
  11013. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  11014. DMA_RWCTRL_WRITE_BNDRY_16) {
  11015. static struct pci_device_id dma_wait_state_chipsets[] = {
  11016. { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
  11017. PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
  11018. { },
  11019. };
  11020. /* DMA test passed without adjusting DMA boundary,
  11021. * now look for chipsets that are known to expose the
  11022. * DMA bug without failing the test.
  11023. */
  11024. if (pci_dev_present(dma_wait_state_chipsets)) {
  11025. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  11026. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  11027. }
  11028. else
  11029. /* Safe to use the calculated DMA boundary. */
  11030. tp->dma_rwctrl = saved_dma_rwctrl;
  11031. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  11032. }
  11033. out:
  11034. pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
  11035. out_nofree:
  11036. return ret;
  11037. }
  11038. static void __devinit tg3_init_link_config(struct tg3 *tp)
  11039. {
  11040. tp->link_config.advertising =
  11041. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  11042. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  11043. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
  11044. ADVERTISED_Autoneg | ADVERTISED_MII);
  11045. tp->link_config.speed = SPEED_INVALID;
  11046. tp->link_config.duplex = DUPLEX_INVALID;
  11047. tp->link_config.autoneg = AUTONEG_ENABLE;
  11048. tp->link_config.active_speed = SPEED_INVALID;
  11049. tp->link_config.active_duplex = DUPLEX_INVALID;
  11050. tp->link_config.phy_is_low_power = 0;
  11051. tp->link_config.orig_speed = SPEED_INVALID;
  11052. tp->link_config.orig_duplex = DUPLEX_INVALID;
  11053. tp->link_config.orig_autoneg = AUTONEG_INVALID;
  11054. }
  11055. static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
  11056. {
  11057. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  11058. tp->bufmgr_config.mbuf_read_dma_low_water =
  11059. DEFAULT_MB_RDMA_LOW_WATER_5705;
  11060. tp->bufmgr_config.mbuf_mac_rx_low_water =
  11061. DEFAULT_MB_MACRX_LOW_WATER_5705;
  11062. tp->bufmgr_config.mbuf_high_water =
  11063. DEFAULT_MB_HIGH_WATER_5705;
  11064. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  11065. tp->bufmgr_config.mbuf_mac_rx_low_water =
  11066. DEFAULT_MB_MACRX_LOW_WATER_5906;
  11067. tp->bufmgr_config.mbuf_high_water =
  11068. DEFAULT_MB_HIGH_WATER_5906;
  11069. }
  11070. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  11071. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
  11072. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  11073. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
  11074. tp->bufmgr_config.mbuf_high_water_jumbo =
  11075. DEFAULT_MB_HIGH_WATER_JUMBO_5780;
  11076. } else {
  11077. tp->bufmgr_config.mbuf_read_dma_low_water =
  11078. DEFAULT_MB_RDMA_LOW_WATER;
  11079. tp->bufmgr_config.mbuf_mac_rx_low_water =
  11080. DEFAULT_MB_MACRX_LOW_WATER;
  11081. tp->bufmgr_config.mbuf_high_water =
  11082. DEFAULT_MB_HIGH_WATER;
  11083. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  11084. DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  11085. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  11086. DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  11087. tp->bufmgr_config.mbuf_high_water_jumbo =
  11088. DEFAULT_MB_HIGH_WATER_JUMBO;
  11089. }
  11090. tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  11091. tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  11092. }
  11093. static char * __devinit tg3_phy_string(struct tg3 *tp)
  11094. {
  11095. switch (tp->phy_id & PHY_ID_MASK) {
  11096. case PHY_ID_BCM5400: return "5400";
  11097. case PHY_ID_BCM5401: return "5401";
  11098. case PHY_ID_BCM5411: return "5411";
  11099. case PHY_ID_BCM5701: return "5701";
  11100. case PHY_ID_BCM5703: return "5703";
  11101. case PHY_ID_BCM5704: return "5704";
  11102. case PHY_ID_BCM5705: return "5705";
  11103. case PHY_ID_BCM5750: return "5750";
  11104. case PHY_ID_BCM5752: return "5752";
  11105. case PHY_ID_BCM5714: return "5714";
  11106. case PHY_ID_BCM5780: return "5780";
  11107. case PHY_ID_BCM5755: return "5755";
  11108. case PHY_ID_BCM5787: return "5787";
  11109. case PHY_ID_BCM5784: return "5784";
  11110. case PHY_ID_BCM5756: return "5722/5756";
  11111. case PHY_ID_BCM5906: return "5906";
  11112. case PHY_ID_BCM5761: return "5761";
  11113. case PHY_ID_BCM8002: return "8002/serdes";
  11114. case 0: return "serdes";
  11115. default: return "unknown";
  11116. }
  11117. }
  11118. static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
  11119. {
  11120. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  11121. strcpy(str, "PCI Express");
  11122. return str;
  11123. } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  11124. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
  11125. strcpy(str, "PCIX:");
  11126. if ((clock_ctrl == 7) ||
  11127. ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
  11128. GRC_MISC_CFG_BOARD_ID_5704CIOBE))
  11129. strcat(str, "133MHz");
  11130. else if (clock_ctrl == 0)
  11131. strcat(str, "33MHz");
  11132. else if (clock_ctrl == 2)
  11133. strcat(str, "50MHz");
  11134. else if (clock_ctrl == 4)
  11135. strcat(str, "66MHz");
  11136. else if (clock_ctrl == 6)
  11137. strcat(str, "100MHz");
  11138. } else {
  11139. strcpy(str, "PCI:");
  11140. if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
  11141. strcat(str, "66MHz");
  11142. else
  11143. strcat(str, "33MHz");
  11144. }
  11145. if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
  11146. strcat(str, ":32-bit");
  11147. else
  11148. strcat(str, ":64-bit");
  11149. return str;
  11150. }
  11151. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
  11152. {
  11153. struct pci_dev *peer;
  11154. unsigned int func, devnr = tp->pdev->devfn & ~7;
  11155. for (func = 0; func < 8; func++) {
  11156. peer = pci_get_slot(tp->pdev->bus, devnr | func);
  11157. if (peer && peer != tp->pdev)
  11158. break;
  11159. pci_dev_put(peer);
  11160. }
  11161. /* 5704 can be configured in single-port mode, set peer to
  11162. * tp->pdev in that case.
  11163. */
  11164. if (!peer) {
  11165. peer = tp->pdev;
  11166. return peer;
  11167. }
  11168. /*
  11169. * We don't need to keep the refcount elevated; there's no way
  11170. * to remove one half of this device without removing the other
  11171. */
  11172. pci_dev_put(peer);
  11173. return peer;
  11174. }
  11175. static void __devinit tg3_init_coal(struct tg3 *tp)
  11176. {
  11177. struct ethtool_coalesce *ec = &tp->coal;
  11178. memset(ec, 0, sizeof(*ec));
  11179. ec->cmd = ETHTOOL_GCOALESCE;
  11180. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
  11181. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
  11182. ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
  11183. ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
  11184. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
  11185. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
  11186. ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
  11187. ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
  11188. ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
  11189. if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
  11190. HOSTCC_MODE_CLRTICK_TXBD)) {
  11191. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
  11192. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
  11193. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
  11194. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
  11195. }
  11196. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  11197. ec->rx_coalesce_usecs_irq = 0;
  11198. ec->tx_coalesce_usecs_irq = 0;
  11199. ec->stats_block_coalesce_usecs = 0;
  11200. }
  11201. }
  11202. static int __devinit tg3_init_one(struct pci_dev *pdev,
  11203. const struct pci_device_id *ent)
  11204. {
  11205. static int tg3_version_printed = 0;
  11206. resource_size_t tg3reg_base;
  11207. unsigned long tg3reg_len;
  11208. struct net_device *dev;
  11209. struct tg3 *tp;
  11210. int err, pm_cap;
  11211. char str[40];
  11212. u64 dma_mask, persist_dma_mask;
  11213. DECLARE_MAC_BUF(mac);
  11214. if (tg3_version_printed++ == 0)
  11215. printk(KERN_INFO "%s", version);
  11216. err = pci_enable_device(pdev);
  11217. if (err) {
  11218. printk(KERN_ERR PFX "Cannot enable PCI device, "
  11219. "aborting.\n");
  11220. return err;
  11221. }
  11222. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  11223. printk(KERN_ERR PFX "Cannot find proper PCI device "
  11224. "base address, aborting.\n");
  11225. err = -ENODEV;
  11226. goto err_out_disable_pdev;
  11227. }
  11228. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  11229. if (err) {
  11230. printk(KERN_ERR PFX "Cannot obtain PCI resources, "
  11231. "aborting.\n");
  11232. goto err_out_disable_pdev;
  11233. }
  11234. pci_set_master(pdev);
  11235. /* Find power-management capability. */
  11236. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  11237. if (pm_cap == 0) {
  11238. printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
  11239. "aborting.\n");
  11240. err = -EIO;
  11241. goto err_out_free_res;
  11242. }
  11243. tg3reg_base = pci_resource_start(pdev, 0);
  11244. tg3reg_len = pci_resource_len(pdev, 0);
  11245. dev = alloc_etherdev(sizeof(*tp));
  11246. if (!dev) {
  11247. printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
  11248. err = -ENOMEM;
  11249. goto err_out_free_res;
  11250. }
  11251. SET_NETDEV_DEV(dev, &pdev->dev);
  11252. #if TG3_VLAN_TAG_USED
  11253. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  11254. dev->vlan_rx_register = tg3_vlan_rx_register;
  11255. #endif
  11256. tp = netdev_priv(dev);
  11257. tp->pdev = pdev;
  11258. tp->dev = dev;
  11259. tp->pm_cap = pm_cap;
  11260. tp->rx_mode = TG3_DEF_RX_MODE;
  11261. tp->tx_mode = TG3_DEF_TX_MODE;
  11262. if (tg3_debug > 0)
  11263. tp->msg_enable = tg3_debug;
  11264. else
  11265. tp->msg_enable = TG3_DEF_MSG_ENABLE;
  11266. /* The word/byte swap controls here control register access byte
  11267. * swapping. DMA data byte swapping is controlled in the GRC_MODE
  11268. * setting below.
  11269. */
  11270. tp->misc_host_ctrl =
  11271. MISC_HOST_CTRL_MASK_PCI_INT |
  11272. MISC_HOST_CTRL_WORD_SWAP |
  11273. MISC_HOST_CTRL_INDIR_ACCESS |
  11274. MISC_HOST_CTRL_PCISTATE_RW;
  11275. /* The NONFRM (non-frame) byte/word swap controls take effect
  11276. * on descriptor entries, anything which isn't packet data.
  11277. *
  11278. * The StrongARM chips on the board (one for tx, one for rx)
  11279. * are running in big-endian mode.
  11280. */
  11281. tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  11282. GRC_MODE_WSWAP_NONFRM_DATA);
  11283. #ifdef __BIG_ENDIAN
  11284. tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  11285. #endif
  11286. spin_lock_init(&tp->lock);
  11287. spin_lock_init(&tp->indirect_lock);
  11288. INIT_WORK(&tp->reset_task, tg3_reset_task);
  11289. tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
  11290. if (!tp->regs) {
  11291. printk(KERN_ERR PFX "Cannot map device registers, "
  11292. "aborting.\n");
  11293. err = -ENOMEM;
  11294. goto err_out_free_dev;
  11295. }
  11296. tg3_init_link_config(tp);
  11297. tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  11298. tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  11299. tp->tx_pending = TG3_DEF_TX_RING_PENDING;
  11300. dev->open = tg3_open;
  11301. dev->stop = tg3_close;
  11302. dev->get_stats = tg3_get_stats;
  11303. dev->set_multicast_list = tg3_set_rx_mode;
  11304. dev->set_mac_address = tg3_set_mac_addr;
  11305. dev->do_ioctl = tg3_ioctl;
  11306. dev->tx_timeout = tg3_tx_timeout;
  11307. netif_napi_add(dev, &tp->napi, tg3_poll, 64);
  11308. dev->ethtool_ops = &tg3_ethtool_ops;
  11309. dev->watchdog_timeo = TG3_TX_TIMEOUT;
  11310. dev->change_mtu = tg3_change_mtu;
  11311. dev->irq = pdev->irq;
  11312. #ifdef CONFIG_NET_POLL_CONTROLLER
  11313. dev->poll_controller = tg3_poll_controller;
  11314. #endif
  11315. err = tg3_get_invariants(tp);
  11316. if (err) {
  11317. printk(KERN_ERR PFX "Problem fetching invariants of chip, "
  11318. "aborting.\n");
  11319. goto err_out_iounmap;
  11320. }
  11321. /* The EPB bridge inside 5714, 5715, and 5780 and any
  11322. * device behind the EPB cannot support DMA addresses > 40-bit.
  11323. * On 64-bit systems with IOMMU, use 40-bit dma_mask.
  11324. * On 64-bit systems without IOMMU, use 64-bit dma_mask and
  11325. * do DMA address check in tg3_start_xmit().
  11326. */
  11327. if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
  11328. persist_dma_mask = dma_mask = DMA_32BIT_MASK;
  11329. else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
  11330. persist_dma_mask = dma_mask = DMA_40BIT_MASK;
  11331. #ifdef CONFIG_HIGHMEM
  11332. dma_mask = DMA_64BIT_MASK;
  11333. #endif
  11334. } else
  11335. persist_dma_mask = dma_mask = DMA_64BIT_MASK;
  11336. /* Configure DMA attributes. */
  11337. if (dma_mask > DMA_32BIT_MASK) {
  11338. err = pci_set_dma_mask(pdev, dma_mask);
  11339. if (!err) {
  11340. dev->features |= NETIF_F_HIGHDMA;
  11341. err = pci_set_consistent_dma_mask(pdev,
  11342. persist_dma_mask);
  11343. if (err < 0) {
  11344. printk(KERN_ERR PFX "Unable to obtain 64 bit "
  11345. "DMA for consistent allocations\n");
  11346. goto err_out_iounmap;
  11347. }
  11348. }
  11349. }
  11350. if (err || dma_mask == DMA_32BIT_MASK) {
  11351. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  11352. if (err) {
  11353. printk(KERN_ERR PFX "No usable DMA configuration, "
  11354. "aborting.\n");
  11355. goto err_out_iounmap;
  11356. }
  11357. }
  11358. tg3_init_bufmgr_config(tp);
  11359. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  11360. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  11361. }
  11362. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  11363. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  11364. tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
  11365. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  11366. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  11367. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  11368. } else {
  11369. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
  11370. }
  11371. /* TSO is on by default on chips that support hardware TSO.
  11372. * Firmware TSO on older chips gives lower performance, so it
  11373. * is off by default, but can be enabled using ethtool.
  11374. */
  11375. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  11376. dev->features |= NETIF_F_TSO;
  11377. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
  11378. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
  11379. dev->features |= NETIF_F_TSO6;
  11380. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  11381. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  11382. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
  11383. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  11384. dev->features |= NETIF_F_TSO_ECN;
  11385. }
  11386. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
  11387. !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
  11388. !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  11389. tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
  11390. tp->rx_pending = 63;
  11391. }
  11392. err = tg3_get_device_address(tp);
  11393. if (err) {
  11394. printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
  11395. "aborting.\n");
  11396. goto err_out_iounmap;
  11397. }
  11398. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  11399. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  11400. printk(KERN_ERR PFX "Cannot find proper PCI device "
  11401. "base address for APE, aborting.\n");
  11402. err = -ENODEV;
  11403. goto err_out_iounmap;
  11404. }
  11405. tg3reg_base = pci_resource_start(pdev, 2);
  11406. tg3reg_len = pci_resource_len(pdev, 2);
  11407. tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
  11408. if (!tp->aperegs) {
  11409. printk(KERN_ERR PFX "Cannot map APE registers, "
  11410. "aborting.\n");
  11411. err = -ENOMEM;
  11412. goto err_out_iounmap;
  11413. }
  11414. tg3_ape_lock_init(tp);
  11415. }
  11416. /*
  11417. * Reset chip in case UNDI or EFI driver did not shutdown
  11418. * DMA self test will enable WDMAC and we'll see (spurious)
  11419. * pending DMA on the PCI bus at that point.
  11420. */
  11421. if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
  11422. (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  11423. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  11424. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  11425. }
  11426. err = tg3_test_dma(tp);
  11427. if (err) {
  11428. printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
  11429. goto err_out_apeunmap;
  11430. }
  11431. /* Tigon3 can do ipv4 only... and some chips have buggy
  11432. * checksumming.
  11433. */
  11434. if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
  11435. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  11436. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  11437. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  11438. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  11439. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  11440. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  11441. dev->features |= NETIF_F_IPV6_CSUM;
  11442. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  11443. } else
  11444. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  11445. /* flow control autonegotiation is default behavior */
  11446. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  11447. tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
  11448. tg3_init_coal(tp);
  11449. pci_set_drvdata(pdev, dev);
  11450. err = register_netdev(dev);
  11451. if (err) {
  11452. printk(KERN_ERR PFX "Cannot register net device, "
  11453. "aborting.\n");
  11454. goto err_out_apeunmap;
  11455. }
  11456. printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
  11457. "(%s) %s Ethernet %s\n",
  11458. dev->name,
  11459. tp->board_part_number,
  11460. tp->pci_chip_rev_id,
  11461. tg3_phy_string(tp),
  11462. tg3_bus_string(tp, str),
  11463. ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
  11464. ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
  11465. "10/100/1000Base-T")),
  11466. print_mac(mac, dev->dev_addr));
  11467. printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
  11468. "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
  11469. dev->name,
  11470. (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
  11471. (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
  11472. (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
  11473. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
  11474. (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
  11475. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
  11476. printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
  11477. dev->name, tp->dma_rwctrl,
  11478. (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
  11479. (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
  11480. return 0;
  11481. err_out_apeunmap:
  11482. if (tp->aperegs) {
  11483. iounmap(tp->aperegs);
  11484. tp->aperegs = NULL;
  11485. }
  11486. err_out_iounmap:
  11487. if (tp->regs) {
  11488. iounmap(tp->regs);
  11489. tp->regs = NULL;
  11490. }
  11491. err_out_free_dev:
  11492. free_netdev(dev);
  11493. err_out_free_res:
  11494. pci_release_regions(pdev);
  11495. err_out_disable_pdev:
  11496. pci_disable_device(pdev);
  11497. pci_set_drvdata(pdev, NULL);
  11498. return err;
  11499. }
  11500. static void __devexit tg3_remove_one(struct pci_dev *pdev)
  11501. {
  11502. struct net_device *dev = pci_get_drvdata(pdev);
  11503. if (dev) {
  11504. struct tg3 *tp = netdev_priv(dev);
  11505. flush_scheduled_work();
  11506. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  11507. tg3_phy_fini(tp);
  11508. tg3_mdio_fini(tp);
  11509. }
  11510. unregister_netdev(dev);
  11511. if (tp->aperegs) {
  11512. iounmap(tp->aperegs);
  11513. tp->aperegs = NULL;
  11514. }
  11515. if (tp->regs) {
  11516. iounmap(tp->regs);
  11517. tp->regs = NULL;
  11518. }
  11519. free_netdev(dev);
  11520. pci_release_regions(pdev);
  11521. pci_disable_device(pdev);
  11522. pci_set_drvdata(pdev, NULL);
  11523. }
  11524. }
  11525. static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
  11526. {
  11527. struct net_device *dev = pci_get_drvdata(pdev);
  11528. struct tg3 *tp = netdev_priv(dev);
  11529. pci_power_t target_state;
  11530. int err;
  11531. /* PCI register 4 needs to be saved whether netif_running() or not.
  11532. * MSI address and data need to be saved if using MSI and
  11533. * netif_running().
  11534. */
  11535. pci_save_state(pdev);
  11536. if (!netif_running(dev))
  11537. return 0;
  11538. flush_scheduled_work();
  11539. tg3_phy_stop(tp);
  11540. tg3_netif_stop(tp);
  11541. del_timer_sync(&tp->timer);
  11542. tg3_full_lock(tp, 1);
  11543. tg3_disable_ints(tp);
  11544. tg3_full_unlock(tp);
  11545. netif_device_detach(dev);
  11546. tg3_full_lock(tp, 0);
  11547. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  11548. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  11549. tg3_full_unlock(tp);
  11550. target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
  11551. err = tg3_set_power_state(tp, target_state);
  11552. if (err) {
  11553. int err2;
  11554. tg3_full_lock(tp, 0);
  11555. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  11556. err2 = tg3_restart_hw(tp, 1);
  11557. if (err2)
  11558. goto out;
  11559. tp->timer.expires = jiffies + tp->timer_offset;
  11560. add_timer(&tp->timer);
  11561. netif_device_attach(dev);
  11562. tg3_netif_start(tp);
  11563. out:
  11564. tg3_full_unlock(tp);
  11565. if (!err2)
  11566. tg3_phy_start(tp);
  11567. }
  11568. return err;
  11569. }
  11570. static int tg3_resume(struct pci_dev *pdev)
  11571. {
  11572. struct net_device *dev = pci_get_drvdata(pdev);
  11573. struct tg3 *tp = netdev_priv(dev);
  11574. int err;
  11575. pci_restore_state(tp->pdev);
  11576. if (!netif_running(dev))
  11577. return 0;
  11578. err = tg3_set_power_state(tp, PCI_D0);
  11579. if (err)
  11580. return err;
  11581. netif_device_attach(dev);
  11582. tg3_full_lock(tp, 0);
  11583. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  11584. err = tg3_restart_hw(tp, 1);
  11585. if (err)
  11586. goto out;
  11587. tp->timer.expires = jiffies + tp->timer_offset;
  11588. add_timer(&tp->timer);
  11589. tg3_netif_start(tp);
  11590. out:
  11591. tg3_full_unlock(tp);
  11592. if (!err)
  11593. tg3_phy_start(tp);
  11594. return err;
  11595. }
  11596. static struct pci_driver tg3_driver = {
  11597. .name = DRV_MODULE_NAME,
  11598. .id_table = tg3_pci_tbl,
  11599. .probe = tg3_init_one,
  11600. .remove = __devexit_p(tg3_remove_one),
  11601. .suspend = tg3_suspend,
  11602. .resume = tg3_resume
  11603. };
  11604. static int __init tg3_init(void)
  11605. {
  11606. return pci_register_driver(&tg3_driver);
  11607. }
  11608. static void __exit tg3_cleanup(void)
  11609. {
  11610. pci_unregister_driver(&tg3_driver);
  11611. }
  11612. module_init(tg3_init);
  11613. module_exit(tg3_cleanup);