smc91x.h 40 KB

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  1. /*------------------------------------------------------------------------
  2. . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
  3. .
  4. . Copyright (C) 1996 by Erik Stahlman
  5. . Copyright (C) 2001 Standard Microsystems Corporation
  6. . Developed by Simple Network Magic Corporation
  7. . Copyright (C) 2003 Monta Vista Software, Inc.
  8. . Unified SMC91x driver by Nicolas Pitre
  9. .
  10. . This program is free software; you can redistribute it and/or modify
  11. . it under the terms of the GNU General Public License as published by
  12. . the Free Software Foundation; either version 2 of the License, or
  13. . (at your option) any later version.
  14. .
  15. . This program is distributed in the hope that it will be useful,
  16. . but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. . GNU General Public License for more details.
  19. .
  20. . You should have received a copy of the GNU General Public License
  21. . along with this program; if not, write to the Free Software
  22. . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. .
  24. . Information contained in this file was obtained from the LAN91C111
  25. . manual from SMC. To get a copy, if you really want one, you can find
  26. . information under www.smsc.com.
  27. .
  28. . Authors
  29. . Erik Stahlman <erik@vt.edu>
  30. . Daris A Nevil <dnevil@snmc.com>
  31. . Nicolas Pitre <nico@cam.org>
  32. .
  33. ---------------------------------------------------------------------------*/
  34. #ifndef _SMC91X_H_
  35. #define _SMC91X_H_
  36. #include <linux/smc91x.h>
  37. /*
  38. * Define your architecture specific bus configuration parameters here.
  39. */
  40. #if defined(CONFIG_ARCH_LUBBOCK) ||\
  41. defined(CONFIG_MACH_MAINSTONE) ||\
  42. defined(CONFIG_MACH_ZYLONITE) ||\
  43. defined(CONFIG_MACH_LITTLETON)
  44. #include <asm/mach-types.h>
  45. /* Now the bus width is specified in the platform data
  46. * pretend here to support all I/O access types
  47. */
  48. #define SMC_CAN_USE_8BIT 1
  49. #define SMC_CAN_USE_16BIT 1
  50. #define SMC_CAN_USE_32BIT 1
  51. #define SMC_NOWAIT 1
  52. #define SMC_IO_SHIFT (lp->io_shift)
  53. #define SMC_inb(a, r) readb((a) + (r))
  54. #define SMC_inw(a, r) readw((a) + (r))
  55. #define SMC_inl(a, r) readl((a) + (r))
  56. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  57. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  58. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  59. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  60. #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
  61. #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
  62. #define SMC_IRQ_FLAGS (-1) /* from resource */
  63. /* We actually can't write halfwords properly if not word aligned */
  64. static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
  65. {
  66. if (machine_is_mainstone() && reg & 2) {
  67. unsigned int v = val << 16;
  68. v |= readl(ioaddr + (reg & ~2)) & 0xffff;
  69. writel(v, ioaddr + (reg & ~2));
  70. } else {
  71. writew(val, ioaddr + reg);
  72. }
  73. }
  74. #elif defined(CONFIG_BLACKFIN)
  75. #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
  76. #define RPC_LSA_DEFAULT RPC_LED_100_10
  77. #define RPC_LSB_DEFAULT RPC_LED_TX_RX
  78. # if defined (CONFIG_BFIN561_EZKIT)
  79. #define SMC_CAN_USE_8BIT 0
  80. #define SMC_CAN_USE_16BIT 1
  81. #define SMC_CAN_USE_32BIT 1
  82. #define SMC_IO_SHIFT 0
  83. #define SMC_NOWAIT 1
  84. #define SMC_USE_BFIN_DMA 0
  85. #define SMC_inw(a, r) readw((a) + (r))
  86. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  87. #define SMC_inl(a, r) readl((a) + (r))
  88. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  89. #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
  90. #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
  91. # else
  92. #define SMC_CAN_USE_8BIT 0
  93. #define SMC_CAN_USE_16BIT 1
  94. #define SMC_CAN_USE_32BIT 0
  95. #define SMC_IO_SHIFT 0
  96. #define SMC_NOWAIT 1
  97. #define SMC_USE_BFIN_DMA 0
  98. #define SMC_inw(a, r) readw((a) + (r))
  99. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  100. #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
  101. #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
  102. # endif
  103. /* check if the mac in reg is valid */
  104. #define SMC_GET_MAC_ADDR(lp, addr) \
  105. do { \
  106. unsigned int __v; \
  107. __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
  108. addr[0] = __v; addr[1] = __v >> 8; \
  109. __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
  110. addr[2] = __v; addr[3] = __v >> 8; \
  111. __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
  112. addr[4] = __v; addr[5] = __v >> 8; \
  113. if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
  114. random_ether_addr(addr); \
  115. } \
  116. } while (0)
  117. #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
  118. /* We can only do 16-bit reads and writes in the static memory space. */
  119. #define SMC_CAN_USE_8BIT 0
  120. #define SMC_CAN_USE_16BIT 1
  121. #define SMC_CAN_USE_32BIT 0
  122. #define SMC_NOWAIT 1
  123. #define SMC_IO_SHIFT 0
  124. #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
  125. #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
  126. #define SMC_insw(a, r, p, l) \
  127. do { \
  128. unsigned long __port = (a) + (r); \
  129. u16 *__p = (u16 *)(p); \
  130. int __l = (l); \
  131. insw(__port, __p, __l); \
  132. while (__l > 0) { \
  133. *__p = swab16(*__p); \
  134. __p++; \
  135. __l--; \
  136. } \
  137. } while (0)
  138. #define SMC_outsw(a, r, p, l) \
  139. do { \
  140. unsigned long __port = (a) + (r); \
  141. u16 *__p = (u16 *)(p); \
  142. int __l = (l); \
  143. while (__l > 0) { \
  144. /* Believe it or not, the swab isn't needed. */ \
  145. outw( /* swab16 */ (*__p++), __port); \
  146. __l--; \
  147. } \
  148. } while (0)
  149. #define SMC_IRQ_FLAGS (0)
  150. #elif defined(CONFIG_SA1100_PLEB)
  151. /* We can only do 16-bit reads and writes in the static memory space. */
  152. #define SMC_CAN_USE_8BIT 1
  153. #define SMC_CAN_USE_16BIT 1
  154. #define SMC_CAN_USE_32BIT 0
  155. #define SMC_IO_SHIFT 0
  156. #define SMC_NOWAIT 1
  157. #define SMC_inb(a, r) readb((a) + (r))
  158. #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
  159. #define SMC_inw(a, r) readw((a) + (r))
  160. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  161. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  162. #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
  163. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  164. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  165. #define SMC_IRQ_FLAGS (-1)
  166. #elif defined(CONFIG_SA1100_ASSABET)
  167. #include <mach/neponset.h>
  168. /* We can only do 8-bit reads and writes in the static memory space. */
  169. #define SMC_CAN_USE_8BIT 1
  170. #define SMC_CAN_USE_16BIT 0
  171. #define SMC_CAN_USE_32BIT 0
  172. #define SMC_NOWAIT 1
  173. /* The first two address lines aren't connected... */
  174. #define SMC_IO_SHIFT 2
  175. #define SMC_inb(a, r) readb((a) + (r))
  176. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  177. #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
  178. #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
  179. #define SMC_IRQ_FLAGS (-1) /* from resource */
  180. #elif defined(CONFIG_MACH_LOGICPD_PXA270)
  181. #define SMC_CAN_USE_8BIT 0
  182. #define SMC_CAN_USE_16BIT 1
  183. #define SMC_CAN_USE_32BIT 0
  184. #define SMC_IO_SHIFT 0
  185. #define SMC_NOWAIT 1
  186. #define SMC_inw(a, r) readw((a) + (r))
  187. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  188. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  189. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  190. #elif defined(CONFIG_ARCH_INNOKOM) || \
  191. defined(CONFIG_ARCH_PXA_IDP) || \
  192. defined(CONFIG_ARCH_RAMSES) || \
  193. defined(CONFIG_ARCH_PCM027)
  194. #define SMC_CAN_USE_8BIT 1
  195. #define SMC_CAN_USE_16BIT 1
  196. #define SMC_CAN_USE_32BIT 1
  197. #define SMC_IO_SHIFT 0
  198. #define SMC_NOWAIT 1
  199. #define SMC_USE_PXA_DMA 1
  200. #define SMC_inb(a, r) readb((a) + (r))
  201. #define SMC_inw(a, r) readw((a) + (r))
  202. #define SMC_inl(a, r) readl((a) + (r))
  203. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  204. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  205. #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
  206. #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
  207. #define SMC_IRQ_FLAGS (-1) /* from resource */
  208. /* We actually can't write halfwords properly if not word aligned */
  209. static inline void
  210. SMC_outw(u16 val, void __iomem *ioaddr, int reg)
  211. {
  212. if (reg & 2) {
  213. unsigned int v = val << 16;
  214. v |= readl(ioaddr + (reg & ~2)) & 0xffff;
  215. writel(v, ioaddr + (reg & ~2));
  216. } else {
  217. writew(val, ioaddr + reg);
  218. }
  219. }
  220. #elif defined(CONFIG_ARCH_OMAP)
  221. /* We can only do 16-bit reads and writes in the static memory space. */
  222. #define SMC_CAN_USE_8BIT 0
  223. #define SMC_CAN_USE_16BIT 1
  224. #define SMC_CAN_USE_32BIT 0
  225. #define SMC_IO_SHIFT 0
  226. #define SMC_NOWAIT 1
  227. #define SMC_inw(a, r) readw((a) + (r))
  228. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  229. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  230. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  231. #define SMC_IRQ_FLAGS (-1) /* from resource */
  232. #elif defined(CONFIG_SH_SH4202_MICRODEV)
  233. #define SMC_CAN_USE_8BIT 0
  234. #define SMC_CAN_USE_16BIT 1
  235. #define SMC_CAN_USE_32BIT 0
  236. #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
  237. #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
  238. #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
  239. #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
  240. #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
  241. #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
  242. #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
  243. #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
  244. #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
  245. #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
  246. #define SMC_IRQ_FLAGS (0)
  247. #elif defined(CONFIG_ISA)
  248. #define SMC_CAN_USE_8BIT 1
  249. #define SMC_CAN_USE_16BIT 1
  250. #define SMC_CAN_USE_32BIT 0
  251. #define SMC_inb(a, r) inb((a) + (r))
  252. #define SMC_inw(a, r) inw((a) + (r))
  253. #define SMC_outb(v, a, r) outb(v, (a) + (r))
  254. #define SMC_outw(v, a, r) outw(v, (a) + (r))
  255. #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
  256. #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
  257. #elif defined(CONFIG_M32R)
  258. #define SMC_CAN_USE_8BIT 0
  259. #define SMC_CAN_USE_16BIT 1
  260. #define SMC_CAN_USE_32BIT 0
  261. #define SMC_inb(a, r) inb(((u32)a) + (r))
  262. #define SMC_inw(a, r) inw(((u32)a) + (r))
  263. #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
  264. #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
  265. #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
  266. #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
  267. #define SMC_IRQ_FLAGS (0)
  268. #define RPC_LSA_DEFAULT RPC_LED_TX_RX
  269. #define RPC_LSB_DEFAULT RPC_LED_100_10
  270. #elif defined(CONFIG_MACH_LPD79520) \
  271. || defined(CONFIG_MACH_LPD7A400) \
  272. || defined(CONFIG_MACH_LPD7A404)
  273. /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
  274. * way that the CPU handles chip selects and the way that the SMC chip
  275. * expects the chip select to operate. Refer to
  276. * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
  277. * IOBARRIER is a byte, in order that we read the least-common
  278. * denominator. It would be wasteful to read 32 bits from an 8-bit
  279. * accessible region.
  280. *
  281. * There is no explicit protection against interrupts intervening
  282. * between the writew and the IOBARRIER. In SMC ISR there is a
  283. * preamble that performs an IOBARRIER in the extremely unlikely event
  284. * that the driver interrupts itself between a writew to the chip an
  285. * the IOBARRIER that follows *and* the cache is large enough that the
  286. * first off-chip access while handing the interrupt is to the SMC
  287. * chip. Other devices in the same address space as the SMC chip must
  288. * be aware of the potential for trouble and perform a similar
  289. * IOBARRIER on entry to their ISR.
  290. */
  291. #include <mach/constants.h> /* IOBARRIER_VIRT */
  292. #define SMC_CAN_USE_8BIT 0
  293. #define SMC_CAN_USE_16BIT 1
  294. #define SMC_CAN_USE_32BIT 0
  295. #define SMC_NOWAIT 0
  296. #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
  297. #define SMC_inw(a,r)\
  298. ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
  299. #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
  300. #define SMC_insw LPD7_SMC_insw
  301. static inline void LPD7_SMC_insw (unsigned char* a, int r,
  302. unsigned char* p, int l)
  303. {
  304. unsigned short* ps = (unsigned short*) p;
  305. while (l-- > 0) {
  306. *ps++ = readw (a + r);
  307. LPD7X_IOBARRIER;
  308. }
  309. }
  310. #define SMC_outsw LPD7_SMC_outsw
  311. static inline void LPD7_SMC_outsw (unsigned char* a, int r,
  312. unsigned char* p, int l)
  313. {
  314. unsigned short* ps = (unsigned short*) p;
  315. while (l-- > 0) {
  316. writew (*ps++, a + r);
  317. LPD7X_IOBARRIER;
  318. }
  319. }
  320. #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
  321. #define RPC_LSA_DEFAULT RPC_LED_TX_RX
  322. #define RPC_LSB_DEFAULT RPC_LED_100_10
  323. #elif defined(CONFIG_SOC_AU1X00)
  324. #include <au1xxx.h>
  325. /* We can only do 16-bit reads and writes in the static memory space. */
  326. #define SMC_CAN_USE_8BIT 0
  327. #define SMC_CAN_USE_16BIT 1
  328. #define SMC_CAN_USE_32BIT 0
  329. #define SMC_IO_SHIFT 0
  330. #define SMC_NOWAIT 1
  331. #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
  332. #define SMC_insw(a, r, p, l) \
  333. do { \
  334. unsigned long _a = (unsigned long)((a) + (r)); \
  335. int _l = (l); \
  336. u16 *_p = (u16 *)(p); \
  337. while (_l-- > 0) \
  338. *_p++ = au_readw(_a); \
  339. } while(0)
  340. #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
  341. #define SMC_outsw(a, r, p, l) \
  342. do { \
  343. unsigned long _a = (unsigned long)((a) + (r)); \
  344. int _l = (l); \
  345. const u16 *_p = (const u16 *)(p); \
  346. while (_l-- > 0) \
  347. au_writew(*_p++ , _a); \
  348. } while(0)
  349. #define SMC_IRQ_FLAGS (0)
  350. #elif defined(CONFIG_ARCH_VERSATILE)
  351. #define SMC_CAN_USE_8BIT 1
  352. #define SMC_CAN_USE_16BIT 1
  353. #define SMC_CAN_USE_32BIT 1
  354. #define SMC_NOWAIT 1
  355. #define SMC_inb(a, r) readb((a) + (r))
  356. #define SMC_inw(a, r) readw((a) + (r))
  357. #define SMC_inl(a, r) readl((a) + (r))
  358. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  359. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  360. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  361. #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
  362. #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
  363. #define SMC_IRQ_FLAGS (-1) /* from resource */
  364. #elif defined(CONFIG_MN10300)
  365. /*
  366. * MN10300/AM33 configuration
  367. */
  368. #include <asm/unit/smc91111.h>
  369. #else
  370. /*
  371. * Default configuration
  372. */
  373. #define SMC_CAN_USE_8BIT 1
  374. #define SMC_CAN_USE_16BIT 1
  375. #define SMC_CAN_USE_32BIT 1
  376. #define SMC_NOWAIT 1
  377. #define SMC_inb(a, r) readb((a) + (r))
  378. #define SMC_inw(a, r) readw((a) + (r))
  379. #define SMC_inl(a, r) readl((a) + (r))
  380. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  381. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  382. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  383. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  384. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  385. #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
  386. #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
  387. #define RPC_LSA_DEFAULT RPC_LED_100_10
  388. #define RPC_LSB_DEFAULT RPC_LED_TX_RX
  389. #endif
  390. /* store this information for the driver.. */
  391. struct smc_local {
  392. /*
  393. * If I have to wait until memory is available to send a
  394. * packet, I will store the skbuff here, until I get the
  395. * desired memory. Then, I'll send it out and free it.
  396. */
  397. struct sk_buff *pending_tx_skb;
  398. struct tasklet_struct tx_task;
  399. /* version/revision of the SMC91x chip */
  400. int version;
  401. /* Contains the current active transmission mode */
  402. int tcr_cur_mode;
  403. /* Contains the current active receive mode */
  404. int rcr_cur_mode;
  405. /* Contains the current active receive/phy mode */
  406. int rpc_cur_mode;
  407. int ctl_rfduplx;
  408. int ctl_rspeed;
  409. u32 msg_enable;
  410. u32 phy_type;
  411. struct mii_if_info mii;
  412. /* work queue */
  413. struct work_struct phy_configure;
  414. struct net_device *dev;
  415. int work_pending;
  416. spinlock_t lock;
  417. #ifdef CONFIG_ARCH_PXA
  418. /* DMA needs the physical address of the chip */
  419. u_long physaddr;
  420. struct device *device;
  421. #endif
  422. void __iomem *base;
  423. void __iomem *datacs;
  424. /* the low address lines on some platforms aren't connected... */
  425. int io_shift;
  426. struct smc91x_platdata cfg;
  427. };
  428. #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
  429. #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
  430. #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
  431. #ifdef CONFIG_ARCH_PXA
  432. /*
  433. * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
  434. * always happening in irq context so no need to worry about races. TX is
  435. * different and probably not worth it for that reason, and not as critical
  436. * as RX which can overrun memory and lose packets.
  437. */
  438. #include <linux/dma-mapping.h>
  439. #include <asm/dma.h>
  440. #include <mach/pxa-regs.h>
  441. #ifdef SMC_insl
  442. #undef SMC_insl
  443. #define SMC_insl(a, r, p, l) \
  444. smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
  445. static inline void
  446. smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
  447. u_char *buf, int len)
  448. {
  449. u_long physaddr = lp->physaddr;
  450. dma_addr_t dmabuf;
  451. /* fallback if no DMA available */
  452. if (dma == (unsigned char)-1) {
  453. readsl(ioaddr + reg, buf, len);
  454. return;
  455. }
  456. /* 64 bit alignment is required for memory to memory DMA */
  457. if ((long)buf & 4) {
  458. *((u32 *)buf) = SMC_inl(ioaddr, reg);
  459. buf += 4;
  460. len--;
  461. }
  462. len *= 4;
  463. dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
  464. DCSR(dma) = DCSR_NODESC;
  465. DTADR(dma) = dmabuf;
  466. DSADR(dma) = physaddr + reg;
  467. DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
  468. DCMD_WIDTH4 | (DCMD_LENGTH & len));
  469. DCSR(dma) = DCSR_NODESC | DCSR_RUN;
  470. while (!(DCSR(dma) & DCSR_STOPSTATE))
  471. cpu_relax();
  472. DCSR(dma) = 0;
  473. dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
  474. }
  475. #endif
  476. #ifdef SMC_insw
  477. #undef SMC_insw
  478. #define SMC_insw(a, r, p, l) \
  479. smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
  480. static inline void
  481. smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
  482. u_char *buf, int len)
  483. {
  484. u_long physaddr = lp->physaddr;
  485. dma_addr_t dmabuf;
  486. /* fallback if no DMA available */
  487. if (dma == (unsigned char)-1) {
  488. readsw(ioaddr + reg, buf, len);
  489. return;
  490. }
  491. /* 64 bit alignment is required for memory to memory DMA */
  492. while ((long)buf & 6) {
  493. *((u16 *)buf) = SMC_inw(ioaddr, reg);
  494. buf += 2;
  495. len--;
  496. }
  497. len *= 2;
  498. dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
  499. DCSR(dma) = DCSR_NODESC;
  500. DTADR(dma) = dmabuf;
  501. DSADR(dma) = physaddr + reg;
  502. DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
  503. DCMD_WIDTH2 | (DCMD_LENGTH & len));
  504. DCSR(dma) = DCSR_NODESC | DCSR_RUN;
  505. while (!(DCSR(dma) & DCSR_STOPSTATE))
  506. cpu_relax();
  507. DCSR(dma) = 0;
  508. dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
  509. }
  510. #endif
  511. static void
  512. smc_pxa_dma_irq(int dma, void *dummy)
  513. {
  514. DCSR(dma) = 0;
  515. }
  516. #endif /* CONFIG_ARCH_PXA */
  517. /*
  518. * Everything a particular hardware setup needs should have been defined
  519. * at this point. Add stubs for the undefined cases, mainly to avoid
  520. * compilation warnings since they'll be optimized away, or to prevent buggy
  521. * use of them.
  522. */
  523. #if ! SMC_CAN_USE_32BIT
  524. #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
  525. #define SMC_outl(x, ioaddr, reg) BUG()
  526. #define SMC_insl(a, r, p, l) BUG()
  527. #define SMC_outsl(a, r, p, l) BUG()
  528. #endif
  529. #if !defined(SMC_insl) || !defined(SMC_outsl)
  530. #define SMC_insl(a, r, p, l) BUG()
  531. #define SMC_outsl(a, r, p, l) BUG()
  532. #endif
  533. #if ! SMC_CAN_USE_16BIT
  534. /*
  535. * Any 16-bit access is performed with two 8-bit accesses if the hardware
  536. * can't do it directly. Most registers are 16-bit so those are mandatory.
  537. */
  538. #define SMC_outw(x, ioaddr, reg) \
  539. do { \
  540. unsigned int __val16 = (x); \
  541. SMC_outb( __val16, ioaddr, reg ); \
  542. SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
  543. } while (0)
  544. #define SMC_inw(ioaddr, reg) \
  545. ({ \
  546. unsigned int __val16; \
  547. __val16 = SMC_inb( ioaddr, reg ); \
  548. __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
  549. __val16; \
  550. })
  551. #define SMC_insw(a, r, p, l) BUG()
  552. #define SMC_outsw(a, r, p, l) BUG()
  553. #endif
  554. #if !defined(SMC_insw) || !defined(SMC_outsw)
  555. #define SMC_insw(a, r, p, l) BUG()
  556. #define SMC_outsw(a, r, p, l) BUG()
  557. #endif
  558. #if ! SMC_CAN_USE_8BIT
  559. #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
  560. #define SMC_outb(x, ioaddr, reg) BUG()
  561. #define SMC_insb(a, r, p, l) BUG()
  562. #define SMC_outsb(a, r, p, l) BUG()
  563. #endif
  564. #if !defined(SMC_insb) || !defined(SMC_outsb)
  565. #define SMC_insb(a, r, p, l) BUG()
  566. #define SMC_outsb(a, r, p, l) BUG()
  567. #endif
  568. #ifndef SMC_CAN_USE_DATACS
  569. #define SMC_CAN_USE_DATACS 0
  570. #endif
  571. #ifndef SMC_IO_SHIFT
  572. #define SMC_IO_SHIFT 0
  573. #endif
  574. #ifndef SMC_IRQ_FLAGS
  575. #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
  576. #endif
  577. #ifndef SMC_INTERRUPT_PREAMBLE
  578. #define SMC_INTERRUPT_PREAMBLE
  579. #endif
  580. /* Because of bank switching, the LAN91x uses only 16 I/O ports */
  581. #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
  582. #define SMC_DATA_EXTENT (4)
  583. /*
  584. . Bank Select Register:
  585. .
  586. . yyyy yyyy 0000 00xx
  587. . xx = bank number
  588. . yyyy yyyy = 0x33, for identification purposes.
  589. */
  590. #define BANK_SELECT (14 << SMC_IO_SHIFT)
  591. // Transmit Control Register
  592. /* BANK 0 */
  593. #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
  594. #define TCR_ENABLE 0x0001 // When 1 we can transmit
  595. #define TCR_LOOP 0x0002 // Controls output pin LBK
  596. #define TCR_FORCOL 0x0004 // When 1 will force a collision
  597. #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
  598. #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
  599. #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
  600. #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
  601. #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
  602. #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
  603. #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
  604. #define TCR_CLEAR 0 /* do NOTHING */
  605. /* the default settings for the TCR register : */
  606. #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
  607. // EPH Status Register
  608. /* BANK 0 */
  609. #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
  610. #define ES_TX_SUC 0x0001 // Last TX was successful
  611. #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
  612. #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
  613. #define ES_LTX_MULT 0x0008 // Last tx was a multicast
  614. #define ES_16COL 0x0010 // 16 Collisions Reached
  615. #define ES_SQET 0x0020 // Signal Quality Error Test
  616. #define ES_LTXBRD 0x0040 // Last tx was a broadcast
  617. #define ES_TXDEFR 0x0080 // Transmit Deferred
  618. #define ES_LATCOL 0x0200 // Late collision detected on last tx
  619. #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
  620. #define ES_EXC_DEF 0x0800 // Excessive Deferral
  621. #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
  622. #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
  623. #define ES_TXUNRN 0x8000 // Tx Underrun
  624. // Receive Control Register
  625. /* BANK 0 */
  626. #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
  627. #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
  628. #define RCR_PRMS 0x0002 // Enable promiscuous mode
  629. #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
  630. #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
  631. #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
  632. #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
  633. #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
  634. #define RCR_SOFTRST 0x8000 // resets the chip
  635. /* the normal settings for the RCR register : */
  636. #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
  637. #define RCR_CLEAR 0x0 // set it to a base state
  638. // Counter Register
  639. /* BANK 0 */
  640. #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
  641. // Memory Information Register
  642. /* BANK 0 */
  643. #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
  644. // Receive/Phy Control Register
  645. /* BANK 0 */
  646. #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
  647. #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
  648. #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
  649. #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
  650. #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
  651. #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
  652. #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
  653. #define RPC_LED_RES (0x01) // LED = Reserved
  654. #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
  655. #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
  656. #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
  657. #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
  658. #define RPC_LED_TX (0x06) // LED = TX packet occurred
  659. #define RPC_LED_RX (0x07) // LED = RX packet occurred
  660. #ifndef RPC_LSA_DEFAULT
  661. #define RPC_LSA_DEFAULT RPC_LED_100
  662. #endif
  663. #ifndef RPC_LSB_DEFAULT
  664. #define RPC_LSB_DEFAULT RPC_LED_FD
  665. #endif
  666. #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
  667. /* Bank 0 0x0C is reserved */
  668. // Bank Select Register
  669. /* All Banks */
  670. #define BSR_REG 0x000E
  671. // Configuration Reg
  672. /* BANK 1 */
  673. #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
  674. #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
  675. #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
  676. #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
  677. #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
  678. // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
  679. #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
  680. // Base Address Register
  681. /* BANK 1 */
  682. #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
  683. // Individual Address Registers
  684. /* BANK 1 */
  685. #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
  686. #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
  687. #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
  688. // General Purpose Register
  689. /* BANK 1 */
  690. #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
  691. // Control Register
  692. /* BANK 1 */
  693. #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
  694. #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
  695. #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
  696. #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
  697. #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
  698. #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
  699. #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
  700. #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
  701. #define CTL_STORE 0x0001 // When set stores registers into EEPROM
  702. // MMU Command Register
  703. /* BANK 2 */
  704. #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
  705. #define MC_BUSY 1 // When 1 the last release has not completed
  706. #define MC_NOP (0<<5) // No Op
  707. #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
  708. #define MC_RESET (2<<5) // Reset MMU to initial state
  709. #define MC_REMOVE (3<<5) // Remove the current rx packet
  710. #define MC_RELEASE (4<<5) // Remove and release the current rx packet
  711. #define MC_FREEPKT (5<<5) // Release packet in PNR register
  712. #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
  713. #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
  714. // Packet Number Register
  715. /* BANK 2 */
  716. #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
  717. // Allocation Result Register
  718. /* BANK 2 */
  719. #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
  720. #define AR_FAILED 0x80 // Alocation Failed
  721. // TX FIFO Ports Register
  722. /* BANK 2 */
  723. #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
  724. #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
  725. // RX FIFO Ports Register
  726. /* BANK 2 */
  727. #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
  728. #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
  729. #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
  730. // Pointer Register
  731. /* BANK 2 */
  732. #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
  733. #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
  734. #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
  735. #define PTR_READ 0x2000 // When 1 the operation is a read
  736. // Data Register
  737. /* BANK 2 */
  738. #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
  739. // Interrupt Status/Acknowledge Register
  740. /* BANK 2 */
  741. #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
  742. // Interrupt Mask Register
  743. /* BANK 2 */
  744. #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
  745. #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
  746. #define IM_ERCV_INT 0x40 // Early Receive Interrupt
  747. #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
  748. #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
  749. #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
  750. #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
  751. #define IM_TX_INT 0x02 // Transmit Interrupt
  752. #define IM_RCV_INT 0x01 // Receive Interrupt
  753. // Multicast Table Registers
  754. /* BANK 3 */
  755. #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
  756. #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
  757. #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
  758. #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
  759. // Management Interface Register (MII)
  760. /* BANK 3 */
  761. #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
  762. #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
  763. #define MII_MDOE 0x0008 // MII Output Enable
  764. #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
  765. #define MII_MDI 0x0002 // MII Input, pin MDI
  766. #define MII_MDO 0x0001 // MII Output, pin MDO
  767. // Revision Register
  768. /* BANK 3 */
  769. /* ( hi: chip id low: rev # ) */
  770. #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
  771. // Early RCV Register
  772. /* BANK 3 */
  773. /* this is NOT on SMC9192 */
  774. #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
  775. #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
  776. #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
  777. // External Register
  778. /* BANK 7 */
  779. #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
  780. #define CHIP_9192 3
  781. #define CHIP_9194 4
  782. #define CHIP_9195 5
  783. #define CHIP_9196 6
  784. #define CHIP_91100 7
  785. #define CHIP_91100FD 8
  786. #define CHIP_91111FD 9
  787. static const char * chip_ids[ 16 ] = {
  788. NULL, NULL, NULL,
  789. /* 3 */ "SMC91C90/91C92",
  790. /* 4 */ "SMC91C94",
  791. /* 5 */ "SMC91C95",
  792. /* 6 */ "SMC91C96",
  793. /* 7 */ "SMC91C100",
  794. /* 8 */ "SMC91C100FD",
  795. /* 9 */ "SMC91C11xFD",
  796. NULL, NULL, NULL,
  797. NULL, NULL, NULL};
  798. /*
  799. . Receive status bits
  800. */
  801. #define RS_ALGNERR 0x8000
  802. #define RS_BRODCAST 0x4000
  803. #define RS_BADCRC 0x2000
  804. #define RS_ODDFRAME 0x1000
  805. #define RS_TOOLONG 0x0800
  806. #define RS_TOOSHORT 0x0400
  807. #define RS_MULTICAST 0x0001
  808. #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
  809. /*
  810. * PHY IDs
  811. * LAN83C183 == LAN91C111 Internal PHY
  812. */
  813. #define PHY_LAN83C183 0x0016f840
  814. #define PHY_LAN83C180 0x02821c50
  815. /*
  816. * PHY Register Addresses (LAN91C111 Internal PHY)
  817. *
  818. * Generic PHY registers can be found in <linux/mii.h>
  819. *
  820. * These phy registers are specific to our on-board phy.
  821. */
  822. // PHY Configuration Register 1
  823. #define PHY_CFG1_REG 0x10
  824. #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
  825. #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
  826. #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
  827. #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
  828. #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
  829. #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
  830. #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
  831. #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
  832. #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
  833. #define PHY_CFG1_TLVL_MASK 0x003C
  834. #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
  835. // PHY Configuration Register 2
  836. #define PHY_CFG2_REG 0x11
  837. #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
  838. #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
  839. #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
  840. #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
  841. // PHY Status Output (and Interrupt status) Register
  842. #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
  843. #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
  844. #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
  845. #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
  846. #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
  847. #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
  848. #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
  849. #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
  850. #define PHY_INT_JAB 0x0100 // 1=Jabber detected
  851. #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
  852. #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
  853. // PHY Interrupt/Status Mask Register
  854. #define PHY_MASK_REG 0x13 // Interrupt Mask
  855. // Uses the same bit definitions as PHY_INT_REG
  856. /*
  857. * SMC91C96 ethernet config and status registers.
  858. * These are in the "attribute" space.
  859. */
  860. #define ECOR 0x8000
  861. #define ECOR_RESET 0x80
  862. #define ECOR_LEVEL_IRQ 0x40
  863. #define ECOR_WR_ATTRIB 0x04
  864. #define ECOR_ENABLE 0x01
  865. #define ECSR 0x8002
  866. #define ECSR_IOIS8 0x20
  867. #define ECSR_PWRDWN 0x04
  868. #define ECSR_INT 0x02
  869. #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
  870. /*
  871. * Macros to abstract register access according to the data bus
  872. * capabilities. Please use those and not the in/out primitives.
  873. * Note: the following macros do *not* select the bank -- this must
  874. * be done separately as needed in the main code. The SMC_REG() macro
  875. * only uses the bank argument for debugging purposes (when enabled).
  876. *
  877. * Note: despite inline functions being safer, everything leading to this
  878. * should preferably be macros to let BUG() display the line number in
  879. * the core source code since we're interested in the top call site
  880. * not in any inline function location.
  881. */
  882. #if SMC_DEBUG > 0
  883. #define SMC_REG(lp, reg, bank) \
  884. ({ \
  885. int __b = SMC_CURRENT_BANK(lp); \
  886. if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
  887. printk( "%s: bank reg screwed (0x%04x)\n", \
  888. CARDNAME, __b ); \
  889. BUG(); \
  890. } \
  891. reg<<SMC_IO_SHIFT; \
  892. })
  893. #else
  894. #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
  895. #endif
  896. /*
  897. * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
  898. * aligned to a 32 bit boundary. I tell you that does exist!
  899. * Fortunately the affected register accesses can be easily worked around
  900. * since we can write zeroes to the preceeding 16 bits without adverse
  901. * effects and use a 32-bit access.
  902. *
  903. * Enforce it on any 32-bit capable setup for now.
  904. */
  905. #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
  906. #define SMC_GET_PN(lp) \
  907. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
  908. : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
  909. #define SMC_SET_PN(lp, x) \
  910. do { \
  911. if (SMC_MUST_ALIGN_WRITE(lp)) \
  912. SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
  913. else if (SMC_8BIT(lp)) \
  914. SMC_outb(x, ioaddr, PN_REG(lp)); \
  915. else \
  916. SMC_outw(x, ioaddr, PN_REG(lp)); \
  917. } while (0)
  918. #define SMC_GET_AR(lp) \
  919. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
  920. : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
  921. #define SMC_GET_TXFIFO(lp) \
  922. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
  923. : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
  924. #define SMC_GET_RXFIFO(lp) \
  925. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
  926. : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
  927. #define SMC_GET_INT(lp) \
  928. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
  929. : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
  930. #define SMC_ACK_INT(lp, x) \
  931. do { \
  932. if (SMC_8BIT(lp)) \
  933. SMC_outb(x, ioaddr, INT_REG(lp)); \
  934. else { \
  935. unsigned long __flags; \
  936. int __mask; \
  937. local_irq_save(__flags); \
  938. __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
  939. SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
  940. local_irq_restore(__flags); \
  941. } \
  942. } while (0)
  943. #define SMC_GET_INT_MASK(lp) \
  944. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
  945. : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
  946. #define SMC_SET_INT_MASK(lp, x) \
  947. do { \
  948. if (SMC_8BIT(lp)) \
  949. SMC_outb(x, ioaddr, IM_REG(lp)); \
  950. else \
  951. SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
  952. } while (0)
  953. #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
  954. #define SMC_SELECT_BANK(lp, x) \
  955. do { \
  956. if (SMC_MUST_ALIGN_WRITE(lp)) \
  957. SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
  958. else \
  959. SMC_outw(x, ioaddr, BANK_SELECT); \
  960. } while (0)
  961. #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
  962. #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
  963. #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
  964. #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
  965. #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
  966. #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
  967. #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
  968. #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
  969. #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
  970. #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
  971. #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
  972. #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
  973. #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
  974. #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
  975. #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
  976. #define SMC_SET_PTR(lp, x) \
  977. do { \
  978. if (SMC_MUST_ALIGN_WRITE(lp)) \
  979. SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
  980. else \
  981. SMC_outw(x, ioaddr, PTR_REG(lp)); \
  982. } while (0)
  983. #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
  984. #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
  985. #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
  986. #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
  987. #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
  988. #define SMC_SET_RPC(lp, x) \
  989. do { \
  990. if (SMC_MUST_ALIGN_WRITE(lp)) \
  991. SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
  992. else \
  993. SMC_outw(x, ioaddr, RPC_REG(lp)); \
  994. } while (0)
  995. #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
  996. #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
  997. #ifndef SMC_GET_MAC_ADDR
  998. #define SMC_GET_MAC_ADDR(lp, addr) \
  999. do { \
  1000. unsigned int __v; \
  1001. __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
  1002. addr[0] = __v; addr[1] = __v >> 8; \
  1003. __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
  1004. addr[2] = __v; addr[3] = __v >> 8; \
  1005. __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
  1006. addr[4] = __v; addr[5] = __v >> 8; \
  1007. } while (0)
  1008. #endif
  1009. #define SMC_SET_MAC_ADDR(lp, addr) \
  1010. do { \
  1011. SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
  1012. SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
  1013. SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
  1014. } while (0)
  1015. #define SMC_SET_MCAST(lp, x) \
  1016. do { \
  1017. const unsigned char *mt = (x); \
  1018. SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
  1019. SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
  1020. SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
  1021. SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
  1022. } while (0)
  1023. #define SMC_PUT_PKT_HDR(lp, status, length) \
  1024. do { \
  1025. if (SMC_32BIT(lp)) \
  1026. SMC_outl((status) | (length)<<16, ioaddr, \
  1027. DATA_REG(lp)); \
  1028. else { \
  1029. SMC_outw(status, ioaddr, DATA_REG(lp)); \
  1030. SMC_outw(length, ioaddr, DATA_REG(lp)); \
  1031. } \
  1032. } while (0)
  1033. #define SMC_GET_PKT_HDR(lp, status, length) \
  1034. do { \
  1035. if (SMC_32BIT(lp)) { \
  1036. unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
  1037. (status) = __val & 0xffff; \
  1038. (length) = __val >> 16; \
  1039. } else { \
  1040. (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
  1041. (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
  1042. } \
  1043. } while (0)
  1044. #define SMC_PUSH_DATA(lp, p, l) \
  1045. do { \
  1046. if (SMC_32BIT(lp)) { \
  1047. void *__ptr = (p); \
  1048. int __len = (l); \
  1049. void __iomem *__ioaddr = ioaddr; \
  1050. if (__len >= 2 && (unsigned long)__ptr & 2) { \
  1051. __len -= 2; \
  1052. SMC_outw(*(u16 *)__ptr, ioaddr, \
  1053. DATA_REG(lp)); \
  1054. __ptr += 2; \
  1055. } \
  1056. if (SMC_CAN_USE_DATACS && lp->datacs) \
  1057. __ioaddr = lp->datacs; \
  1058. SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
  1059. if (__len & 2) { \
  1060. __ptr += (__len & ~3); \
  1061. SMC_outw(*((u16 *)__ptr), ioaddr, \
  1062. DATA_REG(lp)); \
  1063. } \
  1064. } else if (SMC_16BIT(lp)) \
  1065. SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
  1066. else if (SMC_8BIT(lp)) \
  1067. SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
  1068. } while (0)
  1069. #define SMC_PULL_DATA(lp, p, l) \
  1070. do { \
  1071. if (SMC_32BIT(lp)) { \
  1072. void *__ptr = (p); \
  1073. int __len = (l); \
  1074. void __iomem *__ioaddr = ioaddr; \
  1075. if ((unsigned long)__ptr & 2) { \
  1076. /* \
  1077. * We want 32bit alignment here. \
  1078. * Since some buses perform a full \
  1079. * 32bit fetch even for 16bit data \
  1080. * we can't use SMC_inw() here. \
  1081. * Back both source (on-chip) and \
  1082. * destination pointers of 2 bytes. \
  1083. * This is possible since the call to \
  1084. * SMC_GET_PKT_HDR() already advanced \
  1085. * the source pointer of 4 bytes, and \
  1086. * the skb_reserve(skb, 2) advanced \
  1087. * the destination pointer of 2 bytes. \
  1088. */ \
  1089. __ptr -= 2; \
  1090. __len += 2; \
  1091. SMC_SET_PTR(lp, \
  1092. 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
  1093. } \
  1094. if (SMC_CAN_USE_DATACS && lp->datacs) \
  1095. __ioaddr = lp->datacs; \
  1096. __len += 2; \
  1097. SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
  1098. } else if (SMC_16BIT(lp)) \
  1099. SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
  1100. else if (SMC_8BIT(lp)) \
  1101. SMC_insb(ioaddr, DATA_REG(lp), p, l); \
  1102. } while (0)
  1103. #endif /* _SMC91X_H_ */