s2io.c 246 KB

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  1. /************************************************************************
  2. * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
  3. * Copyright(c) 2002-2007 Neterion Inc.
  4. * This software may be used and distributed according to the terms of
  5. * the GNU General Public License (GPL), incorporated herein by reference.
  6. * Drivers based on or derived from this code fall under the GPL and must
  7. * retain the authorship, copyright and license notice. This file is not
  8. * a complete program and may only be used when the entire operating
  9. * system is licensed under the GPL.
  10. * See the file COPYING in this distribution for more information.
  11. *
  12. * Credits:
  13. * Jeff Garzik : For pointing out the improper error condition
  14. * check in the s2io_xmit routine and also some
  15. * issues in the Tx watch dog function. Also for
  16. * patiently answering all those innumerable
  17. * questions regaring the 2.6 porting issues.
  18. * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
  19. * macros available only in 2.6 Kernel.
  20. * Francois Romieu : For pointing out all code part that were
  21. * deprecated and also styling related comments.
  22. * Grant Grundler : For helping me get rid of some Architecture
  23. * dependent code.
  24. * Christopher Hellwig : Some more 2.6 specific issues in the driver.
  25. *
  26. * The module loadable parameters that are supported by the driver and a brief
  27. * explaination of all the variables.
  28. *
  29. * rx_ring_num : This can be used to program the number of receive rings used
  30. * in the driver.
  31. * rx_ring_sz: This defines the number of receive blocks each ring can have.
  32. * This is also an array of size 8.
  33. * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  34. * values are 1, 2.
  35. * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  36. * tx_fifo_len: This too is an array of 8. Each element defines the number of
  37. * Tx descriptors that can be associated with each corresponding FIFO.
  38. * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  39. * 2(MSI_X). Default value is '2(MSI_X)'
  40. * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
  41. * Possible values '1' for enable '0' for disable. Default is '0'
  42. * lro_max_pkts: This parameter defines maximum number of packets can be
  43. * aggregated as a single large packet
  44. * napi: This parameter used to enable/disable NAPI (polling Rx)
  45. * Possible values '1' for enable and '0' for disable. Default is '1'
  46. * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
  47. * Possible values '1' for enable and '0' for disable. Default is '0'
  48. * vlan_tag_strip: This can be used to enable or disable vlan stripping.
  49. * Possible values '1' for enable , '0' for disable.
  50. * Default is '2' - which means disable in promisc mode
  51. * and enable in non-promiscuous mode.
  52. * multiq: This parameter used to enable/disable MULTIQUEUE support.
  53. * Possible values '1' for enable and '0' for disable. Default is '0'
  54. ************************************************************************/
  55. #include <linux/module.h>
  56. #include <linux/types.h>
  57. #include <linux/errno.h>
  58. #include <linux/ioport.h>
  59. #include <linux/pci.h>
  60. #include <linux/dma-mapping.h>
  61. #include <linux/kernel.h>
  62. #include <linux/netdevice.h>
  63. #include <linux/etherdevice.h>
  64. #include <linux/skbuff.h>
  65. #include <linux/init.h>
  66. #include <linux/delay.h>
  67. #include <linux/stddef.h>
  68. #include <linux/ioctl.h>
  69. #include <linux/timex.h>
  70. #include <linux/ethtool.h>
  71. #include <linux/workqueue.h>
  72. #include <linux/if_vlan.h>
  73. #include <linux/ip.h>
  74. #include <linux/tcp.h>
  75. #include <net/tcp.h>
  76. #include <asm/system.h>
  77. #include <asm/uaccess.h>
  78. #include <asm/io.h>
  79. #include <asm/div64.h>
  80. #include <asm/irq.h>
  81. /* local include */
  82. #include "s2io.h"
  83. #include "s2io-regs.h"
  84. #define DRV_VERSION "2.0.26.25"
  85. /* S2io Driver name & version. */
  86. static char s2io_driver_name[] = "Neterion";
  87. static char s2io_driver_version[] = DRV_VERSION;
  88. static int rxd_size[2] = {32,48};
  89. static int rxd_count[2] = {127,85};
  90. static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
  91. {
  92. int ret;
  93. ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
  94. (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
  95. return ret;
  96. }
  97. /*
  98. * Cards with following subsystem_id have a link state indication
  99. * problem, 600B, 600C, 600D, 640B, 640C and 640D.
  100. * macro below identifies these cards given the subsystem_id.
  101. */
  102. #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
  103. (dev_type == XFRAME_I_DEVICE) ? \
  104. ((((subid >= 0x600B) && (subid <= 0x600D)) || \
  105. ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
  106. #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
  107. ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
  108. static inline int is_s2io_card_up(const struct s2io_nic * sp)
  109. {
  110. return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
  111. }
  112. /* Ethtool related variables and Macros. */
  113. static char s2io_gstrings[][ETH_GSTRING_LEN] = {
  114. "Register test\t(offline)",
  115. "Eeprom test\t(offline)",
  116. "Link test\t(online)",
  117. "RLDRAM test\t(offline)",
  118. "BIST Test\t(offline)"
  119. };
  120. static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
  121. {"tmac_frms"},
  122. {"tmac_data_octets"},
  123. {"tmac_drop_frms"},
  124. {"tmac_mcst_frms"},
  125. {"tmac_bcst_frms"},
  126. {"tmac_pause_ctrl_frms"},
  127. {"tmac_ttl_octets"},
  128. {"tmac_ucst_frms"},
  129. {"tmac_nucst_frms"},
  130. {"tmac_any_err_frms"},
  131. {"tmac_ttl_less_fb_octets"},
  132. {"tmac_vld_ip_octets"},
  133. {"tmac_vld_ip"},
  134. {"tmac_drop_ip"},
  135. {"tmac_icmp"},
  136. {"tmac_rst_tcp"},
  137. {"tmac_tcp"},
  138. {"tmac_udp"},
  139. {"rmac_vld_frms"},
  140. {"rmac_data_octets"},
  141. {"rmac_fcs_err_frms"},
  142. {"rmac_drop_frms"},
  143. {"rmac_vld_mcst_frms"},
  144. {"rmac_vld_bcst_frms"},
  145. {"rmac_in_rng_len_err_frms"},
  146. {"rmac_out_rng_len_err_frms"},
  147. {"rmac_long_frms"},
  148. {"rmac_pause_ctrl_frms"},
  149. {"rmac_unsup_ctrl_frms"},
  150. {"rmac_ttl_octets"},
  151. {"rmac_accepted_ucst_frms"},
  152. {"rmac_accepted_nucst_frms"},
  153. {"rmac_discarded_frms"},
  154. {"rmac_drop_events"},
  155. {"rmac_ttl_less_fb_octets"},
  156. {"rmac_ttl_frms"},
  157. {"rmac_usized_frms"},
  158. {"rmac_osized_frms"},
  159. {"rmac_frag_frms"},
  160. {"rmac_jabber_frms"},
  161. {"rmac_ttl_64_frms"},
  162. {"rmac_ttl_65_127_frms"},
  163. {"rmac_ttl_128_255_frms"},
  164. {"rmac_ttl_256_511_frms"},
  165. {"rmac_ttl_512_1023_frms"},
  166. {"rmac_ttl_1024_1518_frms"},
  167. {"rmac_ip"},
  168. {"rmac_ip_octets"},
  169. {"rmac_hdr_err_ip"},
  170. {"rmac_drop_ip"},
  171. {"rmac_icmp"},
  172. {"rmac_tcp"},
  173. {"rmac_udp"},
  174. {"rmac_err_drp_udp"},
  175. {"rmac_xgmii_err_sym"},
  176. {"rmac_frms_q0"},
  177. {"rmac_frms_q1"},
  178. {"rmac_frms_q2"},
  179. {"rmac_frms_q3"},
  180. {"rmac_frms_q4"},
  181. {"rmac_frms_q5"},
  182. {"rmac_frms_q6"},
  183. {"rmac_frms_q7"},
  184. {"rmac_full_q0"},
  185. {"rmac_full_q1"},
  186. {"rmac_full_q2"},
  187. {"rmac_full_q3"},
  188. {"rmac_full_q4"},
  189. {"rmac_full_q5"},
  190. {"rmac_full_q6"},
  191. {"rmac_full_q7"},
  192. {"rmac_pause_cnt"},
  193. {"rmac_xgmii_data_err_cnt"},
  194. {"rmac_xgmii_ctrl_err_cnt"},
  195. {"rmac_accepted_ip"},
  196. {"rmac_err_tcp"},
  197. {"rd_req_cnt"},
  198. {"new_rd_req_cnt"},
  199. {"new_rd_req_rtry_cnt"},
  200. {"rd_rtry_cnt"},
  201. {"wr_rtry_rd_ack_cnt"},
  202. {"wr_req_cnt"},
  203. {"new_wr_req_cnt"},
  204. {"new_wr_req_rtry_cnt"},
  205. {"wr_rtry_cnt"},
  206. {"wr_disc_cnt"},
  207. {"rd_rtry_wr_ack_cnt"},
  208. {"txp_wr_cnt"},
  209. {"txd_rd_cnt"},
  210. {"txd_wr_cnt"},
  211. {"rxd_rd_cnt"},
  212. {"rxd_wr_cnt"},
  213. {"txf_rd_cnt"},
  214. {"rxf_wr_cnt"}
  215. };
  216. static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
  217. {"rmac_ttl_1519_4095_frms"},
  218. {"rmac_ttl_4096_8191_frms"},
  219. {"rmac_ttl_8192_max_frms"},
  220. {"rmac_ttl_gt_max_frms"},
  221. {"rmac_osized_alt_frms"},
  222. {"rmac_jabber_alt_frms"},
  223. {"rmac_gt_max_alt_frms"},
  224. {"rmac_vlan_frms"},
  225. {"rmac_len_discard"},
  226. {"rmac_fcs_discard"},
  227. {"rmac_pf_discard"},
  228. {"rmac_da_discard"},
  229. {"rmac_red_discard"},
  230. {"rmac_rts_discard"},
  231. {"rmac_ingm_full_discard"},
  232. {"link_fault_cnt"}
  233. };
  234. static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
  235. {"\n DRIVER STATISTICS"},
  236. {"single_bit_ecc_errs"},
  237. {"double_bit_ecc_errs"},
  238. {"parity_err_cnt"},
  239. {"serious_err_cnt"},
  240. {"soft_reset_cnt"},
  241. {"fifo_full_cnt"},
  242. {"ring_0_full_cnt"},
  243. {"ring_1_full_cnt"},
  244. {"ring_2_full_cnt"},
  245. {"ring_3_full_cnt"},
  246. {"ring_4_full_cnt"},
  247. {"ring_5_full_cnt"},
  248. {"ring_6_full_cnt"},
  249. {"ring_7_full_cnt"},
  250. {"alarm_transceiver_temp_high"},
  251. {"alarm_transceiver_temp_low"},
  252. {"alarm_laser_bias_current_high"},
  253. {"alarm_laser_bias_current_low"},
  254. {"alarm_laser_output_power_high"},
  255. {"alarm_laser_output_power_low"},
  256. {"warn_transceiver_temp_high"},
  257. {"warn_transceiver_temp_low"},
  258. {"warn_laser_bias_current_high"},
  259. {"warn_laser_bias_current_low"},
  260. {"warn_laser_output_power_high"},
  261. {"warn_laser_output_power_low"},
  262. {"lro_aggregated_pkts"},
  263. {"lro_flush_both_count"},
  264. {"lro_out_of_sequence_pkts"},
  265. {"lro_flush_due_to_max_pkts"},
  266. {"lro_avg_aggr_pkts"},
  267. {"mem_alloc_fail_cnt"},
  268. {"pci_map_fail_cnt"},
  269. {"watchdog_timer_cnt"},
  270. {"mem_allocated"},
  271. {"mem_freed"},
  272. {"link_up_cnt"},
  273. {"link_down_cnt"},
  274. {"link_up_time"},
  275. {"link_down_time"},
  276. {"tx_tcode_buf_abort_cnt"},
  277. {"tx_tcode_desc_abort_cnt"},
  278. {"tx_tcode_parity_err_cnt"},
  279. {"tx_tcode_link_loss_cnt"},
  280. {"tx_tcode_list_proc_err_cnt"},
  281. {"rx_tcode_parity_err_cnt"},
  282. {"rx_tcode_abort_cnt"},
  283. {"rx_tcode_parity_abort_cnt"},
  284. {"rx_tcode_rda_fail_cnt"},
  285. {"rx_tcode_unkn_prot_cnt"},
  286. {"rx_tcode_fcs_err_cnt"},
  287. {"rx_tcode_buf_size_err_cnt"},
  288. {"rx_tcode_rxd_corrupt_cnt"},
  289. {"rx_tcode_unkn_err_cnt"},
  290. {"tda_err_cnt"},
  291. {"pfc_err_cnt"},
  292. {"pcc_err_cnt"},
  293. {"tti_err_cnt"},
  294. {"tpa_err_cnt"},
  295. {"sm_err_cnt"},
  296. {"lso_err_cnt"},
  297. {"mac_tmac_err_cnt"},
  298. {"mac_rmac_err_cnt"},
  299. {"xgxs_txgxs_err_cnt"},
  300. {"xgxs_rxgxs_err_cnt"},
  301. {"rc_err_cnt"},
  302. {"prc_pcix_err_cnt"},
  303. {"rpa_err_cnt"},
  304. {"rda_err_cnt"},
  305. {"rti_err_cnt"},
  306. {"mc_err_cnt"}
  307. };
  308. #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
  309. #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
  310. #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
  311. #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
  312. #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
  313. #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
  314. #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
  315. #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
  316. #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
  317. #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
  318. init_timer(&timer); \
  319. timer.function = handle; \
  320. timer.data = (unsigned long) arg; \
  321. mod_timer(&timer, (jiffies + exp)) \
  322. /* copy mac addr to def_mac_addr array */
  323. static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
  324. {
  325. sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
  326. sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
  327. sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
  328. sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
  329. sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
  330. sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
  331. }
  332. /* Add the vlan */
  333. static void s2io_vlan_rx_register(struct net_device *dev,
  334. struct vlan_group *grp)
  335. {
  336. int i;
  337. struct s2io_nic *nic = dev->priv;
  338. unsigned long flags[MAX_TX_FIFOS];
  339. struct mac_info *mac_control = &nic->mac_control;
  340. struct config_param *config = &nic->config;
  341. for (i = 0; i < config->tx_fifo_num; i++)
  342. spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
  343. nic->vlgrp = grp;
  344. for (i = config->tx_fifo_num - 1; i >= 0; i--)
  345. spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
  346. flags[i]);
  347. }
  348. /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
  349. static int vlan_strip_flag;
  350. /* Unregister the vlan */
  351. static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
  352. {
  353. int i;
  354. struct s2io_nic *nic = dev->priv;
  355. unsigned long flags[MAX_TX_FIFOS];
  356. struct mac_info *mac_control = &nic->mac_control;
  357. struct config_param *config = &nic->config;
  358. for (i = 0; i < config->tx_fifo_num; i++)
  359. spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
  360. if (nic->vlgrp)
  361. vlan_group_set_device(nic->vlgrp, vid, NULL);
  362. for (i = config->tx_fifo_num - 1; i >= 0; i--)
  363. spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
  364. flags[i]);
  365. }
  366. /*
  367. * Constants to be programmed into the Xena's registers, to configure
  368. * the XAUI.
  369. */
  370. #define END_SIGN 0x0
  371. static const u64 herc_act_dtx_cfg[] = {
  372. /* Set address */
  373. 0x8000051536750000ULL, 0x80000515367500E0ULL,
  374. /* Write data */
  375. 0x8000051536750004ULL, 0x80000515367500E4ULL,
  376. /* Set address */
  377. 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
  378. /* Write data */
  379. 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
  380. /* Set address */
  381. 0x801205150D440000ULL, 0x801205150D4400E0ULL,
  382. /* Write data */
  383. 0x801205150D440004ULL, 0x801205150D4400E4ULL,
  384. /* Set address */
  385. 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
  386. /* Write data */
  387. 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
  388. /* Done */
  389. END_SIGN
  390. };
  391. static const u64 xena_dtx_cfg[] = {
  392. /* Set address */
  393. 0x8000051500000000ULL, 0x80000515000000E0ULL,
  394. /* Write data */
  395. 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
  396. /* Set address */
  397. 0x8001051500000000ULL, 0x80010515000000E0ULL,
  398. /* Write data */
  399. 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
  400. /* Set address */
  401. 0x8002051500000000ULL, 0x80020515000000E0ULL,
  402. /* Write data */
  403. 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
  404. END_SIGN
  405. };
  406. /*
  407. * Constants for Fixing the MacAddress problem seen mostly on
  408. * Alpha machines.
  409. */
  410. static const u64 fix_mac[] = {
  411. 0x0060000000000000ULL, 0x0060600000000000ULL,
  412. 0x0040600000000000ULL, 0x0000600000000000ULL,
  413. 0x0020600000000000ULL, 0x0060600000000000ULL,
  414. 0x0020600000000000ULL, 0x0060600000000000ULL,
  415. 0x0020600000000000ULL, 0x0060600000000000ULL,
  416. 0x0020600000000000ULL, 0x0060600000000000ULL,
  417. 0x0020600000000000ULL, 0x0060600000000000ULL,
  418. 0x0020600000000000ULL, 0x0060600000000000ULL,
  419. 0x0020600000000000ULL, 0x0060600000000000ULL,
  420. 0x0020600000000000ULL, 0x0060600000000000ULL,
  421. 0x0020600000000000ULL, 0x0060600000000000ULL,
  422. 0x0020600000000000ULL, 0x0060600000000000ULL,
  423. 0x0020600000000000ULL, 0x0000600000000000ULL,
  424. 0x0040600000000000ULL, 0x0060600000000000ULL,
  425. END_SIGN
  426. };
  427. MODULE_LICENSE("GPL");
  428. MODULE_VERSION(DRV_VERSION);
  429. /* Module Loadable parameters. */
  430. S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
  431. S2IO_PARM_INT(rx_ring_num, 1);
  432. S2IO_PARM_INT(multiq, 0);
  433. S2IO_PARM_INT(rx_ring_mode, 1);
  434. S2IO_PARM_INT(use_continuous_tx_intrs, 1);
  435. S2IO_PARM_INT(rmac_pause_time, 0x100);
  436. S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
  437. S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
  438. S2IO_PARM_INT(shared_splits, 0);
  439. S2IO_PARM_INT(tmac_util_period, 5);
  440. S2IO_PARM_INT(rmac_util_period, 5);
  441. S2IO_PARM_INT(l3l4hdr_size, 128);
  442. /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
  443. S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
  444. /* Frequency of Rx desc syncs expressed as power of 2 */
  445. S2IO_PARM_INT(rxsync_frequency, 3);
  446. /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
  447. S2IO_PARM_INT(intr_type, 2);
  448. /* Large receive offload feature */
  449. static unsigned int lro_enable;
  450. module_param_named(lro, lro_enable, uint, 0);
  451. /* Max pkts to be aggregated by LRO at one time. If not specified,
  452. * aggregation happens until we hit max IP pkt size(64K)
  453. */
  454. S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
  455. S2IO_PARM_INT(indicate_max_pkts, 0);
  456. S2IO_PARM_INT(napi, 1);
  457. S2IO_PARM_INT(ufo, 0);
  458. S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
  459. static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
  460. {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
  461. static unsigned int rx_ring_sz[MAX_RX_RINGS] =
  462. {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
  463. static unsigned int rts_frm_len[MAX_RX_RINGS] =
  464. {[0 ...(MAX_RX_RINGS - 1)] = 0 };
  465. module_param_array(tx_fifo_len, uint, NULL, 0);
  466. module_param_array(rx_ring_sz, uint, NULL, 0);
  467. module_param_array(rts_frm_len, uint, NULL, 0);
  468. /*
  469. * S2IO device table.
  470. * This table lists all the devices that this driver supports.
  471. */
  472. static struct pci_device_id s2io_tbl[] __devinitdata = {
  473. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
  474. PCI_ANY_ID, PCI_ANY_ID},
  475. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
  476. PCI_ANY_ID, PCI_ANY_ID},
  477. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
  478. PCI_ANY_ID, PCI_ANY_ID},
  479. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
  480. PCI_ANY_ID, PCI_ANY_ID},
  481. {0,}
  482. };
  483. MODULE_DEVICE_TABLE(pci, s2io_tbl);
  484. static struct pci_error_handlers s2io_err_handler = {
  485. .error_detected = s2io_io_error_detected,
  486. .slot_reset = s2io_io_slot_reset,
  487. .resume = s2io_io_resume,
  488. };
  489. static struct pci_driver s2io_driver = {
  490. .name = "S2IO",
  491. .id_table = s2io_tbl,
  492. .probe = s2io_init_nic,
  493. .remove = __devexit_p(s2io_rem_nic),
  494. .err_handler = &s2io_err_handler,
  495. };
  496. /* A simplifier macro used both by init and free shared_mem Fns(). */
  497. #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
  498. /* netqueue manipulation helper functions */
  499. static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
  500. {
  501. if (!sp->config.multiq) {
  502. int i;
  503. for (i = 0; i < sp->config.tx_fifo_num; i++)
  504. sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
  505. }
  506. netif_tx_stop_all_queues(sp->dev);
  507. }
  508. static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
  509. {
  510. if (!sp->config.multiq)
  511. sp->mac_control.fifos[fifo_no].queue_state =
  512. FIFO_QUEUE_STOP;
  513. netif_tx_stop_all_queues(sp->dev);
  514. }
  515. static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
  516. {
  517. if (!sp->config.multiq) {
  518. int i;
  519. for (i = 0; i < sp->config.tx_fifo_num; i++)
  520. sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
  521. }
  522. netif_tx_start_all_queues(sp->dev);
  523. }
  524. static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
  525. {
  526. if (!sp->config.multiq)
  527. sp->mac_control.fifos[fifo_no].queue_state =
  528. FIFO_QUEUE_START;
  529. netif_tx_start_all_queues(sp->dev);
  530. }
  531. static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
  532. {
  533. if (!sp->config.multiq) {
  534. int i;
  535. for (i = 0; i < sp->config.tx_fifo_num; i++)
  536. sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
  537. }
  538. netif_tx_wake_all_queues(sp->dev);
  539. }
  540. static inline void s2io_wake_tx_queue(
  541. struct fifo_info *fifo, int cnt, u8 multiq)
  542. {
  543. if (multiq) {
  544. if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
  545. netif_wake_subqueue(fifo->dev, fifo->fifo_no);
  546. } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
  547. if (netif_queue_stopped(fifo->dev)) {
  548. fifo->queue_state = FIFO_QUEUE_START;
  549. netif_wake_queue(fifo->dev);
  550. }
  551. }
  552. }
  553. /**
  554. * init_shared_mem - Allocation and Initialization of Memory
  555. * @nic: Device private variable.
  556. * Description: The function allocates all the memory areas shared
  557. * between the NIC and the driver. This includes Tx descriptors,
  558. * Rx descriptors and the statistics block.
  559. */
  560. static int init_shared_mem(struct s2io_nic *nic)
  561. {
  562. u32 size;
  563. void *tmp_v_addr, *tmp_v_addr_next;
  564. dma_addr_t tmp_p_addr, tmp_p_addr_next;
  565. struct RxD_block *pre_rxd_blk = NULL;
  566. int i, j, blk_cnt;
  567. int lst_size, lst_per_page;
  568. struct net_device *dev = nic->dev;
  569. unsigned long tmp;
  570. struct buffAdd *ba;
  571. struct mac_info *mac_control;
  572. struct config_param *config;
  573. unsigned long long mem_allocated = 0;
  574. mac_control = &nic->mac_control;
  575. config = &nic->config;
  576. /* Allocation and initialization of TXDLs in FIOFs */
  577. size = 0;
  578. for (i = 0; i < config->tx_fifo_num; i++) {
  579. size += config->tx_cfg[i].fifo_len;
  580. }
  581. if (size > MAX_AVAILABLE_TXDS) {
  582. DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
  583. DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
  584. return -EINVAL;
  585. }
  586. size = 0;
  587. for (i = 0; i < config->tx_fifo_num; i++) {
  588. size = config->tx_cfg[i].fifo_len;
  589. /*
  590. * Legal values are from 2 to 8192
  591. */
  592. if (size < 2) {
  593. DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
  594. DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
  595. DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
  596. "are 2 to 8192\n");
  597. return -EINVAL;
  598. }
  599. }
  600. lst_size = (sizeof(struct TxD) * config->max_txds);
  601. lst_per_page = PAGE_SIZE / lst_size;
  602. for (i = 0; i < config->tx_fifo_num; i++) {
  603. int fifo_len = config->tx_cfg[i].fifo_len;
  604. int list_holder_size = fifo_len * sizeof(struct list_info_hold);
  605. mac_control->fifos[i].list_info = kzalloc(list_holder_size,
  606. GFP_KERNEL);
  607. if (!mac_control->fifos[i].list_info) {
  608. DBG_PRINT(INFO_DBG,
  609. "Malloc failed for list_info\n");
  610. return -ENOMEM;
  611. }
  612. mem_allocated += list_holder_size;
  613. }
  614. for (i = 0; i < config->tx_fifo_num; i++) {
  615. int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
  616. lst_per_page);
  617. mac_control->fifos[i].tx_curr_put_info.offset = 0;
  618. mac_control->fifos[i].tx_curr_put_info.fifo_len =
  619. config->tx_cfg[i].fifo_len - 1;
  620. mac_control->fifos[i].tx_curr_get_info.offset = 0;
  621. mac_control->fifos[i].tx_curr_get_info.fifo_len =
  622. config->tx_cfg[i].fifo_len - 1;
  623. mac_control->fifos[i].fifo_no = i;
  624. mac_control->fifos[i].nic = nic;
  625. mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
  626. mac_control->fifos[i].dev = dev;
  627. for (j = 0; j < page_num; j++) {
  628. int k = 0;
  629. dma_addr_t tmp_p;
  630. void *tmp_v;
  631. tmp_v = pci_alloc_consistent(nic->pdev,
  632. PAGE_SIZE, &tmp_p);
  633. if (!tmp_v) {
  634. DBG_PRINT(INFO_DBG,
  635. "pci_alloc_consistent ");
  636. DBG_PRINT(INFO_DBG, "failed for TxDL\n");
  637. return -ENOMEM;
  638. }
  639. /* If we got a zero DMA address(can happen on
  640. * certain platforms like PPC), reallocate.
  641. * Store virtual address of page we don't want,
  642. * to be freed later.
  643. */
  644. if (!tmp_p) {
  645. mac_control->zerodma_virt_addr = tmp_v;
  646. DBG_PRINT(INIT_DBG,
  647. "%s: Zero DMA address for TxDL. ", dev->name);
  648. DBG_PRINT(INIT_DBG,
  649. "Virtual address %p\n", tmp_v);
  650. tmp_v = pci_alloc_consistent(nic->pdev,
  651. PAGE_SIZE, &tmp_p);
  652. if (!tmp_v) {
  653. DBG_PRINT(INFO_DBG,
  654. "pci_alloc_consistent ");
  655. DBG_PRINT(INFO_DBG, "failed for TxDL\n");
  656. return -ENOMEM;
  657. }
  658. mem_allocated += PAGE_SIZE;
  659. }
  660. while (k < lst_per_page) {
  661. int l = (j * lst_per_page) + k;
  662. if (l == config->tx_cfg[i].fifo_len)
  663. break;
  664. mac_control->fifos[i].list_info[l].list_virt_addr =
  665. tmp_v + (k * lst_size);
  666. mac_control->fifos[i].list_info[l].list_phy_addr =
  667. tmp_p + (k * lst_size);
  668. k++;
  669. }
  670. }
  671. }
  672. for (i = 0; i < config->tx_fifo_num; i++) {
  673. size = config->tx_cfg[i].fifo_len;
  674. mac_control->fifos[i].ufo_in_band_v
  675. = kcalloc(size, sizeof(u64), GFP_KERNEL);
  676. if (!mac_control->fifos[i].ufo_in_band_v)
  677. return -ENOMEM;
  678. mem_allocated += (size * sizeof(u64));
  679. }
  680. /* Allocation and initialization of RXDs in Rings */
  681. size = 0;
  682. for (i = 0; i < config->rx_ring_num; i++) {
  683. if (config->rx_cfg[i].num_rxd %
  684. (rxd_count[nic->rxd_mode] + 1)) {
  685. DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
  686. DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
  687. i);
  688. DBG_PRINT(ERR_DBG, "RxDs per Block");
  689. return FAILURE;
  690. }
  691. size += config->rx_cfg[i].num_rxd;
  692. mac_control->rings[i].block_count =
  693. config->rx_cfg[i].num_rxd /
  694. (rxd_count[nic->rxd_mode] + 1 );
  695. mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
  696. mac_control->rings[i].block_count;
  697. }
  698. if (nic->rxd_mode == RXD_MODE_1)
  699. size = (size * (sizeof(struct RxD1)));
  700. else
  701. size = (size * (sizeof(struct RxD3)));
  702. for (i = 0; i < config->rx_ring_num; i++) {
  703. mac_control->rings[i].rx_curr_get_info.block_index = 0;
  704. mac_control->rings[i].rx_curr_get_info.offset = 0;
  705. mac_control->rings[i].rx_curr_get_info.ring_len =
  706. config->rx_cfg[i].num_rxd - 1;
  707. mac_control->rings[i].rx_curr_put_info.block_index = 0;
  708. mac_control->rings[i].rx_curr_put_info.offset = 0;
  709. mac_control->rings[i].rx_curr_put_info.ring_len =
  710. config->rx_cfg[i].num_rxd - 1;
  711. mac_control->rings[i].nic = nic;
  712. mac_control->rings[i].ring_no = i;
  713. mac_control->rings[i].lro = lro_enable;
  714. blk_cnt = config->rx_cfg[i].num_rxd /
  715. (rxd_count[nic->rxd_mode] + 1);
  716. /* Allocating all the Rx blocks */
  717. for (j = 0; j < blk_cnt; j++) {
  718. struct rx_block_info *rx_blocks;
  719. int l;
  720. rx_blocks = &mac_control->rings[i].rx_blocks[j];
  721. size = SIZE_OF_BLOCK; //size is always page size
  722. tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
  723. &tmp_p_addr);
  724. if (tmp_v_addr == NULL) {
  725. /*
  726. * In case of failure, free_shared_mem()
  727. * is called, which should free any
  728. * memory that was alloced till the
  729. * failure happened.
  730. */
  731. rx_blocks->block_virt_addr = tmp_v_addr;
  732. return -ENOMEM;
  733. }
  734. mem_allocated += size;
  735. memset(tmp_v_addr, 0, size);
  736. rx_blocks->block_virt_addr = tmp_v_addr;
  737. rx_blocks->block_dma_addr = tmp_p_addr;
  738. rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
  739. rxd_count[nic->rxd_mode],
  740. GFP_KERNEL);
  741. if (!rx_blocks->rxds)
  742. return -ENOMEM;
  743. mem_allocated +=
  744. (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
  745. for (l=0; l<rxd_count[nic->rxd_mode];l++) {
  746. rx_blocks->rxds[l].virt_addr =
  747. rx_blocks->block_virt_addr +
  748. (rxd_size[nic->rxd_mode] * l);
  749. rx_blocks->rxds[l].dma_addr =
  750. rx_blocks->block_dma_addr +
  751. (rxd_size[nic->rxd_mode] * l);
  752. }
  753. }
  754. /* Interlinking all Rx Blocks */
  755. for (j = 0; j < blk_cnt; j++) {
  756. tmp_v_addr =
  757. mac_control->rings[i].rx_blocks[j].block_virt_addr;
  758. tmp_v_addr_next =
  759. mac_control->rings[i].rx_blocks[(j + 1) %
  760. blk_cnt].block_virt_addr;
  761. tmp_p_addr =
  762. mac_control->rings[i].rx_blocks[j].block_dma_addr;
  763. tmp_p_addr_next =
  764. mac_control->rings[i].rx_blocks[(j + 1) %
  765. blk_cnt].block_dma_addr;
  766. pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
  767. pre_rxd_blk->reserved_2_pNext_RxD_block =
  768. (unsigned long) tmp_v_addr_next;
  769. pre_rxd_blk->pNext_RxD_Blk_physical =
  770. (u64) tmp_p_addr_next;
  771. }
  772. }
  773. if (nic->rxd_mode == RXD_MODE_3B) {
  774. /*
  775. * Allocation of Storages for buffer addresses in 2BUFF mode
  776. * and the buffers as well.
  777. */
  778. for (i = 0; i < config->rx_ring_num; i++) {
  779. blk_cnt = config->rx_cfg[i].num_rxd /
  780. (rxd_count[nic->rxd_mode]+ 1);
  781. mac_control->rings[i].ba =
  782. kmalloc((sizeof(struct buffAdd *) * blk_cnt),
  783. GFP_KERNEL);
  784. if (!mac_control->rings[i].ba)
  785. return -ENOMEM;
  786. mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
  787. for (j = 0; j < blk_cnt; j++) {
  788. int k = 0;
  789. mac_control->rings[i].ba[j] =
  790. kmalloc((sizeof(struct buffAdd) *
  791. (rxd_count[nic->rxd_mode] + 1)),
  792. GFP_KERNEL);
  793. if (!mac_control->rings[i].ba[j])
  794. return -ENOMEM;
  795. mem_allocated += (sizeof(struct buffAdd) * \
  796. (rxd_count[nic->rxd_mode] + 1));
  797. while (k != rxd_count[nic->rxd_mode]) {
  798. ba = &mac_control->rings[i].ba[j][k];
  799. ba->ba_0_org = (void *) kmalloc
  800. (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
  801. if (!ba->ba_0_org)
  802. return -ENOMEM;
  803. mem_allocated +=
  804. (BUF0_LEN + ALIGN_SIZE);
  805. tmp = (unsigned long)ba->ba_0_org;
  806. tmp += ALIGN_SIZE;
  807. tmp &= ~((unsigned long) ALIGN_SIZE);
  808. ba->ba_0 = (void *) tmp;
  809. ba->ba_1_org = (void *) kmalloc
  810. (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
  811. if (!ba->ba_1_org)
  812. return -ENOMEM;
  813. mem_allocated
  814. += (BUF1_LEN + ALIGN_SIZE);
  815. tmp = (unsigned long) ba->ba_1_org;
  816. tmp += ALIGN_SIZE;
  817. tmp &= ~((unsigned long) ALIGN_SIZE);
  818. ba->ba_1 = (void *) tmp;
  819. k++;
  820. }
  821. }
  822. }
  823. }
  824. /* Allocation and initialization of Statistics block */
  825. size = sizeof(struct stat_block);
  826. mac_control->stats_mem = pci_alloc_consistent
  827. (nic->pdev, size, &mac_control->stats_mem_phy);
  828. if (!mac_control->stats_mem) {
  829. /*
  830. * In case of failure, free_shared_mem() is called, which
  831. * should free any memory that was alloced till the
  832. * failure happened.
  833. */
  834. return -ENOMEM;
  835. }
  836. mem_allocated += size;
  837. mac_control->stats_mem_sz = size;
  838. tmp_v_addr = mac_control->stats_mem;
  839. mac_control->stats_info = (struct stat_block *) tmp_v_addr;
  840. memset(tmp_v_addr, 0, size);
  841. DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
  842. (unsigned long long) tmp_p_addr);
  843. mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
  844. return SUCCESS;
  845. }
  846. /**
  847. * free_shared_mem - Free the allocated Memory
  848. * @nic: Device private variable.
  849. * Description: This function is to free all memory locations allocated by
  850. * the init_shared_mem() function and return it to the kernel.
  851. */
  852. static void free_shared_mem(struct s2io_nic *nic)
  853. {
  854. int i, j, blk_cnt, size;
  855. void *tmp_v_addr;
  856. dma_addr_t tmp_p_addr;
  857. struct mac_info *mac_control;
  858. struct config_param *config;
  859. int lst_size, lst_per_page;
  860. struct net_device *dev;
  861. int page_num = 0;
  862. if (!nic)
  863. return;
  864. dev = nic->dev;
  865. mac_control = &nic->mac_control;
  866. config = &nic->config;
  867. lst_size = (sizeof(struct TxD) * config->max_txds);
  868. lst_per_page = PAGE_SIZE / lst_size;
  869. for (i = 0; i < config->tx_fifo_num; i++) {
  870. page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
  871. lst_per_page);
  872. for (j = 0; j < page_num; j++) {
  873. int mem_blks = (j * lst_per_page);
  874. if (!mac_control->fifos[i].list_info)
  875. return;
  876. if (!mac_control->fifos[i].list_info[mem_blks].
  877. list_virt_addr)
  878. break;
  879. pci_free_consistent(nic->pdev, PAGE_SIZE,
  880. mac_control->fifos[i].
  881. list_info[mem_blks].
  882. list_virt_addr,
  883. mac_control->fifos[i].
  884. list_info[mem_blks].
  885. list_phy_addr);
  886. nic->mac_control.stats_info->sw_stat.mem_freed
  887. += PAGE_SIZE;
  888. }
  889. /* If we got a zero DMA address during allocation,
  890. * free the page now
  891. */
  892. if (mac_control->zerodma_virt_addr) {
  893. pci_free_consistent(nic->pdev, PAGE_SIZE,
  894. mac_control->zerodma_virt_addr,
  895. (dma_addr_t)0);
  896. DBG_PRINT(INIT_DBG,
  897. "%s: Freeing TxDL with zero DMA addr. ",
  898. dev->name);
  899. DBG_PRINT(INIT_DBG, "Virtual address %p\n",
  900. mac_control->zerodma_virt_addr);
  901. nic->mac_control.stats_info->sw_stat.mem_freed
  902. += PAGE_SIZE;
  903. }
  904. kfree(mac_control->fifos[i].list_info);
  905. nic->mac_control.stats_info->sw_stat.mem_freed +=
  906. (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
  907. }
  908. size = SIZE_OF_BLOCK;
  909. for (i = 0; i < config->rx_ring_num; i++) {
  910. blk_cnt = mac_control->rings[i].block_count;
  911. for (j = 0; j < blk_cnt; j++) {
  912. tmp_v_addr = mac_control->rings[i].rx_blocks[j].
  913. block_virt_addr;
  914. tmp_p_addr = mac_control->rings[i].rx_blocks[j].
  915. block_dma_addr;
  916. if (tmp_v_addr == NULL)
  917. break;
  918. pci_free_consistent(nic->pdev, size,
  919. tmp_v_addr, tmp_p_addr);
  920. nic->mac_control.stats_info->sw_stat.mem_freed += size;
  921. kfree(mac_control->rings[i].rx_blocks[j].rxds);
  922. nic->mac_control.stats_info->sw_stat.mem_freed +=
  923. ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
  924. }
  925. }
  926. if (nic->rxd_mode == RXD_MODE_3B) {
  927. /* Freeing buffer storage addresses in 2BUFF mode. */
  928. for (i = 0; i < config->rx_ring_num; i++) {
  929. blk_cnt = config->rx_cfg[i].num_rxd /
  930. (rxd_count[nic->rxd_mode] + 1);
  931. for (j = 0; j < blk_cnt; j++) {
  932. int k = 0;
  933. if (!mac_control->rings[i].ba[j])
  934. continue;
  935. while (k != rxd_count[nic->rxd_mode]) {
  936. struct buffAdd *ba =
  937. &mac_control->rings[i].ba[j][k];
  938. kfree(ba->ba_0_org);
  939. nic->mac_control.stats_info->sw_stat.\
  940. mem_freed += (BUF0_LEN + ALIGN_SIZE);
  941. kfree(ba->ba_1_org);
  942. nic->mac_control.stats_info->sw_stat.\
  943. mem_freed += (BUF1_LEN + ALIGN_SIZE);
  944. k++;
  945. }
  946. kfree(mac_control->rings[i].ba[j]);
  947. nic->mac_control.stats_info->sw_stat.mem_freed +=
  948. (sizeof(struct buffAdd) *
  949. (rxd_count[nic->rxd_mode] + 1));
  950. }
  951. kfree(mac_control->rings[i].ba);
  952. nic->mac_control.stats_info->sw_stat.mem_freed +=
  953. (sizeof(struct buffAdd *) * blk_cnt);
  954. }
  955. }
  956. for (i = 0; i < nic->config.tx_fifo_num; i++) {
  957. if (mac_control->fifos[i].ufo_in_band_v) {
  958. nic->mac_control.stats_info->sw_stat.mem_freed
  959. += (config->tx_cfg[i].fifo_len * sizeof(u64));
  960. kfree(mac_control->fifos[i].ufo_in_band_v);
  961. }
  962. }
  963. if (mac_control->stats_mem) {
  964. nic->mac_control.stats_info->sw_stat.mem_freed +=
  965. mac_control->stats_mem_sz;
  966. pci_free_consistent(nic->pdev,
  967. mac_control->stats_mem_sz,
  968. mac_control->stats_mem,
  969. mac_control->stats_mem_phy);
  970. }
  971. }
  972. /**
  973. * s2io_verify_pci_mode -
  974. */
  975. static int s2io_verify_pci_mode(struct s2io_nic *nic)
  976. {
  977. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  978. register u64 val64 = 0;
  979. int mode;
  980. val64 = readq(&bar0->pci_mode);
  981. mode = (u8)GET_PCI_MODE(val64);
  982. if ( val64 & PCI_MODE_UNKNOWN_MODE)
  983. return -1; /* Unknown PCI mode */
  984. return mode;
  985. }
  986. #define NEC_VENID 0x1033
  987. #define NEC_DEVID 0x0125
  988. static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
  989. {
  990. struct pci_dev *tdev = NULL;
  991. while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
  992. if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
  993. if (tdev->bus == s2io_pdev->bus->parent) {
  994. pci_dev_put(tdev);
  995. return 1;
  996. }
  997. }
  998. }
  999. return 0;
  1000. }
  1001. static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
  1002. /**
  1003. * s2io_print_pci_mode -
  1004. */
  1005. static int s2io_print_pci_mode(struct s2io_nic *nic)
  1006. {
  1007. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  1008. register u64 val64 = 0;
  1009. int mode;
  1010. struct config_param *config = &nic->config;
  1011. val64 = readq(&bar0->pci_mode);
  1012. mode = (u8)GET_PCI_MODE(val64);
  1013. if ( val64 & PCI_MODE_UNKNOWN_MODE)
  1014. return -1; /* Unknown PCI mode */
  1015. config->bus_speed = bus_speed[mode];
  1016. if (s2io_on_nec_bridge(nic->pdev)) {
  1017. DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
  1018. nic->dev->name);
  1019. return mode;
  1020. }
  1021. if (val64 & PCI_MODE_32_BITS) {
  1022. DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
  1023. } else {
  1024. DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
  1025. }
  1026. switch(mode) {
  1027. case PCI_MODE_PCI_33:
  1028. DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
  1029. break;
  1030. case PCI_MODE_PCI_66:
  1031. DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
  1032. break;
  1033. case PCI_MODE_PCIX_M1_66:
  1034. DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
  1035. break;
  1036. case PCI_MODE_PCIX_M1_100:
  1037. DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
  1038. break;
  1039. case PCI_MODE_PCIX_M1_133:
  1040. DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
  1041. break;
  1042. case PCI_MODE_PCIX_M2_66:
  1043. DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
  1044. break;
  1045. case PCI_MODE_PCIX_M2_100:
  1046. DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
  1047. break;
  1048. case PCI_MODE_PCIX_M2_133:
  1049. DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
  1050. break;
  1051. default:
  1052. return -1; /* Unsupported bus speed */
  1053. }
  1054. return mode;
  1055. }
  1056. /**
  1057. * init_tti - Initialization transmit traffic interrupt scheme
  1058. * @nic: device private variable
  1059. * @link: link status (UP/DOWN) used to enable/disable continuous
  1060. * transmit interrupts
  1061. * Description: The function configures transmit traffic interrupts
  1062. * Return Value: SUCCESS on success and
  1063. * '-1' on failure
  1064. */
  1065. static int init_tti(struct s2io_nic *nic, int link)
  1066. {
  1067. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  1068. register u64 val64 = 0;
  1069. int i;
  1070. struct config_param *config;
  1071. config = &nic->config;
  1072. for (i = 0; i < config->tx_fifo_num; i++) {
  1073. /*
  1074. * TTI Initialization. Default Tx timer gets us about
  1075. * 250 interrupts per sec. Continuous interrupts are enabled
  1076. * by default.
  1077. */
  1078. if (nic->device_type == XFRAME_II_DEVICE) {
  1079. int count = (nic->config.bus_speed * 125)/2;
  1080. val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
  1081. } else
  1082. val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
  1083. val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
  1084. TTI_DATA1_MEM_TX_URNG_B(0x10) |
  1085. TTI_DATA1_MEM_TX_URNG_C(0x30) |
  1086. TTI_DATA1_MEM_TX_TIMER_AC_EN;
  1087. if (i == 0)
  1088. if (use_continuous_tx_intrs && (link == LINK_UP))
  1089. val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
  1090. writeq(val64, &bar0->tti_data1_mem);
  1091. if (nic->config.intr_type == MSI_X) {
  1092. val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
  1093. TTI_DATA2_MEM_TX_UFC_B(0x100) |
  1094. TTI_DATA2_MEM_TX_UFC_C(0x200) |
  1095. TTI_DATA2_MEM_TX_UFC_D(0x300);
  1096. } else {
  1097. if ((nic->config.tx_steering_type ==
  1098. TX_DEFAULT_STEERING) &&
  1099. (config->tx_fifo_num > 1) &&
  1100. (i >= nic->udp_fifo_idx) &&
  1101. (i < (nic->udp_fifo_idx +
  1102. nic->total_udp_fifos)))
  1103. val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
  1104. TTI_DATA2_MEM_TX_UFC_B(0x80) |
  1105. TTI_DATA2_MEM_TX_UFC_C(0x100) |
  1106. TTI_DATA2_MEM_TX_UFC_D(0x120);
  1107. else
  1108. val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
  1109. TTI_DATA2_MEM_TX_UFC_B(0x20) |
  1110. TTI_DATA2_MEM_TX_UFC_C(0x40) |
  1111. TTI_DATA2_MEM_TX_UFC_D(0x80);
  1112. }
  1113. writeq(val64, &bar0->tti_data2_mem);
  1114. val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
  1115. TTI_CMD_MEM_OFFSET(i);
  1116. writeq(val64, &bar0->tti_command_mem);
  1117. if (wait_for_cmd_complete(&bar0->tti_command_mem,
  1118. TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
  1119. return FAILURE;
  1120. }
  1121. return SUCCESS;
  1122. }
  1123. /**
  1124. * init_nic - Initialization of hardware
  1125. * @nic: device private variable
  1126. * Description: The function sequentially configures every block
  1127. * of the H/W from their reset values.
  1128. * Return Value: SUCCESS on success and
  1129. * '-1' on failure (endian settings incorrect).
  1130. */
  1131. static int init_nic(struct s2io_nic *nic)
  1132. {
  1133. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  1134. struct net_device *dev = nic->dev;
  1135. register u64 val64 = 0;
  1136. void __iomem *add;
  1137. u32 time;
  1138. int i, j;
  1139. struct mac_info *mac_control;
  1140. struct config_param *config;
  1141. int dtx_cnt = 0;
  1142. unsigned long long mem_share;
  1143. int mem_size;
  1144. mac_control = &nic->mac_control;
  1145. config = &nic->config;
  1146. /* to set the swapper controle on the card */
  1147. if(s2io_set_swapper(nic)) {
  1148. DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
  1149. return -EIO;
  1150. }
  1151. /*
  1152. * Herc requires EOI to be removed from reset before XGXS, so..
  1153. */
  1154. if (nic->device_type & XFRAME_II_DEVICE) {
  1155. val64 = 0xA500000000ULL;
  1156. writeq(val64, &bar0->sw_reset);
  1157. msleep(500);
  1158. val64 = readq(&bar0->sw_reset);
  1159. }
  1160. /* Remove XGXS from reset state */
  1161. val64 = 0;
  1162. writeq(val64, &bar0->sw_reset);
  1163. msleep(500);
  1164. val64 = readq(&bar0->sw_reset);
  1165. /* Ensure that it's safe to access registers by checking
  1166. * RIC_RUNNING bit is reset. Check is valid only for XframeII.
  1167. */
  1168. if (nic->device_type == XFRAME_II_DEVICE) {
  1169. for (i = 0; i < 50; i++) {
  1170. val64 = readq(&bar0->adapter_status);
  1171. if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
  1172. break;
  1173. msleep(10);
  1174. }
  1175. if (i == 50)
  1176. return -ENODEV;
  1177. }
  1178. /* Enable Receiving broadcasts */
  1179. add = &bar0->mac_cfg;
  1180. val64 = readq(&bar0->mac_cfg);
  1181. val64 |= MAC_RMAC_BCAST_ENABLE;
  1182. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1183. writel((u32) val64, add);
  1184. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1185. writel((u32) (val64 >> 32), (add + 4));
  1186. /* Read registers in all blocks */
  1187. val64 = readq(&bar0->mac_int_mask);
  1188. val64 = readq(&bar0->mc_int_mask);
  1189. val64 = readq(&bar0->xgxs_int_mask);
  1190. /* Set MTU */
  1191. val64 = dev->mtu;
  1192. writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
  1193. if (nic->device_type & XFRAME_II_DEVICE) {
  1194. while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
  1195. SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
  1196. &bar0->dtx_control, UF);
  1197. if (dtx_cnt & 0x1)
  1198. msleep(1); /* Necessary!! */
  1199. dtx_cnt++;
  1200. }
  1201. } else {
  1202. while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
  1203. SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
  1204. &bar0->dtx_control, UF);
  1205. val64 = readq(&bar0->dtx_control);
  1206. dtx_cnt++;
  1207. }
  1208. }
  1209. /* Tx DMA Initialization */
  1210. val64 = 0;
  1211. writeq(val64, &bar0->tx_fifo_partition_0);
  1212. writeq(val64, &bar0->tx_fifo_partition_1);
  1213. writeq(val64, &bar0->tx_fifo_partition_2);
  1214. writeq(val64, &bar0->tx_fifo_partition_3);
  1215. for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
  1216. val64 |=
  1217. vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
  1218. 13) | vBIT(config->tx_cfg[i].fifo_priority,
  1219. ((j * 32) + 5), 3);
  1220. if (i == (config->tx_fifo_num - 1)) {
  1221. if (i % 2 == 0)
  1222. i++;
  1223. }
  1224. switch (i) {
  1225. case 1:
  1226. writeq(val64, &bar0->tx_fifo_partition_0);
  1227. val64 = 0;
  1228. j = 0;
  1229. break;
  1230. case 3:
  1231. writeq(val64, &bar0->tx_fifo_partition_1);
  1232. val64 = 0;
  1233. j = 0;
  1234. break;
  1235. case 5:
  1236. writeq(val64, &bar0->tx_fifo_partition_2);
  1237. val64 = 0;
  1238. j = 0;
  1239. break;
  1240. case 7:
  1241. writeq(val64, &bar0->tx_fifo_partition_3);
  1242. val64 = 0;
  1243. j = 0;
  1244. break;
  1245. default:
  1246. j++;
  1247. break;
  1248. }
  1249. }
  1250. /*
  1251. * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
  1252. * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
  1253. */
  1254. if ((nic->device_type == XFRAME_I_DEVICE) &&
  1255. (nic->pdev->revision < 4))
  1256. writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
  1257. val64 = readq(&bar0->tx_fifo_partition_0);
  1258. DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
  1259. &bar0->tx_fifo_partition_0, (unsigned long long) val64);
  1260. /*
  1261. * Initialization of Tx_PA_CONFIG register to ignore packet
  1262. * integrity checking.
  1263. */
  1264. val64 = readq(&bar0->tx_pa_cfg);
  1265. val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
  1266. TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
  1267. writeq(val64, &bar0->tx_pa_cfg);
  1268. /* Rx DMA intialization. */
  1269. val64 = 0;
  1270. for (i = 0; i < config->rx_ring_num; i++) {
  1271. val64 |=
  1272. vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
  1273. 3);
  1274. }
  1275. writeq(val64, &bar0->rx_queue_priority);
  1276. /*
  1277. * Allocating equal share of memory to all the
  1278. * configured Rings.
  1279. */
  1280. val64 = 0;
  1281. if (nic->device_type & XFRAME_II_DEVICE)
  1282. mem_size = 32;
  1283. else
  1284. mem_size = 64;
  1285. for (i = 0; i < config->rx_ring_num; i++) {
  1286. switch (i) {
  1287. case 0:
  1288. mem_share = (mem_size / config->rx_ring_num +
  1289. mem_size % config->rx_ring_num);
  1290. val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
  1291. continue;
  1292. case 1:
  1293. mem_share = (mem_size / config->rx_ring_num);
  1294. val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
  1295. continue;
  1296. case 2:
  1297. mem_share = (mem_size / config->rx_ring_num);
  1298. val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
  1299. continue;
  1300. case 3:
  1301. mem_share = (mem_size / config->rx_ring_num);
  1302. val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
  1303. continue;
  1304. case 4:
  1305. mem_share = (mem_size / config->rx_ring_num);
  1306. val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
  1307. continue;
  1308. case 5:
  1309. mem_share = (mem_size / config->rx_ring_num);
  1310. val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
  1311. continue;
  1312. case 6:
  1313. mem_share = (mem_size / config->rx_ring_num);
  1314. val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
  1315. continue;
  1316. case 7:
  1317. mem_share = (mem_size / config->rx_ring_num);
  1318. val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
  1319. continue;
  1320. }
  1321. }
  1322. writeq(val64, &bar0->rx_queue_cfg);
  1323. /*
  1324. * Filling Tx round robin registers
  1325. * as per the number of FIFOs for equal scheduling priority
  1326. */
  1327. switch (config->tx_fifo_num) {
  1328. case 1:
  1329. val64 = 0x0;
  1330. writeq(val64, &bar0->tx_w_round_robin_0);
  1331. writeq(val64, &bar0->tx_w_round_robin_1);
  1332. writeq(val64, &bar0->tx_w_round_robin_2);
  1333. writeq(val64, &bar0->tx_w_round_robin_3);
  1334. writeq(val64, &bar0->tx_w_round_robin_4);
  1335. break;
  1336. case 2:
  1337. val64 = 0x0001000100010001ULL;
  1338. writeq(val64, &bar0->tx_w_round_robin_0);
  1339. writeq(val64, &bar0->tx_w_round_robin_1);
  1340. writeq(val64, &bar0->tx_w_round_robin_2);
  1341. writeq(val64, &bar0->tx_w_round_robin_3);
  1342. val64 = 0x0001000100000000ULL;
  1343. writeq(val64, &bar0->tx_w_round_robin_4);
  1344. break;
  1345. case 3:
  1346. val64 = 0x0001020001020001ULL;
  1347. writeq(val64, &bar0->tx_w_round_robin_0);
  1348. val64 = 0x0200010200010200ULL;
  1349. writeq(val64, &bar0->tx_w_round_robin_1);
  1350. val64 = 0x0102000102000102ULL;
  1351. writeq(val64, &bar0->tx_w_round_robin_2);
  1352. val64 = 0x0001020001020001ULL;
  1353. writeq(val64, &bar0->tx_w_round_robin_3);
  1354. val64 = 0x0200010200000000ULL;
  1355. writeq(val64, &bar0->tx_w_round_robin_4);
  1356. break;
  1357. case 4:
  1358. val64 = 0x0001020300010203ULL;
  1359. writeq(val64, &bar0->tx_w_round_robin_0);
  1360. writeq(val64, &bar0->tx_w_round_robin_1);
  1361. writeq(val64, &bar0->tx_w_round_robin_2);
  1362. writeq(val64, &bar0->tx_w_round_robin_3);
  1363. val64 = 0x0001020300000000ULL;
  1364. writeq(val64, &bar0->tx_w_round_robin_4);
  1365. break;
  1366. case 5:
  1367. val64 = 0x0001020304000102ULL;
  1368. writeq(val64, &bar0->tx_w_round_robin_0);
  1369. val64 = 0x0304000102030400ULL;
  1370. writeq(val64, &bar0->tx_w_round_robin_1);
  1371. val64 = 0x0102030400010203ULL;
  1372. writeq(val64, &bar0->tx_w_round_robin_2);
  1373. val64 = 0x0400010203040001ULL;
  1374. writeq(val64, &bar0->tx_w_round_robin_3);
  1375. val64 = 0x0203040000000000ULL;
  1376. writeq(val64, &bar0->tx_w_round_robin_4);
  1377. break;
  1378. case 6:
  1379. val64 = 0x0001020304050001ULL;
  1380. writeq(val64, &bar0->tx_w_round_robin_0);
  1381. val64 = 0x0203040500010203ULL;
  1382. writeq(val64, &bar0->tx_w_round_robin_1);
  1383. val64 = 0x0405000102030405ULL;
  1384. writeq(val64, &bar0->tx_w_round_robin_2);
  1385. val64 = 0x0001020304050001ULL;
  1386. writeq(val64, &bar0->tx_w_round_robin_3);
  1387. val64 = 0x0203040500000000ULL;
  1388. writeq(val64, &bar0->tx_w_round_robin_4);
  1389. break;
  1390. case 7:
  1391. val64 = 0x0001020304050600ULL;
  1392. writeq(val64, &bar0->tx_w_round_robin_0);
  1393. val64 = 0x0102030405060001ULL;
  1394. writeq(val64, &bar0->tx_w_round_robin_1);
  1395. val64 = 0x0203040506000102ULL;
  1396. writeq(val64, &bar0->tx_w_round_robin_2);
  1397. val64 = 0x0304050600010203ULL;
  1398. writeq(val64, &bar0->tx_w_round_robin_3);
  1399. val64 = 0x0405060000000000ULL;
  1400. writeq(val64, &bar0->tx_w_round_robin_4);
  1401. break;
  1402. case 8:
  1403. val64 = 0x0001020304050607ULL;
  1404. writeq(val64, &bar0->tx_w_round_robin_0);
  1405. writeq(val64, &bar0->tx_w_round_robin_1);
  1406. writeq(val64, &bar0->tx_w_round_robin_2);
  1407. writeq(val64, &bar0->tx_w_round_robin_3);
  1408. val64 = 0x0001020300000000ULL;
  1409. writeq(val64, &bar0->tx_w_round_robin_4);
  1410. break;
  1411. }
  1412. /* Enable all configured Tx FIFO partitions */
  1413. val64 = readq(&bar0->tx_fifo_partition_0);
  1414. val64 |= (TX_FIFO_PARTITION_EN);
  1415. writeq(val64, &bar0->tx_fifo_partition_0);
  1416. /* Filling the Rx round robin registers as per the
  1417. * number of Rings and steering based on QoS with
  1418. * equal priority.
  1419. */
  1420. switch (config->rx_ring_num) {
  1421. case 1:
  1422. val64 = 0x0;
  1423. writeq(val64, &bar0->rx_w_round_robin_0);
  1424. writeq(val64, &bar0->rx_w_round_robin_1);
  1425. writeq(val64, &bar0->rx_w_round_robin_2);
  1426. writeq(val64, &bar0->rx_w_round_robin_3);
  1427. writeq(val64, &bar0->rx_w_round_robin_4);
  1428. val64 = 0x8080808080808080ULL;
  1429. writeq(val64, &bar0->rts_qos_steering);
  1430. break;
  1431. case 2:
  1432. val64 = 0x0001000100010001ULL;
  1433. writeq(val64, &bar0->rx_w_round_robin_0);
  1434. writeq(val64, &bar0->rx_w_round_robin_1);
  1435. writeq(val64, &bar0->rx_w_round_robin_2);
  1436. writeq(val64, &bar0->rx_w_round_robin_3);
  1437. val64 = 0x0001000100000000ULL;
  1438. writeq(val64, &bar0->rx_w_round_robin_4);
  1439. val64 = 0x8080808040404040ULL;
  1440. writeq(val64, &bar0->rts_qos_steering);
  1441. break;
  1442. case 3:
  1443. val64 = 0x0001020001020001ULL;
  1444. writeq(val64, &bar0->rx_w_round_robin_0);
  1445. val64 = 0x0200010200010200ULL;
  1446. writeq(val64, &bar0->rx_w_round_robin_1);
  1447. val64 = 0x0102000102000102ULL;
  1448. writeq(val64, &bar0->rx_w_round_robin_2);
  1449. val64 = 0x0001020001020001ULL;
  1450. writeq(val64, &bar0->rx_w_round_robin_3);
  1451. val64 = 0x0200010200000000ULL;
  1452. writeq(val64, &bar0->rx_w_round_robin_4);
  1453. val64 = 0x8080804040402020ULL;
  1454. writeq(val64, &bar0->rts_qos_steering);
  1455. break;
  1456. case 4:
  1457. val64 = 0x0001020300010203ULL;
  1458. writeq(val64, &bar0->rx_w_round_robin_0);
  1459. writeq(val64, &bar0->rx_w_round_robin_1);
  1460. writeq(val64, &bar0->rx_w_round_robin_2);
  1461. writeq(val64, &bar0->rx_w_round_robin_3);
  1462. val64 = 0x0001020300000000ULL;
  1463. writeq(val64, &bar0->rx_w_round_robin_4);
  1464. val64 = 0x8080404020201010ULL;
  1465. writeq(val64, &bar0->rts_qos_steering);
  1466. break;
  1467. case 5:
  1468. val64 = 0x0001020304000102ULL;
  1469. writeq(val64, &bar0->rx_w_round_robin_0);
  1470. val64 = 0x0304000102030400ULL;
  1471. writeq(val64, &bar0->rx_w_round_robin_1);
  1472. val64 = 0x0102030400010203ULL;
  1473. writeq(val64, &bar0->rx_w_round_robin_2);
  1474. val64 = 0x0400010203040001ULL;
  1475. writeq(val64, &bar0->rx_w_round_robin_3);
  1476. val64 = 0x0203040000000000ULL;
  1477. writeq(val64, &bar0->rx_w_round_robin_4);
  1478. val64 = 0x8080404020201008ULL;
  1479. writeq(val64, &bar0->rts_qos_steering);
  1480. break;
  1481. case 6:
  1482. val64 = 0x0001020304050001ULL;
  1483. writeq(val64, &bar0->rx_w_round_robin_0);
  1484. val64 = 0x0203040500010203ULL;
  1485. writeq(val64, &bar0->rx_w_round_robin_1);
  1486. val64 = 0x0405000102030405ULL;
  1487. writeq(val64, &bar0->rx_w_round_robin_2);
  1488. val64 = 0x0001020304050001ULL;
  1489. writeq(val64, &bar0->rx_w_round_robin_3);
  1490. val64 = 0x0203040500000000ULL;
  1491. writeq(val64, &bar0->rx_w_round_robin_4);
  1492. val64 = 0x8080404020100804ULL;
  1493. writeq(val64, &bar0->rts_qos_steering);
  1494. break;
  1495. case 7:
  1496. val64 = 0x0001020304050600ULL;
  1497. writeq(val64, &bar0->rx_w_round_robin_0);
  1498. val64 = 0x0102030405060001ULL;
  1499. writeq(val64, &bar0->rx_w_round_robin_1);
  1500. val64 = 0x0203040506000102ULL;
  1501. writeq(val64, &bar0->rx_w_round_robin_2);
  1502. val64 = 0x0304050600010203ULL;
  1503. writeq(val64, &bar0->rx_w_round_robin_3);
  1504. val64 = 0x0405060000000000ULL;
  1505. writeq(val64, &bar0->rx_w_round_robin_4);
  1506. val64 = 0x8080402010080402ULL;
  1507. writeq(val64, &bar0->rts_qos_steering);
  1508. break;
  1509. case 8:
  1510. val64 = 0x0001020304050607ULL;
  1511. writeq(val64, &bar0->rx_w_round_robin_0);
  1512. writeq(val64, &bar0->rx_w_round_robin_1);
  1513. writeq(val64, &bar0->rx_w_round_robin_2);
  1514. writeq(val64, &bar0->rx_w_round_robin_3);
  1515. val64 = 0x0001020300000000ULL;
  1516. writeq(val64, &bar0->rx_w_round_robin_4);
  1517. val64 = 0x8040201008040201ULL;
  1518. writeq(val64, &bar0->rts_qos_steering);
  1519. break;
  1520. }
  1521. /* UDP Fix */
  1522. val64 = 0;
  1523. for (i = 0; i < 8; i++)
  1524. writeq(val64, &bar0->rts_frm_len_n[i]);
  1525. /* Set the default rts frame length for the rings configured */
  1526. val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
  1527. for (i = 0 ; i < config->rx_ring_num ; i++)
  1528. writeq(val64, &bar0->rts_frm_len_n[i]);
  1529. /* Set the frame length for the configured rings
  1530. * desired by the user
  1531. */
  1532. for (i = 0; i < config->rx_ring_num; i++) {
  1533. /* If rts_frm_len[i] == 0 then it is assumed that user not
  1534. * specified frame length steering.
  1535. * If the user provides the frame length then program
  1536. * the rts_frm_len register for those values or else
  1537. * leave it as it is.
  1538. */
  1539. if (rts_frm_len[i] != 0) {
  1540. writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
  1541. &bar0->rts_frm_len_n[i]);
  1542. }
  1543. }
  1544. /* Disable differentiated services steering logic */
  1545. for (i = 0; i < 64; i++) {
  1546. if (rts_ds_steer(nic, i, 0) == FAILURE) {
  1547. DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
  1548. dev->name);
  1549. DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
  1550. return -ENODEV;
  1551. }
  1552. }
  1553. /* Program statistics memory */
  1554. writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
  1555. if (nic->device_type == XFRAME_II_DEVICE) {
  1556. val64 = STAT_BC(0x320);
  1557. writeq(val64, &bar0->stat_byte_cnt);
  1558. }
  1559. /*
  1560. * Initializing the sampling rate for the device to calculate the
  1561. * bandwidth utilization.
  1562. */
  1563. val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
  1564. MAC_RX_LINK_UTIL_VAL(rmac_util_period);
  1565. writeq(val64, &bar0->mac_link_util);
  1566. /*
  1567. * Initializing the Transmit and Receive Traffic Interrupt
  1568. * Scheme.
  1569. */
  1570. /* Initialize TTI */
  1571. if (SUCCESS != init_tti(nic, nic->last_link_state))
  1572. return -ENODEV;
  1573. /* RTI Initialization */
  1574. if (nic->device_type == XFRAME_II_DEVICE) {
  1575. /*
  1576. * Programmed to generate Apprx 500 Intrs per
  1577. * second
  1578. */
  1579. int count = (nic->config.bus_speed * 125)/4;
  1580. val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
  1581. } else
  1582. val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
  1583. val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
  1584. RTI_DATA1_MEM_RX_URNG_B(0x10) |
  1585. RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
  1586. writeq(val64, &bar0->rti_data1_mem);
  1587. val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
  1588. RTI_DATA2_MEM_RX_UFC_B(0x2) ;
  1589. if (nic->config.intr_type == MSI_X)
  1590. val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
  1591. RTI_DATA2_MEM_RX_UFC_D(0x40));
  1592. else
  1593. val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
  1594. RTI_DATA2_MEM_RX_UFC_D(0x80));
  1595. writeq(val64, &bar0->rti_data2_mem);
  1596. for (i = 0; i < config->rx_ring_num; i++) {
  1597. val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
  1598. | RTI_CMD_MEM_OFFSET(i);
  1599. writeq(val64, &bar0->rti_command_mem);
  1600. /*
  1601. * Once the operation completes, the Strobe bit of the
  1602. * command register will be reset. We poll for this
  1603. * particular condition. We wait for a maximum of 500ms
  1604. * for the operation to complete, if it's not complete
  1605. * by then we return error.
  1606. */
  1607. time = 0;
  1608. while (TRUE) {
  1609. val64 = readq(&bar0->rti_command_mem);
  1610. if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
  1611. break;
  1612. if (time > 10) {
  1613. DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
  1614. dev->name);
  1615. return -ENODEV;
  1616. }
  1617. time++;
  1618. msleep(50);
  1619. }
  1620. }
  1621. /*
  1622. * Initializing proper values as Pause threshold into all
  1623. * the 8 Queues on Rx side.
  1624. */
  1625. writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
  1626. writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
  1627. /* Disable RMAC PAD STRIPPING */
  1628. add = &bar0->mac_cfg;
  1629. val64 = readq(&bar0->mac_cfg);
  1630. val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
  1631. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1632. writel((u32) (val64), add);
  1633. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1634. writel((u32) (val64 >> 32), (add + 4));
  1635. val64 = readq(&bar0->mac_cfg);
  1636. /* Enable FCS stripping by adapter */
  1637. add = &bar0->mac_cfg;
  1638. val64 = readq(&bar0->mac_cfg);
  1639. val64 |= MAC_CFG_RMAC_STRIP_FCS;
  1640. if (nic->device_type == XFRAME_II_DEVICE)
  1641. writeq(val64, &bar0->mac_cfg);
  1642. else {
  1643. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1644. writel((u32) (val64), add);
  1645. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1646. writel((u32) (val64 >> 32), (add + 4));
  1647. }
  1648. /*
  1649. * Set the time value to be inserted in the pause frame
  1650. * generated by xena.
  1651. */
  1652. val64 = readq(&bar0->rmac_pause_cfg);
  1653. val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
  1654. val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
  1655. writeq(val64, &bar0->rmac_pause_cfg);
  1656. /*
  1657. * Set the Threshold Limit for Generating the pause frame
  1658. * If the amount of data in any Queue exceeds ratio of
  1659. * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
  1660. * pause frame is generated
  1661. */
  1662. val64 = 0;
  1663. for (i = 0; i < 4; i++) {
  1664. val64 |=
  1665. (((u64) 0xFF00 | nic->mac_control.
  1666. mc_pause_threshold_q0q3)
  1667. << (i * 2 * 8));
  1668. }
  1669. writeq(val64, &bar0->mc_pause_thresh_q0q3);
  1670. val64 = 0;
  1671. for (i = 0; i < 4; i++) {
  1672. val64 |=
  1673. (((u64) 0xFF00 | nic->mac_control.
  1674. mc_pause_threshold_q4q7)
  1675. << (i * 2 * 8));
  1676. }
  1677. writeq(val64, &bar0->mc_pause_thresh_q4q7);
  1678. /*
  1679. * TxDMA will stop Read request if the number of read split has
  1680. * exceeded the limit pointed by shared_splits
  1681. */
  1682. val64 = readq(&bar0->pic_control);
  1683. val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
  1684. writeq(val64, &bar0->pic_control);
  1685. if (nic->config.bus_speed == 266) {
  1686. writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
  1687. writeq(0x0, &bar0->read_retry_delay);
  1688. writeq(0x0, &bar0->write_retry_delay);
  1689. }
  1690. /*
  1691. * Programming the Herc to split every write transaction
  1692. * that does not start on an ADB to reduce disconnects.
  1693. */
  1694. if (nic->device_type == XFRAME_II_DEVICE) {
  1695. val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
  1696. MISC_LINK_STABILITY_PRD(3);
  1697. writeq(val64, &bar0->misc_control);
  1698. val64 = readq(&bar0->pic_control2);
  1699. val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
  1700. writeq(val64, &bar0->pic_control2);
  1701. }
  1702. if (strstr(nic->product_name, "CX4")) {
  1703. val64 = TMAC_AVG_IPG(0x17);
  1704. writeq(val64, &bar0->tmac_avg_ipg);
  1705. }
  1706. return SUCCESS;
  1707. }
  1708. #define LINK_UP_DOWN_INTERRUPT 1
  1709. #define MAC_RMAC_ERR_TIMER 2
  1710. static int s2io_link_fault_indication(struct s2io_nic *nic)
  1711. {
  1712. if (nic->device_type == XFRAME_II_DEVICE)
  1713. return LINK_UP_DOWN_INTERRUPT;
  1714. else
  1715. return MAC_RMAC_ERR_TIMER;
  1716. }
  1717. /**
  1718. * do_s2io_write_bits - update alarm bits in alarm register
  1719. * @value: alarm bits
  1720. * @flag: interrupt status
  1721. * @addr: address value
  1722. * Description: update alarm bits in alarm register
  1723. * Return Value:
  1724. * NONE.
  1725. */
  1726. static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
  1727. {
  1728. u64 temp64;
  1729. temp64 = readq(addr);
  1730. if(flag == ENABLE_INTRS)
  1731. temp64 &= ~((u64) value);
  1732. else
  1733. temp64 |= ((u64) value);
  1734. writeq(temp64, addr);
  1735. }
  1736. static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
  1737. {
  1738. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  1739. register u64 gen_int_mask = 0;
  1740. u64 interruptible;
  1741. writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
  1742. if (mask & TX_DMA_INTR) {
  1743. gen_int_mask |= TXDMA_INT_M;
  1744. do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
  1745. TXDMA_PCC_INT | TXDMA_TTI_INT |
  1746. TXDMA_LSO_INT | TXDMA_TPA_INT |
  1747. TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
  1748. do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
  1749. PFC_MISC_0_ERR | PFC_MISC_1_ERR |
  1750. PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
  1751. &bar0->pfc_err_mask);
  1752. do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
  1753. TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
  1754. TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
  1755. do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
  1756. PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
  1757. PCC_N_SERR | PCC_6_COF_OV_ERR |
  1758. PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
  1759. PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
  1760. PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
  1761. do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
  1762. TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
  1763. do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
  1764. LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
  1765. LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
  1766. flag, &bar0->lso_err_mask);
  1767. do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
  1768. flag, &bar0->tpa_err_mask);
  1769. do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
  1770. }
  1771. if (mask & TX_MAC_INTR) {
  1772. gen_int_mask |= TXMAC_INT_M;
  1773. do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
  1774. &bar0->mac_int_mask);
  1775. do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
  1776. TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
  1777. TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
  1778. flag, &bar0->mac_tmac_err_mask);
  1779. }
  1780. if (mask & TX_XGXS_INTR) {
  1781. gen_int_mask |= TXXGXS_INT_M;
  1782. do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
  1783. &bar0->xgxs_int_mask);
  1784. do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
  1785. TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
  1786. flag, &bar0->xgxs_txgxs_err_mask);
  1787. }
  1788. if (mask & RX_DMA_INTR) {
  1789. gen_int_mask |= RXDMA_INT_M;
  1790. do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
  1791. RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
  1792. flag, &bar0->rxdma_int_mask);
  1793. do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
  1794. RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
  1795. RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
  1796. RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
  1797. do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
  1798. PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
  1799. PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
  1800. &bar0->prc_pcix_err_mask);
  1801. do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
  1802. RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
  1803. &bar0->rpa_err_mask);
  1804. do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
  1805. RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
  1806. RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
  1807. RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
  1808. flag, &bar0->rda_err_mask);
  1809. do_s2io_write_bits(RTI_SM_ERR_ALARM |
  1810. RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
  1811. flag, &bar0->rti_err_mask);
  1812. }
  1813. if (mask & RX_MAC_INTR) {
  1814. gen_int_mask |= RXMAC_INT_M;
  1815. do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
  1816. &bar0->mac_int_mask);
  1817. interruptible = RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
  1818. RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
  1819. RMAC_DOUBLE_ECC_ERR;
  1820. if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
  1821. interruptible |= RMAC_LINK_STATE_CHANGE_INT;
  1822. do_s2io_write_bits(interruptible,
  1823. flag, &bar0->mac_rmac_err_mask);
  1824. }
  1825. if (mask & RX_XGXS_INTR)
  1826. {
  1827. gen_int_mask |= RXXGXS_INT_M;
  1828. do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
  1829. &bar0->xgxs_int_mask);
  1830. do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
  1831. &bar0->xgxs_rxgxs_err_mask);
  1832. }
  1833. if (mask & MC_INTR) {
  1834. gen_int_mask |= MC_INT_M;
  1835. do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
  1836. do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
  1837. MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
  1838. &bar0->mc_err_mask);
  1839. }
  1840. nic->general_int_mask = gen_int_mask;
  1841. /* Remove this line when alarm interrupts are enabled */
  1842. nic->general_int_mask = 0;
  1843. }
  1844. /**
  1845. * en_dis_able_nic_intrs - Enable or Disable the interrupts
  1846. * @nic: device private variable,
  1847. * @mask: A mask indicating which Intr block must be modified and,
  1848. * @flag: A flag indicating whether to enable or disable the Intrs.
  1849. * Description: This function will either disable or enable the interrupts
  1850. * depending on the flag argument. The mask argument can be used to
  1851. * enable/disable any Intr block.
  1852. * Return Value: NONE.
  1853. */
  1854. static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
  1855. {
  1856. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  1857. register u64 temp64 = 0, intr_mask = 0;
  1858. intr_mask = nic->general_int_mask;
  1859. /* Top level interrupt classification */
  1860. /* PIC Interrupts */
  1861. if (mask & TX_PIC_INTR) {
  1862. /* Enable PIC Intrs in the general intr mask register */
  1863. intr_mask |= TXPIC_INT_M;
  1864. if (flag == ENABLE_INTRS) {
  1865. /*
  1866. * If Hercules adapter enable GPIO otherwise
  1867. * disable all PCIX, Flash, MDIO, IIC and GPIO
  1868. * interrupts for now.
  1869. * TODO
  1870. */
  1871. if (s2io_link_fault_indication(nic) ==
  1872. LINK_UP_DOWN_INTERRUPT ) {
  1873. do_s2io_write_bits(PIC_INT_GPIO, flag,
  1874. &bar0->pic_int_mask);
  1875. do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
  1876. &bar0->gpio_int_mask);
  1877. } else
  1878. writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
  1879. } else if (flag == DISABLE_INTRS) {
  1880. /*
  1881. * Disable PIC Intrs in the general
  1882. * intr mask register
  1883. */
  1884. writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
  1885. }
  1886. }
  1887. /* Tx traffic interrupts */
  1888. if (mask & TX_TRAFFIC_INTR) {
  1889. intr_mask |= TXTRAFFIC_INT_M;
  1890. if (flag == ENABLE_INTRS) {
  1891. /*
  1892. * Enable all the Tx side interrupts
  1893. * writing 0 Enables all 64 TX interrupt levels
  1894. */
  1895. writeq(0x0, &bar0->tx_traffic_mask);
  1896. } else if (flag == DISABLE_INTRS) {
  1897. /*
  1898. * Disable Tx Traffic Intrs in the general intr mask
  1899. * register.
  1900. */
  1901. writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
  1902. }
  1903. }
  1904. /* Rx traffic interrupts */
  1905. if (mask & RX_TRAFFIC_INTR) {
  1906. intr_mask |= RXTRAFFIC_INT_M;
  1907. if (flag == ENABLE_INTRS) {
  1908. /* writing 0 Enables all 8 RX interrupt levels */
  1909. writeq(0x0, &bar0->rx_traffic_mask);
  1910. } else if (flag == DISABLE_INTRS) {
  1911. /*
  1912. * Disable Rx Traffic Intrs in the general intr mask
  1913. * register.
  1914. */
  1915. writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
  1916. }
  1917. }
  1918. temp64 = readq(&bar0->general_int_mask);
  1919. if (flag == ENABLE_INTRS)
  1920. temp64 &= ~((u64) intr_mask);
  1921. else
  1922. temp64 = DISABLE_ALL_INTRS;
  1923. writeq(temp64, &bar0->general_int_mask);
  1924. nic->general_int_mask = readq(&bar0->general_int_mask);
  1925. }
  1926. /**
  1927. * verify_pcc_quiescent- Checks for PCC quiescent state
  1928. * Return: 1 If PCC is quiescence
  1929. * 0 If PCC is not quiescence
  1930. */
  1931. static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
  1932. {
  1933. int ret = 0, herc;
  1934. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  1935. u64 val64 = readq(&bar0->adapter_status);
  1936. herc = (sp->device_type == XFRAME_II_DEVICE);
  1937. if (flag == FALSE) {
  1938. if ((!herc && (sp->pdev->revision >= 4)) || herc) {
  1939. if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
  1940. ret = 1;
  1941. } else {
  1942. if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
  1943. ret = 1;
  1944. }
  1945. } else {
  1946. if ((!herc && (sp->pdev->revision >= 4)) || herc) {
  1947. if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
  1948. ADAPTER_STATUS_RMAC_PCC_IDLE))
  1949. ret = 1;
  1950. } else {
  1951. if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
  1952. ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
  1953. ret = 1;
  1954. }
  1955. }
  1956. return ret;
  1957. }
  1958. /**
  1959. * verify_xena_quiescence - Checks whether the H/W is ready
  1960. * Description: Returns whether the H/W is ready to go or not. Depending
  1961. * on whether adapter enable bit was written or not the comparison
  1962. * differs and the calling function passes the input argument flag to
  1963. * indicate this.
  1964. * Return: 1 If xena is quiescence
  1965. * 0 If Xena is not quiescence
  1966. */
  1967. static int verify_xena_quiescence(struct s2io_nic *sp)
  1968. {
  1969. int mode;
  1970. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  1971. u64 val64 = readq(&bar0->adapter_status);
  1972. mode = s2io_verify_pci_mode(sp);
  1973. if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
  1974. DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
  1975. return 0;
  1976. }
  1977. if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
  1978. DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
  1979. return 0;
  1980. }
  1981. if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
  1982. DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
  1983. return 0;
  1984. }
  1985. if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
  1986. DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
  1987. return 0;
  1988. }
  1989. if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
  1990. DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
  1991. return 0;
  1992. }
  1993. if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
  1994. DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
  1995. return 0;
  1996. }
  1997. if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
  1998. DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
  1999. return 0;
  2000. }
  2001. if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
  2002. DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
  2003. return 0;
  2004. }
  2005. /*
  2006. * In PCI 33 mode, the P_PLL is not used, and therefore,
  2007. * the the P_PLL_LOCK bit in the adapter_status register will
  2008. * not be asserted.
  2009. */
  2010. if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
  2011. sp->device_type == XFRAME_II_DEVICE && mode !=
  2012. PCI_MODE_PCI_33) {
  2013. DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
  2014. return 0;
  2015. }
  2016. if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
  2017. ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
  2018. DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
  2019. return 0;
  2020. }
  2021. return 1;
  2022. }
  2023. /**
  2024. * fix_mac_address - Fix for Mac addr problem on Alpha platforms
  2025. * @sp: Pointer to device specifc structure
  2026. * Description :
  2027. * New procedure to clear mac address reading problems on Alpha platforms
  2028. *
  2029. */
  2030. static void fix_mac_address(struct s2io_nic * sp)
  2031. {
  2032. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  2033. u64 val64;
  2034. int i = 0;
  2035. while (fix_mac[i] != END_SIGN) {
  2036. writeq(fix_mac[i++], &bar0->gpio_control);
  2037. udelay(10);
  2038. val64 = readq(&bar0->gpio_control);
  2039. }
  2040. }
  2041. /**
  2042. * start_nic - Turns the device on
  2043. * @nic : device private variable.
  2044. * Description:
  2045. * This function actually turns the device on. Before this function is
  2046. * called,all Registers are configured from their reset states
  2047. * and shared memory is allocated but the NIC is still quiescent. On
  2048. * calling this function, the device interrupts are cleared and the NIC is
  2049. * literally switched on by writing into the adapter control register.
  2050. * Return Value:
  2051. * SUCCESS on success and -1 on failure.
  2052. */
  2053. static int start_nic(struct s2io_nic *nic)
  2054. {
  2055. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  2056. struct net_device *dev = nic->dev;
  2057. register u64 val64 = 0;
  2058. u16 subid, i;
  2059. struct mac_info *mac_control;
  2060. struct config_param *config;
  2061. mac_control = &nic->mac_control;
  2062. config = &nic->config;
  2063. /* PRC Initialization and configuration */
  2064. for (i = 0; i < config->rx_ring_num; i++) {
  2065. writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
  2066. &bar0->prc_rxd0_n[i]);
  2067. val64 = readq(&bar0->prc_ctrl_n[i]);
  2068. if (nic->rxd_mode == RXD_MODE_1)
  2069. val64 |= PRC_CTRL_RC_ENABLED;
  2070. else
  2071. val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
  2072. if (nic->device_type == XFRAME_II_DEVICE)
  2073. val64 |= PRC_CTRL_GROUP_READS;
  2074. val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
  2075. val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
  2076. writeq(val64, &bar0->prc_ctrl_n[i]);
  2077. }
  2078. if (nic->rxd_mode == RXD_MODE_3B) {
  2079. /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
  2080. val64 = readq(&bar0->rx_pa_cfg);
  2081. val64 |= RX_PA_CFG_IGNORE_L2_ERR;
  2082. writeq(val64, &bar0->rx_pa_cfg);
  2083. }
  2084. if (vlan_tag_strip == 0) {
  2085. val64 = readq(&bar0->rx_pa_cfg);
  2086. val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
  2087. writeq(val64, &bar0->rx_pa_cfg);
  2088. vlan_strip_flag = 0;
  2089. }
  2090. /*
  2091. * Enabling MC-RLDRAM. After enabling the device, we timeout
  2092. * for around 100ms, which is approximately the time required
  2093. * for the device to be ready for operation.
  2094. */
  2095. val64 = readq(&bar0->mc_rldram_mrs);
  2096. val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
  2097. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
  2098. val64 = readq(&bar0->mc_rldram_mrs);
  2099. msleep(100); /* Delay by around 100 ms. */
  2100. /* Enabling ECC Protection. */
  2101. val64 = readq(&bar0->adapter_control);
  2102. val64 &= ~ADAPTER_ECC_EN;
  2103. writeq(val64, &bar0->adapter_control);
  2104. /*
  2105. * Verify if the device is ready to be enabled, if so enable
  2106. * it.
  2107. */
  2108. val64 = readq(&bar0->adapter_status);
  2109. if (!verify_xena_quiescence(nic)) {
  2110. DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
  2111. DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
  2112. (unsigned long long) val64);
  2113. return FAILURE;
  2114. }
  2115. /*
  2116. * With some switches, link might be already up at this point.
  2117. * Because of this weird behavior, when we enable laser,
  2118. * we may not get link. We need to handle this. We cannot
  2119. * figure out which switch is misbehaving. So we are forced to
  2120. * make a global change.
  2121. */
  2122. /* Enabling Laser. */
  2123. val64 = readq(&bar0->adapter_control);
  2124. val64 |= ADAPTER_EOI_TX_ON;
  2125. writeq(val64, &bar0->adapter_control);
  2126. if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
  2127. /*
  2128. * Dont see link state interrupts initally on some switches,
  2129. * so directly scheduling the link state task here.
  2130. */
  2131. schedule_work(&nic->set_link_task);
  2132. }
  2133. /* SXE-002: Initialize link and activity LED */
  2134. subid = nic->pdev->subsystem_device;
  2135. if (((subid & 0xFF) >= 0x07) &&
  2136. (nic->device_type == XFRAME_I_DEVICE)) {
  2137. val64 = readq(&bar0->gpio_control);
  2138. val64 |= 0x0000800000000000ULL;
  2139. writeq(val64, &bar0->gpio_control);
  2140. val64 = 0x0411040400000000ULL;
  2141. writeq(val64, (void __iomem *)bar0 + 0x2700);
  2142. }
  2143. return SUCCESS;
  2144. }
  2145. /**
  2146. * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
  2147. */
  2148. static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
  2149. TxD *txdlp, int get_off)
  2150. {
  2151. struct s2io_nic *nic = fifo_data->nic;
  2152. struct sk_buff *skb;
  2153. struct TxD *txds;
  2154. u16 j, frg_cnt;
  2155. txds = txdlp;
  2156. if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
  2157. pci_unmap_single(nic->pdev, (dma_addr_t)
  2158. txds->Buffer_Pointer, sizeof(u64),
  2159. PCI_DMA_TODEVICE);
  2160. txds++;
  2161. }
  2162. skb = (struct sk_buff *) ((unsigned long)
  2163. txds->Host_Control);
  2164. if (!skb) {
  2165. memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
  2166. return NULL;
  2167. }
  2168. pci_unmap_single(nic->pdev, (dma_addr_t)
  2169. txds->Buffer_Pointer,
  2170. skb->len - skb->data_len,
  2171. PCI_DMA_TODEVICE);
  2172. frg_cnt = skb_shinfo(skb)->nr_frags;
  2173. if (frg_cnt) {
  2174. txds++;
  2175. for (j = 0; j < frg_cnt; j++, txds++) {
  2176. skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
  2177. if (!txds->Buffer_Pointer)
  2178. break;
  2179. pci_unmap_page(nic->pdev, (dma_addr_t)
  2180. txds->Buffer_Pointer,
  2181. frag->size, PCI_DMA_TODEVICE);
  2182. }
  2183. }
  2184. memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
  2185. return(skb);
  2186. }
  2187. /**
  2188. * free_tx_buffers - Free all queued Tx buffers
  2189. * @nic : device private variable.
  2190. * Description:
  2191. * Free all queued Tx buffers.
  2192. * Return Value: void
  2193. */
  2194. static void free_tx_buffers(struct s2io_nic *nic)
  2195. {
  2196. struct net_device *dev = nic->dev;
  2197. struct sk_buff *skb;
  2198. struct TxD *txdp;
  2199. int i, j;
  2200. struct mac_info *mac_control;
  2201. struct config_param *config;
  2202. int cnt = 0;
  2203. mac_control = &nic->mac_control;
  2204. config = &nic->config;
  2205. for (i = 0; i < config->tx_fifo_num; i++) {
  2206. unsigned long flags;
  2207. spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
  2208. for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
  2209. txdp = (struct TxD *) \
  2210. mac_control->fifos[i].list_info[j].list_virt_addr;
  2211. skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
  2212. if (skb) {
  2213. nic->mac_control.stats_info->sw_stat.mem_freed
  2214. += skb->truesize;
  2215. dev_kfree_skb(skb);
  2216. cnt++;
  2217. }
  2218. }
  2219. DBG_PRINT(INTR_DBG,
  2220. "%s:forcibly freeing %d skbs on FIFO%d\n",
  2221. dev->name, cnt, i);
  2222. mac_control->fifos[i].tx_curr_get_info.offset = 0;
  2223. mac_control->fifos[i].tx_curr_put_info.offset = 0;
  2224. spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
  2225. }
  2226. }
  2227. /**
  2228. * stop_nic - To stop the nic
  2229. * @nic ; device private variable.
  2230. * Description:
  2231. * This function does exactly the opposite of what the start_nic()
  2232. * function does. This function is called to stop the device.
  2233. * Return Value:
  2234. * void.
  2235. */
  2236. static void stop_nic(struct s2io_nic *nic)
  2237. {
  2238. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  2239. register u64 val64 = 0;
  2240. u16 interruptible;
  2241. struct mac_info *mac_control;
  2242. struct config_param *config;
  2243. mac_control = &nic->mac_control;
  2244. config = &nic->config;
  2245. /* Disable all interrupts */
  2246. en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
  2247. interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
  2248. interruptible |= TX_PIC_INTR;
  2249. en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
  2250. /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
  2251. val64 = readq(&bar0->adapter_control);
  2252. val64 &= ~(ADAPTER_CNTL_EN);
  2253. writeq(val64, &bar0->adapter_control);
  2254. }
  2255. /**
  2256. * fill_rx_buffers - Allocates the Rx side skbs
  2257. * @ring_info: per ring structure
  2258. * @from_card_up: If this is true, we will map the buffer to get
  2259. * the dma address for buf0 and buf1 to give it to the card.
  2260. * Else we will sync the already mapped buffer to give it to the card.
  2261. * Description:
  2262. * The function allocates Rx side skbs and puts the physical
  2263. * address of these buffers into the RxD buffer pointers, so that the NIC
  2264. * can DMA the received frame into these locations.
  2265. * The NIC supports 3 receive modes, viz
  2266. * 1. single buffer,
  2267. * 2. three buffer and
  2268. * 3. Five buffer modes.
  2269. * Each mode defines how many fragments the received frame will be split
  2270. * up into by the NIC. The frame is split into L3 header, L4 Header,
  2271. * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
  2272. * is split into 3 fragments. As of now only single buffer mode is
  2273. * supported.
  2274. * Return Value:
  2275. * SUCCESS on success or an appropriate -ve value on failure.
  2276. */
  2277. static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
  2278. int from_card_up)
  2279. {
  2280. struct sk_buff *skb;
  2281. struct RxD_t *rxdp;
  2282. int off, size, block_no, block_no1;
  2283. u32 alloc_tab = 0;
  2284. u32 alloc_cnt;
  2285. u64 tmp;
  2286. struct buffAdd *ba;
  2287. struct RxD_t *first_rxdp = NULL;
  2288. u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
  2289. int rxd_index = 0;
  2290. struct RxD1 *rxdp1;
  2291. struct RxD3 *rxdp3;
  2292. struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
  2293. alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
  2294. block_no1 = ring->rx_curr_get_info.block_index;
  2295. while (alloc_tab < alloc_cnt) {
  2296. block_no = ring->rx_curr_put_info.block_index;
  2297. off = ring->rx_curr_put_info.offset;
  2298. rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
  2299. rxd_index = off + 1;
  2300. if (block_no)
  2301. rxd_index += (block_no * ring->rxd_count);
  2302. if ((block_no == block_no1) &&
  2303. (off == ring->rx_curr_get_info.offset) &&
  2304. (rxdp->Host_Control)) {
  2305. DBG_PRINT(INTR_DBG, "%s: Get and Put",
  2306. ring->dev->name);
  2307. DBG_PRINT(INTR_DBG, " info equated\n");
  2308. goto end;
  2309. }
  2310. if (off && (off == ring->rxd_count)) {
  2311. ring->rx_curr_put_info.block_index++;
  2312. if (ring->rx_curr_put_info.block_index ==
  2313. ring->block_count)
  2314. ring->rx_curr_put_info.block_index = 0;
  2315. block_no = ring->rx_curr_put_info.block_index;
  2316. off = 0;
  2317. ring->rx_curr_put_info.offset = off;
  2318. rxdp = ring->rx_blocks[block_no].block_virt_addr;
  2319. DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
  2320. ring->dev->name, rxdp);
  2321. }
  2322. if ((rxdp->Control_1 & RXD_OWN_XENA) &&
  2323. ((ring->rxd_mode == RXD_MODE_3B) &&
  2324. (rxdp->Control_2 & s2BIT(0)))) {
  2325. ring->rx_curr_put_info.offset = off;
  2326. goto end;
  2327. }
  2328. /* calculate size of skb based on ring mode */
  2329. size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE +
  2330. HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
  2331. if (ring->rxd_mode == RXD_MODE_1)
  2332. size += NET_IP_ALIGN;
  2333. else
  2334. size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
  2335. /* allocate skb */
  2336. skb = dev_alloc_skb(size);
  2337. if(!skb) {
  2338. DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
  2339. DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
  2340. if (first_rxdp) {
  2341. wmb();
  2342. first_rxdp->Control_1 |= RXD_OWN_XENA;
  2343. }
  2344. stats->mem_alloc_fail_cnt++;
  2345. return -ENOMEM ;
  2346. }
  2347. stats->mem_allocated += skb->truesize;
  2348. if (ring->rxd_mode == RXD_MODE_1) {
  2349. /* 1 buffer mode - normal operation mode */
  2350. rxdp1 = (struct RxD1*)rxdp;
  2351. memset(rxdp, 0, sizeof(struct RxD1));
  2352. skb_reserve(skb, NET_IP_ALIGN);
  2353. rxdp1->Buffer0_ptr = pci_map_single
  2354. (ring->pdev, skb->data, size - NET_IP_ALIGN,
  2355. PCI_DMA_FROMDEVICE);
  2356. if (pci_dma_mapping_error(nic->pdev,
  2357. rxdp1->Buffer0_ptr))
  2358. goto pci_map_failed;
  2359. rxdp->Control_2 =
  2360. SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
  2361. rxdp->Host_Control = (unsigned long) (skb);
  2362. } else if (ring->rxd_mode == RXD_MODE_3B) {
  2363. /*
  2364. * 2 buffer mode -
  2365. * 2 buffer mode provides 128
  2366. * byte aligned receive buffers.
  2367. */
  2368. rxdp3 = (struct RxD3*)rxdp;
  2369. /* save buffer pointers to avoid frequent dma mapping */
  2370. Buffer0_ptr = rxdp3->Buffer0_ptr;
  2371. Buffer1_ptr = rxdp3->Buffer1_ptr;
  2372. memset(rxdp, 0, sizeof(struct RxD3));
  2373. /* restore the buffer pointers for dma sync*/
  2374. rxdp3->Buffer0_ptr = Buffer0_ptr;
  2375. rxdp3->Buffer1_ptr = Buffer1_ptr;
  2376. ba = &ring->ba[block_no][off];
  2377. skb_reserve(skb, BUF0_LEN);
  2378. tmp = (u64)(unsigned long) skb->data;
  2379. tmp += ALIGN_SIZE;
  2380. tmp &= ~ALIGN_SIZE;
  2381. skb->data = (void *) (unsigned long)tmp;
  2382. skb_reset_tail_pointer(skb);
  2383. if (from_card_up) {
  2384. rxdp3->Buffer0_ptr =
  2385. pci_map_single(ring->pdev, ba->ba_0,
  2386. BUF0_LEN, PCI_DMA_FROMDEVICE);
  2387. if (pci_dma_mapping_error(nic->pdev,
  2388. rxdp3->Buffer0_ptr))
  2389. goto pci_map_failed;
  2390. } else
  2391. pci_dma_sync_single_for_device(ring->pdev,
  2392. (dma_addr_t) rxdp3->Buffer0_ptr,
  2393. BUF0_LEN, PCI_DMA_FROMDEVICE);
  2394. rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
  2395. if (ring->rxd_mode == RXD_MODE_3B) {
  2396. /* Two buffer mode */
  2397. /*
  2398. * Buffer2 will have L3/L4 header plus
  2399. * L4 payload
  2400. */
  2401. rxdp3->Buffer2_ptr = pci_map_single
  2402. (ring->pdev, skb->data, ring->mtu + 4,
  2403. PCI_DMA_FROMDEVICE);
  2404. if (pci_dma_mapping_error(nic->pdev,
  2405. rxdp3->Buffer2_ptr))
  2406. goto pci_map_failed;
  2407. if (from_card_up) {
  2408. rxdp3->Buffer1_ptr =
  2409. pci_map_single(ring->pdev,
  2410. ba->ba_1, BUF1_LEN,
  2411. PCI_DMA_FROMDEVICE);
  2412. if (pci_dma_mapping_error(nic->pdev,
  2413. rxdp3->Buffer1_ptr)) {
  2414. pci_unmap_single
  2415. (ring->pdev,
  2416. (dma_addr_t)(unsigned long)
  2417. skb->data,
  2418. ring->mtu + 4,
  2419. PCI_DMA_FROMDEVICE);
  2420. goto pci_map_failed;
  2421. }
  2422. }
  2423. rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
  2424. rxdp->Control_2 |= SET_BUFFER2_SIZE_3
  2425. (ring->mtu + 4);
  2426. }
  2427. rxdp->Control_2 |= s2BIT(0);
  2428. rxdp->Host_Control = (unsigned long) (skb);
  2429. }
  2430. if (alloc_tab & ((1 << rxsync_frequency) - 1))
  2431. rxdp->Control_1 |= RXD_OWN_XENA;
  2432. off++;
  2433. if (off == (ring->rxd_count + 1))
  2434. off = 0;
  2435. ring->rx_curr_put_info.offset = off;
  2436. rxdp->Control_2 |= SET_RXD_MARKER;
  2437. if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
  2438. if (first_rxdp) {
  2439. wmb();
  2440. first_rxdp->Control_1 |= RXD_OWN_XENA;
  2441. }
  2442. first_rxdp = rxdp;
  2443. }
  2444. ring->rx_bufs_left += 1;
  2445. alloc_tab++;
  2446. }
  2447. end:
  2448. /* Transfer ownership of first descriptor to adapter just before
  2449. * exiting. Before that, use memory barrier so that ownership
  2450. * and other fields are seen by adapter correctly.
  2451. */
  2452. if (first_rxdp) {
  2453. wmb();
  2454. first_rxdp->Control_1 |= RXD_OWN_XENA;
  2455. }
  2456. return SUCCESS;
  2457. pci_map_failed:
  2458. stats->pci_map_fail_cnt++;
  2459. stats->mem_freed += skb->truesize;
  2460. dev_kfree_skb_irq(skb);
  2461. return -ENOMEM;
  2462. }
  2463. static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
  2464. {
  2465. struct net_device *dev = sp->dev;
  2466. int j;
  2467. struct sk_buff *skb;
  2468. struct RxD_t *rxdp;
  2469. struct mac_info *mac_control;
  2470. struct buffAdd *ba;
  2471. struct RxD1 *rxdp1;
  2472. struct RxD3 *rxdp3;
  2473. mac_control = &sp->mac_control;
  2474. for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
  2475. rxdp = mac_control->rings[ring_no].
  2476. rx_blocks[blk].rxds[j].virt_addr;
  2477. skb = (struct sk_buff *)
  2478. ((unsigned long) rxdp->Host_Control);
  2479. if (!skb) {
  2480. continue;
  2481. }
  2482. if (sp->rxd_mode == RXD_MODE_1) {
  2483. rxdp1 = (struct RxD1*)rxdp;
  2484. pci_unmap_single(sp->pdev, (dma_addr_t)
  2485. rxdp1->Buffer0_ptr,
  2486. dev->mtu +
  2487. HEADER_ETHERNET_II_802_3_SIZE
  2488. + HEADER_802_2_SIZE +
  2489. HEADER_SNAP_SIZE,
  2490. PCI_DMA_FROMDEVICE);
  2491. memset(rxdp, 0, sizeof(struct RxD1));
  2492. } else if(sp->rxd_mode == RXD_MODE_3B) {
  2493. rxdp3 = (struct RxD3*)rxdp;
  2494. ba = &mac_control->rings[ring_no].
  2495. ba[blk][j];
  2496. pci_unmap_single(sp->pdev, (dma_addr_t)
  2497. rxdp3->Buffer0_ptr,
  2498. BUF0_LEN,
  2499. PCI_DMA_FROMDEVICE);
  2500. pci_unmap_single(sp->pdev, (dma_addr_t)
  2501. rxdp3->Buffer1_ptr,
  2502. BUF1_LEN,
  2503. PCI_DMA_FROMDEVICE);
  2504. pci_unmap_single(sp->pdev, (dma_addr_t)
  2505. rxdp3->Buffer2_ptr,
  2506. dev->mtu + 4,
  2507. PCI_DMA_FROMDEVICE);
  2508. memset(rxdp, 0, sizeof(struct RxD3));
  2509. }
  2510. sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
  2511. dev_kfree_skb(skb);
  2512. mac_control->rings[ring_no].rx_bufs_left -= 1;
  2513. }
  2514. }
  2515. /**
  2516. * free_rx_buffers - Frees all Rx buffers
  2517. * @sp: device private variable.
  2518. * Description:
  2519. * This function will free all Rx buffers allocated by host.
  2520. * Return Value:
  2521. * NONE.
  2522. */
  2523. static void free_rx_buffers(struct s2io_nic *sp)
  2524. {
  2525. struct net_device *dev = sp->dev;
  2526. int i, blk = 0, buf_cnt = 0;
  2527. struct mac_info *mac_control;
  2528. struct config_param *config;
  2529. mac_control = &sp->mac_control;
  2530. config = &sp->config;
  2531. for (i = 0; i < config->rx_ring_num; i++) {
  2532. for (blk = 0; blk < rx_ring_sz[i]; blk++)
  2533. free_rxd_blk(sp,i,blk);
  2534. mac_control->rings[i].rx_curr_put_info.block_index = 0;
  2535. mac_control->rings[i].rx_curr_get_info.block_index = 0;
  2536. mac_control->rings[i].rx_curr_put_info.offset = 0;
  2537. mac_control->rings[i].rx_curr_get_info.offset = 0;
  2538. mac_control->rings[i].rx_bufs_left = 0;
  2539. DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
  2540. dev->name, buf_cnt, i);
  2541. }
  2542. }
  2543. static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
  2544. {
  2545. if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
  2546. DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
  2547. DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
  2548. }
  2549. return 0;
  2550. }
  2551. /**
  2552. * s2io_poll - Rx interrupt handler for NAPI support
  2553. * @napi : pointer to the napi structure.
  2554. * @budget : The number of packets that were budgeted to be processed
  2555. * during one pass through the 'Poll" function.
  2556. * Description:
  2557. * Comes into picture only if NAPI support has been incorporated. It does
  2558. * the same thing that rx_intr_handler does, but not in a interrupt context
  2559. * also It will process only a given number of packets.
  2560. * Return value:
  2561. * 0 on success and 1 if there are No Rx packets to be processed.
  2562. */
  2563. static int s2io_poll_msix(struct napi_struct *napi, int budget)
  2564. {
  2565. struct ring_info *ring = container_of(napi, struct ring_info, napi);
  2566. struct net_device *dev = ring->dev;
  2567. struct config_param *config;
  2568. struct mac_info *mac_control;
  2569. int pkts_processed = 0;
  2570. u8 __iomem *addr = NULL;
  2571. u8 val8 = 0;
  2572. struct s2io_nic *nic = dev->priv;
  2573. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  2574. int budget_org = budget;
  2575. config = &nic->config;
  2576. mac_control = &nic->mac_control;
  2577. if (unlikely(!is_s2io_card_up(nic)))
  2578. return 0;
  2579. pkts_processed = rx_intr_handler(ring, budget);
  2580. s2io_chk_rx_buffers(nic, ring);
  2581. if (pkts_processed < budget_org) {
  2582. netif_rx_complete(dev, napi);
  2583. /*Re Enable MSI-Rx Vector*/
  2584. addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
  2585. addr += 7 - ring->ring_no;
  2586. val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
  2587. writeb(val8, addr);
  2588. val8 = readb(addr);
  2589. }
  2590. return pkts_processed;
  2591. }
  2592. static int s2io_poll_inta(struct napi_struct *napi, int budget)
  2593. {
  2594. struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
  2595. struct ring_info *ring;
  2596. struct net_device *dev = nic->dev;
  2597. struct config_param *config;
  2598. struct mac_info *mac_control;
  2599. int pkts_processed = 0;
  2600. int ring_pkts_processed, i;
  2601. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  2602. int budget_org = budget;
  2603. config = &nic->config;
  2604. mac_control = &nic->mac_control;
  2605. if (unlikely(!is_s2io_card_up(nic)))
  2606. return 0;
  2607. for (i = 0; i < config->rx_ring_num; i++) {
  2608. ring = &mac_control->rings[i];
  2609. ring_pkts_processed = rx_intr_handler(ring, budget);
  2610. s2io_chk_rx_buffers(nic, ring);
  2611. pkts_processed += ring_pkts_processed;
  2612. budget -= ring_pkts_processed;
  2613. if (budget <= 0)
  2614. break;
  2615. }
  2616. if (pkts_processed < budget_org) {
  2617. netif_rx_complete(dev, napi);
  2618. /* Re enable the Rx interrupts for the ring */
  2619. writeq(0, &bar0->rx_traffic_mask);
  2620. readl(&bar0->rx_traffic_mask);
  2621. }
  2622. return pkts_processed;
  2623. }
  2624. #ifdef CONFIG_NET_POLL_CONTROLLER
  2625. /**
  2626. * s2io_netpoll - netpoll event handler entry point
  2627. * @dev : pointer to the device structure.
  2628. * Description:
  2629. * This function will be called by upper layer to check for events on the
  2630. * interface in situations where interrupts are disabled. It is used for
  2631. * specific in-kernel networking tasks, such as remote consoles and kernel
  2632. * debugging over the network (example netdump in RedHat).
  2633. */
  2634. static void s2io_netpoll(struct net_device *dev)
  2635. {
  2636. struct s2io_nic *nic = dev->priv;
  2637. struct mac_info *mac_control;
  2638. struct config_param *config;
  2639. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  2640. u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
  2641. int i;
  2642. if (pci_channel_offline(nic->pdev))
  2643. return;
  2644. disable_irq(dev->irq);
  2645. mac_control = &nic->mac_control;
  2646. config = &nic->config;
  2647. writeq(val64, &bar0->rx_traffic_int);
  2648. writeq(val64, &bar0->tx_traffic_int);
  2649. /* we need to free up the transmitted skbufs or else netpoll will
  2650. * run out of skbs and will fail and eventually netpoll application such
  2651. * as netdump will fail.
  2652. */
  2653. for (i = 0; i < config->tx_fifo_num; i++)
  2654. tx_intr_handler(&mac_control->fifos[i]);
  2655. /* check for received packet and indicate up to network */
  2656. for (i = 0; i < config->rx_ring_num; i++)
  2657. rx_intr_handler(&mac_control->rings[i], 0);
  2658. for (i = 0; i < config->rx_ring_num; i++) {
  2659. if (fill_rx_buffers(nic, &mac_control->rings[i], 0) ==
  2660. -ENOMEM) {
  2661. DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
  2662. DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
  2663. break;
  2664. }
  2665. }
  2666. enable_irq(dev->irq);
  2667. return;
  2668. }
  2669. #endif
  2670. /**
  2671. * rx_intr_handler - Rx interrupt handler
  2672. * @ring_info: per ring structure.
  2673. * @budget: budget for napi processing.
  2674. * Description:
  2675. * If the interrupt is because of a received frame or if the
  2676. * receive ring contains fresh as yet un-processed frames,this function is
  2677. * called. It picks out the RxD at which place the last Rx processing had
  2678. * stopped and sends the skb to the OSM's Rx handler and then increments
  2679. * the offset.
  2680. * Return Value:
  2681. * No. of napi packets processed.
  2682. */
  2683. static int rx_intr_handler(struct ring_info *ring_data, int budget)
  2684. {
  2685. int get_block, put_block;
  2686. struct rx_curr_get_info get_info, put_info;
  2687. struct RxD_t *rxdp;
  2688. struct sk_buff *skb;
  2689. int pkt_cnt = 0, napi_pkts = 0;
  2690. int i;
  2691. struct RxD1* rxdp1;
  2692. struct RxD3* rxdp3;
  2693. get_info = ring_data->rx_curr_get_info;
  2694. get_block = get_info.block_index;
  2695. memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
  2696. put_block = put_info.block_index;
  2697. rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
  2698. while (RXD_IS_UP2DT(rxdp)) {
  2699. /*
  2700. * If your are next to put index then it's
  2701. * FIFO full condition
  2702. */
  2703. if ((get_block == put_block) &&
  2704. (get_info.offset + 1) == put_info.offset) {
  2705. DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
  2706. ring_data->dev->name);
  2707. break;
  2708. }
  2709. skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
  2710. if (skb == NULL) {
  2711. DBG_PRINT(ERR_DBG, "%s: The skb is ",
  2712. ring_data->dev->name);
  2713. DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
  2714. return 0;
  2715. }
  2716. if (ring_data->rxd_mode == RXD_MODE_1) {
  2717. rxdp1 = (struct RxD1*)rxdp;
  2718. pci_unmap_single(ring_data->pdev, (dma_addr_t)
  2719. rxdp1->Buffer0_ptr,
  2720. ring_data->mtu +
  2721. HEADER_ETHERNET_II_802_3_SIZE +
  2722. HEADER_802_2_SIZE +
  2723. HEADER_SNAP_SIZE,
  2724. PCI_DMA_FROMDEVICE);
  2725. } else if (ring_data->rxd_mode == RXD_MODE_3B) {
  2726. rxdp3 = (struct RxD3*)rxdp;
  2727. pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t)
  2728. rxdp3->Buffer0_ptr,
  2729. BUF0_LEN, PCI_DMA_FROMDEVICE);
  2730. pci_unmap_single(ring_data->pdev, (dma_addr_t)
  2731. rxdp3->Buffer2_ptr,
  2732. ring_data->mtu + 4,
  2733. PCI_DMA_FROMDEVICE);
  2734. }
  2735. prefetch(skb->data);
  2736. rx_osm_handler(ring_data, rxdp);
  2737. get_info.offset++;
  2738. ring_data->rx_curr_get_info.offset = get_info.offset;
  2739. rxdp = ring_data->rx_blocks[get_block].
  2740. rxds[get_info.offset].virt_addr;
  2741. if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
  2742. get_info.offset = 0;
  2743. ring_data->rx_curr_get_info.offset = get_info.offset;
  2744. get_block++;
  2745. if (get_block == ring_data->block_count)
  2746. get_block = 0;
  2747. ring_data->rx_curr_get_info.block_index = get_block;
  2748. rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
  2749. }
  2750. if (ring_data->nic->config.napi) {
  2751. budget--;
  2752. napi_pkts++;
  2753. if (!budget)
  2754. break;
  2755. }
  2756. pkt_cnt++;
  2757. if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
  2758. break;
  2759. }
  2760. if (ring_data->lro) {
  2761. /* Clear all LRO sessions before exiting */
  2762. for (i=0; i<MAX_LRO_SESSIONS; i++) {
  2763. struct lro *lro = &ring_data->lro0_n[i];
  2764. if (lro->in_use) {
  2765. update_L3L4_header(ring_data->nic, lro);
  2766. queue_rx_frame(lro->parent, lro->vlan_tag);
  2767. clear_lro_session(lro);
  2768. }
  2769. }
  2770. }
  2771. return(napi_pkts);
  2772. }
  2773. /**
  2774. * tx_intr_handler - Transmit interrupt handler
  2775. * @nic : device private variable
  2776. * Description:
  2777. * If an interrupt was raised to indicate DMA complete of the
  2778. * Tx packet, this function is called. It identifies the last TxD
  2779. * whose buffer was freed and frees all skbs whose data have already
  2780. * DMA'ed into the NICs internal memory.
  2781. * Return Value:
  2782. * NONE
  2783. */
  2784. static void tx_intr_handler(struct fifo_info *fifo_data)
  2785. {
  2786. struct s2io_nic *nic = fifo_data->nic;
  2787. struct tx_curr_get_info get_info, put_info;
  2788. struct sk_buff *skb = NULL;
  2789. struct TxD *txdlp;
  2790. int pkt_cnt = 0;
  2791. unsigned long flags = 0;
  2792. u8 err_mask;
  2793. if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
  2794. return;
  2795. get_info = fifo_data->tx_curr_get_info;
  2796. memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
  2797. txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
  2798. list_virt_addr;
  2799. while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
  2800. (get_info.offset != put_info.offset) &&
  2801. (txdlp->Host_Control)) {
  2802. /* Check for TxD errors */
  2803. if (txdlp->Control_1 & TXD_T_CODE) {
  2804. unsigned long long err;
  2805. err = txdlp->Control_1 & TXD_T_CODE;
  2806. if (err & 0x1) {
  2807. nic->mac_control.stats_info->sw_stat.
  2808. parity_err_cnt++;
  2809. }
  2810. /* update t_code statistics */
  2811. err_mask = err >> 48;
  2812. switch(err_mask) {
  2813. case 2:
  2814. nic->mac_control.stats_info->sw_stat.
  2815. tx_buf_abort_cnt++;
  2816. break;
  2817. case 3:
  2818. nic->mac_control.stats_info->sw_stat.
  2819. tx_desc_abort_cnt++;
  2820. break;
  2821. case 7:
  2822. nic->mac_control.stats_info->sw_stat.
  2823. tx_parity_err_cnt++;
  2824. break;
  2825. case 10:
  2826. nic->mac_control.stats_info->sw_stat.
  2827. tx_link_loss_cnt++;
  2828. break;
  2829. case 15:
  2830. nic->mac_control.stats_info->sw_stat.
  2831. tx_list_proc_err_cnt++;
  2832. break;
  2833. }
  2834. }
  2835. skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
  2836. if (skb == NULL) {
  2837. spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
  2838. DBG_PRINT(ERR_DBG, "%s: Null skb ",
  2839. __FUNCTION__);
  2840. DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
  2841. return;
  2842. }
  2843. pkt_cnt++;
  2844. /* Updating the statistics block */
  2845. nic->dev->stats.tx_bytes += skb->len;
  2846. nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
  2847. dev_kfree_skb_irq(skb);
  2848. get_info.offset++;
  2849. if (get_info.offset == get_info.fifo_len + 1)
  2850. get_info.offset = 0;
  2851. txdlp = (struct TxD *) fifo_data->list_info
  2852. [get_info.offset].list_virt_addr;
  2853. fifo_data->tx_curr_get_info.offset =
  2854. get_info.offset;
  2855. }
  2856. s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
  2857. spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
  2858. }
  2859. /**
  2860. * s2io_mdio_write - Function to write in to MDIO registers
  2861. * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
  2862. * @addr : address value
  2863. * @value : data value
  2864. * @dev : pointer to net_device structure
  2865. * Description:
  2866. * This function is used to write values to the MDIO registers
  2867. * NONE
  2868. */
  2869. static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
  2870. {
  2871. u64 val64 = 0x0;
  2872. struct s2io_nic *sp = dev->priv;
  2873. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  2874. //address transaction
  2875. val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
  2876. | MDIO_MMD_DEV_ADDR(mmd_type)
  2877. | MDIO_MMS_PRT_ADDR(0x0);
  2878. writeq(val64, &bar0->mdio_control);
  2879. val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
  2880. writeq(val64, &bar0->mdio_control);
  2881. udelay(100);
  2882. //Data transaction
  2883. val64 = 0x0;
  2884. val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
  2885. | MDIO_MMD_DEV_ADDR(mmd_type)
  2886. | MDIO_MMS_PRT_ADDR(0x0)
  2887. | MDIO_MDIO_DATA(value)
  2888. | MDIO_OP(MDIO_OP_WRITE_TRANS);
  2889. writeq(val64, &bar0->mdio_control);
  2890. val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
  2891. writeq(val64, &bar0->mdio_control);
  2892. udelay(100);
  2893. val64 = 0x0;
  2894. val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
  2895. | MDIO_MMD_DEV_ADDR(mmd_type)
  2896. | MDIO_MMS_PRT_ADDR(0x0)
  2897. | MDIO_OP(MDIO_OP_READ_TRANS);
  2898. writeq(val64, &bar0->mdio_control);
  2899. val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
  2900. writeq(val64, &bar0->mdio_control);
  2901. udelay(100);
  2902. }
  2903. /**
  2904. * s2io_mdio_read - Function to write in to MDIO registers
  2905. * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
  2906. * @addr : address value
  2907. * @dev : pointer to net_device structure
  2908. * Description:
  2909. * This function is used to read values to the MDIO registers
  2910. * NONE
  2911. */
  2912. static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
  2913. {
  2914. u64 val64 = 0x0;
  2915. u64 rval64 = 0x0;
  2916. struct s2io_nic *sp = dev->priv;
  2917. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  2918. /* address transaction */
  2919. val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
  2920. | MDIO_MMD_DEV_ADDR(mmd_type)
  2921. | MDIO_MMS_PRT_ADDR(0x0);
  2922. writeq(val64, &bar0->mdio_control);
  2923. val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
  2924. writeq(val64, &bar0->mdio_control);
  2925. udelay(100);
  2926. /* Data transaction */
  2927. val64 = 0x0;
  2928. val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
  2929. | MDIO_MMD_DEV_ADDR(mmd_type)
  2930. | MDIO_MMS_PRT_ADDR(0x0)
  2931. | MDIO_OP(MDIO_OP_READ_TRANS);
  2932. writeq(val64, &bar0->mdio_control);
  2933. val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
  2934. writeq(val64, &bar0->mdio_control);
  2935. udelay(100);
  2936. /* Read the value from regs */
  2937. rval64 = readq(&bar0->mdio_control);
  2938. rval64 = rval64 & 0xFFFF0000;
  2939. rval64 = rval64 >> 16;
  2940. return rval64;
  2941. }
  2942. /**
  2943. * s2io_chk_xpak_counter - Function to check the status of the xpak counters
  2944. * @counter : couter value to be updated
  2945. * @flag : flag to indicate the status
  2946. * @type : counter type
  2947. * Description:
  2948. * This function is to check the status of the xpak counters value
  2949. * NONE
  2950. */
  2951. static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
  2952. {
  2953. u64 mask = 0x3;
  2954. u64 val64;
  2955. int i;
  2956. for(i = 0; i <index; i++)
  2957. mask = mask << 0x2;
  2958. if(flag > 0)
  2959. {
  2960. *counter = *counter + 1;
  2961. val64 = *regs_stat & mask;
  2962. val64 = val64 >> (index * 0x2);
  2963. val64 = val64 + 1;
  2964. if(val64 == 3)
  2965. {
  2966. switch(type)
  2967. {
  2968. case 1:
  2969. DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
  2970. "service. Excessive temperatures may "
  2971. "result in premature transceiver "
  2972. "failure \n");
  2973. break;
  2974. case 2:
  2975. DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
  2976. "service Excessive bias currents may "
  2977. "indicate imminent laser diode "
  2978. "failure \n");
  2979. break;
  2980. case 3:
  2981. DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
  2982. "service Excessive laser output "
  2983. "power may saturate far-end "
  2984. "receiver\n");
  2985. break;
  2986. default:
  2987. DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
  2988. "type \n");
  2989. }
  2990. val64 = 0x0;
  2991. }
  2992. val64 = val64 << (index * 0x2);
  2993. *regs_stat = (*regs_stat & (~mask)) | (val64);
  2994. } else {
  2995. *regs_stat = *regs_stat & (~mask);
  2996. }
  2997. }
  2998. /**
  2999. * s2io_updt_xpak_counter - Function to update the xpak counters
  3000. * @dev : pointer to net_device struct
  3001. * Description:
  3002. * This function is to upate the status of the xpak counters value
  3003. * NONE
  3004. */
  3005. static void s2io_updt_xpak_counter(struct net_device *dev)
  3006. {
  3007. u16 flag = 0x0;
  3008. u16 type = 0x0;
  3009. u16 val16 = 0x0;
  3010. u64 val64 = 0x0;
  3011. u64 addr = 0x0;
  3012. struct s2io_nic *sp = dev->priv;
  3013. struct stat_block *stat_info = sp->mac_control.stats_info;
  3014. /* Check the communication with the MDIO slave */
  3015. addr = 0x0000;
  3016. val64 = 0x0;
  3017. val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
  3018. if((val64 == 0xFFFF) || (val64 == 0x0000))
  3019. {
  3020. DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
  3021. "Returned %llx\n", (unsigned long long)val64);
  3022. return;
  3023. }
  3024. /* Check for the expecte value of 2040 at PMA address 0x0000 */
  3025. if(val64 != 0x2040)
  3026. {
  3027. DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
  3028. DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
  3029. (unsigned long long)val64);
  3030. return;
  3031. }
  3032. /* Loading the DOM register to MDIO register */
  3033. addr = 0xA100;
  3034. s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
  3035. val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
  3036. /* Reading the Alarm flags */
  3037. addr = 0xA070;
  3038. val64 = 0x0;
  3039. val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
  3040. flag = CHECKBIT(val64, 0x7);
  3041. type = 1;
  3042. s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
  3043. &stat_info->xpak_stat.xpak_regs_stat,
  3044. 0x0, flag, type);
  3045. if(CHECKBIT(val64, 0x6))
  3046. stat_info->xpak_stat.alarm_transceiver_temp_low++;
  3047. flag = CHECKBIT(val64, 0x3);
  3048. type = 2;
  3049. s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
  3050. &stat_info->xpak_stat.xpak_regs_stat,
  3051. 0x2, flag, type);
  3052. if(CHECKBIT(val64, 0x2))
  3053. stat_info->xpak_stat.alarm_laser_bias_current_low++;
  3054. flag = CHECKBIT(val64, 0x1);
  3055. type = 3;
  3056. s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
  3057. &stat_info->xpak_stat.xpak_regs_stat,
  3058. 0x4, flag, type);
  3059. if(CHECKBIT(val64, 0x0))
  3060. stat_info->xpak_stat.alarm_laser_output_power_low++;
  3061. /* Reading the Warning flags */
  3062. addr = 0xA074;
  3063. val64 = 0x0;
  3064. val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
  3065. if(CHECKBIT(val64, 0x7))
  3066. stat_info->xpak_stat.warn_transceiver_temp_high++;
  3067. if(CHECKBIT(val64, 0x6))
  3068. stat_info->xpak_stat.warn_transceiver_temp_low++;
  3069. if(CHECKBIT(val64, 0x3))
  3070. stat_info->xpak_stat.warn_laser_bias_current_high++;
  3071. if(CHECKBIT(val64, 0x2))
  3072. stat_info->xpak_stat.warn_laser_bias_current_low++;
  3073. if(CHECKBIT(val64, 0x1))
  3074. stat_info->xpak_stat.warn_laser_output_power_high++;
  3075. if(CHECKBIT(val64, 0x0))
  3076. stat_info->xpak_stat.warn_laser_output_power_low++;
  3077. }
  3078. /**
  3079. * wait_for_cmd_complete - waits for a command to complete.
  3080. * @sp : private member of the device structure, which is a pointer to the
  3081. * s2io_nic structure.
  3082. * Description: Function that waits for a command to Write into RMAC
  3083. * ADDR DATA registers to be completed and returns either success or
  3084. * error depending on whether the command was complete or not.
  3085. * Return value:
  3086. * SUCCESS on success and FAILURE on failure.
  3087. */
  3088. static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
  3089. int bit_state)
  3090. {
  3091. int ret = FAILURE, cnt = 0, delay = 1;
  3092. u64 val64;
  3093. if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
  3094. return FAILURE;
  3095. do {
  3096. val64 = readq(addr);
  3097. if (bit_state == S2IO_BIT_RESET) {
  3098. if (!(val64 & busy_bit)) {
  3099. ret = SUCCESS;
  3100. break;
  3101. }
  3102. } else {
  3103. if (!(val64 & busy_bit)) {
  3104. ret = SUCCESS;
  3105. break;
  3106. }
  3107. }
  3108. if(in_interrupt())
  3109. mdelay(delay);
  3110. else
  3111. msleep(delay);
  3112. if (++cnt >= 10)
  3113. delay = 50;
  3114. } while (cnt < 20);
  3115. return ret;
  3116. }
  3117. /*
  3118. * check_pci_device_id - Checks if the device id is supported
  3119. * @id : device id
  3120. * Description: Function to check if the pci device id is supported by driver.
  3121. * Return value: Actual device id if supported else PCI_ANY_ID
  3122. */
  3123. static u16 check_pci_device_id(u16 id)
  3124. {
  3125. switch (id) {
  3126. case PCI_DEVICE_ID_HERC_WIN:
  3127. case PCI_DEVICE_ID_HERC_UNI:
  3128. return XFRAME_II_DEVICE;
  3129. case PCI_DEVICE_ID_S2IO_UNI:
  3130. case PCI_DEVICE_ID_S2IO_WIN:
  3131. return XFRAME_I_DEVICE;
  3132. default:
  3133. return PCI_ANY_ID;
  3134. }
  3135. }
  3136. /**
  3137. * s2io_reset - Resets the card.
  3138. * @sp : private member of the device structure.
  3139. * Description: Function to Reset the card. This function then also
  3140. * restores the previously saved PCI configuration space registers as
  3141. * the card reset also resets the configuration space.
  3142. * Return value:
  3143. * void.
  3144. */
  3145. static void s2io_reset(struct s2io_nic * sp)
  3146. {
  3147. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3148. u64 val64;
  3149. u16 subid, pci_cmd;
  3150. int i;
  3151. u16 val16;
  3152. unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
  3153. unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
  3154. DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
  3155. __FUNCTION__, sp->dev->name);
  3156. /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
  3157. pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
  3158. val64 = SW_RESET_ALL;
  3159. writeq(val64, &bar0->sw_reset);
  3160. if (strstr(sp->product_name, "CX4")) {
  3161. msleep(750);
  3162. }
  3163. msleep(250);
  3164. for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
  3165. /* Restore the PCI state saved during initialization. */
  3166. pci_restore_state(sp->pdev);
  3167. pci_read_config_word(sp->pdev, 0x2, &val16);
  3168. if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
  3169. break;
  3170. msleep(200);
  3171. }
  3172. if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
  3173. DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
  3174. }
  3175. pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
  3176. s2io_init_pci(sp);
  3177. /* Set swapper to enable I/O register access */
  3178. s2io_set_swapper(sp);
  3179. /* restore mac_addr entries */
  3180. do_s2io_restore_unicast_mc(sp);
  3181. /* Restore the MSIX table entries from local variables */
  3182. restore_xmsi_data(sp);
  3183. /* Clear certain PCI/PCI-X fields after reset */
  3184. if (sp->device_type == XFRAME_II_DEVICE) {
  3185. /* Clear "detected parity error" bit */
  3186. pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
  3187. /* Clearing PCIX Ecc status register */
  3188. pci_write_config_dword(sp->pdev, 0x68, 0x7C);
  3189. /* Clearing PCI_STATUS error reflected here */
  3190. writeq(s2BIT(62), &bar0->txpic_int_reg);
  3191. }
  3192. /* Reset device statistics maintained by OS */
  3193. memset(&sp->stats, 0, sizeof (struct net_device_stats));
  3194. up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
  3195. down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
  3196. up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
  3197. down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
  3198. reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
  3199. mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
  3200. mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
  3201. watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
  3202. /* save link up/down time/cnt, reset/memory/watchdog cnt */
  3203. memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
  3204. /* restore link up/down time/cnt, reset/memory/watchdog cnt */
  3205. sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
  3206. sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
  3207. sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
  3208. sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
  3209. sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
  3210. sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
  3211. sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
  3212. sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
  3213. /* SXE-002: Configure link and activity LED to turn it off */
  3214. subid = sp->pdev->subsystem_device;
  3215. if (((subid & 0xFF) >= 0x07) &&
  3216. (sp->device_type == XFRAME_I_DEVICE)) {
  3217. val64 = readq(&bar0->gpio_control);
  3218. val64 |= 0x0000800000000000ULL;
  3219. writeq(val64, &bar0->gpio_control);
  3220. val64 = 0x0411040400000000ULL;
  3221. writeq(val64, (void __iomem *)bar0 + 0x2700);
  3222. }
  3223. /*
  3224. * Clear spurious ECC interrupts that would have occured on
  3225. * XFRAME II cards after reset.
  3226. */
  3227. if (sp->device_type == XFRAME_II_DEVICE) {
  3228. val64 = readq(&bar0->pcc_err_reg);
  3229. writeq(val64, &bar0->pcc_err_reg);
  3230. }
  3231. sp->device_enabled_once = FALSE;
  3232. }
  3233. /**
  3234. * s2io_set_swapper - to set the swapper controle on the card
  3235. * @sp : private member of the device structure,
  3236. * pointer to the s2io_nic structure.
  3237. * Description: Function to set the swapper control on the card
  3238. * correctly depending on the 'endianness' of the system.
  3239. * Return value:
  3240. * SUCCESS on success and FAILURE on failure.
  3241. */
  3242. static int s2io_set_swapper(struct s2io_nic * sp)
  3243. {
  3244. struct net_device *dev = sp->dev;
  3245. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3246. u64 val64, valt, valr;
  3247. /*
  3248. * Set proper endian settings and verify the same by reading
  3249. * the PIF Feed-back register.
  3250. */
  3251. val64 = readq(&bar0->pif_rd_swapper_fb);
  3252. if (val64 != 0x0123456789ABCDEFULL) {
  3253. int i = 0;
  3254. u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
  3255. 0x8100008181000081ULL, /* FE=1, SE=0 */
  3256. 0x4200004242000042ULL, /* FE=0, SE=1 */
  3257. 0}; /* FE=0, SE=0 */
  3258. while(i<4) {
  3259. writeq(value[i], &bar0->swapper_ctrl);
  3260. val64 = readq(&bar0->pif_rd_swapper_fb);
  3261. if (val64 == 0x0123456789ABCDEFULL)
  3262. break;
  3263. i++;
  3264. }
  3265. if (i == 4) {
  3266. DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
  3267. dev->name);
  3268. DBG_PRINT(ERR_DBG, "feedback read %llx\n",
  3269. (unsigned long long) val64);
  3270. return FAILURE;
  3271. }
  3272. valr = value[i];
  3273. } else {
  3274. valr = readq(&bar0->swapper_ctrl);
  3275. }
  3276. valt = 0x0123456789ABCDEFULL;
  3277. writeq(valt, &bar0->xmsi_address);
  3278. val64 = readq(&bar0->xmsi_address);
  3279. if(val64 != valt) {
  3280. int i = 0;
  3281. u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
  3282. 0x0081810000818100ULL, /* FE=1, SE=0 */
  3283. 0x0042420000424200ULL, /* FE=0, SE=1 */
  3284. 0}; /* FE=0, SE=0 */
  3285. while(i<4) {
  3286. writeq((value[i] | valr), &bar0->swapper_ctrl);
  3287. writeq(valt, &bar0->xmsi_address);
  3288. val64 = readq(&bar0->xmsi_address);
  3289. if(val64 == valt)
  3290. break;
  3291. i++;
  3292. }
  3293. if(i == 4) {
  3294. unsigned long long x = val64;
  3295. DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
  3296. DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
  3297. return FAILURE;
  3298. }
  3299. }
  3300. val64 = readq(&bar0->swapper_ctrl);
  3301. val64 &= 0xFFFF000000000000ULL;
  3302. #ifdef __BIG_ENDIAN
  3303. /*
  3304. * The device by default set to a big endian format, so a
  3305. * big endian driver need not set anything.
  3306. */
  3307. val64 |= (SWAPPER_CTRL_TXP_FE |
  3308. SWAPPER_CTRL_TXP_SE |
  3309. SWAPPER_CTRL_TXD_R_FE |
  3310. SWAPPER_CTRL_TXD_W_FE |
  3311. SWAPPER_CTRL_TXF_R_FE |
  3312. SWAPPER_CTRL_RXD_R_FE |
  3313. SWAPPER_CTRL_RXD_W_FE |
  3314. SWAPPER_CTRL_RXF_W_FE |
  3315. SWAPPER_CTRL_XMSI_FE |
  3316. SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
  3317. if (sp->config.intr_type == INTA)
  3318. val64 |= SWAPPER_CTRL_XMSI_SE;
  3319. writeq(val64, &bar0->swapper_ctrl);
  3320. #else
  3321. /*
  3322. * Initially we enable all bits to make it accessible by the
  3323. * driver, then we selectively enable only those bits that
  3324. * we want to set.
  3325. */
  3326. val64 |= (SWAPPER_CTRL_TXP_FE |
  3327. SWAPPER_CTRL_TXP_SE |
  3328. SWAPPER_CTRL_TXD_R_FE |
  3329. SWAPPER_CTRL_TXD_R_SE |
  3330. SWAPPER_CTRL_TXD_W_FE |
  3331. SWAPPER_CTRL_TXD_W_SE |
  3332. SWAPPER_CTRL_TXF_R_FE |
  3333. SWAPPER_CTRL_RXD_R_FE |
  3334. SWAPPER_CTRL_RXD_R_SE |
  3335. SWAPPER_CTRL_RXD_W_FE |
  3336. SWAPPER_CTRL_RXD_W_SE |
  3337. SWAPPER_CTRL_RXF_W_FE |
  3338. SWAPPER_CTRL_XMSI_FE |
  3339. SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
  3340. if (sp->config.intr_type == INTA)
  3341. val64 |= SWAPPER_CTRL_XMSI_SE;
  3342. writeq(val64, &bar0->swapper_ctrl);
  3343. #endif
  3344. val64 = readq(&bar0->swapper_ctrl);
  3345. /*
  3346. * Verifying if endian settings are accurate by reading a
  3347. * feedback register.
  3348. */
  3349. val64 = readq(&bar0->pif_rd_swapper_fb);
  3350. if (val64 != 0x0123456789ABCDEFULL) {
  3351. /* Endian settings are incorrect, calls for another dekko. */
  3352. DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
  3353. dev->name);
  3354. DBG_PRINT(ERR_DBG, "feedback read %llx\n",
  3355. (unsigned long long) val64);
  3356. return FAILURE;
  3357. }
  3358. return SUCCESS;
  3359. }
  3360. static int wait_for_msix_trans(struct s2io_nic *nic, int i)
  3361. {
  3362. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  3363. u64 val64;
  3364. int ret = 0, cnt = 0;
  3365. do {
  3366. val64 = readq(&bar0->xmsi_access);
  3367. if (!(val64 & s2BIT(15)))
  3368. break;
  3369. mdelay(1);
  3370. cnt++;
  3371. } while(cnt < 5);
  3372. if (cnt == 5) {
  3373. DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
  3374. ret = 1;
  3375. }
  3376. return ret;
  3377. }
  3378. static void restore_xmsi_data(struct s2io_nic *nic)
  3379. {
  3380. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  3381. u64 val64;
  3382. int i, msix_index;
  3383. if (nic->device_type == XFRAME_I_DEVICE)
  3384. return;
  3385. for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
  3386. msix_index = (i) ? ((i-1) * 8 + 1): 0;
  3387. writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
  3388. writeq(nic->msix_info[i].data, &bar0->xmsi_data);
  3389. val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
  3390. writeq(val64, &bar0->xmsi_access);
  3391. if (wait_for_msix_trans(nic, msix_index)) {
  3392. DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
  3393. continue;
  3394. }
  3395. }
  3396. }
  3397. static void store_xmsi_data(struct s2io_nic *nic)
  3398. {
  3399. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  3400. u64 val64, addr, data;
  3401. int i, msix_index;
  3402. if (nic->device_type == XFRAME_I_DEVICE)
  3403. return;
  3404. /* Store and display */
  3405. for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
  3406. msix_index = (i) ? ((i-1) * 8 + 1): 0;
  3407. val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
  3408. writeq(val64, &bar0->xmsi_access);
  3409. if (wait_for_msix_trans(nic, msix_index)) {
  3410. DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
  3411. continue;
  3412. }
  3413. addr = readq(&bar0->xmsi_address);
  3414. data = readq(&bar0->xmsi_data);
  3415. if (addr && data) {
  3416. nic->msix_info[i].addr = addr;
  3417. nic->msix_info[i].data = data;
  3418. }
  3419. }
  3420. }
  3421. static int s2io_enable_msi_x(struct s2io_nic *nic)
  3422. {
  3423. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  3424. u64 rx_mat;
  3425. u16 msi_control; /* Temp variable */
  3426. int ret, i, j, msix_indx = 1;
  3427. nic->entries = kmalloc(nic->num_entries * sizeof(struct msix_entry),
  3428. GFP_KERNEL);
  3429. if (!nic->entries) {
  3430. DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
  3431. __FUNCTION__);
  3432. nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
  3433. return -ENOMEM;
  3434. }
  3435. nic->mac_control.stats_info->sw_stat.mem_allocated
  3436. += (nic->num_entries * sizeof(struct msix_entry));
  3437. memset(nic->entries, 0, nic->num_entries * sizeof(struct msix_entry));
  3438. nic->s2io_entries =
  3439. kmalloc(nic->num_entries * sizeof(struct s2io_msix_entry),
  3440. GFP_KERNEL);
  3441. if (!nic->s2io_entries) {
  3442. DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
  3443. __FUNCTION__);
  3444. nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
  3445. kfree(nic->entries);
  3446. nic->mac_control.stats_info->sw_stat.mem_freed
  3447. += (nic->num_entries * sizeof(struct msix_entry));
  3448. return -ENOMEM;
  3449. }
  3450. nic->mac_control.stats_info->sw_stat.mem_allocated
  3451. += (nic->num_entries * sizeof(struct s2io_msix_entry));
  3452. memset(nic->s2io_entries, 0,
  3453. nic->num_entries * sizeof(struct s2io_msix_entry));
  3454. nic->entries[0].entry = 0;
  3455. nic->s2io_entries[0].entry = 0;
  3456. nic->s2io_entries[0].in_use = MSIX_FLG;
  3457. nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
  3458. nic->s2io_entries[0].arg = &nic->mac_control.fifos;
  3459. for (i = 1; i < nic->num_entries; i++) {
  3460. nic->entries[i].entry = ((i - 1) * 8) + 1;
  3461. nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
  3462. nic->s2io_entries[i].arg = NULL;
  3463. nic->s2io_entries[i].in_use = 0;
  3464. }
  3465. rx_mat = readq(&bar0->rx_mat);
  3466. for (j = 0; j < nic->config.rx_ring_num; j++) {
  3467. rx_mat |= RX_MAT_SET(j, msix_indx);
  3468. nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
  3469. nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
  3470. nic->s2io_entries[j+1].in_use = MSIX_FLG;
  3471. msix_indx += 8;
  3472. }
  3473. writeq(rx_mat, &bar0->rx_mat);
  3474. readq(&bar0->rx_mat);
  3475. ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
  3476. /* We fail init if error or we get less vectors than min required */
  3477. if (ret) {
  3478. DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
  3479. kfree(nic->entries);
  3480. nic->mac_control.stats_info->sw_stat.mem_freed
  3481. += (nic->num_entries * sizeof(struct msix_entry));
  3482. kfree(nic->s2io_entries);
  3483. nic->mac_control.stats_info->sw_stat.mem_freed
  3484. += (nic->num_entries * sizeof(struct s2io_msix_entry));
  3485. nic->entries = NULL;
  3486. nic->s2io_entries = NULL;
  3487. return -ENOMEM;
  3488. }
  3489. /*
  3490. * To enable MSI-X, MSI also needs to be enabled, due to a bug
  3491. * in the herc NIC. (Temp change, needs to be removed later)
  3492. */
  3493. pci_read_config_word(nic->pdev, 0x42, &msi_control);
  3494. msi_control |= 0x1; /* Enable MSI */
  3495. pci_write_config_word(nic->pdev, 0x42, msi_control);
  3496. return 0;
  3497. }
  3498. /* Handle software interrupt used during MSI(X) test */
  3499. static irqreturn_t s2io_test_intr(int irq, void *dev_id)
  3500. {
  3501. struct s2io_nic *sp = dev_id;
  3502. sp->msi_detected = 1;
  3503. wake_up(&sp->msi_wait);
  3504. return IRQ_HANDLED;
  3505. }
  3506. /* Test interrupt path by forcing a a software IRQ */
  3507. static int s2io_test_msi(struct s2io_nic *sp)
  3508. {
  3509. struct pci_dev *pdev = sp->pdev;
  3510. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3511. int err;
  3512. u64 val64, saved64;
  3513. err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
  3514. sp->name, sp);
  3515. if (err) {
  3516. DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
  3517. sp->dev->name, pci_name(pdev), pdev->irq);
  3518. return err;
  3519. }
  3520. init_waitqueue_head (&sp->msi_wait);
  3521. sp->msi_detected = 0;
  3522. saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
  3523. val64 |= SCHED_INT_CTRL_ONE_SHOT;
  3524. val64 |= SCHED_INT_CTRL_TIMER_EN;
  3525. val64 |= SCHED_INT_CTRL_INT2MSI(1);
  3526. writeq(val64, &bar0->scheduled_int_ctrl);
  3527. wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
  3528. if (!sp->msi_detected) {
  3529. /* MSI(X) test failed, go back to INTx mode */
  3530. DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
  3531. "using MSI(X) during test\n", sp->dev->name,
  3532. pci_name(pdev));
  3533. err = -EOPNOTSUPP;
  3534. }
  3535. free_irq(sp->entries[1].vector, sp);
  3536. writeq(saved64, &bar0->scheduled_int_ctrl);
  3537. return err;
  3538. }
  3539. static void remove_msix_isr(struct s2io_nic *sp)
  3540. {
  3541. int i;
  3542. u16 msi_control;
  3543. for (i = 0; i < sp->num_entries; i++) {
  3544. if (sp->s2io_entries[i].in_use ==
  3545. MSIX_REGISTERED_SUCCESS) {
  3546. int vector = sp->entries[i].vector;
  3547. void *arg = sp->s2io_entries[i].arg;
  3548. free_irq(vector, arg);
  3549. }
  3550. }
  3551. kfree(sp->entries);
  3552. kfree(sp->s2io_entries);
  3553. sp->entries = NULL;
  3554. sp->s2io_entries = NULL;
  3555. pci_read_config_word(sp->pdev, 0x42, &msi_control);
  3556. msi_control &= 0xFFFE; /* Disable MSI */
  3557. pci_write_config_word(sp->pdev, 0x42, msi_control);
  3558. pci_disable_msix(sp->pdev);
  3559. }
  3560. static void remove_inta_isr(struct s2io_nic *sp)
  3561. {
  3562. struct net_device *dev = sp->dev;
  3563. free_irq(sp->pdev->irq, dev);
  3564. }
  3565. /* ********************************************************* *
  3566. * Functions defined below concern the OS part of the driver *
  3567. * ********************************************************* */
  3568. /**
  3569. * s2io_open - open entry point of the driver
  3570. * @dev : pointer to the device structure.
  3571. * Description:
  3572. * This function is the open entry point of the driver. It mainly calls a
  3573. * function to allocate Rx buffers and inserts them into the buffer
  3574. * descriptors and then enables the Rx part of the NIC.
  3575. * Return value:
  3576. * 0 on success and an appropriate (-)ve integer as defined in errno.h
  3577. * file on failure.
  3578. */
  3579. static int s2io_open(struct net_device *dev)
  3580. {
  3581. struct s2io_nic *sp = dev->priv;
  3582. int err = 0;
  3583. /*
  3584. * Make sure you have link off by default every time
  3585. * Nic is initialized
  3586. */
  3587. netif_carrier_off(dev);
  3588. sp->last_link_state = 0;
  3589. /* Initialize H/W and enable interrupts */
  3590. err = s2io_card_up(sp);
  3591. if (err) {
  3592. DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
  3593. dev->name);
  3594. goto hw_init_failed;
  3595. }
  3596. if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
  3597. DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
  3598. s2io_card_down(sp);
  3599. err = -ENODEV;
  3600. goto hw_init_failed;
  3601. }
  3602. s2io_start_all_tx_queue(sp);
  3603. return 0;
  3604. hw_init_failed:
  3605. if (sp->config.intr_type == MSI_X) {
  3606. if (sp->entries) {
  3607. kfree(sp->entries);
  3608. sp->mac_control.stats_info->sw_stat.mem_freed
  3609. += (sp->num_entries * sizeof(struct msix_entry));
  3610. }
  3611. if (sp->s2io_entries) {
  3612. kfree(sp->s2io_entries);
  3613. sp->mac_control.stats_info->sw_stat.mem_freed
  3614. += (sp->num_entries * sizeof(struct s2io_msix_entry));
  3615. }
  3616. }
  3617. return err;
  3618. }
  3619. /**
  3620. * s2io_close -close entry point of the driver
  3621. * @dev : device pointer.
  3622. * Description:
  3623. * This is the stop entry point of the driver. It needs to undo exactly
  3624. * whatever was done by the open entry point,thus it's usually referred to
  3625. * as the close function.Among other things this function mainly stops the
  3626. * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
  3627. * Return value:
  3628. * 0 on success and an appropriate (-)ve integer as defined in errno.h
  3629. * file on failure.
  3630. */
  3631. static int s2io_close(struct net_device *dev)
  3632. {
  3633. struct s2io_nic *sp = dev->priv;
  3634. struct config_param *config = &sp->config;
  3635. u64 tmp64;
  3636. int offset;
  3637. /* Return if the device is already closed *
  3638. * Can happen when s2io_card_up failed in change_mtu *
  3639. */
  3640. if (!is_s2io_card_up(sp))
  3641. return 0;
  3642. s2io_stop_all_tx_queue(sp);
  3643. /* delete all populated mac entries */
  3644. for (offset = 1; offset < config->max_mc_addr; offset++) {
  3645. tmp64 = do_s2io_read_unicast_mc(sp, offset);
  3646. if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
  3647. do_s2io_delete_unicast_mc(sp, tmp64);
  3648. }
  3649. s2io_card_down(sp);
  3650. return 0;
  3651. }
  3652. /**
  3653. * s2io_xmit - Tx entry point of te driver
  3654. * @skb : the socket buffer containing the Tx data.
  3655. * @dev : device pointer.
  3656. * Description :
  3657. * This function is the Tx entry point of the driver. S2IO NIC supports
  3658. * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
  3659. * NOTE: when device cant queue the pkt,just the trans_start variable will
  3660. * not be upadted.
  3661. * Return value:
  3662. * 0 on success & 1 on failure.
  3663. */
  3664. static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
  3665. {
  3666. struct s2io_nic *sp = dev->priv;
  3667. u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
  3668. register u64 val64;
  3669. struct TxD *txdp;
  3670. struct TxFIFO_element __iomem *tx_fifo;
  3671. unsigned long flags = 0;
  3672. u16 vlan_tag = 0;
  3673. struct fifo_info *fifo = NULL;
  3674. struct mac_info *mac_control;
  3675. struct config_param *config;
  3676. int do_spin_lock = 1;
  3677. int offload_type;
  3678. int enable_per_list_interrupt = 0;
  3679. struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
  3680. mac_control = &sp->mac_control;
  3681. config = &sp->config;
  3682. DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
  3683. if (unlikely(skb->len <= 0)) {
  3684. DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
  3685. dev_kfree_skb_any(skb);
  3686. return 0;
  3687. }
  3688. if (!is_s2io_card_up(sp)) {
  3689. DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
  3690. dev->name);
  3691. dev_kfree_skb(skb);
  3692. return 0;
  3693. }
  3694. queue = 0;
  3695. if (sp->vlgrp && vlan_tx_tag_present(skb))
  3696. vlan_tag = vlan_tx_tag_get(skb);
  3697. if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
  3698. if (skb->protocol == htons(ETH_P_IP)) {
  3699. struct iphdr *ip;
  3700. struct tcphdr *th;
  3701. ip = ip_hdr(skb);
  3702. if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
  3703. th = (struct tcphdr *)(((unsigned char *)ip) +
  3704. ip->ihl*4);
  3705. if (ip->protocol == IPPROTO_TCP) {
  3706. queue_len = sp->total_tcp_fifos;
  3707. queue = (ntohs(th->source) +
  3708. ntohs(th->dest)) &
  3709. sp->fifo_selector[queue_len - 1];
  3710. if (queue >= queue_len)
  3711. queue = queue_len - 1;
  3712. } else if (ip->protocol == IPPROTO_UDP) {
  3713. queue_len = sp->total_udp_fifos;
  3714. queue = (ntohs(th->source) +
  3715. ntohs(th->dest)) &
  3716. sp->fifo_selector[queue_len - 1];
  3717. if (queue >= queue_len)
  3718. queue = queue_len - 1;
  3719. queue += sp->udp_fifo_idx;
  3720. if (skb->len > 1024)
  3721. enable_per_list_interrupt = 1;
  3722. do_spin_lock = 0;
  3723. }
  3724. }
  3725. }
  3726. } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
  3727. /* get fifo number based on skb->priority value */
  3728. queue = config->fifo_mapping
  3729. [skb->priority & (MAX_TX_FIFOS - 1)];
  3730. fifo = &mac_control->fifos[queue];
  3731. if (do_spin_lock)
  3732. spin_lock_irqsave(&fifo->tx_lock, flags);
  3733. else {
  3734. if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
  3735. return NETDEV_TX_LOCKED;
  3736. }
  3737. if (sp->config.multiq) {
  3738. if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
  3739. spin_unlock_irqrestore(&fifo->tx_lock, flags);
  3740. return NETDEV_TX_BUSY;
  3741. }
  3742. } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
  3743. if (netif_queue_stopped(dev)) {
  3744. spin_unlock_irqrestore(&fifo->tx_lock, flags);
  3745. return NETDEV_TX_BUSY;
  3746. }
  3747. }
  3748. put_off = (u16) fifo->tx_curr_put_info.offset;
  3749. get_off = (u16) fifo->tx_curr_get_info.offset;
  3750. txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
  3751. queue_len = fifo->tx_curr_put_info.fifo_len + 1;
  3752. /* Avoid "put" pointer going beyond "get" pointer */
  3753. if (txdp->Host_Control ||
  3754. ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
  3755. DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
  3756. s2io_stop_tx_queue(sp, fifo->fifo_no);
  3757. dev_kfree_skb(skb);
  3758. spin_unlock_irqrestore(&fifo->tx_lock, flags);
  3759. return 0;
  3760. }
  3761. offload_type = s2io_offload_type(skb);
  3762. if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
  3763. txdp->Control_1 |= TXD_TCP_LSO_EN;
  3764. txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
  3765. }
  3766. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  3767. txdp->Control_2 |=
  3768. (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
  3769. TXD_TX_CKO_UDP_EN);
  3770. }
  3771. txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
  3772. txdp->Control_1 |= TXD_LIST_OWN_XENA;
  3773. txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
  3774. if (enable_per_list_interrupt)
  3775. if (put_off & (queue_len >> 5))
  3776. txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
  3777. if (vlan_tag) {
  3778. txdp->Control_2 |= TXD_VLAN_ENABLE;
  3779. txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
  3780. }
  3781. frg_len = skb->len - skb->data_len;
  3782. if (offload_type == SKB_GSO_UDP) {
  3783. int ufo_size;
  3784. ufo_size = s2io_udp_mss(skb);
  3785. ufo_size &= ~7;
  3786. txdp->Control_1 |= TXD_UFO_EN;
  3787. txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
  3788. txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
  3789. #ifdef __BIG_ENDIAN
  3790. /* both variants do cpu_to_be64(be32_to_cpu(...)) */
  3791. fifo->ufo_in_band_v[put_off] =
  3792. (__force u64)skb_shinfo(skb)->ip6_frag_id;
  3793. #else
  3794. fifo->ufo_in_band_v[put_off] =
  3795. (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
  3796. #endif
  3797. txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
  3798. txdp->Buffer_Pointer = pci_map_single(sp->pdev,
  3799. fifo->ufo_in_band_v,
  3800. sizeof(u64), PCI_DMA_TODEVICE);
  3801. if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
  3802. goto pci_map_failed;
  3803. txdp++;
  3804. }
  3805. txdp->Buffer_Pointer = pci_map_single
  3806. (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
  3807. if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
  3808. goto pci_map_failed;
  3809. txdp->Host_Control = (unsigned long) skb;
  3810. txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
  3811. if (offload_type == SKB_GSO_UDP)
  3812. txdp->Control_1 |= TXD_UFO_EN;
  3813. frg_cnt = skb_shinfo(skb)->nr_frags;
  3814. /* For fragmented SKB. */
  3815. for (i = 0; i < frg_cnt; i++) {
  3816. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3817. /* A '0' length fragment will be ignored */
  3818. if (!frag->size)
  3819. continue;
  3820. txdp++;
  3821. txdp->Buffer_Pointer = (u64) pci_map_page
  3822. (sp->pdev, frag->page, frag->page_offset,
  3823. frag->size, PCI_DMA_TODEVICE);
  3824. txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
  3825. if (offload_type == SKB_GSO_UDP)
  3826. txdp->Control_1 |= TXD_UFO_EN;
  3827. }
  3828. txdp->Control_1 |= TXD_GATHER_CODE_LAST;
  3829. if (offload_type == SKB_GSO_UDP)
  3830. frg_cnt++; /* as Txd0 was used for inband header */
  3831. tx_fifo = mac_control->tx_FIFO_start[queue];
  3832. val64 = fifo->list_info[put_off].list_phy_addr;
  3833. writeq(val64, &tx_fifo->TxDL_Pointer);
  3834. val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
  3835. TX_FIFO_LAST_LIST);
  3836. if (offload_type)
  3837. val64 |= TX_FIFO_SPECIAL_FUNC;
  3838. writeq(val64, &tx_fifo->List_Control);
  3839. mmiowb();
  3840. put_off++;
  3841. if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
  3842. put_off = 0;
  3843. fifo->tx_curr_put_info.offset = put_off;
  3844. /* Avoid "put" pointer going beyond "get" pointer */
  3845. if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
  3846. sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
  3847. DBG_PRINT(TX_DBG,
  3848. "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
  3849. put_off, get_off);
  3850. s2io_stop_tx_queue(sp, fifo->fifo_no);
  3851. }
  3852. mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
  3853. dev->trans_start = jiffies;
  3854. spin_unlock_irqrestore(&fifo->tx_lock, flags);
  3855. if (sp->config.intr_type == MSI_X)
  3856. tx_intr_handler(fifo);
  3857. return 0;
  3858. pci_map_failed:
  3859. stats->pci_map_fail_cnt++;
  3860. s2io_stop_tx_queue(sp, fifo->fifo_no);
  3861. stats->mem_freed += skb->truesize;
  3862. dev_kfree_skb(skb);
  3863. spin_unlock_irqrestore(&fifo->tx_lock, flags);
  3864. return 0;
  3865. }
  3866. static void
  3867. s2io_alarm_handle(unsigned long data)
  3868. {
  3869. struct s2io_nic *sp = (struct s2io_nic *)data;
  3870. struct net_device *dev = sp->dev;
  3871. s2io_handle_errors(dev);
  3872. mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
  3873. }
  3874. static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
  3875. {
  3876. struct ring_info *ring = (struct ring_info *)dev_id;
  3877. struct s2io_nic *sp = ring->nic;
  3878. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3879. struct net_device *dev = sp->dev;
  3880. if (unlikely(!is_s2io_card_up(sp)))
  3881. return IRQ_HANDLED;
  3882. if (sp->config.napi) {
  3883. u8 __iomem *addr = NULL;
  3884. u8 val8 = 0;
  3885. addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
  3886. addr += (7 - ring->ring_no);
  3887. val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
  3888. writeb(val8, addr);
  3889. val8 = readb(addr);
  3890. netif_rx_schedule(dev, &ring->napi);
  3891. } else {
  3892. rx_intr_handler(ring, 0);
  3893. s2io_chk_rx_buffers(sp, ring);
  3894. }
  3895. return IRQ_HANDLED;
  3896. }
  3897. static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
  3898. {
  3899. int i;
  3900. struct fifo_info *fifos = (struct fifo_info *)dev_id;
  3901. struct s2io_nic *sp = fifos->nic;
  3902. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3903. struct config_param *config = &sp->config;
  3904. u64 reason;
  3905. if (unlikely(!is_s2io_card_up(sp)))
  3906. return IRQ_NONE;
  3907. reason = readq(&bar0->general_int_status);
  3908. if (unlikely(reason == S2IO_MINUS_ONE))
  3909. /* Nothing much can be done. Get out */
  3910. return IRQ_HANDLED;
  3911. if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
  3912. writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
  3913. if (reason & GEN_INTR_TXPIC)
  3914. s2io_txpic_intr_handle(sp);
  3915. if (reason & GEN_INTR_TXTRAFFIC)
  3916. writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
  3917. for (i = 0; i < config->tx_fifo_num; i++)
  3918. tx_intr_handler(&fifos[i]);
  3919. writeq(sp->general_int_mask, &bar0->general_int_mask);
  3920. readl(&bar0->general_int_status);
  3921. return IRQ_HANDLED;
  3922. }
  3923. /* The interrupt was not raised by us */
  3924. return IRQ_NONE;
  3925. }
  3926. static void s2io_txpic_intr_handle(struct s2io_nic *sp)
  3927. {
  3928. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3929. u64 val64;
  3930. val64 = readq(&bar0->pic_int_status);
  3931. if (val64 & PIC_INT_GPIO) {
  3932. val64 = readq(&bar0->gpio_int_reg);
  3933. if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
  3934. (val64 & GPIO_INT_REG_LINK_UP)) {
  3935. /*
  3936. * This is unstable state so clear both up/down
  3937. * interrupt and adapter to re-evaluate the link state.
  3938. */
  3939. val64 |= GPIO_INT_REG_LINK_DOWN;
  3940. val64 |= GPIO_INT_REG_LINK_UP;
  3941. writeq(val64, &bar0->gpio_int_reg);
  3942. val64 = readq(&bar0->gpio_int_mask);
  3943. val64 &= ~(GPIO_INT_MASK_LINK_UP |
  3944. GPIO_INT_MASK_LINK_DOWN);
  3945. writeq(val64, &bar0->gpio_int_mask);
  3946. }
  3947. else if (val64 & GPIO_INT_REG_LINK_UP) {
  3948. val64 = readq(&bar0->adapter_status);
  3949. /* Enable Adapter */
  3950. val64 = readq(&bar0->adapter_control);
  3951. val64 |= ADAPTER_CNTL_EN;
  3952. writeq(val64, &bar0->adapter_control);
  3953. val64 |= ADAPTER_LED_ON;
  3954. writeq(val64, &bar0->adapter_control);
  3955. if (!sp->device_enabled_once)
  3956. sp->device_enabled_once = 1;
  3957. s2io_link(sp, LINK_UP);
  3958. /*
  3959. * unmask link down interrupt and mask link-up
  3960. * intr
  3961. */
  3962. val64 = readq(&bar0->gpio_int_mask);
  3963. val64 &= ~GPIO_INT_MASK_LINK_DOWN;
  3964. val64 |= GPIO_INT_MASK_LINK_UP;
  3965. writeq(val64, &bar0->gpio_int_mask);
  3966. }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
  3967. val64 = readq(&bar0->adapter_status);
  3968. s2io_link(sp, LINK_DOWN);
  3969. /* Link is down so unmaks link up interrupt */
  3970. val64 = readq(&bar0->gpio_int_mask);
  3971. val64 &= ~GPIO_INT_MASK_LINK_UP;
  3972. val64 |= GPIO_INT_MASK_LINK_DOWN;
  3973. writeq(val64, &bar0->gpio_int_mask);
  3974. /* turn off LED */
  3975. val64 = readq(&bar0->adapter_control);
  3976. val64 = val64 &(~ADAPTER_LED_ON);
  3977. writeq(val64, &bar0->adapter_control);
  3978. }
  3979. }
  3980. val64 = readq(&bar0->gpio_int_mask);
  3981. }
  3982. /**
  3983. * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
  3984. * @value: alarm bits
  3985. * @addr: address value
  3986. * @cnt: counter variable
  3987. * Description: Check for alarm and increment the counter
  3988. * Return Value:
  3989. * 1 - if alarm bit set
  3990. * 0 - if alarm bit is not set
  3991. */
  3992. static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
  3993. unsigned long long *cnt)
  3994. {
  3995. u64 val64;
  3996. val64 = readq(addr);
  3997. if ( val64 & value ) {
  3998. writeq(val64, addr);
  3999. (*cnt)++;
  4000. return 1;
  4001. }
  4002. return 0;
  4003. }
  4004. /**
  4005. * s2io_handle_errors - Xframe error indication handler
  4006. * @nic: device private variable
  4007. * Description: Handle alarms such as loss of link, single or
  4008. * double ECC errors, critical and serious errors.
  4009. * Return Value:
  4010. * NONE
  4011. */
  4012. static void s2io_handle_errors(void * dev_id)
  4013. {
  4014. struct net_device *dev = (struct net_device *) dev_id;
  4015. struct s2io_nic *sp = dev->priv;
  4016. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4017. u64 temp64 = 0,val64=0;
  4018. int i = 0;
  4019. struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
  4020. struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
  4021. if (!is_s2io_card_up(sp))
  4022. return;
  4023. if (pci_channel_offline(sp->pdev))
  4024. return;
  4025. memset(&sw_stat->ring_full_cnt, 0,
  4026. sizeof(sw_stat->ring_full_cnt));
  4027. /* Handling the XPAK counters update */
  4028. if(stats->xpak_timer_count < 72000) {
  4029. /* waiting for an hour */
  4030. stats->xpak_timer_count++;
  4031. } else {
  4032. s2io_updt_xpak_counter(dev);
  4033. /* reset the count to zero */
  4034. stats->xpak_timer_count = 0;
  4035. }
  4036. /* Handling link status change error Intr */
  4037. if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
  4038. val64 = readq(&bar0->mac_rmac_err_reg);
  4039. writeq(val64, &bar0->mac_rmac_err_reg);
  4040. if (val64 & RMAC_LINK_STATE_CHANGE_INT)
  4041. schedule_work(&sp->set_link_task);
  4042. }
  4043. /* In case of a serious error, the device will be Reset. */
  4044. if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
  4045. &sw_stat->serious_err_cnt))
  4046. goto reset;
  4047. /* Check for data parity error */
  4048. if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
  4049. &sw_stat->parity_err_cnt))
  4050. goto reset;
  4051. /* Check for ring full counter */
  4052. if (sp->device_type == XFRAME_II_DEVICE) {
  4053. val64 = readq(&bar0->ring_bump_counter1);
  4054. for (i=0; i<4; i++) {
  4055. temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
  4056. temp64 >>= 64 - ((i+1)*16);
  4057. sw_stat->ring_full_cnt[i] += temp64;
  4058. }
  4059. val64 = readq(&bar0->ring_bump_counter2);
  4060. for (i=0; i<4; i++) {
  4061. temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
  4062. temp64 >>= 64 - ((i+1)*16);
  4063. sw_stat->ring_full_cnt[i+4] += temp64;
  4064. }
  4065. }
  4066. val64 = readq(&bar0->txdma_int_status);
  4067. /*check for pfc_err*/
  4068. if (val64 & TXDMA_PFC_INT) {
  4069. if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
  4070. PFC_MISC_0_ERR | PFC_MISC_1_ERR|
  4071. PFC_PCIX_ERR, &bar0->pfc_err_reg,
  4072. &sw_stat->pfc_err_cnt))
  4073. goto reset;
  4074. do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
  4075. &sw_stat->pfc_err_cnt);
  4076. }
  4077. /*check for tda_err*/
  4078. if (val64 & TXDMA_TDA_INT) {
  4079. if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
  4080. TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
  4081. &sw_stat->tda_err_cnt))
  4082. goto reset;
  4083. do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
  4084. &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
  4085. }
  4086. /*check for pcc_err*/
  4087. if (val64 & TXDMA_PCC_INT) {
  4088. if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
  4089. | PCC_N_SERR | PCC_6_COF_OV_ERR
  4090. | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
  4091. | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
  4092. | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
  4093. &sw_stat->pcc_err_cnt))
  4094. goto reset;
  4095. do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
  4096. &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
  4097. }
  4098. /*check for tti_err*/
  4099. if (val64 & TXDMA_TTI_INT) {
  4100. if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
  4101. &sw_stat->tti_err_cnt))
  4102. goto reset;
  4103. do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
  4104. &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
  4105. }
  4106. /*check for lso_err*/
  4107. if (val64 & TXDMA_LSO_INT) {
  4108. if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
  4109. | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
  4110. &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
  4111. goto reset;
  4112. do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
  4113. &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
  4114. }
  4115. /*check for tpa_err*/
  4116. if (val64 & TXDMA_TPA_INT) {
  4117. if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
  4118. &sw_stat->tpa_err_cnt))
  4119. goto reset;
  4120. do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
  4121. &sw_stat->tpa_err_cnt);
  4122. }
  4123. /*check for sm_err*/
  4124. if (val64 & TXDMA_SM_INT) {
  4125. if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
  4126. &sw_stat->sm_err_cnt))
  4127. goto reset;
  4128. }
  4129. val64 = readq(&bar0->mac_int_status);
  4130. if (val64 & MAC_INT_STATUS_TMAC_INT) {
  4131. if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
  4132. &bar0->mac_tmac_err_reg,
  4133. &sw_stat->mac_tmac_err_cnt))
  4134. goto reset;
  4135. do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
  4136. | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
  4137. &bar0->mac_tmac_err_reg,
  4138. &sw_stat->mac_tmac_err_cnt);
  4139. }
  4140. val64 = readq(&bar0->xgxs_int_status);
  4141. if (val64 & XGXS_INT_STATUS_TXGXS) {
  4142. if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
  4143. &bar0->xgxs_txgxs_err_reg,
  4144. &sw_stat->xgxs_txgxs_err_cnt))
  4145. goto reset;
  4146. do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
  4147. &bar0->xgxs_txgxs_err_reg,
  4148. &sw_stat->xgxs_txgxs_err_cnt);
  4149. }
  4150. val64 = readq(&bar0->rxdma_int_status);
  4151. if (val64 & RXDMA_INT_RC_INT_M) {
  4152. if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
  4153. | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
  4154. &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
  4155. goto reset;
  4156. do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
  4157. | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
  4158. &sw_stat->rc_err_cnt);
  4159. if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
  4160. | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
  4161. &sw_stat->prc_pcix_err_cnt))
  4162. goto reset;
  4163. do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
  4164. | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
  4165. &sw_stat->prc_pcix_err_cnt);
  4166. }
  4167. if (val64 & RXDMA_INT_RPA_INT_M) {
  4168. if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
  4169. &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
  4170. goto reset;
  4171. do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
  4172. &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
  4173. }
  4174. if (val64 & RXDMA_INT_RDA_INT_M) {
  4175. if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
  4176. | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
  4177. | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
  4178. &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
  4179. goto reset;
  4180. do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
  4181. | RDA_MISC_ERR | RDA_PCIX_ERR,
  4182. &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
  4183. }
  4184. if (val64 & RXDMA_INT_RTI_INT_M) {
  4185. if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
  4186. &sw_stat->rti_err_cnt))
  4187. goto reset;
  4188. do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
  4189. &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
  4190. }
  4191. val64 = readq(&bar0->mac_int_status);
  4192. if (val64 & MAC_INT_STATUS_RMAC_INT) {
  4193. if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
  4194. &bar0->mac_rmac_err_reg,
  4195. &sw_stat->mac_rmac_err_cnt))
  4196. goto reset;
  4197. do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
  4198. RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
  4199. &sw_stat->mac_rmac_err_cnt);
  4200. }
  4201. val64 = readq(&bar0->xgxs_int_status);
  4202. if (val64 & XGXS_INT_STATUS_RXGXS) {
  4203. if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
  4204. &bar0->xgxs_rxgxs_err_reg,
  4205. &sw_stat->xgxs_rxgxs_err_cnt))
  4206. goto reset;
  4207. }
  4208. val64 = readq(&bar0->mc_int_status);
  4209. if(val64 & MC_INT_STATUS_MC_INT) {
  4210. if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
  4211. &sw_stat->mc_err_cnt))
  4212. goto reset;
  4213. /* Handling Ecc errors */
  4214. if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
  4215. writeq(val64, &bar0->mc_err_reg);
  4216. if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
  4217. sw_stat->double_ecc_errs++;
  4218. if (sp->device_type != XFRAME_II_DEVICE) {
  4219. /*
  4220. * Reset XframeI only if critical error
  4221. */
  4222. if (val64 &
  4223. (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
  4224. MC_ERR_REG_MIRI_ECC_DB_ERR_1))
  4225. goto reset;
  4226. }
  4227. } else
  4228. sw_stat->single_ecc_errs++;
  4229. }
  4230. }
  4231. return;
  4232. reset:
  4233. s2io_stop_all_tx_queue(sp);
  4234. schedule_work(&sp->rst_timer_task);
  4235. sw_stat->soft_reset_cnt++;
  4236. return;
  4237. }
  4238. /**
  4239. * s2io_isr - ISR handler of the device .
  4240. * @irq: the irq of the device.
  4241. * @dev_id: a void pointer to the dev structure of the NIC.
  4242. * Description: This function is the ISR handler of the device. It
  4243. * identifies the reason for the interrupt and calls the relevant
  4244. * service routines. As a contongency measure, this ISR allocates the
  4245. * recv buffers, if their numbers are below the panic value which is
  4246. * presently set to 25% of the original number of rcv buffers allocated.
  4247. * Return value:
  4248. * IRQ_HANDLED: will be returned if IRQ was handled by this routine
  4249. * IRQ_NONE: will be returned if interrupt is not from our device
  4250. */
  4251. static irqreturn_t s2io_isr(int irq, void *dev_id)
  4252. {
  4253. struct net_device *dev = (struct net_device *) dev_id;
  4254. struct s2io_nic *sp = dev->priv;
  4255. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4256. int i;
  4257. u64 reason = 0;
  4258. struct mac_info *mac_control;
  4259. struct config_param *config;
  4260. /* Pretend we handled any irq's from a disconnected card */
  4261. if (pci_channel_offline(sp->pdev))
  4262. return IRQ_NONE;
  4263. if (!is_s2io_card_up(sp))
  4264. return IRQ_NONE;
  4265. mac_control = &sp->mac_control;
  4266. config = &sp->config;
  4267. /*
  4268. * Identify the cause for interrupt and call the appropriate
  4269. * interrupt handler. Causes for the interrupt could be;
  4270. * 1. Rx of packet.
  4271. * 2. Tx complete.
  4272. * 3. Link down.
  4273. */
  4274. reason = readq(&bar0->general_int_status);
  4275. if (unlikely(reason == S2IO_MINUS_ONE) ) {
  4276. /* Nothing much can be done. Get out */
  4277. return IRQ_HANDLED;
  4278. }
  4279. if (reason & (GEN_INTR_RXTRAFFIC |
  4280. GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
  4281. {
  4282. writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
  4283. if (config->napi) {
  4284. if (reason & GEN_INTR_RXTRAFFIC) {
  4285. netif_rx_schedule(dev, &sp->napi);
  4286. writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
  4287. writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
  4288. readl(&bar0->rx_traffic_int);
  4289. }
  4290. } else {
  4291. /*
  4292. * rx_traffic_int reg is an R1 register, writing all 1's
  4293. * will ensure that the actual interrupt causing bit
  4294. * get's cleared and hence a read can be avoided.
  4295. */
  4296. if (reason & GEN_INTR_RXTRAFFIC)
  4297. writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
  4298. for (i = 0; i < config->rx_ring_num; i++)
  4299. rx_intr_handler(&mac_control->rings[i], 0);
  4300. }
  4301. /*
  4302. * tx_traffic_int reg is an R1 register, writing all 1's
  4303. * will ensure that the actual interrupt causing bit get's
  4304. * cleared and hence a read can be avoided.
  4305. */
  4306. if (reason & GEN_INTR_TXTRAFFIC)
  4307. writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
  4308. for (i = 0; i < config->tx_fifo_num; i++)
  4309. tx_intr_handler(&mac_control->fifos[i]);
  4310. if (reason & GEN_INTR_TXPIC)
  4311. s2io_txpic_intr_handle(sp);
  4312. /*
  4313. * Reallocate the buffers from the interrupt handler itself.
  4314. */
  4315. if (!config->napi) {
  4316. for (i = 0; i < config->rx_ring_num; i++)
  4317. s2io_chk_rx_buffers(sp, &mac_control->rings[i]);
  4318. }
  4319. writeq(sp->general_int_mask, &bar0->general_int_mask);
  4320. readl(&bar0->general_int_status);
  4321. return IRQ_HANDLED;
  4322. }
  4323. else if (!reason) {
  4324. /* The interrupt was not raised by us */
  4325. return IRQ_NONE;
  4326. }
  4327. return IRQ_HANDLED;
  4328. }
  4329. /**
  4330. * s2io_updt_stats -
  4331. */
  4332. static void s2io_updt_stats(struct s2io_nic *sp)
  4333. {
  4334. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4335. u64 val64;
  4336. int cnt = 0;
  4337. if (is_s2io_card_up(sp)) {
  4338. /* Apprx 30us on a 133 MHz bus */
  4339. val64 = SET_UPDT_CLICKS(10) |
  4340. STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
  4341. writeq(val64, &bar0->stat_cfg);
  4342. do {
  4343. udelay(100);
  4344. val64 = readq(&bar0->stat_cfg);
  4345. if (!(val64 & s2BIT(0)))
  4346. break;
  4347. cnt++;
  4348. if (cnt == 5)
  4349. break; /* Updt failed */
  4350. } while(1);
  4351. }
  4352. }
  4353. /**
  4354. * s2io_get_stats - Updates the device statistics structure.
  4355. * @dev : pointer to the device structure.
  4356. * Description:
  4357. * This function updates the device statistics structure in the s2io_nic
  4358. * structure and returns a pointer to the same.
  4359. * Return value:
  4360. * pointer to the updated net_device_stats structure.
  4361. */
  4362. static struct net_device_stats *s2io_get_stats(struct net_device *dev)
  4363. {
  4364. struct s2io_nic *sp = dev->priv;
  4365. struct mac_info *mac_control;
  4366. struct config_param *config;
  4367. int i;
  4368. mac_control = &sp->mac_control;
  4369. config = &sp->config;
  4370. /* Configure Stats for immediate updt */
  4371. s2io_updt_stats(sp);
  4372. /* Using sp->stats as a staging area, because reset (due to mtu
  4373. change, for example) will clear some hardware counters */
  4374. dev->stats.tx_packets +=
  4375. le32_to_cpu(mac_control->stats_info->tmac_frms) -
  4376. sp->stats.tx_packets;
  4377. sp->stats.tx_packets =
  4378. le32_to_cpu(mac_control->stats_info->tmac_frms);
  4379. dev->stats.tx_errors +=
  4380. le32_to_cpu(mac_control->stats_info->tmac_any_err_frms) -
  4381. sp->stats.tx_errors;
  4382. sp->stats.tx_errors =
  4383. le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
  4384. dev->stats.rx_errors +=
  4385. le64_to_cpu(mac_control->stats_info->rmac_drop_frms) -
  4386. sp->stats.rx_errors;
  4387. sp->stats.rx_errors =
  4388. le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
  4389. dev->stats.multicast =
  4390. le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms) -
  4391. sp->stats.multicast;
  4392. sp->stats.multicast =
  4393. le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
  4394. dev->stats.rx_length_errors =
  4395. le64_to_cpu(mac_control->stats_info->rmac_long_frms) -
  4396. sp->stats.rx_length_errors;
  4397. sp->stats.rx_length_errors =
  4398. le64_to_cpu(mac_control->stats_info->rmac_long_frms);
  4399. /* collect per-ring rx_packets and rx_bytes */
  4400. dev->stats.rx_packets = dev->stats.rx_bytes = 0;
  4401. for (i = 0; i < config->rx_ring_num; i++) {
  4402. dev->stats.rx_packets += mac_control->rings[i].rx_packets;
  4403. dev->stats.rx_bytes += mac_control->rings[i].rx_bytes;
  4404. }
  4405. return (&dev->stats);
  4406. }
  4407. /**
  4408. * s2io_set_multicast - entry point for multicast address enable/disable.
  4409. * @dev : pointer to the device structure
  4410. * Description:
  4411. * This function is a driver entry point which gets called by the kernel
  4412. * whenever multicast addresses must be enabled/disabled. This also gets
  4413. * called to set/reset promiscuous mode. Depending on the deivce flag, we
  4414. * determine, if multicast address must be enabled or if promiscuous mode
  4415. * is to be disabled etc.
  4416. * Return value:
  4417. * void.
  4418. */
  4419. static void s2io_set_multicast(struct net_device *dev)
  4420. {
  4421. int i, j, prev_cnt;
  4422. struct dev_mc_list *mclist;
  4423. struct s2io_nic *sp = dev->priv;
  4424. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4425. u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
  4426. 0xfeffffffffffULL;
  4427. u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
  4428. void __iomem *add;
  4429. struct config_param *config = &sp->config;
  4430. if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
  4431. /* Enable all Multicast addresses */
  4432. writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
  4433. &bar0->rmac_addr_data0_mem);
  4434. writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
  4435. &bar0->rmac_addr_data1_mem);
  4436. val64 = RMAC_ADDR_CMD_MEM_WE |
  4437. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  4438. RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
  4439. writeq(val64, &bar0->rmac_addr_cmd_mem);
  4440. /* Wait till command completes */
  4441. wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  4442. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
  4443. S2IO_BIT_RESET);
  4444. sp->m_cast_flg = 1;
  4445. sp->all_multi_pos = config->max_mc_addr - 1;
  4446. } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
  4447. /* Disable all Multicast addresses */
  4448. writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
  4449. &bar0->rmac_addr_data0_mem);
  4450. writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
  4451. &bar0->rmac_addr_data1_mem);
  4452. val64 = RMAC_ADDR_CMD_MEM_WE |
  4453. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  4454. RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
  4455. writeq(val64, &bar0->rmac_addr_cmd_mem);
  4456. /* Wait till command completes */
  4457. wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  4458. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
  4459. S2IO_BIT_RESET);
  4460. sp->m_cast_flg = 0;
  4461. sp->all_multi_pos = 0;
  4462. }
  4463. if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
  4464. /* Put the NIC into promiscuous mode */
  4465. add = &bar0->mac_cfg;
  4466. val64 = readq(&bar0->mac_cfg);
  4467. val64 |= MAC_CFG_RMAC_PROM_ENABLE;
  4468. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  4469. writel((u32) val64, add);
  4470. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  4471. writel((u32) (val64 >> 32), (add + 4));
  4472. if (vlan_tag_strip != 1) {
  4473. val64 = readq(&bar0->rx_pa_cfg);
  4474. val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
  4475. writeq(val64, &bar0->rx_pa_cfg);
  4476. vlan_strip_flag = 0;
  4477. }
  4478. val64 = readq(&bar0->mac_cfg);
  4479. sp->promisc_flg = 1;
  4480. DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
  4481. dev->name);
  4482. } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
  4483. /* Remove the NIC from promiscuous mode */
  4484. add = &bar0->mac_cfg;
  4485. val64 = readq(&bar0->mac_cfg);
  4486. val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
  4487. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  4488. writel((u32) val64, add);
  4489. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  4490. writel((u32) (val64 >> 32), (add + 4));
  4491. if (vlan_tag_strip != 0) {
  4492. val64 = readq(&bar0->rx_pa_cfg);
  4493. val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
  4494. writeq(val64, &bar0->rx_pa_cfg);
  4495. vlan_strip_flag = 1;
  4496. }
  4497. val64 = readq(&bar0->mac_cfg);
  4498. sp->promisc_flg = 0;
  4499. DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
  4500. dev->name);
  4501. }
  4502. /* Update individual M_CAST address list */
  4503. if ((!sp->m_cast_flg) && dev->mc_count) {
  4504. if (dev->mc_count >
  4505. (config->max_mc_addr - config->max_mac_addr)) {
  4506. DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
  4507. dev->name);
  4508. DBG_PRINT(ERR_DBG, "can be added, please enable ");
  4509. DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
  4510. return;
  4511. }
  4512. prev_cnt = sp->mc_addr_count;
  4513. sp->mc_addr_count = dev->mc_count;
  4514. /* Clear out the previous list of Mc in the H/W. */
  4515. for (i = 0; i < prev_cnt; i++) {
  4516. writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
  4517. &bar0->rmac_addr_data0_mem);
  4518. writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
  4519. &bar0->rmac_addr_data1_mem);
  4520. val64 = RMAC_ADDR_CMD_MEM_WE |
  4521. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  4522. RMAC_ADDR_CMD_MEM_OFFSET
  4523. (config->mc_start_offset + i);
  4524. writeq(val64, &bar0->rmac_addr_cmd_mem);
  4525. /* Wait for command completes */
  4526. if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  4527. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
  4528. S2IO_BIT_RESET)) {
  4529. DBG_PRINT(ERR_DBG, "%s: Adding ",
  4530. dev->name);
  4531. DBG_PRINT(ERR_DBG, "Multicasts failed\n");
  4532. return;
  4533. }
  4534. }
  4535. /* Create the new Rx filter list and update the same in H/W. */
  4536. for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
  4537. i++, mclist = mclist->next) {
  4538. memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
  4539. ETH_ALEN);
  4540. mac_addr = 0;
  4541. for (j = 0; j < ETH_ALEN; j++) {
  4542. mac_addr |= mclist->dmi_addr[j];
  4543. mac_addr <<= 8;
  4544. }
  4545. mac_addr >>= 8;
  4546. writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
  4547. &bar0->rmac_addr_data0_mem);
  4548. writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
  4549. &bar0->rmac_addr_data1_mem);
  4550. val64 = RMAC_ADDR_CMD_MEM_WE |
  4551. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  4552. RMAC_ADDR_CMD_MEM_OFFSET
  4553. (i + config->mc_start_offset);
  4554. writeq(val64, &bar0->rmac_addr_cmd_mem);
  4555. /* Wait for command completes */
  4556. if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  4557. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
  4558. S2IO_BIT_RESET)) {
  4559. DBG_PRINT(ERR_DBG, "%s: Adding ",
  4560. dev->name);
  4561. DBG_PRINT(ERR_DBG, "Multicasts failed\n");
  4562. return;
  4563. }
  4564. }
  4565. }
  4566. }
  4567. /* read from CAM unicast & multicast addresses and store it in
  4568. * def_mac_addr structure
  4569. */
  4570. void do_s2io_store_unicast_mc(struct s2io_nic *sp)
  4571. {
  4572. int offset;
  4573. u64 mac_addr = 0x0;
  4574. struct config_param *config = &sp->config;
  4575. /* store unicast & multicast mac addresses */
  4576. for (offset = 0; offset < config->max_mc_addr; offset++) {
  4577. mac_addr = do_s2io_read_unicast_mc(sp, offset);
  4578. /* if read fails disable the entry */
  4579. if (mac_addr == FAILURE)
  4580. mac_addr = S2IO_DISABLE_MAC_ENTRY;
  4581. do_s2io_copy_mac_addr(sp, offset, mac_addr);
  4582. }
  4583. }
  4584. /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
  4585. static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
  4586. {
  4587. int offset;
  4588. struct config_param *config = &sp->config;
  4589. /* restore unicast mac address */
  4590. for (offset = 0; offset < config->max_mac_addr; offset++)
  4591. do_s2io_prog_unicast(sp->dev,
  4592. sp->def_mac_addr[offset].mac_addr);
  4593. /* restore multicast mac address */
  4594. for (offset = config->mc_start_offset;
  4595. offset < config->max_mc_addr; offset++)
  4596. do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
  4597. }
  4598. /* add a multicast MAC address to CAM */
  4599. static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
  4600. {
  4601. int i;
  4602. u64 mac_addr = 0;
  4603. struct config_param *config = &sp->config;
  4604. for (i = 0; i < ETH_ALEN; i++) {
  4605. mac_addr <<= 8;
  4606. mac_addr |= addr[i];
  4607. }
  4608. if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
  4609. return SUCCESS;
  4610. /* check if the multicast mac already preset in CAM */
  4611. for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
  4612. u64 tmp64;
  4613. tmp64 = do_s2io_read_unicast_mc(sp, i);
  4614. if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
  4615. break;
  4616. if (tmp64 == mac_addr)
  4617. return SUCCESS;
  4618. }
  4619. if (i == config->max_mc_addr) {
  4620. DBG_PRINT(ERR_DBG,
  4621. "CAM full no space left for multicast MAC\n");
  4622. return FAILURE;
  4623. }
  4624. /* Update the internal structure with this new mac address */
  4625. do_s2io_copy_mac_addr(sp, i, mac_addr);
  4626. return (do_s2io_add_mac(sp, mac_addr, i));
  4627. }
  4628. /* add MAC address to CAM */
  4629. static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
  4630. {
  4631. u64 val64;
  4632. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4633. writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
  4634. &bar0->rmac_addr_data0_mem);
  4635. val64 =
  4636. RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  4637. RMAC_ADDR_CMD_MEM_OFFSET(off);
  4638. writeq(val64, &bar0->rmac_addr_cmd_mem);
  4639. /* Wait till command completes */
  4640. if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  4641. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
  4642. S2IO_BIT_RESET)) {
  4643. DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
  4644. return FAILURE;
  4645. }
  4646. return SUCCESS;
  4647. }
  4648. /* deletes a specified unicast/multicast mac entry from CAM */
  4649. static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
  4650. {
  4651. int offset;
  4652. u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
  4653. struct config_param *config = &sp->config;
  4654. for (offset = 1;
  4655. offset < config->max_mc_addr; offset++) {
  4656. tmp64 = do_s2io_read_unicast_mc(sp, offset);
  4657. if (tmp64 == addr) {
  4658. /* disable the entry by writing 0xffffffffffffULL */
  4659. if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
  4660. return FAILURE;
  4661. /* store the new mac list from CAM */
  4662. do_s2io_store_unicast_mc(sp);
  4663. return SUCCESS;
  4664. }
  4665. }
  4666. DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
  4667. (unsigned long long)addr);
  4668. return FAILURE;
  4669. }
  4670. /* read mac entries from CAM */
  4671. static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
  4672. {
  4673. u64 tmp64 = 0xffffffffffff0000ULL, val64;
  4674. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4675. /* read mac addr */
  4676. val64 =
  4677. RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  4678. RMAC_ADDR_CMD_MEM_OFFSET(offset);
  4679. writeq(val64, &bar0->rmac_addr_cmd_mem);
  4680. /* Wait till command completes */
  4681. if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  4682. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
  4683. S2IO_BIT_RESET)) {
  4684. DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
  4685. return FAILURE;
  4686. }
  4687. tmp64 = readq(&bar0->rmac_addr_data0_mem);
  4688. return (tmp64 >> 16);
  4689. }
  4690. /**
  4691. * s2io_set_mac_addr driver entry point
  4692. */
  4693. static int s2io_set_mac_addr(struct net_device *dev, void *p)
  4694. {
  4695. struct sockaddr *addr = p;
  4696. if (!is_valid_ether_addr(addr->sa_data))
  4697. return -EINVAL;
  4698. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  4699. /* store the MAC address in CAM */
  4700. return (do_s2io_prog_unicast(dev, dev->dev_addr));
  4701. }
  4702. /**
  4703. * do_s2io_prog_unicast - Programs the Xframe mac address
  4704. * @dev : pointer to the device structure.
  4705. * @addr: a uchar pointer to the new mac address which is to be set.
  4706. * Description : This procedure will program the Xframe to receive
  4707. * frames with new Mac Address
  4708. * Return value: SUCCESS on success and an appropriate (-)ve integer
  4709. * as defined in errno.h file on failure.
  4710. */
  4711. static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
  4712. {
  4713. struct s2io_nic *sp = dev->priv;
  4714. register u64 mac_addr = 0, perm_addr = 0;
  4715. int i;
  4716. u64 tmp64;
  4717. struct config_param *config = &sp->config;
  4718. /*
  4719. * Set the new MAC address as the new unicast filter and reflect this
  4720. * change on the device address registered with the OS. It will be
  4721. * at offset 0.
  4722. */
  4723. for (i = 0; i < ETH_ALEN; i++) {
  4724. mac_addr <<= 8;
  4725. mac_addr |= addr[i];
  4726. perm_addr <<= 8;
  4727. perm_addr |= sp->def_mac_addr[0].mac_addr[i];
  4728. }
  4729. /* check if the dev_addr is different than perm_addr */
  4730. if (mac_addr == perm_addr)
  4731. return SUCCESS;
  4732. /* check if the mac already preset in CAM */
  4733. for (i = 1; i < config->max_mac_addr; i++) {
  4734. tmp64 = do_s2io_read_unicast_mc(sp, i);
  4735. if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
  4736. break;
  4737. if (tmp64 == mac_addr) {
  4738. DBG_PRINT(INFO_DBG,
  4739. "MAC addr:0x%llx already present in CAM\n",
  4740. (unsigned long long)mac_addr);
  4741. return SUCCESS;
  4742. }
  4743. }
  4744. if (i == config->max_mac_addr) {
  4745. DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
  4746. return FAILURE;
  4747. }
  4748. /* Update the internal structure with this new mac address */
  4749. do_s2io_copy_mac_addr(sp, i, mac_addr);
  4750. return (do_s2io_add_mac(sp, mac_addr, i));
  4751. }
  4752. /**
  4753. * s2io_ethtool_sset - Sets different link parameters.
  4754. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
  4755. * @info: pointer to the structure with parameters given by ethtool to set
  4756. * link information.
  4757. * Description:
  4758. * The function sets different link parameters provided by the user onto
  4759. * the NIC.
  4760. * Return value:
  4761. * 0 on success.
  4762. */
  4763. static int s2io_ethtool_sset(struct net_device *dev,
  4764. struct ethtool_cmd *info)
  4765. {
  4766. struct s2io_nic *sp = dev->priv;
  4767. if ((info->autoneg == AUTONEG_ENABLE) ||
  4768. (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
  4769. return -EINVAL;
  4770. else {
  4771. s2io_close(sp->dev);
  4772. s2io_open(sp->dev);
  4773. }
  4774. return 0;
  4775. }
  4776. /**
  4777. * s2io_ethtol_gset - Return link specific information.
  4778. * @sp : private member of the device structure, pointer to the
  4779. * s2io_nic structure.
  4780. * @info : pointer to the structure with parameters given by ethtool
  4781. * to return link information.
  4782. * Description:
  4783. * Returns link specific information like speed, duplex etc.. to ethtool.
  4784. * Return value :
  4785. * return 0 on success.
  4786. */
  4787. static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
  4788. {
  4789. struct s2io_nic *sp = dev->priv;
  4790. info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
  4791. info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
  4792. info->port = PORT_FIBRE;
  4793. /* info->transceiver */
  4794. info->transceiver = XCVR_EXTERNAL;
  4795. if (netif_carrier_ok(sp->dev)) {
  4796. info->speed = 10000;
  4797. info->duplex = DUPLEX_FULL;
  4798. } else {
  4799. info->speed = -1;
  4800. info->duplex = -1;
  4801. }
  4802. info->autoneg = AUTONEG_DISABLE;
  4803. return 0;
  4804. }
  4805. /**
  4806. * s2io_ethtool_gdrvinfo - Returns driver specific information.
  4807. * @sp : private member of the device structure, which is a pointer to the
  4808. * s2io_nic structure.
  4809. * @info : pointer to the structure with parameters given by ethtool to
  4810. * return driver information.
  4811. * Description:
  4812. * Returns driver specefic information like name, version etc.. to ethtool.
  4813. * Return value:
  4814. * void
  4815. */
  4816. static void s2io_ethtool_gdrvinfo(struct net_device *dev,
  4817. struct ethtool_drvinfo *info)
  4818. {
  4819. struct s2io_nic *sp = dev->priv;
  4820. strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
  4821. strncpy(info->version, s2io_driver_version, sizeof(info->version));
  4822. strncpy(info->fw_version, "", sizeof(info->fw_version));
  4823. strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
  4824. info->regdump_len = XENA_REG_SPACE;
  4825. info->eedump_len = XENA_EEPROM_SPACE;
  4826. }
  4827. /**
  4828. * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
  4829. * @sp: private member of the device structure, which is a pointer to the
  4830. * s2io_nic structure.
  4831. * @regs : pointer to the structure with parameters given by ethtool for
  4832. * dumping the registers.
  4833. * @reg_space: The input argumnet into which all the registers are dumped.
  4834. * Description:
  4835. * Dumps the entire register space of xFrame NIC into the user given
  4836. * buffer area.
  4837. * Return value :
  4838. * void .
  4839. */
  4840. static void s2io_ethtool_gregs(struct net_device *dev,
  4841. struct ethtool_regs *regs, void *space)
  4842. {
  4843. int i;
  4844. u64 reg;
  4845. u8 *reg_space = (u8 *) space;
  4846. struct s2io_nic *sp = dev->priv;
  4847. regs->len = XENA_REG_SPACE;
  4848. regs->version = sp->pdev->subsystem_device;
  4849. for (i = 0; i < regs->len; i += 8) {
  4850. reg = readq(sp->bar0 + i);
  4851. memcpy((reg_space + i), &reg, 8);
  4852. }
  4853. }
  4854. /**
  4855. * s2io_phy_id - timer function that alternates adapter LED.
  4856. * @data : address of the private member of the device structure, which
  4857. * is a pointer to the s2io_nic structure, provided as an u32.
  4858. * Description: This is actually the timer function that alternates the
  4859. * adapter LED bit of the adapter control bit to set/reset every time on
  4860. * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
  4861. * once every second.
  4862. */
  4863. static void s2io_phy_id(unsigned long data)
  4864. {
  4865. struct s2io_nic *sp = (struct s2io_nic *) data;
  4866. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4867. u64 val64 = 0;
  4868. u16 subid;
  4869. subid = sp->pdev->subsystem_device;
  4870. if ((sp->device_type == XFRAME_II_DEVICE) ||
  4871. ((subid & 0xFF) >= 0x07)) {
  4872. val64 = readq(&bar0->gpio_control);
  4873. val64 ^= GPIO_CTRL_GPIO_0;
  4874. writeq(val64, &bar0->gpio_control);
  4875. } else {
  4876. val64 = readq(&bar0->adapter_control);
  4877. val64 ^= ADAPTER_LED_ON;
  4878. writeq(val64, &bar0->adapter_control);
  4879. }
  4880. mod_timer(&sp->id_timer, jiffies + HZ / 2);
  4881. }
  4882. /**
  4883. * s2io_ethtool_idnic - To physically identify the nic on the system.
  4884. * @sp : private member of the device structure, which is a pointer to the
  4885. * s2io_nic structure.
  4886. * @id : pointer to the structure with identification parameters given by
  4887. * ethtool.
  4888. * Description: Used to physically identify the NIC on the system.
  4889. * The Link LED will blink for a time specified by the user for
  4890. * identification.
  4891. * NOTE: The Link has to be Up to be able to blink the LED. Hence
  4892. * identification is possible only if it's link is up.
  4893. * Return value:
  4894. * int , returns 0 on success
  4895. */
  4896. static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
  4897. {
  4898. u64 val64 = 0, last_gpio_ctrl_val;
  4899. struct s2io_nic *sp = dev->priv;
  4900. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4901. u16 subid;
  4902. subid = sp->pdev->subsystem_device;
  4903. last_gpio_ctrl_val = readq(&bar0->gpio_control);
  4904. if ((sp->device_type == XFRAME_I_DEVICE) &&
  4905. ((subid & 0xFF) < 0x07)) {
  4906. val64 = readq(&bar0->adapter_control);
  4907. if (!(val64 & ADAPTER_CNTL_EN)) {
  4908. printk(KERN_ERR
  4909. "Adapter Link down, cannot blink LED\n");
  4910. return -EFAULT;
  4911. }
  4912. }
  4913. if (sp->id_timer.function == NULL) {
  4914. init_timer(&sp->id_timer);
  4915. sp->id_timer.function = s2io_phy_id;
  4916. sp->id_timer.data = (unsigned long) sp;
  4917. }
  4918. mod_timer(&sp->id_timer, jiffies);
  4919. if (data)
  4920. msleep_interruptible(data * HZ);
  4921. else
  4922. msleep_interruptible(MAX_FLICKER_TIME);
  4923. del_timer_sync(&sp->id_timer);
  4924. if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
  4925. writeq(last_gpio_ctrl_val, &bar0->gpio_control);
  4926. last_gpio_ctrl_val = readq(&bar0->gpio_control);
  4927. }
  4928. return 0;
  4929. }
  4930. static void s2io_ethtool_gringparam(struct net_device *dev,
  4931. struct ethtool_ringparam *ering)
  4932. {
  4933. struct s2io_nic *sp = dev->priv;
  4934. int i,tx_desc_count=0,rx_desc_count=0;
  4935. if (sp->rxd_mode == RXD_MODE_1)
  4936. ering->rx_max_pending = MAX_RX_DESC_1;
  4937. else if (sp->rxd_mode == RXD_MODE_3B)
  4938. ering->rx_max_pending = MAX_RX_DESC_2;
  4939. ering->tx_max_pending = MAX_TX_DESC;
  4940. for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
  4941. tx_desc_count += sp->config.tx_cfg[i].fifo_len;
  4942. DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
  4943. ering->tx_pending = tx_desc_count;
  4944. rx_desc_count = 0;
  4945. for (i = 0 ; i < sp->config.rx_ring_num ; i++)
  4946. rx_desc_count += sp->config.rx_cfg[i].num_rxd;
  4947. ering->rx_pending = rx_desc_count;
  4948. ering->rx_mini_max_pending = 0;
  4949. ering->rx_mini_pending = 0;
  4950. if(sp->rxd_mode == RXD_MODE_1)
  4951. ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
  4952. else if (sp->rxd_mode == RXD_MODE_3B)
  4953. ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
  4954. ering->rx_jumbo_pending = rx_desc_count;
  4955. }
  4956. /**
  4957. * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
  4958. * @sp : private member of the device structure, which is a pointer to the
  4959. * s2io_nic structure.
  4960. * @ep : pointer to the structure with pause parameters given by ethtool.
  4961. * Description:
  4962. * Returns the Pause frame generation and reception capability of the NIC.
  4963. * Return value:
  4964. * void
  4965. */
  4966. static void s2io_ethtool_getpause_data(struct net_device *dev,
  4967. struct ethtool_pauseparam *ep)
  4968. {
  4969. u64 val64;
  4970. struct s2io_nic *sp = dev->priv;
  4971. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4972. val64 = readq(&bar0->rmac_pause_cfg);
  4973. if (val64 & RMAC_PAUSE_GEN_ENABLE)
  4974. ep->tx_pause = TRUE;
  4975. if (val64 & RMAC_PAUSE_RX_ENABLE)
  4976. ep->rx_pause = TRUE;
  4977. ep->autoneg = FALSE;
  4978. }
  4979. /**
  4980. * s2io_ethtool_setpause_data - set/reset pause frame generation.
  4981. * @sp : private member of the device structure, which is a pointer to the
  4982. * s2io_nic structure.
  4983. * @ep : pointer to the structure with pause parameters given by ethtool.
  4984. * Description:
  4985. * It can be used to set or reset Pause frame generation or reception
  4986. * support of the NIC.
  4987. * Return value:
  4988. * int, returns 0 on Success
  4989. */
  4990. static int s2io_ethtool_setpause_data(struct net_device *dev,
  4991. struct ethtool_pauseparam *ep)
  4992. {
  4993. u64 val64;
  4994. struct s2io_nic *sp = dev->priv;
  4995. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4996. val64 = readq(&bar0->rmac_pause_cfg);
  4997. if (ep->tx_pause)
  4998. val64 |= RMAC_PAUSE_GEN_ENABLE;
  4999. else
  5000. val64 &= ~RMAC_PAUSE_GEN_ENABLE;
  5001. if (ep->rx_pause)
  5002. val64 |= RMAC_PAUSE_RX_ENABLE;
  5003. else
  5004. val64 &= ~RMAC_PAUSE_RX_ENABLE;
  5005. writeq(val64, &bar0->rmac_pause_cfg);
  5006. return 0;
  5007. }
  5008. /**
  5009. * read_eeprom - reads 4 bytes of data from user given offset.
  5010. * @sp : private member of the device structure, which is a pointer to the
  5011. * s2io_nic structure.
  5012. * @off : offset at which the data must be written
  5013. * @data : Its an output parameter where the data read at the given
  5014. * offset is stored.
  5015. * Description:
  5016. * Will read 4 bytes of data from the user given offset and return the
  5017. * read data.
  5018. * NOTE: Will allow to read only part of the EEPROM visible through the
  5019. * I2C bus.
  5020. * Return value:
  5021. * -1 on failure and 0 on success.
  5022. */
  5023. #define S2IO_DEV_ID 5
  5024. static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
  5025. {
  5026. int ret = -1;
  5027. u32 exit_cnt = 0;
  5028. u64 val64;
  5029. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  5030. if (sp->device_type == XFRAME_I_DEVICE) {
  5031. val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
  5032. I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
  5033. I2C_CONTROL_CNTL_START;
  5034. SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
  5035. while (exit_cnt < 5) {
  5036. val64 = readq(&bar0->i2c_control);
  5037. if (I2C_CONTROL_CNTL_END(val64)) {
  5038. *data = I2C_CONTROL_GET_DATA(val64);
  5039. ret = 0;
  5040. break;
  5041. }
  5042. msleep(50);
  5043. exit_cnt++;
  5044. }
  5045. }
  5046. if (sp->device_type == XFRAME_II_DEVICE) {
  5047. val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
  5048. SPI_CONTROL_BYTECNT(0x3) |
  5049. SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
  5050. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  5051. val64 |= SPI_CONTROL_REQ;
  5052. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  5053. while (exit_cnt < 5) {
  5054. val64 = readq(&bar0->spi_control);
  5055. if (val64 & SPI_CONTROL_NACK) {
  5056. ret = 1;
  5057. break;
  5058. } else if (val64 & SPI_CONTROL_DONE) {
  5059. *data = readq(&bar0->spi_data);
  5060. *data &= 0xffffff;
  5061. ret = 0;
  5062. break;
  5063. }
  5064. msleep(50);
  5065. exit_cnt++;
  5066. }
  5067. }
  5068. return ret;
  5069. }
  5070. /**
  5071. * write_eeprom - actually writes the relevant part of the data value.
  5072. * @sp : private member of the device structure, which is a pointer to the
  5073. * s2io_nic structure.
  5074. * @off : offset at which the data must be written
  5075. * @data : The data that is to be written
  5076. * @cnt : Number of bytes of the data that are actually to be written into
  5077. * the Eeprom. (max of 3)
  5078. * Description:
  5079. * Actually writes the relevant part of the data value into the Eeprom
  5080. * through the I2C bus.
  5081. * Return value:
  5082. * 0 on success, -1 on failure.
  5083. */
  5084. static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
  5085. {
  5086. int exit_cnt = 0, ret = -1;
  5087. u64 val64;
  5088. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  5089. if (sp->device_type == XFRAME_I_DEVICE) {
  5090. val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
  5091. I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
  5092. I2C_CONTROL_CNTL_START;
  5093. SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
  5094. while (exit_cnt < 5) {
  5095. val64 = readq(&bar0->i2c_control);
  5096. if (I2C_CONTROL_CNTL_END(val64)) {
  5097. if (!(val64 & I2C_CONTROL_NACK))
  5098. ret = 0;
  5099. break;
  5100. }
  5101. msleep(50);
  5102. exit_cnt++;
  5103. }
  5104. }
  5105. if (sp->device_type == XFRAME_II_DEVICE) {
  5106. int write_cnt = (cnt == 8) ? 0 : cnt;
  5107. writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
  5108. val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
  5109. SPI_CONTROL_BYTECNT(write_cnt) |
  5110. SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
  5111. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  5112. val64 |= SPI_CONTROL_REQ;
  5113. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  5114. while (exit_cnt < 5) {
  5115. val64 = readq(&bar0->spi_control);
  5116. if (val64 & SPI_CONTROL_NACK) {
  5117. ret = 1;
  5118. break;
  5119. } else if (val64 & SPI_CONTROL_DONE) {
  5120. ret = 0;
  5121. break;
  5122. }
  5123. msleep(50);
  5124. exit_cnt++;
  5125. }
  5126. }
  5127. return ret;
  5128. }
  5129. static void s2io_vpd_read(struct s2io_nic *nic)
  5130. {
  5131. u8 *vpd_data;
  5132. u8 data;
  5133. int i=0, cnt, fail = 0;
  5134. int vpd_addr = 0x80;
  5135. if (nic->device_type == XFRAME_II_DEVICE) {
  5136. strcpy(nic->product_name, "Xframe II 10GbE network adapter");
  5137. vpd_addr = 0x80;
  5138. }
  5139. else {
  5140. strcpy(nic->product_name, "Xframe I 10GbE network adapter");
  5141. vpd_addr = 0x50;
  5142. }
  5143. strcpy(nic->serial_num, "NOT AVAILABLE");
  5144. vpd_data = kmalloc(256, GFP_KERNEL);
  5145. if (!vpd_data) {
  5146. nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
  5147. return;
  5148. }
  5149. nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
  5150. for (i = 0; i < 256; i +=4 ) {
  5151. pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
  5152. pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
  5153. pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
  5154. for (cnt = 0; cnt <5; cnt++) {
  5155. msleep(2);
  5156. pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
  5157. if (data == 0x80)
  5158. break;
  5159. }
  5160. if (cnt >= 5) {
  5161. DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
  5162. fail = 1;
  5163. break;
  5164. }
  5165. pci_read_config_dword(nic->pdev, (vpd_addr + 4),
  5166. (u32 *)&vpd_data[i]);
  5167. }
  5168. if(!fail) {
  5169. /* read serial number of adapter */
  5170. for (cnt = 0; cnt < 256; cnt++) {
  5171. if ((vpd_data[cnt] == 'S') &&
  5172. (vpd_data[cnt+1] == 'N') &&
  5173. (vpd_data[cnt+2] < VPD_STRING_LEN)) {
  5174. memset(nic->serial_num, 0, VPD_STRING_LEN);
  5175. memcpy(nic->serial_num, &vpd_data[cnt + 3],
  5176. vpd_data[cnt+2]);
  5177. break;
  5178. }
  5179. }
  5180. }
  5181. if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
  5182. memset(nic->product_name, 0, vpd_data[1]);
  5183. memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
  5184. }
  5185. kfree(vpd_data);
  5186. nic->mac_control.stats_info->sw_stat.mem_freed += 256;
  5187. }
  5188. /**
  5189. * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
  5190. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
  5191. * @eeprom : pointer to the user level structure provided by ethtool,
  5192. * containing all relevant information.
  5193. * @data_buf : user defined value to be written into Eeprom.
  5194. * Description: Reads the values stored in the Eeprom at given offset
  5195. * for a given length. Stores these values int the input argument data
  5196. * buffer 'data_buf' and returns these to the caller (ethtool.)
  5197. * Return value:
  5198. * int 0 on success
  5199. */
  5200. static int s2io_ethtool_geeprom(struct net_device *dev,
  5201. struct ethtool_eeprom *eeprom, u8 * data_buf)
  5202. {
  5203. u32 i, valid;
  5204. u64 data;
  5205. struct s2io_nic *sp = dev->priv;
  5206. eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
  5207. if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
  5208. eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
  5209. for (i = 0; i < eeprom->len; i += 4) {
  5210. if (read_eeprom(sp, (eeprom->offset + i), &data)) {
  5211. DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
  5212. return -EFAULT;
  5213. }
  5214. valid = INV(data);
  5215. memcpy((data_buf + i), &valid, 4);
  5216. }
  5217. return 0;
  5218. }
  5219. /**
  5220. * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
  5221. * @sp : private member of the device structure, which is a pointer to the
  5222. * s2io_nic structure.
  5223. * @eeprom : pointer to the user level structure provided by ethtool,
  5224. * containing all relevant information.
  5225. * @data_buf ; user defined value to be written into Eeprom.
  5226. * Description:
  5227. * Tries to write the user provided value in the Eeprom, at the offset
  5228. * given by the user.
  5229. * Return value:
  5230. * 0 on success, -EFAULT on failure.
  5231. */
  5232. static int s2io_ethtool_seeprom(struct net_device *dev,
  5233. struct ethtool_eeprom *eeprom,
  5234. u8 * data_buf)
  5235. {
  5236. int len = eeprom->len, cnt = 0;
  5237. u64 valid = 0, data;
  5238. struct s2io_nic *sp = dev->priv;
  5239. if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
  5240. DBG_PRINT(ERR_DBG,
  5241. "ETHTOOL_WRITE_EEPROM Err: Magic value ");
  5242. DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
  5243. eeprom->magic);
  5244. return -EFAULT;
  5245. }
  5246. while (len) {
  5247. data = (u32) data_buf[cnt] & 0x000000FF;
  5248. if (data) {
  5249. valid = (u32) (data << 24);
  5250. } else
  5251. valid = data;
  5252. if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
  5253. DBG_PRINT(ERR_DBG,
  5254. "ETHTOOL_WRITE_EEPROM Err: Cannot ");
  5255. DBG_PRINT(ERR_DBG,
  5256. "write into the specified offset\n");
  5257. return -EFAULT;
  5258. }
  5259. cnt++;
  5260. len--;
  5261. }
  5262. return 0;
  5263. }
  5264. /**
  5265. * s2io_register_test - reads and writes into all clock domains.
  5266. * @sp : private member of the device structure, which is a pointer to the
  5267. * s2io_nic structure.
  5268. * @data : variable that returns the result of each of the test conducted b
  5269. * by the driver.
  5270. * Description:
  5271. * Read and write into all clock domains. The NIC has 3 clock domains,
  5272. * see that registers in all the three regions are accessible.
  5273. * Return value:
  5274. * 0 on success.
  5275. */
  5276. static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
  5277. {
  5278. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  5279. u64 val64 = 0, exp_val;
  5280. int fail = 0;
  5281. val64 = readq(&bar0->pif_rd_swapper_fb);
  5282. if (val64 != 0x123456789abcdefULL) {
  5283. fail = 1;
  5284. DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
  5285. }
  5286. val64 = readq(&bar0->rmac_pause_cfg);
  5287. if (val64 != 0xc000ffff00000000ULL) {
  5288. fail = 1;
  5289. DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
  5290. }
  5291. val64 = readq(&bar0->rx_queue_cfg);
  5292. if (sp->device_type == XFRAME_II_DEVICE)
  5293. exp_val = 0x0404040404040404ULL;
  5294. else
  5295. exp_val = 0x0808080808080808ULL;
  5296. if (val64 != exp_val) {
  5297. fail = 1;
  5298. DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
  5299. }
  5300. val64 = readq(&bar0->xgxs_efifo_cfg);
  5301. if (val64 != 0x000000001923141EULL) {
  5302. fail = 1;
  5303. DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
  5304. }
  5305. val64 = 0x5A5A5A5A5A5A5A5AULL;
  5306. writeq(val64, &bar0->xmsi_data);
  5307. val64 = readq(&bar0->xmsi_data);
  5308. if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
  5309. fail = 1;
  5310. DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
  5311. }
  5312. val64 = 0xA5A5A5A5A5A5A5A5ULL;
  5313. writeq(val64, &bar0->xmsi_data);
  5314. val64 = readq(&bar0->xmsi_data);
  5315. if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
  5316. fail = 1;
  5317. DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
  5318. }
  5319. *data = fail;
  5320. return fail;
  5321. }
  5322. /**
  5323. * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
  5324. * @sp : private member of the device structure, which is a pointer to the
  5325. * s2io_nic structure.
  5326. * @data:variable that returns the result of each of the test conducted by
  5327. * the driver.
  5328. * Description:
  5329. * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
  5330. * register.
  5331. * Return value:
  5332. * 0 on success.
  5333. */
  5334. static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
  5335. {
  5336. int fail = 0;
  5337. u64 ret_data, org_4F0, org_7F0;
  5338. u8 saved_4F0 = 0, saved_7F0 = 0;
  5339. struct net_device *dev = sp->dev;
  5340. /* Test Write Error at offset 0 */
  5341. /* Note that SPI interface allows write access to all areas
  5342. * of EEPROM. Hence doing all negative testing only for Xframe I.
  5343. */
  5344. if (sp->device_type == XFRAME_I_DEVICE)
  5345. if (!write_eeprom(sp, 0, 0, 3))
  5346. fail = 1;
  5347. /* Save current values at offsets 0x4F0 and 0x7F0 */
  5348. if (!read_eeprom(sp, 0x4F0, &org_4F0))
  5349. saved_4F0 = 1;
  5350. if (!read_eeprom(sp, 0x7F0, &org_7F0))
  5351. saved_7F0 = 1;
  5352. /* Test Write at offset 4f0 */
  5353. if (write_eeprom(sp, 0x4F0, 0x012345, 3))
  5354. fail = 1;
  5355. if (read_eeprom(sp, 0x4F0, &ret_data))
  5356. fail = 1;
  5357. if (ret_data != 0x012345) {
  5358. DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
  5359. "Data written %llx Data read %llx\n",
  5360. dev->name, (unsigned long long)0x12345,
  5361. (unsigned long long)ret_data);
  5362. fail = 1;
  5363. }
  5364. /* Reset the EEPROM data go FFFF */
  5365. write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
  5366. /* Test Write Request Error at offset 0x7c */
  5367. if (sp->device_type == XFRAME_I_DEVICE)
  5368. if (!write_eeprom(sp, 0x07C, 0, 3))
  5369. fail = 1;
  5370. /* Test Write Request at offset 0x7f0 */
  5371. if (write_eeprom(sp, 0x7F0, 0x012345, 3))
  5372. fail = 1;
  5373. if (read_eeprom(sp, 0x7F0, &ret_data))
  5374. fail = 1;
  5375. if (ret_data != 0x012345) {
  5376. DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
  5377. "Data written %llx Data read %llx\n",
  5378. dev->name, (unsigned long long)0x12345,
  5379. (unsigned long long)ret_data);
  5380. fail = 1;
  5381. }
  5382. /* Reset the EEPROM data go FFFF */
  5383. write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
  5384. if (sp->device_type == XFRAME_I_DEVICE) {
  5385. /* Test Write Error at offset 0x80 */
  5386. if (!write_eeprom(sp, 0x080, 0, 3))
  5387. fail = 1;
  5388. /* Test Write Error at offset 0xfc */
  5389. if (!write_eeprom(sp, 0x0FC, 0, 3))
  5390. fail = 1;
  5391. /* Test Write Error at offset 0x100 */
  5392. if (!write_eeprom(sp, 0x100, 0, 3))
  5393. fail = 1;
  5394. /* Test Write Error at offset 4ec */
  5395. if (!write_eeprom(sp, 0x4EC, 0, 3))
  5396. fail = 1;
  5397. }
  5398. /* Restore values at offsets 0x4F0 and 0x7F0 */
  5399. if (saved_4F0)
  5400. write_eeprom(sp, 0x4F0, org_4F0, 3);
  5401. if (saved_7F0)
  5402. write_eeprom(sp, 0x7F0, org_7F0, 3);
  5403. *data = fail;
  5404. return fail;
  5405. }
  5406. /**
  5407. * s2io_bist_test - invokes the MemBist test of the card .
  5408. * @sp : private member of the device structure, which is a pointer to the
  5409. * s2io_nic structure.
  5410. * @data:variable that returns the result of each of the test conducted by
  5411. * the driver.
  5412. * Description:
  5413. * This invokes the MemBist test of the card. We give around
  5414. * 2 secs time for the Test to complete. If it's still not complete
  5415. * within this peiod, we consider that the test failed.
  5416. * Return value:
  5417. * 0 on success and -1 on failure.
  5418. */
  5419. static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
  5420. {
  5421. u8 bist = 0;
  5422. int cnt = 0, ret = -1;
  5423. pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
  5424. bist |= PCI_BIST_START;
  5425. pci_write_config_word(sp->pdev, PCI_BIST, bist);
  5426. while (cnt < 20) {
  5427. pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
  5428. if (!(bist & PCI_BIST_START)) {
  5429. *data = (bist & PCI_BIST_CODE_MASK);
  5430. ret = 0;
  5431. break;
  5432. }
  5433. msleep(100);
  5434. cnt++;
  5435. }
  5436. return ret;
  5437. }
  5438. /**
  5439. * s2io-link_test - verifies the link state of the nic
  5440. * @sp ; private member of the device structure, which is a pointer to the
  5441. * s2io_nic structure.
  5442. * @data: variable that returns the result of each of the test conducted by
  5443. * the driver.
  5444. * Description:
  5445. * The function verifies the link state of the NIC and updates the input
  5446. * argument 'data' appropriately.
  5447. * Return value:
  5448. * 0 on success.
  5449. */
  5450. static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
  5451. {
  5452. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  5453. u64 val64;
  5454. val64 = readq(&bar0->adapter_status);
  5455. if(!(LINK_IS_UP(val64)))
  5456. *data = 1;
  5457. else
  5458. *data = 0;
  5459. return *data;
  5460. }
  5461. /**
  5462. * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
  5463. * @sp - private member of the device structure, which is a pointer to the
  5464. * s2io_nic structure.
  5465. * @data - variable that returns the result of each of the test
  5466. * conducted by the driver.
  5467. * Description:
  5468. * This is one of the offline test that tests the read and write
  5469. * access to the RldRam chip on the NIC.
  5470. * Return value:
  5471. * 0 on success.
  5472. */
  5473. static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
  5474. {
  5475. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  5476. u64 val64;
  5477. int cnt, iteration = 0, test_fail = 0;
  5478. val64 = readq(&bar0->adapter_control);
  5479. val64 &= ~ADAPTER_ECC_EN;
  5480. writeq(val64, &bar0->adapter_control);
  5481. val64 = readq(&bar0->mc_rldram_test_ctrl);
  5482. val64 |= MC_RLDRAM_TEST_MODE;
  5483. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
  5484. val64 = readq(&bar0->mc_rldram_mrs);
  5485. val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
  5486. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
  5487. val64 |= MC_RLDRAM_MRS_ENABLE;
  5488. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
  5489. while (iteration < 2) {
  5490. val64 = 0x55555555aaaa0000ULL;
  5491. if (iteration == 1) {
  5492. val64 ^= 0xFFFFFFFFFFFF0000ULL;
  5493. }
  5494. writeq(val64, &bar0->mc_rldram_test_d0);
  5495. val64 = 0xaaaa5a5555550000ULL;
  5496. if (iteration == 1) {
  5497. val64 ^= 0xFFFFFFFFFFFF0000ULL;
  5498. }
  5499. writeq(val64, &bar0->mc_rldram_test_d1);
  5500. val64 = 0x55aaaaaaaa5a0000ULL;
  5501. if (iteration == 1) {
  5502. val64 ^= 0xFFFFFFFFFFFF0000ULL;
  5503. }
  5504. writeq(val64, &bar0->mc_rldram_test_d2);
  5505. val64 = (u64) (0x0000003ffffe0100ULL);
  5506. writeq(val64, &bar0->mc_rldram_test_add);
  5507. val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
  5508. MC_RLDRAM_TEST_GO;
  5509. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
  5510. for (cnt = 0; cnt < 5; cnt++) {
  5511. val64 = readq(&bar0->mc_rldram_test_ctrl);
  5512. if (val64 & MC_RLDRAM_TEST_DONE)
  5513. break;
  5514. msleep(200);
  5515. }
  5516. if (cnt == 5)
  5517. break;
  5518. val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
  5519. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
  5520. for (cnt = 0; cnt < 5; cnt++) {
  5521. val64 = readq(&bar0->mc_rldram_test_ctrl);
  5522. if (val64 & MC_RLDRAM_TEST_DONE)
  5523. break;
  5524. msleep(500);
  5525. }
  5526. if (cnt == 5)
  5527. break;
  5528. val64 = readq(&bar0->mc_rldram_test_ctrl);
  5529. if (!(val64 & MC_RLDRAM_TEST_PASS))
  5530. test_fail = 1;
  5531. iteration++;
  5532. }
  5533. *data = test_fail;
  5534. /* Bring the adapter out of test mode */
  5535. SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
  5536. return test_fail;
  5537. }
  5538. /**
  5539. * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
  5540. * @sp : private member of the device structure, which is a pointer to the
  5541. * s2io_nic structure.
  5542. * @ethtest : pointer to a ethtool command specific structure that will be
  5543. * returned to the user.
  5544. * @data : variable that returns the result of each of the test
  5545. * conducted by the driver.
  5546. * Description:
  5547. * This function conducts 6 tests ( 4 offline and 2 online) to determine
  5548. * the health of the card.
  5549. * Return value:
  5550. * void
  5551. */
  5552. static void s2io_ethtool_test(struct net_device *dev,
  5553. struct ethtool_test *ethtest,
  5554. uint64_t * data)
  5555. {
  5556. struct s2io_nic *sp = dev->priv;
  5557. int orig_state = netif_running(sp->dev);
  5558. if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
  5559. /* Offline Tests. */
  5560. if (orig_state)
  5561. s2io_close(sp->dev);
  5562. if (s2io_register_test(sp, &data[0]))
  5563. ethtest->flags |= ETH_TEST_FL_FAILED;
  5564. s2io_reset(sp);
  5565. if (s2io_rldram_test(sp, &data[3]))
  5566. ethtest->flags |= ETH_TEST_FL_FAILED;
  5567. s2io_reset(sp);
  5568. if (s2io_eeprom_test(sp, &data[1]))
  5569. ethtest->flags |= ETH_TEST_FL_FAILED;
  5570. if (s2io_bist_test(sp, &data[4]))
  5571. ethtest->flags |= ETH_TEST_FL_FAILED;
  5572. if (orig_state)
  5573. s2io_open(sp->dev);
  5574. data[2] = 0;
  5575. } else {
  5576. /* Online Tests. */
  5577. if (!orig_state) {
  5578. DBG_PRINT(ERR_DBG,
  5579. "%s: is not up, cannot run test\n",
  5580. dev->name);
  5581. data[0] = -1;
  5582. data[1] = -1;
  5583. data[2] = -1;
  5584. data[3] = -1;
  5585. data[4] = -1;
  5586. }
  5587. if (s2io_link_test(sp, &data[2]))
  5588. ethtest->flags |= ETH_TEST_FL_FAILED;
  5589. data[0] = 0;
  5590. data[1] = 0;
  5591. data[3] = 0;
  5592. data[4] = 0;
  5593. }
  5594. }
  5595. static void s2io_get_ethtool_stats(struct net_device *dev,
  5596. struct ethtool_stats *estats,
  5597. u64 * tmp_stats)
  5598. {
  5599. int i = 0, k;
  5600. struct s2io_nic *sp = dev->priv;
  5601. struct stat_block *stat_info = sp->mac_control.stats_info;
  5602. s2io_updt_stats(sp);
  5603. tmp_stats[i++] =
  5604. (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
  5605. le32_to_cpu(stat_info->tmac_frms);
  5606. tmp_stats[i++] =
  5607. (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
  5608. le32_to_cpu(stat_info->tmac_data_octets);
  5609. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
  5610. tmp_stats[i++] =
  5611. (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
  5612. le32_to_cpu(stat_info->tmac_mcst_frms);
  5613. tmp_stats[i++] =
  5614. (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
  5615. le32_to_cpu(stat_info->tmac_bcst_frms);
  5616. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
  5617. tmp_stats[i++] =
  5618. (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
  5619. le32_to_cpu(stat_info->tmac_ttl_octets);
  5620. tmp_stats[i++] =
  5621. (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
  5622. le32_to_cpu(stat_info->tmac_ucst_frms);
  5623. tmp_stats[i++] =
  5624. (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
  5625. le32_to_cpu(stat_info->tmac_nucst_frms);
  5626. tmp_stats[i++] =
  5627. (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
  5628. le32_to_cpu(stat_info->tmac_any_err_frms);
  5629. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
  5630. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
  5631. tmp_stats[i++] =
  5632. (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
  5633. le32_to_cpu(stat_info->tmac_vld_ip);
  5634. tmp_stats[i++] =
  5635. (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
  5636. le32_to_cpu(stat_info->tmac_drop_ip);
  5637. tmp_stats[i++] =
  5638. (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
  5639. le32_to_cpu(stat_info->tmac_icmp);
  5640. tmp_stats[i++] =
  5641. (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
  5642. le32_to_cpu(stat_info->tmac_rst_tcp);
  5643. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
  5644. tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
  5645. le32_to_cpu(stat_info->tmac_udp);
  5646. tmp_stats[i++] =
  5647. (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
  5648. le32_to_cpu(stat_info->rmac_vld_frms);
  5649. tmp_stats[i++] =
  5650. (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
  5651. le32_to_cpu(stat_info->rmac_data_octets);
  5652. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
  5653. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
  5654. tmp_stats[i++] =
  5655. (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
  5656. le32_to_cpu(stat_info->rmac_vld_mcst_frms);
  5657. tmp_stats[i++] =
  5658. (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
  5659. le32_to_cpu(stat_info->rmac_vld_bcst_frms);
  5660. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
  5661. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
  5662. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
  5663. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
  5664. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
  5665. tmp_stats[i++] =
  5666. (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
  5667. le32_to_cpu(stat_info->rmac_ttl_octets);
  5668. tmp_stats[i++] =
  5669. (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
  5670. << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
  5671. tmp_stats[i++] =
  5672. (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
  5673. << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
  5674. tmp_stats[i++] =
  5675. (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
  5676. le32_to_cpu(stat_info->rmac_discarded_frms);
  5677. tmp_stats[i++] =
  5678. (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
  5679. << 32 | le32_to_cpu(stat_info->rmac_drop_events);
  5680. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
  5681. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
  5682. tmp_stats[i++] =
  5683. (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
  5684. le32_to_cpu(stat_info->rmac_usized_frms);
  5685. tmp_stats[i++] =
  5686. (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
  5687. le32_to_cpu(stat_info->rmac_osized_frms);
  5688. tmp_stats[i++] =
  5689. (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
  5690. le32_to_cpu(stat_info->rmac_frag_frms);
  5691. tmp_stats[i++] =
  5692. (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
  5693. le32_to_cpu(stat_info->rmac_jabber_frms);
  5694. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
  5695. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
  5696. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
  5697. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
  5698. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
  5699. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
  5700. tmp_stats[i++] =
  5701. (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
  5702. le32_to_cpu(stat_info->rmac_ip);
  5703. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
  5704. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
  5705. tmp_stats[i++] =
  5706. (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
  5707. le32_to_cpu(stat_info->rmac_drop_ip);
  5708. tmp_stats[i++] =
  5709. (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
  5710. le32_to_cpu(stat_info->rmac_icmp);
  5711. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
  5712. tmp_stats[i++] =
  5713. (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
  5714. le32_to_cpu(stat_info->rmac_udp);
  5715. tmp_stats[i++] =
  5716. (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
  5717. le32_to_cpu(stat_info->rmac_err_drp_udp);
  5718. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
  5719. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
  5720. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
  5721. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
  5722. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
  5723. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
  5724. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
  5725. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
  5726. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
  5727. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
  5728. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
  5729. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
  5730. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
  5731. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
  5732. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
  5733. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
  5734. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
  5735. tmp_stats[i++] =
  5736. (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
  5737. le32_to_cpu(stat_info->rmac_pause_cnt);
  5738. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
  5739. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
  5740. tmp_stats[i++] =
  5741. (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
  5742. le32_to_cpu(stat_info->rmac_accepted_ip);
  5743. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
  5744. tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
  5745. tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
  5746. tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
  5747. tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
  5748. tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
  5749. tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
  5750. tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
  5751. tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
  5752. tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
  5753. tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
  5754. tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
  5755. tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
  5756. tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
  5757. tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
  5758. tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
  5759. tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
  5760. tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
  5761. tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
  5762. /* Enhanced statistics exist only for Hercules */
  5763. if(sp->device_type == XFRAME_II_DEVICE) {
  5764. tmp_stats[i++] =
  5765. le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
  5766. tmp_stats[i++] =
  5767. le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
  5768. tmp_stats[i++] =
  5769. le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
  5770. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
  5771. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
  5772. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
  5773. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
  5774. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
  5775. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
  5776. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
  5777. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
  5778. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
  5779. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
  5780. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
  5781. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
  5782. tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
  5783. }
  5784. tmp_stats[i++] = 0;
  5785. tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
  5786. tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
  5787. tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
  5788. tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
  5789. tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
  5790. tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
  5791. for (k = 0; k < MAX_RX_RINGS; k++)
  5792. tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
  5793. tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
  5794. tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
  5795. tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
  5796. tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
  5797. tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
  5798. tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
  5799. tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
  5800. tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
  5801. tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
  5802. tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
  5803. tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
  5804. tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
  5805. tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
  5806. tmp_stats[i++] = stat_info->sw_stat.sending_both;
  5807. tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
  5808. tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
  5809. if (stat_info->sw_stat.num_aggregations) {
  5810. u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
  5811. int count = 0;
  5812. /*
  5813. * Since 64-bit divide does not work on all platforms,
  5814. * do repeated subtraction.
  5815. */
  5816. while (tmp >= stat_info->sw_stat.num_aggregations) {
  5817. tmp -= stat_info->sw_stat.num_aggregations;
  5818. count++;
  5819. }
  5820. tmp_stats[i++] = count;
  5821. }
  5822. else
  5823. tmp_stats[i++] = 0;
  5824. tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
  5825. tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
  5826. tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
  5827. tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
  5828. tmp_stats[i++] = stat_info->sw_stat.mem_freed;
  5829. tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
  5830. tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
  5831. tmp_stats[i++] = stat_info->sw_stat.link_up_time;
  5832. tmp_stats[i++] = stat_info->sw_stat.link_down_time;
  5833. tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
  5834. tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
  5835. tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
  5836. tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
  5837. tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
  5838. tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
  5839. tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
  5840. tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
  5841. tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
  5842. tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
  5843. tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
  5844. tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
  5845. tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
  5846. tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
  5847. tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
  5848. tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
  5849. tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
  5850. tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
  5851. tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
  5852. tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
  5853. tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
  5854. tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
  5855. tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
  5856. tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
  5857. tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
  5858. tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
  5859. tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
  5860. tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
  5861. tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
  5862. tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
  5863. tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
  5864. }
  5865. static int s2io_ethtool_get_regs_len(struct net_device *dev)
  5866. {
  5867. return (XENA_REG_SPACE);
  5868. }
  5869. static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
  5870. {
  5871. struct s2io_nic *sp = dev->priv;
  5872. return (sp->rx_csum);
  5873. }
  5874. static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
  5875. {
  5876. struct s2io_nic *sp = dev->priv;
  5877. if (data)
  5878. sp->rx_csum = 1;
  5879. else
  5880. sp->rx_csum = 0;
  5881. return 0;
  5882. }
  5883. static int s2io_get_eeprom_len(struct net_device *dev)
  5884. {
  5885. return (XENA_EEPROM_SPACE);
  5886. }
  5887. static int s2io_get_sset_count(struct net_device *dev, int sset)
  5888. {
  5889. struct s2io_nic *sp = dev->priv;
  5890. switch (sset) {
  5891. case ETH_SS_TEST:
  5892. return S2IO_TEST_LEN;
  5893. case ETH_SS_STATS:
  5894. switch(sp->device_type) {
  5895. case XFRAME_I_DEVICE:
  5896. return XFRAME_I_STAT_LEN;
  5897. case XFRAME_II_DEVICE:
  5898. return XFRAME_II_STAT_LEN;
  5899. default:
  5900. return 0;
  5901. }
  5902. default:
  5903. return -EOPNOTSUPP;
  5904. }
  5905. }
  5906. static void s2io_ethtool_get_strings(struct net_device *dev,
  5907. u32 stringset, u8 * data)
  5908. {
  5909. int stat_size = 0;
  5910. struct s2io_nic *sp = dev->priv;
  5911. switch (stringset) {
  5912. case ETH_SS_TEST:
  5913. memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
  5914. break;
  5915. case ETH_SS_STATS:
  5916. stat_size = sizeof(ethtool_xena_stats_keys);
  5917. memcpy(data, &ethtool_xena_stats_keys,stat_size);
  5918. if(sp->device_type == XFRAME_II_DEVICE) {
  5919. memcpy(data + stat_size,
  5920. &ethtool_enhanced_stats_keys,
  5921. sizeof(ethtool_enhanced_stats_keys));
  5922. stat_size += sizeof(ethtool_enhanced_stats_keys);
  5923. }
  5924. memcpy(data + stat_size, &ethtool_driver_stats_keys,
  5925. sizeof(ethtool_driver_stats_keys));
  5926. }
  5927. }
  5928. static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
  5929. {
  5930. if (data)
  5931. dev->features |= NETIF_F_IP_CSUM;
  5932. else
  5933. dev->features &= ~NETIF_F_IP_CSUM;
  5934. return 0;
  5935. }
  5936. static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
  5937. {
  5938. return (dev->features & NETIF_F_TSO) != 0;
  5939. }
  5940. static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
  5941. {
  5942. if (data)
  5943. dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
  5944. else
  5945. dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
  5946. return 0;
  5947. }
  5948. static const struct ethtool_ops netdev_ethtool_ops = {
  5949. .get_settings = s2io_ethtool_gset,
  5950. .set_settings = s2io_ethtool_sset,
  5951. .get_drvinfo = s2io_ethtool_gdrvinfo,
  5952. .get_regs_len = s2io_ethtool_get_regs_len,
  5953. .get_regs = s2io_ethtool_gregs,
  5954. .get_link = ethtool_op_get_link,
  5955. .get_eeprom_len = s2io_get_eeprom_len,
  5956. .get_eeprom = s2io_ethtool_geeprom,
  5957. .set_eeprom = s2io_ethtool_seeprom,
  5958. .get_ringparam = s2io_ethtool_gringparam,
  5959. .get_pauseparam = s2io_ethtool_getpause_data,
  5960. .set_pauseparam = s2io_ethtool_setpause_data,
  5961. .get_rx_csum = s2io_ethtool_get_rx_csum,
  5962. .set_rx_csum = s2io_ethtool_set_rx_csum,
  5963. .set_tx_csum = s2io_ethtool_op_set_tx_csum,
  5964. .set_sg = ethtool_op_set_sg,
  5965. .get_tso = s2io_ethtool_op_get_tso,
  5966. .set_tso = s2io_ethtool_op_set_tso,
  5967. .set_ufo = ethtool_op_set_ufo,
  5968. .self_test = s2io_ethtool_test,
  5969. .get_strings = s2io_ethtool_get_strings,
  5970. .phys_id = s2io_ethtool_idnic,
  5971. .get_ethtool_stats = s2io_get_ethtool_stats,
  5972. .get_sset_count = s2io_get_sset_count,
  5973. };
  5974. /**
  5975. * s2io_ioctl - Entry point for the Ioctl
  5976. * @dev : Device pointer.
  5977. * @ifr : An IOCTL specefic structure, that can contain a pointer to
  5978. * a proprietary structure used to pass information to the driver.
  5979. * @cmd : This is used to distinguish between the different commands that
  5980. * can be passed to the IOCTL functions.
  5981. * Description:
  5982. * Currently there are no special functionality supported in IOCTL, hence
  5983. * function always return EOPNOTSUPPORTED
  5984. */
  5985. static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  5986. {
  5987. return -EOPNOTSUPP;
  5988. }
  5989. /**
  5990. * s2io_change_mtu - entry point to change MTU size for the device.
  5991. * @dev : device pointer.
  5992. * @new_mtu : the new MTU size for the device.
  5993. * Description: A driver entry point to change MTU size for the device.
  5994. * Before changing the MTU the device must be stopped.
  5995. * Return value:
  5996. * 0 on success and an appropriate (-)ve integer as defined in errno.h
  5997. * file on failure.
  5998. */
  5999. static int s2io_change_mtu(struct net_device *dev, int new_mtu)
  6000. {
  6001. struct s2io_nic *sp = dev->priv;
  6002. int ret = 0;
  6003. if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
  6004. DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
  6005. dev->name);
  6006. return -EPERM;
  6007. }
  6008. dev->mtu = new_mtu;
  6009. if (netif_running(dev)) {
  6010. s2io_stop_all_tx_queue(sp);
  6011. s2io_card_down(sp);
  6012. ret = s2io_card_up(sp);
  6013. if (ret) {
  6014. DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
  6015. __FUNCTION__);
  6016. return ret;
  6017. }
  6018. s2io_wake_all_tx_queue(sp);
  6019. } else { /* Device is down */
  6020. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  6021. u64 val64 = new_mtu;
  6022. writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
  6023. }
  6024. return ret;
  6025. }
  6026. /**
  6027. * s2io_set_link - Set the LInk status
  6028. * @data: long pointer to device private structue
  6029. * Description: Sets the link status for the adapter
  6030. */
  6031. static void s2io_set_link(struct work_struct *work)
  6032. {
  6033. struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
  6034. struct net_device *dev = nic->dev;
  6035. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  6036. register u64 val64;
  6037. u16 subid;
  6038. rtnl_lock();
  6039. if (!netif_running(dev))
  6040. goto out_unlock;
  6041. if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
  6042. /* The card is being reset, no point doing anything */
  6043. goto out_unlock;
  6044. }
  6045. subid = nic->pdev->subsystem_device;
  6046. if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
  6047. /*
  6048. * Allow a small delay for the NICs self initiated
  6049. * cleanup to complete.
  6050. */
  6051. msleep(100);
  6052. }
  6053. val64 = readq(&bar0->adapter_status);
  6054. if (LINK_IS_UP(val64)) {
  6055. if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
  6056. if (verify_xena_quiescence(nic)) {
  6057. val64 = readq(&bar0->adapter_control);
  6058. val64 |= ADAPTER_CNTL_EN;
  6059. writeq(val64, &bar0->adapter_control);
  6060. if (CARDS_WITH_FAULTY_LINK_INDICATORS(
  6061. nic->device_type, subid)) {
  6062. val64 = readq(&bar0->gpio_control);
  6063. val64 |= GPIO_CTRL_GPIO_0;
  6064. writeq(val64, &bar0->gpio_control);
  6065. val64 = readq(&bar0->gpio_control);
  6066. } else {
  6067. val64 |= ADAPTER_LED_ON;
  6068. writeq(val64, &bar0->adapter_control);
  6069. }
  6070. nic->device_enabled_once = TRUE;
  6071. } else {
  6072. DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
  6073. DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
  6074. s2io_stop_all_tx_queue(nic);
  6075. }
  6076. }
  6077. val64 = readq(&bar0->adapter_control);
  6078. val64 |= ADAPTER_LED_ON;
  6079. writeq(val64, &bar0->adapter_control);
  6080. s2io_link(nic, LINK_UP);
  6081. } else {
  6082. if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
  6083. subid)) {
  6084. val64 = readq(&bar0->gpio_control);
  6085. val64 &= ~GPIO_CTRL_GPIO_0;
  6086. writeq(val64, &bar0->gpio_control);
  6087. val64 = readq(&bar0->gpio_control);
  6088. }
  6089. /* turn off LED */
  6090. val64 = readq(&bar0->adapter_control);
  6091. val64 = val64 &(~ADAPTER_LED_ON);
  6092. writeq(val64, &bar0->adapter_control);
  6093. s2io_link(nic, LINK_DOWN);
  6094. }
  6095. clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
  6096. out_unlock:
  6097. rtnl_unlock();
  6098. }
  6099. static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
  6100. struct buffAdd *ba,
  6101. struct sk_buff **skb, u64 *temp0, u64 *temp1,
  6102. u64 *temp2, int size)
  6103. {
  6104. struct net_device *dev = sp->dev;
  6105. struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
  6106. if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
  6107. struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
  6108. /* allocate skb */
  6109. if (*skb) {
  6110. DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
  6111. /*
  6112. * As Rx frame are not going to be processed,
  6113. * using same mapped address for the Rxd
  6114. * buffer pointer
  6115. */
  6116. rxdp1->Buffer0_ptr = *temp0;
  6117. } else {
  6118. *skb = dev_alloc_skb(size);
  6119. if (!(*skb)) {
  6120. DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
  6121. DBG_PRINT(INFO_DBG, "memory to allocate ");
  6122. DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
  6123. sp->mac_control.stats_info->sw_stat. \
  6124. mem_alloc_fail_cnt++;
  6125. return -ENOMEM ;
  6126. }
  6127. sp->mac_control.stats_info->sw_stat.mem_allocated
  6128. += (*skb)->truesize;
  6129. /* storing the mapped addr in a temp variable
  6130. * such it will be used for next rxd whose
  6131. * Host Control is NULL
  6132. */
  6133. rxdp1->Buffer0_ptr = *temp0 =
  6134. pci_map_single( sp->pdev, (*skb)->data,
  6135. size - NET_IP_ALIGN,
  6136. PCI_DMA_FROMDEVICE);
  6137. if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
  6138. goto memalloc_failed;
  6139. rxdp->Host_Control = (unsigned long) (*skb);
  6140. }
  6141. } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
  6142. struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
  6143. /* Two buffer Mode */
  6144. if (*skb) {
  6145. rxdp3->Buffer2_ptr = *temp2;
  6146. rxdp3->Buffer0_ptr = *temp0;
  6147. rxdp3->Buffer1_ptr = *temp1;
  6148. } else {
  6149. *skb = dev_alloc_skb(size);
  6150. if (!(*skb)) {
  6151. DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
  6152. DBG_PRINT(INFO_DBG, "memory to allocate ");
  6153. DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
  6154. sp->mac_control.stats_info->sw_stat. \
  6155. mem_alloc_fail_cnt++;
  6156. return -ENOMEM;
  6157. }
  6158. sp->mac_control.stats_info->sw_stat.mem_allocated
  6159. += (*skb)->truesize;
  6160. rxdp3->Buffer2_ptr = *temp2 =
  6161. pci_map_single(sp->pdev, (*skb)->data,
  6162. dev->mtu + 4,
  6163. PCI_DMA_FROMDEVICE);
  6164. if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
  6165. goto memalloc_failed;
  6166. rxdp3->Buffer0_ptr = *temp0 =
  6167. pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
  6168. PCI_DMA_FROMDEVICE);
  6169. if (pci_dma_mapping_error(sp->pdev,
  6170. rxdp3->Buffer0_ptr)) {
  6171. pci_unmap_single (sp->pdev,
  6172. (dma_addr_t)rxdp3->Buffer2_ptr,
  6173. dev->mtu + 4, PCI_DMA_FROMDEVICE);
  6174. goto memalloc_failed;
  6175. }
  6176. rxdp->Host_Control = (unsigned long) (*skb);
  6177. /* Buffer-1 will be dummy buffer not used */
  6178. rxdp3->Buffer1_ptr = *temp1 =
  6179. pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
  6180. PCI_DMA_FROMDEVICE);
  6181. if (pci_dma_mapping_error(sp->pdev,
  6182. rxdp3->Buffer1_ptr)) {
  6183. pci_unmap_single (sp->pdev,
  6184. (dma_addr_t)rxdp3->Buffer0_ptr,
  6185. BUF0_LEN, PCI_DMA_FROMDEVICE);
  6186. pci_unmap_single (sp->pdev,
  6187. (dma_addr_t)rxdp3->Buffer2_ptr,
  6188. dev->mtu + 4, PCI_DMA_FROMDEVICE);
  6189. goto memalloc_failed;
  6190. }
  6191. }
  6192. }
  6193. return 0;
  6194. memalloc_failed:
  6195. stats->pci_map_fail_cnt++;
  6196. stats->mem_freed += (*skb)->truesize;
  6197. dev_kfree_skb(*skb);
  6198. return -ENOMEM;
  6199. }
  6200. static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
  6201. int size)
  6202. {
  6203. struct net_device *dev = sp->dev;
  6204. if (sp->rxd_mode == RXD_MODE_1) {
  6205. rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
  6206. } else if (sp->rxd_mode == RXD_MODE_3B) {
  6207. rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
  6208. rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
  6209. rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
  6210. }
  6211. }
  6212. static int rxd_owner_bit_reset(struct s2io_nic *sp)
  6213. {
  6214. int i, j, k, blk_cnt = 0, size;
  6215. struct mac_info * mac_control = &sp->mac_control;
  6216. struct config_param *config = &sp->config;
  6217. struct net_device *dev = sp->dev;
  6218. struct RxD_t *rxdp = NULL;
  6219. struct sk_buff *skb = NULL;
  6220. struct buffAdd *ba = NULL;
  6221. u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
  6222. /* Calculate the size based on ring mode */
  6223. size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
  6224. HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
  6225. if (sp->rxd_mode == RXD_MODE_1)
  6226. size += NET_IP_ALIGN;
  6227. else if (sp->rxd_mode == RXD_MODE_3B)
  6228. size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
  6229. for (i = 0; i < config->rx_ring_num; i++) {
  6230. blk_cnt = config->rx_cfg[i].num_rxd /
  6231. (rxd_count[sp->rxd_mode] +1);
  6232. for (j = 0; j < blk_cnt; j++) {
  6233. for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
  6234. rxdp = mac_control->rings[i].
  6235. rx_blocks[j].rxds[k].virt_addr;
  6236. if(sp->rxd_mode == RXD_MODE_3B)
  6237. ba = &mac_control->rings[i].ba[j][k];
  6238. if (set_rxd_buffer_pointer(sp, rxdp, ba,
  6239. &skb,(u64 *)&temp0_64,
  6240. (u64 *)&temp1_64,
  6241. (u64 *)&temp2_64,
  6242. size) == -ENOMEM) {
  6243. return 0;
  6244. }
  6245. set_rxd_buffer_size(sp, rxdp, size);
  6246. wmb();
  6247. /* flip the Ownership bit to Hardware */
  6248. rxdp->Control_1 |= RXD_OWN_XENA;
  6249. }
  6250. }
  6251. }
  6252. return 0;
  6253. }
  6254. static int s2io_add_isr(struct s2io_nic * sp)
  6255. {
  6256. int ret = 0;
  6257. struct net_device *dev = sp->dev;
  6258. int err = 0;
  6259. if (sp->config.intr_type == MSI_X)
  6260. ret = s2io_enable_msi_x(sp);
  6261. if (ret) {
  6262. DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
  6263. sp->config.intr_type = INTA;
  6264. }
  6265. /* Store the values of the MSIX table in the struct s2io_nic structure */
  6266. store_xmsi_data(sp);
  6267. /* After proper initialization of H/W, register ISR */
  6268. if (sp->config.intr_type == MSI_X) {
  6269. int i, msix_rx_cnt = 0;
  6270. for (i = 0; i < sp->num_entries; i++) {
  6271. if (sp->s2io_entries[i].in_use == MSIX_FLG) {
  6272. if (sp->s2io_entries[i].type ==
  6273. MSIX_RING_TYPE) {
  6274. sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
  6275. dev->name, i);
  6276. err = request_irq(sp->entries[i].vector,
  6277. s2io_msix_ring_handle, 0,
  6278. sp->desc[i],
  6279. sp->s2io_entries[i].arg);
  6280. } else if (sp->s2io_entries[i].type ==
  6281. MSIX_ALARM_TYPE) {
  6282. sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
  6283. dev->name, i);
  6284. err = request_irq(sp->entries[i].vector,
  6285. s2io_msix_fifo_handle, 0,
  6286. sp->desc[i],
  6287. sp->s2io_entries[i].arg);
  6288. }
  6289. /* if either data or addr is zero print it. */
  6290. if (!(sp->msix_info[i].addr &&
  6291. sp->msix_info[i].data)) {
  6292. DBG_PRINT(ERR_DBG,
  6293. "%s @Addr:0x%llx Data:0x%llx\n",
  6294. sp->desc[i],
  6295. (unsigned long long)
  6296. sp->msix_info[i].addr,
  6297. (unsigned long long)
  6298. ntohl(sp->msix_info[i].data));
  6299. } else
  6300. msix_rx_cnt++;
  6301. if (err) {
  6302. remove_msix_isr(sp);
  6303. DBG_PRINT(ERR_DBG,
  6304. "%s:MSI-X-%d registration "
  6305. "failed\n", dev->name, i);
  6306. DBG_PRINT(ERR_DBG,
  6307. "%s: Defaulting to INTA\n",
  6308. dev->name);
  6309. sp->config.intr_type = INTA;
  6310. break;
  6311. }
  6312. sp->s2io_entries[i].in_use =
  6313. MSIX_REGISTERED_SUCCESS;
  6314. }
  6315. }
  6316. if (!err) {
  6317. printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
  6318. --msix_rx_cnt);
  6319. DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
  6320. " through alarm vector\n");
  6321. }
  6322. }
  6323. if (sp->config.intr_type == INTA) {
  6324. err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
  6325. sp->name, dev);
  6326. if (err) {
  6327. DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
  6328. dev->name);
  6329. return -1;
  6330. }
  6331. }
  6332. return 0;
  6333. }
  6334. static void s2io_rem_isr(struct s2io_nic * sp)
  6335. {
  6336. if (sp->config.intr_type == MSI_X)
  6337. remove_msix_isr(sp);
  6338. else
  6339. remove_inta_isr(sp);
  6340. }
  6341. static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
  6342. {
  6343. int cnt = 0;
  6344. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  6345. register u64 val64 = 0;
  6346. struct config_param *config;
  6347. config = &sp->config;
  6348. if (!is_s2io_card_up(sp))
  6349. return;
  6350. del_timer_sync(&sp->alarm_timer);
  6351. /* If s2io_set_link task is executing, wait till it completes. */
  6352. while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
  6353. msleep(50);
  6354. }
  6355. clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
  6356. /* Disable napi */
  6357. if (sp->config.napi) {
  6358. int off = 0;
  6359. if (config->intr_type == MSI_X) {
  6360. for (; off < sp->config.rx_ring_num; off++)
  6361. napi_disable(&sp->mac_control.rings[off].napi);
  6362. }
  6363. else
  6364. napi_disable(&sp->napi);
  6365. }
  6366. /* disable Tx and Rx traffic on the NIC */
  6367. if (do_io)
  6368. stop_nic(sp);
  6369. s2io_rem_isr(sp);
  6370. /* stop the tx queue, indicate link down */
  6371. s2io_link(sp, LINK_DOWN);
  6372. /* Check if the device is Quiescent and then Reset the NIC */
  6373. while(do_io) {
  6374. /* As per the HW requirement we need to replenish the
  6375. * receive buffer to avoid the ring bump. Since there is
  6376. * no intention of processing the Rx frame at this pointwe are
  6377. * just settting the ownership bit of rxd in Each Rx
  6378. * ring to HW and set the appropriate buffer size
  6379. * based on the ring mode
  6380. */
  6381. rxd_owner_bit_reset(sp);
  6382. val64 = readq(&bar0->adapter_status);
  6383. if (verify_xena_quiescence(sp)) {
  6384. if(verify_pcc_quiescent(sp, sp->device_enabled_once))
  6385. break;
  6386. }
  6387. msleep(50);
  6388. cnt++;
  6389. if (cnt == 10) {
  6390. DBG_PRINT(ERR_DBG,
  6391. "s2io_close:Device not Quiescent ");
  6392. DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
  6393. (unsigned long long) val64);
  6394. break;
  6395. }
  6396. }
  6397. if (do_io)
  6398. s2io_reset(sp);
  6399. /* Free all Tx buffers */
  6400. free_tx_buffers(sp);
  6401. /* Free all Rx buffers */
  6402. free_rx_buffers(sp);
  6403. clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
  6404. }
  6405. static void s2io_card_down(struct s2io_nic * sp)
  6406. {
  6407. do_s2io_card_down(sp, 1);
  6408. }
  6409. static int s2io_card_up(struct s2io_nic * sp)
  6410. {
  6411. int i, ret = 0;
  6412. struct mac_info *mac_control;
  6413. struct config_param *config;
  6414. struct net_device *dev = (struct net_device *) sp->dev;
  6415. u16 interruptible;
  6416. /* Initialize the H/W I/O registers */
  6417. ret = init_nic(sp);
  6418. if (ret != 0) {
  6419. DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
  6420. dev->name);
  6421. if (ret != -EIO)
  6422. s2io_reset(sp);
  6423. return ret;
  6424. }
  6425. /*
  6426. * Initializing the Rx buffers. For now we are considering only 1
  6427. * Rx ring and initializing buffers into 30 Rx blocks
  6428. */
  6429. mac_control = &sp->mac_control;
  6430. config = &sp->config;
  6431. for (i = 0; i < config->rx_ring_num; i++) {
  6432. mac_control->rings[i].mtu = dev->mtu;
  6433. ret = fill_rx_buffers(sp, &mac_control->rings[i], 1);
  6434. if (ret) {
  6435. DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
  6436. dev->name);
  6437. s2io_reset(sp);
  6438. free_rx_buffers(sp);
  6439. return -ENOMEM;
  6440. }
  6441. DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
  6442. mac_control->rings[i].rx_bufs_left);
  6443. }
  6444. /* Initialise napi */
  6445. if (config->napi) {
  6446. int i;
  6447. if (config->intr_type == MSI_X) {
  6448. for (i = 0; i < sp->config.rx_ring_num; i++)
  6449. napi_enable(&sp->mac_control.rings[i].napi);
  6450. } else {
  6451. napi_enable(&sp->napi);
  6452. }
  6453. }
  6454. /* Maintain the state prior to the open */
  6455. if (sp->promisc_flg)
  6456. sp->promisc_flg = 0;
  6457. if (sp->m_cast_flg) {
  6458. sp->m_cast_flg = 0;
  6459. sp->all_multi_pos= 0;
  6460. }
  6461. /* Setting its receive mode */
  6462. s2io_set_multicast(dev);
  6463. if (sp->lro) {
  6464. /* Initialize max aggregatable pkts per session based on MTU */
  6465. sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
  6466. /* Check if we can use(if specified) user provided value */
  6467. if (lro_max_pkts < sp->lro_max_aggr_per_sess)
  6468. sp->lro_max_aggr_per_sess = lro_max_pkts;
  6469. }
  6470. /* Enable Rx Traffic and interrupts on the NIC */
  6471. if (start_nic(sp)) {
  6472. DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
  6473. s2io_reset(sp);
  6474. free_rx_buffers(sp);
  6475. return -ENODEV;
  6476. }
  6477. /* Add interrupt service routine */
  6478. if (s2io_add_isr(sp) != 0) {
  6479. if (sp->config.intr_type == MSI_X)
  6480. s2io_rem_isr(sp);
  6481. s2io_reset(sp);
  6482. free_rx_buffers(sp);
  6483. return -ENODEV;
  6484. }
  6485. S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
  6486. set_bit(__S2IO_STATE_CARD_UP, &sp->state);
  6487. /* Enable select interrupts */
  6488. en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
  6489. if (sp->config.intr_type != INTA) {
  6490. interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
  6491. en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
  6492. } else {
  6493. interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
  6494. interruptible |= TX_PIC_INTR;
  6495. en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
  6496. }
  6497. return 0;
  6498. }
  6499. /**
  6500. * s2io_restart_nic - Resets the NIC.
  6501. * @data : long pointer to the device private structure
  6502. * Description:
  6503. * This function is scheduled to be run by the s2io_tx_watchdog
  6504. * function after 0.5 secs to reset the NIC. The idea is to reduce
  6505. * the run time of the watch dog routine which is run holding a
  6506. * spin lock.
  6507. */
  6508. static void s2io_restart_nic(struct work_struct *work)
  6509. {
  6510. struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
  6511. struct net_device *dev = sp->dev;
  6512. rtnl_lock();
  6513. if (!netif_running(dev))
  6514. goto out_unlock;
  6515. s2io_card_down(sp);
  6516. if (s2io_card_up(sp)) {
  6517. DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
  6518. dev->name);
  6519. }
  6520. s2io_wake_all_tx_queue(sp);
  6521. DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
  6522. dev->name);
  6523. out_unlock:
  6524. rtnl_unlock();
  6525. }
  6526. /**
  6527. * s2io_tx_watchdog - Watchdog for transmit side.
  6528. * @dev : Pointer to net device structure
  6529. * Description:
  6530. * This function is triggered if the Tx Queue is stopped
  6531. * for a pre-defined amount of time when the Interface is still up.
  6532. * If the Interface is jammed in such a situation, the hardware is
  6533. * reset (by s2io_close) and restarted again (by s2io_open) to
  6534. * overcome any problem that might have been caused in the hardware.
  6535. * Return value:
  6536. * void
  6537. */
  6538. static void s2io_tx_watchdog(struct net_device *dev)
  6539. {
  6540. struct s2io_nic *sp = dev->priv;
  6541. if (netif_carrier_ok(dev)) {
  6542. sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
  6543. schedule_work(&sp->rst_timer_task);
  6544. sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
  6545. }
  6546. }
  6547. /**
  6548. * rx_osm_handler - To perform some OS related operations on SKB.
  6549. * @sp: private member of the device structure,pointer to s2io_nic structure.
  6550. * @skb : the socket buffer pointer.
  6551. * @len : length of the packet
  6552. * @cksum : FCS checksum of the frame.
  6553. * @ring_no : the ring from which this RxD was extracted.
  6554. * Description:
  6555. * This function is called by the Rx interrupt serivce routine to perform
  6556. * some OS related operations on the SKB before passing it to the upper
  6557. * layers. It mainly checks if the checksum is OK, if so adds it to the
  6558. * SKBs cksum variable, increments the Rx packet count and passes the SKB
  6559. * to the upper layer. If the checksum is wrong, it increments the Rx
  6560. * packet error count, frees the SKB and returns error.
  6561. * Return value:
  6562. * SUCCESS on success and -1 on failure.
  6563. */
  6564. static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
  6565. {
  6566. struct s2io_nic *sp = ring_data->nic;
  6567. struct net_device *dev = (struct net_device *) ring_data->dev;
  6568. struct sk_buff *skb = (struct sk_buff *)
  6569. ((unsigned long) rxdp->Host_Control);
  6570. int ring_no = ring_data->ring_no;
  6571. u16 l3_csum, l4_csum;
  6572. unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
  6573. struct lro *lro;
  6574. u8 err_mask;
  6575. skb->dev = dev;
  6576. if (err) {
  6577. /* Check for parity error */
  6578. if (err & 0x1) {
  6579. sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
  6580. }
  6581. err_mask = err >> 48;
  6582. switch(err_mask) {
  6583. case 1:
  6584. sp->mac_control.stats_info->sw_stat.
  6585. rx_parity_err_cnt++;
  6586. break;
  6587. case 2:
  6588. sp->mac_control.stats_info->sw_stat.
  6589. rx_abort_cnt++;
  6590. break;
  6591. case 3:
  6592. sp->mac_control.stats_info->sw_stat.
  6593. rx_parity_abort_cnt++;
  6594. break;
  6595. case 4:
  6596. sp->mac_control.stats_info->sw_stat.
  6597. rx_rda_fail_cnt++;
  6598. break;
  6599. case 5:
  6600. sp->mac_control.stats_info->sw_stat.
  6601. rx_unkn_prot_cnt++;
  6602. break;
  6603. case 6:
  6604. sp->mac_control.stats_info->sw_stat.
  6605. rx_fcs_err_cnt++;
  6606. break;
  6607. case 7:
  6608. sp->mac_control.stats_info->sw_stat.
  6609. rx_buf_size_err_cnt++;
  6610. break;
  6611. case 8:
  6612. sp->mac_control.stats_info->sw_stat.
  6613. rx_rxd_corrupt_cnt++;
  6614. break;
  6615. case 15:
  6616. sp->mac_control.stats_info->sw_stat.
  6617. rx_unkn_err_cnt++;
  6618. break;
  6619. }
  6620. /*
  6621. * Drop the packet if bad transfer code. Exception being
  6622. * 0x5, which could be due to unsupported IPv6 extension header.
  6623. * In this case, we let stack handle the packet.
  6624. * Note that in this case, since checksum will be incorrect,
  6625. * stack will validate the same.
  6626. */
  6627. if (err_mask != 0x5) {
  6628. DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
  6629. dev->name, err_mask);
  6630. dev->stats.rx_crc_errors++;
  6631. sp->mac_control.stats_info->sw_stat.mem_freed
  6632. += skb->truesize;
  6633. dev_kfree_skb(skb);
  6634. ring_data->rx_bufs_left -= 1;
  6635. rxdp->Host_Control = 0;
  6636. return 0;
  6637. }
  6638. }
  6639. /* Updating statistics */
  6640. ring_data->rx_packets++;
  6641. rxdp->Host_Control = 0;
  6642. if (sp->rxd_mode == RXD_MODE_1) {
  6643. int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
  6644. ring_data->rx_bytes += len;
  6645. skb_put(skb, len);
  6646. } else if (sp->rxd_mode == RXD_MODE_3B) {
  6647. int get_block = ring_data->rx_curr_get_info.block_index;
  6648. int get_off = ring_data->rx_curr_get_info.offset;
  6649. int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
  6650. int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
  6651. unsigned char *buff = skb_push(skb, buf0_len);
  6652. struct buffAdd *ba = &ring_data->ba[get_block][get_off];
  6653. ring_data->rx_bytes += buf0_len + buf2_len;
  6654. memcpy(buff, ba->ba_0, buf0_len);
  6655. skb_put(skb, buf2_len);
  6656. }
  6657. if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!ring_data->lro) ||
  6658. (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
  6659. (sp->rx_csum)) {
  6660. l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
  6661. l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
  6662. if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
  6663. /*
  6664. * NIC verifies if the Checksum of the received
  6665. * frame is Ok or not and accordingly returns
  6666. * a flag in the RxD.
  6667. */
  6668. skb->ip_summed = CHECKSUM_UNNECESSARY;
  6669. if (ring_data->lro) {
  6670. u32 tcp_len;
  6671. u8 *tcp;
  6672. int ret = 0;
  6673. ret = s2io_club_tcp_session(ring_data,
  6674. skb->data, &tcp, &tcp_len, &lro,
  6675. rxdp, sp);
  6676. switch (ret) {
  6677. case 3: /* Begin anew */
  6678. lro->parent = skb;
  6679. goto aggregate;
  6680. case 1: /* Aggregate */
  6681. {
  6682. lro_append_pkt(sp, lro,
  6683. skb, tcp_len);
  6684. goto aggregate;
  6685. }
  6686. case 4: /* Flush session */
  6687. {
  6688. lro_append_pkt(sp, lro,
  6689. skb, tcp_len);
  6690. queue_rx_frame(lro->parent,
  6691. lro->vlan_tag);
  6692. clear_lro_session(lro);
  6693. sp->mac_control.stats_info->
  6694. sw_stat.flush_max_pkts++;
  6695. goto aggregate;
  6696. }
  6697. case 2: /* Flush both */
  6698. lro->parent->data_len =
  6699. lro->frags_len;
  6700. sp->mac_control.stats_info->
  6701. sw_stat.sending_both++;
  6702. queue_rx_frame(lro->parent,
  6703. lro->vlan_tag);
  6704. clear_lro_session(lro);
  6705. goto send_up;
  6706. case 0: /* sessions exceeded */
  6707. case -1: /* non-TCP or not
  6708. * L2 aggregatable
  6709. */
  6710. case 5: /*
  6711. * First pkt in session not
  6712. * L3/L4 aggregatable
  6713. */
  6714. break;
  6715. default:
  6716. DBG_PRINT(ERR_DBG,
  6717. "%s: Samadhana!!\n",
  6718. __FUNCTION__);
  6719. BUG();
  6720. }
  6721. }
  6722. } else {
  6723. /*
  6724. * Packet with erroneous checksum, let the
  6725. * upper layers deal with it.
  6726. */
  6727. skb->ip_summed = CHECKSUM_NONE;
  6728. }
  6729. } else
  6730. skb->ip_summed = CHECKSUM_NONE;
  6731. sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
  6732. send_up:
  6733. queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
  6734. dev->last_rx = jiffies;
  6735. aggregate:
  6736. sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
  6737. return SUCCESS;
  6738. }
  6739. /**
  6740. * s2io_link - stops/starts the Tx queue.
  6741. * @sp : private member of the device structure, which is a pointer to the
  6742. * s2io_nic structure.
  6743. * @link : inidicates whether link is UP/DOWN.
  6744. * Description:
  6745. * This function stops/starts the Tx queue depending on whether the link
  6746. * status of the NIC is is down or up. This is called by the Alarm
  6747. * interrupt handler whenever a link change interrupt comes up.
  6748. * Return value:
  6749. * void.
  6750. */
  6751. static void s2io_link(struct s2io_nic * sp, int link)
  6752. {
  6753. struct net_device *dev = (struct net_device *) sp->dev;
  6754. if (link != sp->last_link_state) {
  6755. init_tti(sp, link);
  6756. if (link == LINK_DOWN) {
  6757. DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
  6758. s2io_stop_all_tx_queue(sp);
  6759. netif_carrier_off(dev);
  6760. if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
  6761. sp->mac_control.stats_info->sw_stat.link_up_time =
  6762. jiffies - sp->start_time;
  6763. sp->mac_control.stats_info->sw_stat.link_down_cnt++;
  6764. } else {
  6765. DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
  6766. if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
  6767. sp->mac_control.stats_info->sw_stat.link_down_time =
  6768. jiffies - sp->start_time;
  6769. sp->mac_control.stats_info->sw_stat.link_up_cnt++;
  6770. netif_carrier_on(dev);
  6771. s2io_wake_all_tx_queue(sp);
  6772. }
  6773. }
  6774. sp->last_link_state = link;
  6775. sp->start_time = jiffies;
  6776. }
  6777. /**
  6778. * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
  6779. * @sp : private member of the device structure, which is a pointer to the
  6780. * s2io_nic structure.
  6781. * Description:
  6782. * This function initializes a few of the PCI and PCI-X configuration registers
  6783. * with recommended values.
  6784. * Return value:
  6785. * void
  6786. */
  6787. static void s2io_init_pci(struct s2io_nic * sp)
  6788. {
  6789. u16 pci_cmd = 0, pcix_cmd = 0;
  6790. /* Enable Data Parity Error Recovery in PCI-X command register. */
  6791. pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  6792. &(pcix_cmd));
  6793. pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  6794. (pcix_cmd | 1));
  6795. pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  6796. &(pcix_cmd));
  6797. /* Set the PErr Response bit in PCI command register. */
  6798. pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
  6799. pci_write_config_word(sp->pdev, PCI_COMMAND,
  6800. (pci_cmd | PCI_COMMAND_PARITY));
  6801. pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
  6802. }
  6803. static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
  6804. u8 *dev_multiq)
  6805. {
  6806. if ((tx_fifo_num > MAX_TX_FIFOS) ||
  6807. (tx_fifo_num < 1)) {
  6808. DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
  6809. "(%d) not supported\n", tx_fifo_num);
  6810. if (tx_fifo_num < 1)
  6811. tx_fifo_num = 1;
  6812. else
  6813. tx_fifo_num = MAX_TX_FIFOS;
  6814. DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
  6815. DBG_PRINT(ERR_DBG, "tx fifos\n");
  6816. }
  6817. if (multiq)
  6818. *dev_multiq = multiq;
  6819. if (tx_steering_type && (1 == tx_fifo_num)) {
  6820. if (tx_steering_type != TX_DEFAULT_STEERING)
  6821. DBG_PRINT(ERR_DBG,
  6822. "s2io: Tx steering is not supported with "
  6823. "one fifo. Disabling Tx steering.\n");
  6824. tx_steering_type = NO_STEERING;
  6825. }
  6826. if ((tx_steering_type < NO_STEERING) ||
  6827. (tx_steering_type > TX_DEFAULT_STEERING)) {
  6828. DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
  6829. "supported\n");
  6830. DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
  6831. tx_steering_type = NO_STEERING;
  6832. }
  6833. if (rx_ring_num > MAX_RX_RINGS) {
  6834. DBG_PRINT(ERR_DBG, "s2io: Requested number of rx rings not "
  6835. "supported\n");
  6836. DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
  6837. MAX_RX_RINGS);
  6838. rx_ring_num = MAX_RX_RINGS;
  6839. }
  6840. if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
  6841. DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
  6842. "Defaulting to INTA\n");
  6843. *dev_intr_type = INTA;
  6844. }
  6845. if ((*dev_intr_type == MSI_X) &&
  6846. ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
  6847. (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
  6848. DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
  6849. "Defaulting to INTA\n");
  6850. *dev_intr_type = INTA;
  6851. }
  6852. if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
  6853. DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
  6854. DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
  6855. rx_ring_mode = 1;
  6856. }
  6857. return SUCCESS;
  6858. }
  6859. /**
  6860. * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
  6861. * or Traffic class respectively.
  6862. * @nic: device private variable
  6863. * Description: The function configures the receive steering to
  6864. * desired receive ring.
  6865. * Return Value: SUCCESS on success and
  6866. * '-1' on failure (endian settings incorrect).
  6867. */
  6868. static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
  6869. {
  6870. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  6871. register u64 val64 = 0;
  6872. if (ds_codepoint > 63)
  6873. return FAILURE;
  6874. val64 = RTS_DS_MEM_DATA(ring);
  6875. writeq(val64, &bar0->rts_ds_mem_data);
  6876. val64 = RTS_DS_MEM_CTRL_WE |
  6877. RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
  6878. RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
  6879. writeq(val64, &bar0->rts_ds_mem_ctrl);
  6880. return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
  6881. RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
  6882. S2IO_BIT_RESET);
  6883. }
  6884. /**
  6885. * s2io_init_nic - Initialization of the adapter .
  6886. * @pdev : structure containing the PCI related information of the device.
  6887. * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
  6888. * Description:
  6889. * The function initializes an adapter identified by the pci_dec structure.
  6890. * All OS related initialization including memory and device structure and
  6891. * initlaization of the device private variable is done. Also the swapper
  6892. * control register is initialized to enable read and write into the I/O
  6893. * registers of the device.
  6894. * Return value:
  6895. * returns 0 on success and negative on failure.
  6896. */
  6897. static int __devinit
  6898. s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
  6899. {
  6900. struct s2io_nic *sp;
  6901. struct net_device *dev;
  6902. int i, j, ret;
  6903. int dma_flag = FALSE;
  6904. u32 mac_up, mac_down;
  6905. u64 val64 = 0, tmp64 = 0;
  6906. struct XENA_dev_config __iomem *bar0 = NULL;
  6907. u16 subid;
  6908. struct mac_info *mac_control;
  6909. struct config_param *config;
  6910. int mode;
  6911. u8 dev_intr_type = intr_type;
  6912. u8 dev_multiq = 0;
  6913. DECLARE_MAC_BUF(mac);
  6914. ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
  6915. if (ret)
  6916. return ret;
  6917. if ((ret = pci_enable_device(pdev))) {
  6918. DBG_PRINT(ERR_DBG,
  6919. "s2io_init_nic: pci_enable_device failed\n");
  6920. return ret;
  6921. }
  6922. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  6923. DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
  6924. dma_flag = TRUE;
  6925. if (pci_set_consistent_dma_mask
  6926. (pdev, DMA_64BIT_MASK)) {
  6927. DBG_PRINT(ERR_DBG,
  6928. "Unable to obtain 64bit DMA for \
  6929. consistent allocations\n");
  6930. pci_disable_device(pdev);
  6931. return -ENOMEM;
  6932. }
  6933. } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  6934. DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
  6935. } else {
  6936. pci_disable_device(pdev);
  6937. return -ENOMEM;
  6938. }
  6939. if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
  6940. DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
  6941. pci_disable_device(pdev);
  6942. return -ENODEV;
  6943. }
  6944. if (dev_multiq)
  6945. dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
  6946. else
  6947. dev = alloc_etherdev(sizeof(struct s2io_nic));
  6948. if (dev == NULL) {
  6949. DBG_PRINT(ERR_DBG, "Device allocation failed\n");
  6950. pci_disable_device(pdev);
  6951. pci_release_regions(pdev);
  6952. return -ENODEV;
  6953. }
  6954. pci_set_master(pdev);
  6955. pci_set_drvdata(pdev, dev);
  6956. SET_NETDEV_DEV(dev, &pdev->dev);
  6957. /* Private member variable initialized to s2io NIC structure */
  6958. sp = dev->priv;
  6959. memset(sp, 0, sizeof(struct s2io_nic));
  6960. sp->dev = dev;
  6961. sp->pdev = pdev;
  6962. sp->high_dma_flag = dma_flag;
  6963. sp->device_enabled_once = FALSE;
  6964. if (rx_ring_mode == 1)
  6965. sp->rxd_mode = RXD_MODE_1;
  6966. if (rx_ring_mode == 2)
  6967. sp->rxd_mode = RXD_MODE_3B;
  6968. sp->config.intr_type = dev_intr_type;
  6969. if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
  6970. (pdev->device == PCI_DEVICE_ID_HERC_UNI))
  6971. sp->device_type = XFRAME_II_DEVICE;
  6972. else
  6973. sp->device_type = XFRAME_I_DEVICE;
  6974. sp->lro = lro_enable;
  6975. /* Initialize some PCI/PCI-X fields of the NIC. */
  6976. s2io_init_pci(sp);
  6977. /*
  6978. * Setting the device configuration parameters.
  6979. * Most of these parameters can be specified by the user during
  6980. * module insertion as they are module loadable parameters. If
  6981. * these parameters are not not specified during load time, they
  6982. * are initialized with default values.
  6983. */
  6984. mac_control = &sp->mac_control;
  6985. config = &sp->config;
  6986. config->napi = napi;
  6987. config->tx_steering_type = tx_steering_type;
  6988. /* Tx side parameters. */
  6989. if (config->tx_steering_type == TX_PRIORITY_STEERING)
  6990. config->tx_fifo_num = MAX_TX_FIFOS;
  6991. else
  6992. config->tx_fifo_num = tx_fifo_num;
  6993. /* Initialize the fifos used for tx steering */
  6994. if (config->tx_fifo_num < 5) {
  6995. if (config->tx_fifo_num == 1)
  6996. sp->total_tcp_fifos = 1;
  6997. else
  6998. sp->total_tcp_fifos = config->tx_fifo_num - 1;
  6999. sp->udp_fifo_idx = config->tx_fifo_num - 1;
  7000. sp->total_udp_fifos = 1;
  7001. sp->other_fifo_idx = sp->total_tcp_fifos - 1;
  7002. } else {
  7003. sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
  7004. FIFO_OTHER_MAX_NUM);
  7005. sp->udp_fifo_idx = sp->total_tcp_fifos;
  7006. sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
  7007. sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
  7008. }
  7009. config->multiq = dev_multiq;
  7010. for (i = 0; i < config->tx_fifo_num; i++) {
  7011. config->tx_cfg[i].fifo_len = tx_fifo_len[i];
  7012. config->tx_cfg[i].fifo_priority = i;
  7013. }
  7014. /* mapping the QoS priority to the configured fifos */
  7015. for (i = 0; i < MAX_TX_FIFOS; i++)
  7016. config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
  7017. /* map the hashing selector table to the configured fifos */
  7018. for (i = 0; i < config->tx_fifo_num; i++)
  7019. sp->fifo_selector[i] = fifo_selector[i];
  7020. config->tx_intr_type = TXD_INT_TYPE_UTILZ;
  7021. for (i = 0; i < config->tx_fifo_num; i++) {
  7022. config->tx_cfg[i].f_no_snoop =
  7023. (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
  7024. if (config->tx_cfg[i].fifo_len < 65) {
  7025. config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
  7026. break;
  7027. }
  7028. }
  7029. /* + 2 because one Txd for skb->data and one Txd for UFO */
  7030. config->max_txds = MAX_SKB_FRAGS + 2;
  7031. /* Rx side parameters. */
  7032. config->rx_ring_num = rx_ring_num;
  7033. for (i = 0; i < config->rx_ring_num; i++) {
  7034. config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
  7035. (rxd_count[sp->rxd_mode] + 1);
  7036. config->rx_cfg[i].ring_priority = i;
  7037. mac_control->rings[i].rx_bufs_left = 0;
  7038. mac_control->rings[i].rxd_mode = sp->rxd_mode;
  7039. mac_control->rings[i].rxd_count = rxd_count[sp->rxd_mode];
  7040. mac_control->rings[i].pdev = sp->pdev;
  7041. mac_control->rings[i].dev = sp->dev;
  7042. }
  7043. for (i = 0; i < rx_ring_num; i++) {
  7044. config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
  7045. config->rx_cfg[i].f_no_snoop =
  7046. (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
  7047. }
  7048. /* Setting Mac Control parameters */
  7049. mac_control->rmac_pause_time = rmac_pause_time;
  7050. mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
  7051. mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
  7052. /* initialize the shared memory used by the NIC and the host */
  7053. if (init_shared_mem(sp)) {
  7054. DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
  7055. dev->name);
  7056. ret = -ENOMEM;
  7057. goto mem_alloc_failed;
  7058. }
  7059. sp->bar0 = ioremap(pci_resource_start(pdev, 0),
  7060. pci_resource_len(pdev, 0));
  7061. if (!sp->bar0) {
  7062. DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
  7063. dev->name);
  7064. ret = -ENOMEM;
  7065. goto bar0_remap_failed;
  7066. }
  7067. sp->bar1 = ioremap(pci_resource_start(pdev, 2),
  7068. pci_resource_len(pdev, 2));
  7069. if (!sp->bar1) {
  7070. DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
  7071. dev->name);
  7072. ret = -ENOMEM;
  7073. goto bar1_remap_failed;
  7074. }
  7075. dev->irq = pdev->irq;
  7076. dev->base_addr = (unsigned long) sp->bar0;
  7077. /* Initializing the BAR1 address as the start of the FIFO pointer. */
  7078. for (j = 0; j < MAX_TX_FIFOS; j++) {
  7079. mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
  7080. (sp->bar1 + (j * 0x00020000));
  7081. }
  7082. /* Driver entry points */
  7083. dev->open = &s2io_open;
  7084. dev->stop = &s2io_close;
  7085. dev->hard_start_xmit = &s2io_xmit;
  7086. dev->get_stats = &s2io_get_stats;
  7087. dev->set_multicast_list = &s2io_set_multicast;
  7088. dev->do_ioctl = &s2io_ioctl;
  7089. dev->set_mac_address = &s2io_set_mac_addr;
  7090. dev->change_mtu = &s2io_change_mtu;
  7091. SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
  7092. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  7093. dev->vlan_rx_register = s2io_vlan_rx_register;
  7094. dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
  7095. /*
  7096. * will use eth_mac_addr() for dev->set_mac_address
  7097. * mac address will be set every time dev->open() is called
  7098. */
  7099. #ifdef CONFIG_NET_POLL_CONTROLLER
  7100. dev->poll_controller = s2io_netpoll;
  7101. #endif
  7102. dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
  7103. if (sp->high_dma_flag == TRUE)
  7104. dev->features |= NETIF_F_HIGHDMA;
  7105. dev->features |= NETIF_F_TSO;
  7106. dev->features |= NETIF_F_TSO6;
  7107. if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
  7108. dev->features |= NETIF_F_UFO;
  7109. dev->features |= NETIF_F_HW_CSUM;
  7110. }
  7111. dev->tx_timeout = &s2io_tx_watchdog;
  7112. dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
  7113. INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
  7114. INIT_WORK(&sp->set_link_task, s2io_set_link);
  7115. pci_save_state(sp->pdev);
  7116. /* Setting swapper control on the NIC, for proper reset operation */
  7117. if (s2io_set_swapper(sp)) {
  7118. DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
  7119. dev->name);
  7120. ret = -EAGAIN;
  7121. goto set_swap_failed;
  7122. }
  7123. /* Verify if the Herc works on the slot its placed into */
  7124. if (sp->device_type & XFRAME_II_DEVICE) {
  7125. mode = s2io_verify_pci_mode(sp);
  7126. if (mode < 0) {
  7127. DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
  7128. DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
  7129. ret = -EBADSLT;
  7130. goto set_swap_failed;
  7131. }
  7132. }
  7133. if (sp->config.intr_type == MSI_X) {
  7134. sp->num_entries = config->rx_ring_num + 1;
  7135. ret = s2io_enable_msi_x(sp);
  7136. if (!ret) {
  7137. ret = s2io_test_msi(sp);
  7138. /* rollback MSI-X, will re-enable during add_isr() */
  7139. remove_msix_isr(sp);
  7140. }
  7141. if (ret) {
  7142. DBG_PRINT(ERR_DBG,
  7143. "%s: MSI-X requested but failed to enable\n",
  7144. dev->name);
  7145. sp->config.intr_type = INTA;
  7146. }
  7147. }
  7148. if (config->intr_type == MSI_X) {
  7149. for (i = 0; i < config->rx_ring_num ; i++)
  7150. netif_napi_add(dev, &mac_control->rings[i].napi,
  7151. s2io_poll_msix, 64);
  7152. } else {
  7153. netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
  7154. }
  7155. /* Not needed for Herc */
  7156. if (sp->device_type & XFRAME_I_DEVICE) {
  7157. /*
  7158. * Fix for all "FFs" MAC address problems observed on
  7159. * Alpha platforms
  7160. */
  7161. fix_mac_address(sp);
  7162. s2io_reset(sp);
  7163. }
  7164. /*
  7165. * MAC address initialization.
  7166. * For now only one mac address will be read and used.
  7167. */
  7168. bar0 = sp->bar0;
  7169. val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  7170. RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
  7171. writeq(val64, &bar0->rmac_addr_cmd_mem);
  7172. wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  7173. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
  7174. tmp64 = readq(&bar0->rmac_addr_data0_mem);
  7175. mac_down = (u32) tmp64;
  7176. mac_up = (u32) (tmp64 >> 32);
  7177. sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
  7178. sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
  7179. sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
  7180. sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
  7181. sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
  7182. sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
  7183. /* Set the factory defined MAC address initially */
  7184. dev->addr_len = ETH_ALEN;
  7185. memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
  7186. memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
  7187. /* initialize number of multicast & unicast MAC entries variables */
  7188. if (sp->device_type == XFRAME_I_DEVICE) {
  7189. config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
  7190. config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
  7191. config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
  7192. } else if (sp->device_type == XFRAME_II_DEVICE) {
  7193. config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
  7194. config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
  7195. config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
  7196. }
  7197. /* store mac addresses from CAM to s2io_nic structure */
  7198. do_s2io_store_unicast_mc(sp);
  7199. /* Configure MSIX vector for number of rings configured plus one */
  7200. if ((sp->device_type == XFRAME_II_DEVICE) &&
  7201. (config->intr_type == MSI_X))
  7202. sp->num_entries = config->rx_ring_num + 1;
  7203. /* Store the values of the MSIX table in the s2io_nic structure */
  7204. store_xmsi_data(sp);
  7205. /* reset Nic and bring it to known state */
  7206. s2io_reset(sp);
  7207. /*
  7208. * Initialize link state flags
  7209. * and the card state parameter
  7210. */
  7211. sp->state = 0;
  7212. /* Initialize spinlocks */
  7213. for (i = 0; i < sp->config.tx_fifo_num; i++)
  7214. spin_lock_init(&mac_control->fifos[i].tx_lock);
  7215. /*
  7216. * SXE-002: Configure link and activity LED to init state
  7217. * on driver load.
  7218. */
  7219. subid = sp->pdev->subsystem_device;
  7220. if ((subid & 0xFF) >= 0x07) {
  7221. val64 = readq(&bar0->gpio_control);
  7222. val64 |= 0x0000800000000000ULL;
  7223. writeq(val64, &bar0->gpio_control);
  7224. val64 = 0x0411040400000000ULL;
  7225. writeq(val64, (void __iomem *) bar0 + 0x2700);
  7226. val64 = readq(&bar0->gpio_control);
  7227. }
  7228. sp->rx_csum = 1; /* Rx chksum verify enabled by default */
  7229. if (register_netdev(dev)) {
  7230. DBG_PRINT(ERR_DBG, "Device registration failed\n");
  7231. ret = -ENODEV;
  7232. goto register_failed;
  7233. }
  7234. s2io_vpd_read(sp);
  7235. DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
  7236. DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
  7237. sp->product_name, pdev->revision);
  7238. DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
  7239. s2io_driver_version);
  7240. DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
  7241. dev->name, print_mac(mac, dev->dev_addr));
  7242. DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
  7243. if (sp->device_type & XFRAME_II_DEVICE) {
  7244. mode = s2io_print_pci_mode(sp);
  7245. if (mode < 0) {
  7246. DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
  7247. ret = -EBADSLT;
  7248. unregister_netdev(dev);
  7249. goto set_swap_failed;
  7250. }
  7251. }
  7252. switch(sp->rxd_mode) {
  7253. case RXD_MODE_1:
  7254. DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
  7255. dev->name);
  7256. break;
  7257. case RXD_MODE_3B:
  7258. DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
  7259. dev->name);
  7260. break;
  7261. }
  7262. switch (sp->config.napi) {
  7263. case 0:
  7264. DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
  7265. break;
  7266. case 1:
  7267. DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
  7268. break;
  7269. }
  7270. DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
  7271. sp->config.tx_fifo_num);
  7272. DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
  7273. sp->config.rx_ring_num);
  7274. switch(sp->config.intr_type) {
  7275. case INTA:
  7276. DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
  7277. break;
  7278. case MSI_X:
  7279. DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
  7280. break;
  7281. }
  7282. if (sp->config.multiq) {
  7283. for (i = 0; i < sp->config.tx_fifo_num; i++)
  7284. mac_control->fifos[i].multiq = config->multiq;
  7285. DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
  7286. dev->name);
  7287. } else
  7288. DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
  7289. dev->name);
  7290. switch (sp->config.tx_steering_type) {
  7291. case NO_STEERING:
  7292. DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
  7293. " transmit\n", dev->name);
  7294. break;
  7295. case TX_PRIORITY_STEERING:
  7296. DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
  7297. " transmit\n", dev->name);
  7298. break;
  7299. case TX_DEFAULT_STEERING:
  7300. DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
  7301. " transmit\n", dev->name);
  7302. }
  7303. if (sp->lro)
  7304. DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
  7305. dev->name);
  7306. if (ufo)
  7307. DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
  7308. " enabled\n", dev->name);
  7309. /* Initialize device name */
  7310. sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
  7311. /*
  7312. * Make Link state as off at this point, when the Link change
  7313. * interrupt comes the state will be automatically changed to
  7314. * the right state.
  7315. */
  7316. netif_carrier_off(dev);
  7317. return 0;
  7318. register_failed:
  7319. set_swap_failed:
  7320. iounmap(sp->bar1);
  7321. bar1_remap_failed:
  7322. iounmap(sp->bar0);
  7323. bar0_remap_failed:
  7324. mem_alloc_failed:
  7325. free_shared_mem(sp);
  7326. pci_disable_device(pdev);
  7327. pci_release_regions(pdev);
  7328. pci_set_drvdata(pdev, NULL);
  7329. free_netdev(dev);
  7330. return ret;
  7331. }
  7332. /**
  7333. * s2io_rem_nic - Free the PCI device
  7334. * @pdev: structure containing the PCI related information of the device.
  7335. * Description: This function is called by the Pci subsystem to release a
  7336. * PCI device and free up all resource held up by the device. This could
  7337. * be in response to a Hot plug event or when the driver is to be removed
  7338. * from memory.
  7339. */
  7340. static void __devexit s2io_rem_nic(struct pci_dev *pdev)
  7341. {
  7342. struct net_device *dev =
  7343. (struct net_device *) pci_get_drvdata(pdev);
  7344. struct s2io_nic *sp;
  7345. if (dev == NULL) {
  7346. DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
  7347. return;
  7348. }
  7349. flush_scheduled_work();
  7350. sp = dev->priv;
  7351. unregister_netdev(dev);
  7352. free_shared_mem(sp);
  7353. iounmap(sp->bar0);
  7354. iounmap(sp->bar1);
  7355. pci_release_regions(pdev);
  7356. pci_set_drvdata(pdev, NULL);
  7357. free_netdev(dev);
  7358. pci_disable_device(pdev);
  7359. }
  7360. /**
  7361. * s2io_starter - Entry point for the driver
  7362. * Description: This function is the entry point for the driver. It verifies
  7363. * the module loadable parameters and initializes PCI configuration space.
  7364. */
  7365. static int __init s2io_starter(void)
  7366. {
  7367. return pci_register_driver(&s2io_driver);
  7368. }
  7369. /**
  7370. * s2io_closer - Cleanup routine for the driver
  7371. * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
  7372. */
  7373. static __exit void s2io_closer(void)
  7374. {
  7375. pci_unregister_driver(&s2io_driver);
  7376. DBG_PRINT(INIT_DBG, "cleanup done\n");
  7377. }
  7378. module_init(s2io_starter);
  7379. module_exit(s2io_closer);
  7380. static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
  7381. struct tcphdr **tcp, struct RxD_t *rxdp,
  7382. struct s2io_nic *sp)
  7383. {
  7384. int ip_off;
  7385. u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
  7386. if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
  7387. DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
  7388. __FUNCTION__);
  7389. return -1;
  7390. }
  7391. /* Checking for DIX type or DIX type with VLAN */
  7392. if ((l2_type == 0)
  7393. || (l2_type == 4)) {
  7394. ip_off = HEADER_ETHERNET_II_802_3_SIZE;
  7395. /*
  7396. * If vlan stripping is disabled and the frame is VLAN tagged,
  7397. * shift the offset by the VLAN header size bytes.
  7398. */
  7399. if ((!vlan_strip_flag) &&
  7400. (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
  7401. ip_off += HEADER_VLAN_SIZE;
  7402. } else {
  7403. /* LLC, SNAP etc are considered non-mergeable */
  7404. return -1;
  7405. }
  7406. *ip = (struct iphdr *)((u8 *)buffer + ip_off);
  7407. ip_len = (u8)((*ip)->ihl);
  7408. ip_len <<= 2;
  7409. *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
  7410. return 0;
  7411. }
  7412. static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
  7413. struct tcphdr *tcp)
  7414. {
  7415. DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
  7416. if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
  7417. (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
  7418. return -1;
  7419. return 0;
  7420. }
  7421. static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
  7422. {
  7423. return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
  7424. }
  7425. static void initiate_new_session(struct lro *lro, u8 *l2h,
  7426. struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
  7427. {
  7428. DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
  7429. lro->l2h = l2h;
  7430. lro->iph = ip;
  7431. lro->tcph = tcp;
  7432. lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
  7433. lro->tcp_ack = tcp->ack_seq;
  7434. lro->sg_num = 1;
  7435. lro->total_len = ntohs(ip->tot_len);
  7436. lro->frags_len = 0;
  7437. lro->vlan_tag = vlan_tag;
  7438. /*
  7439. * check if we saw TCP timestamp. Other consistency checks have
  7440. * already been done.
  7441. */
  7442. if (tcp->doff == 8) {
  7443. __be32 *ptr;
  7444. ptr = (__be32 *)(tcp+1);
  7445. lro->saw_ts = 1;
  7446. lro->cur_tsval = ntohl(*(ptr+1));
  7447. lro->cur_tsecr = *(ptr+2);
  7448. }
  7449. lro->in_use = 1;
  7450. }
  7451. static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
  7452. {
  7453. struct iphdr *ip = lro->iph;
  7454. struct tcphdr *tcp = lro->tcph;
  7455. __sum16 nchk;
  7456. struct stat_block *statinfo = sp->mac_control.stats_info;
  7457. DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
  7458. /* Update L3 header */
  7459. ip->tot_len = htons(lro->total_len);
  7460. ip->check = 0;
  7461. nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
  7462. ip->check = nchk;
  7463. /* Update L4 header */
  7464. tcp->ack_seq = lro->tcp_ack;
  7465. tcp->window = lro->window;
  7466. /* Update tsecr field if this session has timestamps enabled */
  7467. if (lro->saw_ts) {
  7468. __be32 *ptr = (__be32 *)(tcp + 1);
  7469. *(ptr+2) = lro->cur_tsecr;
  7470. }
  7471. /* Update counters required for calculation of
  7472. * average no. of packets aggregated.
  7473. */
  7474. statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
  7475. statinfo->sw_stat.num_aggregations++;
  7476. }
  7477. static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
  7478. struct tcphdr *tcp, u32 l4_pyld)
  7479. {
  7480. DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
  7481. lro->total_len += l4_pyld;
  7482. lro->frags_len += l4_pyld;
  7483. lro->tcp_next_seq += l4_pyld;
  7484. lro->sg_num++;
  7485. /* Update ack seq no. and window ad(from this pkt) in LRO object */
  7486. lro->tcp_ack = tcp->ack_seq;
  7487. lro->window = tcp->window;
  7488. if (lro->saw_ts) {
  7489. __be32 *ptr;
  7490. /* Update tsecr and tsval from this packet */
  7491. ptr = (__be32 *)(tcp+1);
  7492. lro->cur_tsval = ntohl(*(ptr+1));
  7493. lro->cur_tsecr = *(ptr + 2);
  7494. }
  7495. }
  7496. static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
  7497. struct tcphdr *tcp, u32 tcp_pyld_len)
  7498. {
  7499. u8 *ptr;
  7500. DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
  7501. if (!tcp_pyld_len) {
  7502. /* Runt frame or a pure ack */
  7503. return -1;
  7504. }
  7505. if (ip->ihl != 5) /* IP has options */
  7506. return -1;
  7507. /* If we see CE codepoint in IP header, packet is not mergeable */
  7508. if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
  7509. return -1;
  7510. /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
  7511. if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
  7512. tcp->ece || tcp->cwr || !tcp->ack) {
  7513. /*
  7514. * Currently recognize only the ack control word and
  7515. * any other control field being set would result in
  7516. * flushing the LRO session
  7517. */
  7518. return -1;
  7519. }
  7520. /*
  7521. * Allow only one TCP timestamp option. Don't aggregate if
  7522. * any other options are detected.
  7523. */
  7524. if (tcp->doff != 5 && tcp->doff != 8)
  7525. return -1;
  7526. if (tcp->doff == 8) {
  7527. ptr = (u8 *)(tcp + 1);
  7528. while (*ptr == TCPOPT_NOP)
  7529. ptr++;
  7530. if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
  7531. return -1;
  7532. /* Ensure timestamp value increases monotonically */
  7533. if (l_lro)
  7534. if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
  7535. return -1;
  7536. /* timestamp echo reply should be non-zero */
  7537. if (*((__be32 *)(ptr+6)) == 0)
  7538. return -1;
  7539. }
  7540. return 0;
  7541. }
  7542. static int
  7543. s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp,
  7544. u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
  7545. struct s2io_nic *sp)
  7546. {
  7547. struct iphdr *ip;
  7548. struct tcphdr *tcph;
  7549. int ret = 0, i;
  7550. u16 vlan_tag = 0;
  7551. if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
  7552. rxdp, sp))) {
  7553. DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
  7554. ip->saddr, ip->daddr);
  7555. } else
  7556. return ret;
  7557. vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
  7558. tcph = (struct tcphdr *)*tcp;
  7559. *tcp_len = get_l4_pyld_length(ip, tcph);
  7560. for (i=0; i<MAX_LRO_SESSIONS; i++) {
  7561. struct lro *l_lro = &ring_data->lro0_n[i];
  7562. if (l_lro->in_use) {
  7563. if (check_for_socket_match(l_lro, ip, tcph))
  7564. continue;
  7565. /* Sock pair matched */
  7566. *lro = l_lro;
  7567. if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
  7568. DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
  7569. "0x%x, actual 0x%x\n", __FUNCTION__,
  7570. (*lro)->tcp_next_seq,
  7571. ntohl(tcph->seq));
  7572. sp->mac_control.stats_info->
  7573. sw_stat.outof_sequence_pkts++;
  7574. ret = 2;
  7575. break;
  7576. }
  7577. if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
  7578. ret = 1; /* Aggregate */
  7579. else
  7580. ret = 2; /* Flush both */
  7581. break;
  7582. }
  7583. }
  7584. if (ret == 0) {
  7585. /* Before searching for available LRO objects,
  7586. * check if the pkt is L3/L4 aggregatable. If not
  7587. * don't create new LRO session. Just send this
  7588. * packet up.
  7589. */
  7590. if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
  7591. return 5;
  7592. }
  7593. for (i=0; i<MAX_LRO_SESSIONS; i++) {
  7594. struct lro *l_lro = &ring_data->lro0_n[i];
  7595. if (!(l_lro->in_use)) {
  7596. *lro = l_lro;
  7597. ret = 3; /* Begin anew */
  7598. break;
  7599. }
  7600. }
  7601. }
  7602. if (ret == 0) { /* sessions exceeded */
  7603. DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
  7604. __FUNCTION__);
  7605. *lro = NULL;
  7606. return ret;
  7607. }
  7608. switch (ret) {
  7609. case 3:
  7610. initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
  7611. vlan_tag);
  7612. break;
  7613. case 2:
  7614. update_L3L4_header(sp, *lro);
  7615. break;
  7616. case 1:
  7617. aggregate_new_rx(*lro, ip, tcph, *tcp_len);
  7618. if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
  7619. update_L3L4_header(sp, *lro);
  7620. ret = 4; /* Flush the LRO */
  7621. }
  7622. break;
  7623. default:
  7624. DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
  7625. __FUNCTION__);
  7626. break;
  7627. }
  7628. return ret;
  7629. }
  7630. static void clear_lro_session(struct lro *lro)
  7631. {
  7632. static u16 lro_struct_size = sizeof(struct lro);
  7633. memset(lro, 0, lro_struct_size);
  7634. }
  7635. static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
  7636. {
  7637. struct net_device *dev = skb->dev;
  7638. struct s2io_nic *sp = dev->priv;
  7639. skb->protocol = eth_type_trans(skb, dev);
  7640. if (sp->vlgrp && vlan_tag
  7641. && (vlan_strip_flag)) {
  7642. /* Queueing the vlan frame to the upper layer */
  7643. if (sp->config.napi)
  7644. vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
  7645. else
  7646. vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
  7647. } else {
  7648. if (sp->config.napi)
  7649. netif_receive_skb(skb);
  7650. else
  7651. netif_rx(skb);
  7652. }
  7653. }
  7654. static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
  7655. struct sk_buff *skb,
  7656. u32 tcp_len)
  7657. {
  7658. struct sk_buff *first = lro->parent;
  7659. first->len += tcp_len;
  7660. first->data_len = lro->frags_len;
  7661. skb_pull(skb, (skb->len - tcp_len));
  7662. if (skb_shinfo(first)->frag_list)
  7663. lro->last_frag->next = skb;
  7664. else
  7665. skb_shinfo(first)->frag_list = skb;
  7666. first->truesize += skb->truesize;
  7667. lro->last_frag = skb;
  7668. sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
  7669. return;
  7670. }
  7671. /**
  7672. * s2io_io_error_detected - called when PCI error is detected
  7673. * @pdev: Pointer to PCI device
  7674. * @state: The current pci connection state
  7675. *
  7676. * This function is called after a PCI bus error affecting
  7677. * this device has been detected.
  7678. */
  7679. static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
  7680. pci_channel_state_t state)
  7681. {
  7682. struct net_device *netdev = pci_get_drvdata(pdev);
  7683. struct s2io_nic *sp = netdev->priv;
  7684. netif_device_detach(netdev);
  7685. if (netif_running(netdev)) {
  7686. /* Bring down the card, while avoiding PCI I/O */
  7687. do_s2io_card_down(sp, 0);
  7688. }
  7689. pci_disable_device(pdev);
  7690. return PCI_ERS_RESULT_NEED_RESET;
  7691. }
  7692. /**
  7693. * s2io_io_slot_reset - called after the pci bus has been reset.
  7694. * @pdev: Pointer to PCI device
  7695. *
  7696. * Restart the card from scratch, as if from a cold-boot.
  7697. * At this point, the card has exprienced a hard reset,
  7698. * followed by fixups by BIOS, and has its config space
  7699. * set up identically to what it was at cold boot.
  7700. */
  7701. static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
  7702. {
  7703. struct net_device *netdev = pci_get_drvdata(pdev);
  7704. struct s2io_nic *sp = netdev->priv;
  7705. if (pci_enable_device(pdev)) {
  7706. printk(KERN_ERR "s2io: "
  7707. "Cannot re-enable PCI device after reset.\n");
  7708. return PCI_ERS_RESULT_DISCONNECT;
  7709. }
  7710. pci_set_master(pdev);
  7711. s2io_reset(sp);
  7712. return PCI_ERS_RESULT_RECOVERED;
  7713. }
  7714. /**
  7715. * s2io_io_resume - called when traffic can start flowing again.
  7716. * @pdev: Pointer to PCI device
  7717. *
  7718. * This callback is called when the error recovery driver tells
  7719. * us that its OK to resume normal operation.
  7720. */
  7721. static void s2io_io_resume(struct pci_dev *pdev)
  7722. {
  7723. struct net_device *netdev = pci_get_drvdata(pdev);
  7724. struct s2io_nic *sp = netdev->priv;
  7725. if (netif_running(netdev)) {
  7726. if (s2io_card_up(sp)) {
  7727. printk(KERN_ERR "s2io: "
  7728. "Can't bring device back up after reset.\n");
  7729. return;
  7730. }
  7731. if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
  7732. s2io_card_down(sp);
  7733. printk(KERN_ERR "s2io: "
  7734. "Can't resetore mac addr after reset.\n");
  7735. return;
  7736. }
  7737. }
  7738. netif_device_attach(netdev);
  7739. netif_tx_wake_all_queues(netdev);
  7740. }