r8169.c 78 KB

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  1. /*
  2. * r8169.c: RealTek 8169/8168/8101 ethernet driver.
  3. *
  4. * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
  5. * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
  6. * Copyright (c) a lot of people too. Please respect their work.
  7. *
  8. * See MAINTAINERS file for support contact information.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/pci.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/delay.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/mii.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/crc32.h>
  20. #include <linux/in.h>
  21. #include <linux/ip.h>
  22. #include <linux/tcp.h>
  23. #include <linux/init.h>
  24. #include <linux/dma-mapping.h>
  25. #include <asm/system.h>
  26. #include <asm/io.h>
  27. #include <asm/irq.h>
  28. #define RTL8169_VERSION "2.3LK-NAPI"
  29. #define MODULENAME "r8169"
  30. #define PFX MODULENAME ": "
  31. #ifdef RTL8169_DEBUG
  32. #define assert(expr) \
  33. if (!(expr)) { \
  34. printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  35. #expr,__FILE__,__FUNCTION__,__LINE__); \
  36. }
  37. #define dprintk(fmt, args...) \
  38. do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  39. #else
  40. #define assert(expr) do {} while (0)
  41. #define dprintk(fmt, args...) do {} while (0)
  42. #endif /* RTL8169_DEBUG */
  43. #define R8169_MSG_DEFAULT \
  44. (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  45. #define TX_BUFFS_AVAIL(tp) \
  46. (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  47. /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  48. static const int max_interrupt_work = 20;
  49. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  50. The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  51. static const int multicast_filter_limit = 32;
  52. /* MAC address length */
  53. #define MAC_ADDR_LEN 6
  54. #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  55. #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
  56. #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
  57. #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
  58. #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  59. #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
  60. #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
  61. #define R8169_REGS_SIZE 256
  62. #define R8169_NAPI_WEIGHT 64
  63. #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
  64. #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
  65. #define RX_BUF_SIZE 1536 /* Rx Buffer size */
  66. #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
  67. #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
  68. #define RTL8169_TX_TIMEOUT (6*HZ)
  69. #define RTL8169_PHY_TIMEOUT (10*HZ)
  70. /* write/read MMIO register */
  71. #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
  72. #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
  73. #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
  74. #define RTL_R8(reg) readb (ioaddr + (reg))
  75. #define RTL_R16(reg) readw (ioaddr + (reg))
  76. #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
  77. enum mac_version {
  78. RTL_GIGA_MAC_VER_01 = 0x01, // 8169
  79. RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
  80. RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
  81. RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
  82. RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
  83. RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
  84. RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
  85. RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
  86. RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
  87. RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
  88. RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
  89. RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
  90. RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
  91. RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
  92. RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
  93. RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
  94. };
  95. #define _R(NAME,MAC,MASK) \
  96. { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
  97. static const struct {
  98. const char *name;
  99. u8 mac_version;
  100. u32 RxConfigMask; /* Clears the bits supported by this chip */
  101. } rtl_chip_info[] = {
  102. _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
  103. _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
  104. _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
  105. _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
  106. _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
  107. _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
  108. _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
  109. _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
  110. _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
  111. _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
  112. _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
  113. _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
  114. _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
  115. _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
  116. _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
  117. _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
  118. };
  119. #undef _R
  120. enum cfg_version {
  121. RTL_CFG_0 = 0x00,
  122. RTL_CFG_1,
  123. RTL_CFG_2
  124. };
  125. static void rtl_hw_start_8169(struct net_device *);
  126. static void rtl_hw_start_8168(struct net_device *);
  127. static void rtl_hw_start_8101(struct net_device *);
  128. static struct pci_device_id rtl8169_pci_tbl[] = {
  129. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
  130. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
  131. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
  132. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
  133. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
  134. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
  135. { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
  136. { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
  137. { PCI_VENDOR_ID_LINKSYS, 0x1032,
  138. PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
  139. { 0x0001, 0x8168,
  140. PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
  141. {0,},
  142. };
  143. MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
  144. static int rx_copybreak = 200;
  145. static int use_dac;
  146. static struct {
  147. u32 msg_enable;
  148. } debug = { -1 };
  149. enum rtl_registers {
  150. MAC0 = 0, /* Ethernet hardware address. */
  151. MAC4 = 4,
  152. MAR0 = 8, /* Multicast filter. */
  153. CounterAddrLow = 0x10,
  154. CounterAddrHigh = 0x14,
  155. TxDescStartAddrLow = 0x20,
  156. TxDescStartAddrHigh = 0x24,
  157. TxHDescStartAddrLow = 0x28,
  158. TxHDescStartAddrHigh = 0x2c,
  159. FLASH = 0x30,
  160. ERSR = 0x36,
  161. ChipCmd = 0x37,
  162. TxPoll = 0x38,
  163. IntrMask = 0x3c,
  164. IntrStatus = 0x3e,
  165. TxConfig = 0x40,
  166. RxConfig = 0x44,
  167. RxMissed = 0x4c,
  168. Cfg9346 = 0x50,
  169. Config0 = 0x51,
  170. Config1 = 0x52,
  171. Config2 = 0x53,
  172. Config3 = 0x54,
  173. Config4 = 0x55,
  174. Config5 = 0x56,
  175. MultiIntr = 0x5c,
  176. PHYAR = 0x60,
  177. TBICSR = 0x64,
  178. TBI_ANAR = 0x68,
  179. TBI_LPAR = 0x6a,
  180. PHYstatus = 0x6c,
  181. RxMaxSize = 0xda,
  182. CPlusCmd = 0xe0,
  183. IntrMitigate = 0xe2,
  184. RxDescAddrLow = 0xe4,
  185. RxDescAddrHigh = 0xe8,
  186. EarlyTxThres = 0xec,
  187. FuncEvent = 0xf0,
  188. FuncEventMask = 0xf4,
  189. FuncPresetState = 0xf8,
  190. FuncForceEvent = 0xfc,
  191. };
  192. enum rtl_register_content {
  193. /* InterruptStatusBits */
  194. SYSErr = 0x8000,
  195. PCSTimeout = 0x4000,
  196. SWInt = 0x0100,
  197. TxDescUnavail = 0x0080,
  198. RxFIFOOver = 0x0040,
  199. LinkChg = 0x0020,
  200. RxOverflow = 0x0010,
  201. TxErr = 0x0008,
  202. TxOK = 0x0004,
  203. RxErr = 0x0002,
  204. RxOK = 0x0001,
  205. /* RxStatusDesc */
  206. RxFOVF = (1 << 23),
  207. RxRWT = (1 << 22),
  208. RxRES = (1 << 21),
  209. RxRUNT = (1 << 20),
  210. RxCRC = (1 << 19),
  211. /* ChipCmdBits */
  212. CmdReset = 0x10,
  213. CmdRxEnb = 0x08,
  214. CmdTxEnb = 0x04,
  215. RxBufEmpty = 0x01,
  216. /* TXPoll register p.5 */
  217. HPQ = 0x80, /* Poll cmd on the high prio queue */
  218. NPQ = 0x40, /* Poll cmd on the low prio queue */
  219. FSWInt = 0x01, /* Forced software interrupt */
  220. /* Cfg9346Bits */
  221. Cfg9346_Lock = 0x00,
  222. Cfg9346_Unlock = 0xc0,
  223. /* rx_mode_bits */
  224. AcceptErr = 0x20,
  225. AcceptRunt = 0x10,
  226. AcceptBroadcast = 0x08,
  227. AcceptMulticast = 0x04,
  228. AcceptMyPhys = 0x02,
  229. AcceptAllPhys = 0x01,
  230. /* RxConfigBits */
  231. RxCfgFIFOShift = 13,
  232. RxCfgDMAShift = 8,
  233. /* TxConfigBits */
  234. TxInterFrameGapShift = 24,
  235. TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
  236. /* Config1 register p.24 */
  237. MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
  238. PMEnable = (1 << 0), /* Power Management Enable */
  239. /* Config2 register p. 25 */
  240. PCI_Clock_66MHz = 0x01,
  241. PCI_Clock_33MHz = 0x00,
  242. /* Config3 register p.25 */
  243. MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
  244. LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
  245. /* Config5 register p.27 */
  246. BWF = (1 << 6), /* Accept Broadcast wakeup frame */
  247. MWF = (1 << 5), /* Accept Multicast wakeup frame */
  248. UWF = (1 << 4), /* Accept Unicast wakeup frame */
  249. LanWake = (1 << 1), /* LanWake enable/disable */
  250. PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
  251. /* TBICSR p.28 */
  252. TBIReset = 0x80000000,
  253. TBILoopback = 0x40000000,
  254. TBINwEnable = 0x20000000,
  255. TBINwRestart = 0x10000000,
  256. TBILinkOk = 0x02000000,
  257. TBINwComplete = 0x01000000,
  258. /* CPlusCmd p.31 */
  259. PktCntrDisable = (1 << 7), // 8168
  260. RxVlan = (1 << 6),
  261. RxChkSum = (1 << 5),
  262. PCIDAC = (1 << 4),
  263. PCIMulRW = (1 << 3),
  264. INTT_0 = 0x0000, // 8168
  265. INTT_1 = 0x0001, // 8168
  266. INTT_2 = 0x0002, // 8168
  267. INTT_3 = 0x0003, // 8168
  268. /* rtl8169_PHYstatus */
  269. TBI_Enable = 0x80,
  270. TxFlowCtrl = 0x40,
  271. RxFlowCtrl = 0x20,
  272. _1000bpsF = 0x10,
  273. _100bps = 0x08,
  274. _10bps = 0x04,
  275. LinkStatus = 0x02,
  276. FullDup = 0x01,
  277. /* _TBICSRBit */
  278. TBILinkOK = 0x02000000,
  279. /* DumpCounterCommand */
  280. CounterDump = 0x8,
  281. };
  282. enum desc_status_bit {
  283. DescOwn = (1 << 31), /* Descriptor is owned by NIC */
  284. RingEnd = (1 << 30), /* End of descriptor ring */
  285. FirstFrag = (1 << 29), /* First segment of a packet */
  286. LastFrag = (1 << 28), /* Final segment of a packet */
  287. /* Tx private */
  288. LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
  289. MSSShift = 16, /* MSS value position */
  290. MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
  291. IPCS = (1 << 18), /* Calculate IP checksum */
  292. UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
  293. TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
  294. TxVlanTag = (1 << 17), /* Add VLAN tag */
  295. /* Rx private */
  296. PID1 = (1 << 18), /* Protocol ID bit 1/2 */
  297. PID0 = (1 << 17), /* Protocol ID bit 2/2 */
  298. #define RxProtoUDP (PID1)
  299. #define RxProtoTCP (PID0)
  300. #define RxProtoIP (PID1 | PID0)
  301. #define RxProtoMask RxProtoIP
  302. IPFail = (1 << 16), /* IP checksum failed */
  303. UDPFail = (1 << 15), /* UDP/IP checksum failed */
  304. TCPFail = (1 << 14), /* TCP/IP checksum failed */
  305. RxVlanTag = (1 << 16), /* VLAN tag available */
  306. };
  307. #define RsvdMask 0x3fffc000
  308. struct TxDesc {
  309. __le32 opts1;
  310. __le32 opts2;
  311. __le64 addr;
  312. };
  313. struct RxDesc {
  314. __le32 opts1;
  315. __le32 opts2;
  316. __le64 addr;
  317. };
  318. struct ring_info {
  319. struct sk_buff *skb;
  320. u32 len;
  321. u8 __pad[sizeof(void *) - sizeof(u32)];
  322. };
  323. enum features {
  324. RTL_FEATURE_WOL = (1 << 0),
  325. RTL_FEATURE_MSI = (1 << 1),
  326. };
  327. struct rtl8169_private {
  328. void __iomem *mmio_addr; /* memory map physical address */
  329. struct pci_dev *pci_dev; /* Index of PCI device */
  330. struct net_device *dev;
  331. struct napi_struct napi;
  332. spinlock_t lock; /* spin lock flag */
  333. u32 msg_enable;
  334. int chipset;
  335. int mac_version;
  336. u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
  337. u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
  338. u32 dirty_rx;
  339. u32 dirty_tx;
  340. struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
  341. struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
  342. dma_addr_t TxPhyAddr;
  343. dma_addr_t RxPhyAddr;
  344. struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
  345. struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
  346. unsigned align;
  347. unsigned rx_buf_sz;
  348. struct timer_list timer;
  349. u16 cp_cmd;
  350. u16 intr_event;
  351. u16 napi_event;
  352. u16 intr_mask;
  353. int phy_auto_nego_reg;
  354. int phy_1000_ctrl_reg;
  355. #ifdef CONFIG_R8169_VLAN
  356. struct vlan_group *vlgrp;
  357. #endif
  358. int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
  359. void (*get_settings)(struct net_device *, struct ethtool_cmd *);
  360. void (*phy_reset_enable)(void __iomem *);
  361. void (*hw_start)(struct net_device *);
  362. unsigned int (*phy_reset_pending)(void __iomem *);
  363. unsigned int (*link_ok)(void __iomem *);
  364. struct delayed_work task;
  365. unsigned features;
  366. };
  367. MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
  368. MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
  369. module_param(rx_copybreak, int, 0);
  370. MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
  371. module_param(use_dac, int, 0);
  372. MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
  373. module_param_named(debug, debug.msg_enable, int, 0);
  374. MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
  375. MODULE_LICENSE("GPL");
  376. MODULE_VERSION(RTL8169_VERSION);
  377. static int rtl8169_open(struct net_device *dev);
  378. static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
  379. static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
  380. static int rtl8169_init_ring(struct net_device *dev);
  381. static void rtl_hw_start(struct net_device *dev);
  382. static int rtl8169_close(struct net_device *dev);
  383. static void rtl_set_rx_mode(struct net_device *dev);
  384. static void rtl8169_tx_timeout(struct net_device *dev);
  385. static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
  386. static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
  387. void __iomem *, u32 budget);
  388. static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
  389. static void rtl8169_down(struct net_device *dev);
  390. static void rtl8169_rx_clear(struct rtl8169_private *tp);
  391. static int rtl8169_poll(struct napi_struct *napi, int budget);
  392. static const unsigned int rtl8169_rx_config =
  393. (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
  394. static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
  395. {
  396. int i;
  397. RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
  398. for (i = 20; i > 0; i--) {
  399. /*
  400. * Check if the RTL8169 has completed writing to the specified
  401. * MII register.
  402. */
  403. if (!(RTL_R32(PHYAR) & 0x80000000))
  404. break;
  405. udelay(25);
  406. }
  407. }
  408. static int mdio_read(void __iomem *ioaddr, int reg_addr)
  409. {
  410. int i, value = -1;
  411. RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
  412. for (i = 20; i > 0; i--) {
  413. /*
  414. * Check if the RTL8169 has completed retrieving data from
  415. * the specified MII register.
  416. */
  417. if (RTL_R32(PHYAR) & 0x80000000) {
  418. value = RTL_R32(PHYAR) & 0xffff;
  419. break;
  420. }
  421. udelay(25);
  422. }
  423. return value;
  424. }
  425. static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
  426. {
  427. RTL_W16(IntrMask, 0x0000);
  428. RTL_W16(IntrStatus, 0xffff);
  429. }
  430. static void rtl8169_asic_down(void __iomem *ioaddr)
  431. {
  432. RTL_W8(ChipCmd, 0x00);
  433. rtl8169_irq_mask_and_ack(ioaddr);
  434. RTL_R16(CPlusCmd);
  435. }
  436. static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
  437. {
  438. return RTL_R32(TBICSR) & TBIReset;
  439. }
  440. static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
  441. {
  442. return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
  443. }
  444. static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
  445. {
  446. return RTL_R32(TBICSR) & TBILinkOk;
  447. }
  448. static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
  449. {
  450. return RTL_R8(PHYstatus) & LinkStatus;
  451. }
  452. static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
  453. {
  454. RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
  455. }
  456. static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
  457. {
  458. unsigned int val;
  459. val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
  460. mdio_write(ioaddr, MII_BMCR, val & 0xffff);
  461. }
  462. static void rtl8169_check_link_status(struct net_device *dev,
  463. struct rtl8169_private *tp,
  464. void __iomem *ioaddr)
  465. {
  466. unsigned long flags;
  467. spin_lock_irqsave(&tp->lock, flags);
  468. if (tp->link_ok(ioaddr)) {
  469. netif_carrier_on(dev);
  470. if (netif_msg_ifup(tp))
  471. printk(KERN_INFO PFX "%s: link up\n", dev->name);
  472. } else {
  473. if (netif_msg_ifdown(tp))
  474. printk(KERN_INFO PFX "%s: link down\n", dev->name);
  475. netif_carrier_off(dev);
  476. }
  477. spin_unlock_irqrestore(&tp->lock, flags);
  478. }
  479. static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  480. {
  481. struct rtl8169_private *tp = netdev_priv(dev);
  482. void __iomem *ioaddr = tp->mmio_addr;
  483. u8 options;
  484. wol->wolopts = 0;
  485. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  486. wol->supported = WAKE_ANY;
  487. spin_lock_irq(&tp->lock);
  488. options = RTL_R8(Config1);
  489. if (!(options & PMEnable))
  490. goto out_unlock;
  491. options = RTL_R8(Config3);
  492. if (options & LinkUp)
  493. wol->wolopts |= WAKE_PHY;
  494. if (options & MagicPacket)
  495. wol->wolopts |= WAKE_MAGIC;
  496. options = RTL_R8(Config5);
  497. if (options & UWF)
  498. wol->wolopts |= WAKE_UCAST;
  499. if (options & BWF)
  500. wol->wolopts |= WAKE_BCAST;
  501. if (options & MWF)
  502. wol->wolopts |= WAKE_MCAST;
  503. out_unlock:
  504. spin_unlock_irq(&tp->lock);
  505. }
  506. static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  507. {
  508. struct rtl8169_private *tp = netdev_priv(dev);
  509. void __iomem *ioaddr = tp->mmio_addr;
  510. unsigned int i;
  511. static struct {
  512. u32 opt;
  513. u16 reg;
  514. u8 mask;
  515. } cfg[] = {
  516. { WAKE_ANY, Config1, PMEnable },
  517. { WAKE_PHY, Config3, LinkUp },
  518. { WAKE_MAGIC, Config3, MagicPacket },
  519. { WAKE_UCAST, Config5, UWF },
  520. { WAKE_BCAST, Config5, BWF },
  521. { WAKE_MCAST, Config5, MWF },
  522. { WAKE_ANY, Config5, LanWake }
  523. };
  524. spin_lock_irq(&tp->lock);
  525. RTL_W8(Cfg9346, Cfg9346_Unlock);
  526. for (i = 0; i < ARRAY_SIZE(cfg); i++) {
  527. u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
  528. if (wol->wolopts & cfg[i].opt)
  529. options |= cfg[i].mask;
  530. RTL_W8(cfg[i].reg, options);
  531. }
  532. RTL_W8(Cfg9346, Cfg9346_Lock);
  533. if (wol->wolopts)
  534. tp->features |= RTL_FEATURE_WOL;
  535. else
  536. tp->features &= ~RTL_FEATURE_WOL;
  537. spin_unlock_irq(&tp->lock);
  538. return 0;
  539. }
  540. static void rtl8169_get_drvinfo(struct net_device *dev,
  541. struct ethtool_drvinfo *info)
  542. {
  543. struct rtl8169_private *tp = netdev_priv(dev);
  544. strcpy(info->driver, MODULENAME);
  545. strcpy(info->version, RTL8169_VERSION);
  546. strcpy(info->bus_info, pci_name(tp->pci_dev));
  547. }
  548. static int rtl8169_get_regs_len(struct net_device *dev)
  549. {
  550. return R8169_REGS_SIZE;
  551. }
  552. static int rtl8169_set_speed_tbi(struct net_device *dev,
  553. u8 autoneg, u16 speed, u8 duplex)
  554. {
  555. struct rtl8169_private *tp = netdev_priv(dev);
  556. void __iomem *ioaddr = tp->mmio_addr;
  557. int ret = 0;
  558. u32 reg;
  559. reg = RTL_R32(TBICSR);
  560. if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
  561. (duplex == DUPLEX_FULL)) {
  562. RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
  563. } else if (autoneg == AUTONEG_ENABLE)
  564. RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
  565. else {
  566. if (netif_msg_link(tp)) {
  567. printk(KERN_WARNING "%s: "
  568. "incorrect speed setting refused in TBI mode\n",
  569. dev->name);
  570. }
  571. ret = -EOPNOTSUPP;
  572. }
  573. return ret;
  574. }
  575. static int rtl8169_set_speed_xmii(struct net_device *dev,
  576. u8 autoneg, u16 speed, u8 duplex)
  577. {
  578. struct rtl8169_private *tp = netdev_priv(dev);
  579. void __iomem *ioaddr = tp->mmio_addr;
  580. int auto_nego, giga_ctrl;
  581. auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
  582. auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  583. ADVERTISE_100HALF | ADVERTISE_100FULL);
  584. giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
  585. giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  586. if (autoneg == AUTONEG_ENABLE) {
  587. auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
  588. ADVERTISE_100HALF | ADVERTISE_100FULL);
  589. giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  590. } else {
  591. if (speed == SPEED_10)
  592. auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  593. else if (speed == SPEED_100)
  594. auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  595. else if (speed == SPEED_1000)
  596. giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  597. if (duplex == DUPLEX_HALF)
  598. auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
  599. if (duplex == DUPLEX_FULL)
  600. auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
  601. /* This tweak comes straight from Realtek's driver. */
  602. if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
  603. ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
  604. (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
  605. auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
  606. }
  607. }
  608. /* The 8100e/8101e do Fast Ethernet only. */
  609. if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
  610. (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
  611. (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
  612. (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
  613. if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
  614. netif_msg_link(tp)) {
  615. printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
  616. dev->name);
  617. }
  618. giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  619. }
  620. auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  621. if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
  622. (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
  623. /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
  624. mdio_write(ioaddr, 0x1f, 0x0000);
  625. mdio_write(ioaddr, 0x0e, 0x0000);
  626. }
  627. tp->phy_auto_nego_reg = auto_nego;
  628. tp->phy_1000_ctrl_reg = giga_ctrl;
  629. mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
  630. mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
  631. mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
  632. return 0;
  633. }
  634. static int rtl8169_set_speed(struct net_device *dev,
  635. u8 autoneg, u16 speed, u8 duplex)
  636. {
  637. struct rtl8169_private *tp = netdev_priv(dev);
  638. int ret;
  639. ret = tp->set_speed(dev, autoneg, speed, duplex);
  640. if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
  641. mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
  642. return ret;
  643. }
  644. static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  645. {
  646. struct rtl8169_private *tp = netdev_priv(dev);
  647. unsigned long flags;
  648. int ret;
  649. spin_lock_irqsave(&tp->lock, flags);
  650. ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
  651. spin_unlock_irqrestore(&tp->lock, flags);
  652. return ret;
  653. }
  654. static u32 rtl8169_get_rx_csum(struct net_device *dev)
  655. {
  656. struct rtl8169_private *tp = netdev_priv(dev);
  657. return tp->cp_cmd & RxChkSum;
  658. }
  659. static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
  660. {
  661. struct rtl8169_private *tp = netdev_priv(dev);
  662. void __iomem *ioaddr = tp->mmio_addr;
  663. unsigned long flags;
  664. spin_lock_irqsave(&tp->lock, flags);
  665. if (data)
  666. tp->cp_cmd |= RxChkSum;
  667. else
  668. tp->cp_cmd &= ~RxChkSum;
  669. RTL_W16(CPlusCmd, tp->cp_cmd);
  670. RTL_R16(CPlusCmd);
  671. spin_unlock_irqrestore(&tp->lock, flags);
  672. return 0;
  673. }
  674. #ifdef CONFIG_R8169_VLAN
  675. static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
  676. struct sk_buff *skb)
  677. {
  678. return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
  679. TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
  680. }
  681. static void rtl8169_vlan_rx_register(struct net_device *dev,
  682. struct vlan_group *grp)
  683. {
  684. struct rtl8169_private *tp = netdev_priv(dev);
  685. void __iomem *ioaddr = tp->mmio_addr;
  686. unsigned long flags;
  687. spin_lock_irqsave(&tp->lock, flags);
  688. tp->vlgrp = grp;
  689. if (tp->vlgrp)
  690. tp->cp_cmd |= RxVlan;
  691. else
  692. tp->cp_cmd &= ~RxVlan;
  693. RTL_W16(CPlusCmd, tp->cp_cmd);
  694. RTL_R16(CPlusCmd);
  695. spin_unlock_irqrestore(&tp->lock, flags);
  696. }
  697. static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
  698. struct sk_buff *skb)
  699. {
  700. u32 opts2 = le32_to_cpu(desc->opts2);
  701. struct vlan_group *vlgrp = tp->vlgrp;
  702. int ret;
  703. if (vlgrp && (opts2 & RxVlanTag)) {
  704. vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
  705. ret = 0;
  706. } else
  707. ret = -1;
  708. desc->opts2 = 0;
  709. return ret;
  710. }
  711. #else /* !CONFIG_R8169_VLAN */
  712. static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
  713. struct sk_buff *skb)
  714. {
  715. return 0;
  716. }
  717. static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
  718. struct sk_buff *skb)
  719. {
  720. return -1;
  721. }
  722. #endif
  723. static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
  724. {
  725. struct rtl8169_private *tp = netdev_priv(dev);
  726. void __iomem *ioaddr = tp->mmio_addr;
  727. u32 status;
  728. cmd->supported =
  729. SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  730. cmd->port = PORT_FIBRE;
  731. cmd->transceiver = XCVR_INTERNAL;
  732. status = RTL_R32(TBICSR);
  733. cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
  734. cmd->autoneg = !!(status & TBINwEnable);
  735. cmd->speed = SPEED_1000;
  736. cmd->duplex = DUPLEX_FULL; /* Always set */
  737. }
  738. static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
  739. {
  740. struct rtl8169_private *tp = netdev_priv(dev);
  741. void __iomem *ioaddr = tp->mmio_addr;
  742. u8 status;
  743. cmd->supported = SUPPORTED_10baseT_Half |
  744. SUPPORTED_10baseT_Full |
  745. SUPPORTED_100baseT_Half |
  746. SUPPORTED_100baseT_Full |
  747. SUPPORTED_1000baseT_Full |
  748. SUPPORTED_Autoneg |
  749. SUPPORTED_TP;
  750. cmd->autoneg = 1;
  751. cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
  752. if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
  753. cmd->advertising |= ADVERTISED_10baseT_Half;
  754. if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
  755. cmd->advertising |= ADVERTISED_10baseT_Full;
  756. if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
  757. cmd->advertising |= ADVERTISED_100baseT_Half;
  758. if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
  759. cmd->advertising |= ADVERTISED_100baseT_Full;
  760. if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
  761. cmd->advertising |= ADVERTISED_1000baseT_Full;
  762. status = RTL_R8(PHYstatus);
  763. if (status & _1000bpsF)
  764. cmd->speed = SPEED_1000;
  765. else if (status & _100bps)
  766. cmd->speed = SPEED_100;
  767. else if (status & _10bps)
  768. cmd->speed = SPEED_10;
  769. if (status & TxFlowCtrl)
  770. cmd->advertising |= ADVERTISED_Asym_Pause;
  771. if (status & RxFlowCtrl)
  772. cmd->advertising |= ADVERTISED_Pause;
  773. cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
  774. DUPLEX_FULL : DUPLEX_HALF;
  775. }
  776. static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  777. {
  778. struct rtl8169_private *tp = netdev_priv(dev);
  779. unsigned long flags;
  780. spin_lock_irqsave(&tp->lock, flags);
  781. tp->get_settings(dev, cmd);
  782. spin_unlock_irqrestore(&tp->lock, flags);
  783. return 0;
  784. }
  785. static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  786. void *p)
  787. {
  788. struct rtl8169_private *tp = netdev_priv(dev);
  789. unsigned long flags;
  790. if (regs->len > R8169_REGS_SIZE)
  791. regs->len = R8169_REGS_SIZE;
  792. spin_lock_irqsave(&tp->lock, flags);
  793. memcpy_fromio(p, tp->mmio_addr, regs->len);
  794. spin_unlock_irqrestore(&tp->lock, flags);
  795. }
  796. static u32 rtl8169_get_msglevel(struct net_device *dev)
  797. {
  798. struct rtl8169_private *tp = netdev_priv(dev);
  799. return tp->msg_enable;
  800. }
  801. static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
  802. {
  803. struct rtl8169_private *tp = netdev_priv(dev);
  804. tp->msg_enable = value;
  805. }
  806. static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
  807. "tx_packets",
  808. "rx_packets",
  809. "tx_errors",
  810. "rx_errors",
  811. "rx_missed",
  812. "align_errors",
  813. "tx_single_collisions",
  814. "tx_multi_collisions",
  815. "unicast",
  816. "broadcast",
  817. "multicast",
  818. "tx_aborted",
  819. "tx_underrun",
  820. };
  821. struct rtl8169_counters {
  822. __le64 tx_packets;
  823. __le64 rx_packets;
  824. __le64 tx_errors;
  825. __le32 rx_errors;
  826. __le16 rx_missed;
  827. __le16 align_errors;
  828. __le32 tx_one_collision;
  829. __le32 tx_multi_collision;
  830. __le64 rx_unicast;
  831. __le64 rx_broadcast;
  832. __le32 rx_multicast;
  833. __le16 tx_aborted;
  834. __le16 tx_underun;
  835. };
  836. static int rtl8169_get_sset_count(struct net_device *dev, int sset)
  837. {
  838. switch (sset) {
  839. case ETH_SS_STATS:
  840. return ARRAY_SIZE(rtl8169_gstrings);
  841. default:
  842. return -EOPNOTSUPP;
  843. }
  844. }
  845. static void rtl8169_get_ethtool_stats(struct net_device *dev,
  846. struct ethtool_stats *stats, u64 *data)
  847. {
  848. struct rtl8169_private *tp = netdev_priv(dev);
  849. void __iomem *ioaddr = tp->mmio_addr;
  850. struct rtl8169_counters *counters;
  851. dma_addr_t paddr;
  852. u32 cmd;
  853. ASSERT_RTNL();
  854. counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
  855. if (!counters)
  856. return;
  857. RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
  858. cmd = (u64)paddr & DMA_32BIT_MASK;
  859. RTL_W32(CounterAddrLow, cmd);
  860. RTL_W32(CounterAddrLow, cmd | CounterDump);
  861. while (RTL_R32(CounterAddrLow) & CounterDump) {
  862. if (msleep_interruptible(1))
  863. break;
  864. }
  865. RTL_W32(CounterAddrLow, 0);
  866. RTL_W32(CounterAddrHigh, 0);
  867. data[0] = le64_to_cpu(counters->tx_packets);
  868. data[1] = le64_to_cpu(counters->rx_packets);
  869. data[2] = le64_to_cpu(counters->tx_errors);
  870. data[3] = le32_to_cpu(counters->rx_errors);
  871. data[4] = le16_to_cpu(counters->rx_missed);
  872. data[5] = le16_to_cpu(counters->align_errors);
  873. data[6] = le32_to_cpu(counters->tx_one_collision);
  874. data[7] = le32_to_cpu(counters->tx_multi_collision);
  875. data[8] = le64_to_cpu(counters->rx_unicast);
  876. data[9] = le64_to_cpu(counters->rx_broadcast);
  877. data[10] = le32_to_cpu(counters->rx_multicast);
  878. data[11] = le16_to_cpu(counters->tx_aborted);
  879. data[12] = le16_to_cpu(counters->tx_underun);
  880. pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
  881. }
  882. static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  883. {
  884. switch(stringset) {
  885. case ETH_SS_STATS:
  886. memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
  887. break;
  888. }
  889. }
  890. static const struct ethtool_ops rtl8169_ethtool_ops = {
  891. .get_drvinfo = rtl8169_get_drvinfo,
  892. .get_regs_len = rtl8169_get_regs_len,
  893. .get_link = ethtool_op_get_link,
  894. .get_settings = rtl8169_get_settings,
  895. .set_settings = rtl8169_set_settings,
  896. .get_msglevel = rtl8169_get_msglevel,
  897. .set_msglevel = rtl8169_set_msglevel,
  898. .get_rx_csum = rtl8169_get_rx_csum,
  899. .set_rx_csum = rtl8169_set_rx_csum,
  900. .set_tx_csum = ethtool_op_set_tx_csum,
  901. .set_sg = ethtool_op_set_sg,
  902. .set_tso = ethtool_op_set_tso,
  903. .get_regs = rtl8169_get_regs,
  904. .get_wol = rtl8169_get_wol,
  905. .set_wol = rtl8169_set_wol,
  906. .get_strings = rtl8169_get_strings,
  907. .get_sset_count = rtl8169_get_sset_count,
  908. .get_ethtool_stats = rtl8169_get_ethtool_stats,
  909. };
  910. static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
  911. int bitnum, int bitval)
  912. {
  913. int val;
  914. val = mdio_read(ioaddr, reg);
  915. val = (bitval == 1) ?
  916. val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
  917. mdio_write(ioaddr, reg, val & 0xffff);
  918. }
  919. static void rtl8169_get_mac_version(struct rtl8169_private *tp,
  920. void __iomem *ioaddr)
  921. {
  922. /*
  923. * The driver currently handles the 8168Bf and the 8168Be identically
  924. * but they can be identified more specifically through the test below
  925. * if needed:
  926. *
  927. * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
  928. *
  929. * Same thing for the 8101Eb and the 8101Ec:
  930. *
  931. * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
  932. */
  933. const struct {
  934. u32 mask;
  935. u32 val;
  936. int mac_version;
  937. } mac_info[] = {
  938. /* 8168B family. */
  939. { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
  940. { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
  941. { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
  942. { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
  943. /* 8168B family. */
  944. { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
  945. { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
  946. { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
  947. { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
  948. /* 8101 family. */
  949. { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
  950. { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
  951. { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
  952. /* FIXME: where did these entries come from ? -- FR */
  953. { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
  954. { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
  955. /* 8110 family. */
  956. { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
  957. { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
  958. { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
  959. { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
  960. { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
  961. { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
  962. { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
  963. }, *p = mac_info;
  964. u32 reg;
  965. reg = RTL_R32(TxConfig);
  966. while ((reg & p->mask) != p->val)
  967. p++;
  968. tp->mac_version = p->mac_version;
  969. if (p->mask == 0x00000000) {
  970. struct pci_dev *pdev = tp->pci_dev;
  971. dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
  972. }
  973. }
  974. static void rtl8169_print_mac_version(struct rtl8169_private *tp)
  975. {
  976. dprintk("mac_version = 0x%02x\n", tp->mac_version);
  977. }
  978. struct phy_reg {
  979. u16 reg;
  980. u16 val;
  981. };
  982. static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
  983. {
  984. while (len-- > 0) {
  985. mdio_write(ioaddr, regs->reg, regs->val);
  986. regs++;
  987. }
  988. }
  989. static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
  990. {
  991. struct {
  992. u16 regs[5]; /* Beware of bit-sign propagation */
  993. } phy_magic[5] = { {
  994. { 0x0000, //w 4 15 12 0
  995. 0x00a1, //w 3 15 0 00a1
  996. 0x0008, //w 2 15 0 0008
  997. 0x1020, //w 1 15 0 1020
  998. 0x1000 } },{ //w 0 15 0 1000
  999. { 0x7000, //w 4 15 12 7
  1000. 0xff41, //w 3 15 0 ff41
  1001. 0xde60, //w 2 15 0 de60
  1002. 0x0140, //w 1 15 0 0140
  1003. 0x0077 } },{ //w 0 15 0 0077
  1004. { 0xa000, //w 4 15 12 a
  1005. 0xdf01, //w 3 15 0 df01
  1006. 0xdf20, //w 2 15 0 df20
  1007. 0xff95, //w 1 15 0 ff95
  1008. 0xfa00 } },{ //w 0 15 0 fa00
  1009. { 0xb000, //w 4 15 12 b
  1010. 0xff41, //w 3 15 0 ff41
  1011. 0xde20, //w 2 15 0 de20
  1012. 0x0140, //w 1 15 0 0140
  1013. 0x00bb } },{ //w 0 15 0 00bb
  1014. { 0xf000, //w 4 15 12 f
  1015. 0xdf01, //w 3 15 0 df01
  1016. 0xdf20, //w 2 15 0 df20
  1017. 0xff95, //w 1 15 0 ff95
  1018. 0xbf00 } //w 0 15 0 bf00
  1019. }
  1020. }, *p = phy_magic;
  1021. unsigned int i;
  1022. mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
  1023. mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
  1024. mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
  1025. rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
  1026. for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
  1027. int val, pos = 4;
  1028. val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
  1029. mdio_write(ioaddr, pos, val);
  1030. while (--pos >= 0)
  1031. mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
  1032. rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
  1033. rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
  1034. }
  1035. mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
  1036. }
  1037. static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
  1038. {
  1039. struct phy_reg phy_reg_init[] = {
  1040. { 0x1f, 0x0002 },
  1041. { 0x01, 0x90d0 },
  1042. { 0x1f, 0x0000 }
  1043. };
  1044. rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  1045. }
  1046. static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
  1047. {
  1048. struct phy_reg phy_reg_init[] = {
  1049. { 0x1f, 0x0000 },
  1050. { 0x1d, 0x0f00 },
  1051. { 0x1f, 0x0002 },
  1052. { 0x0c, 0x1ec8 },
  1053. { 0x1f, 0x0000 }
  1054. };
  1055. rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  1056. }
  1057. static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
  1058. {
  1059. struct phy_reg phy_reg_init[] = {
  1060. { 0x1f, 0x0001 },
  1061. { 0x12, 0x2300 },
  1062. { 0x1f, 0x0002 },
  1063. { 0x00, 0x88d4 },
  1064. { 0x01, 0x82b1 },
  1065. { 0x03, 0x7002 },
  1066. { 0x08, 0x9e30 },
  1067. { 0x09, 0x01f0 },
  1068. { 0x0a, 0x5500 },
  1069. { 0x0c, 0x00c8 },
  1070. { 0x1f, 0x0003 },
  1071. { 0x12, 0xc096 },
  1072. { 0x16, 0x000a },
  1073. { 0x1f, 0x0000 }
  1074. };
  1075. rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  1076. }
  1077. static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
  1078. {
  1079. struct phy_reg phy_reg_init[] = {
  1080. { 0x1f, 0x0000 },
  1081. { 0x12, 0x2300 },
  1082. { 0x1f, 0x0003 },
  1083. { 0x16, 0x0f0a },
  1084. { 0x1f, 0x0000 },
  1085. { 0x1f, 0x0002 },
  1086. { 0x0c, 0x7eb8 },
  1087. { 0x1f, 0x0000 }
  1088. };
  1089. rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  1090. }
  1091. static void rtl_hw_phy_config(struct net_device *dev)
  1092. {
  1093. struct rtl8169_private *tp = netdev_priv(dev);
  1094. void __iomem *ioaddr = tp->mmio_addr;
  1095. rtl8169_print_mac_version(tp);
  1096. switch (tp->mac_version) {
  1097. case RTL_GIGA_MAC_VER_01:
  1098. break;
  1099. case RTL_GIGA_MAC_VER_02:
  1100. case RTL_GIGA_MAC_VER_03:
  1101. rtl8169s_hw_phy_config(ioaddr);
  1102. break;
  1103. case RTL_GIGA_MAC_VER_04:
  1104. rtl8169sb_hw_phy_config(ioaddr);
  1105. break;
  1106. case RTL_GIGA_MAC_VER_18:
  1107. rtl8168cp_hw_phy_config(ioaddr);
  1108. break;
  1109. case RTL_GIGA_MAC_VER_19:
  1110. rtl8168c_hw_phy_config(ioaddr);
  1111. break;
  1112. case RTL_GIGA_MAC_VER_20:
  1113. rtl8168cx_hw_phy_config(ioaddr);
  1114. break;
  1115. default:
  1116. break;
  1117. }
  1118. }
  1119. static void rtl8169_phy_timer(unsigned long __opaque)
  1120. {
  1121. struct net_device *dev = (struct net_device *)__opaque;
  1122. struct rtl8169_private *tp = netdev_priv(dev);
  1123. struct timer_list *timer = &tp->timer;
  1124. void __iomem *ioaddr = tp->mmio_addr;
  1125. unsigned long timeout = RTL8169_PHY_TIMEOUT;
  1126. assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
  1127. if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
  1128. return;
  1129. spin_lock_irq(&tp->lock);
  1130. if (tp->phy_reset_pending(ioaddr)) {
  1131. /*
  1132. * A busy loop could burn quite a few cycles on nowadays CPU.
  1133. * Let's delay the execution of the timer for a few ticks.
  1134. */
  1135. timeout = HZ/10;
  1136. goto out_mod_timer;
  1137. }
  1138. if (tp->link_ok(ioaddr))
  1139. goto out_unlock;
  1140. if (netif_msg_link(tp))
  1141. printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
  1142. tp->phy_reset_enable(ioaddr);
  1143. out_mod_timer:
  1144. mod_timer(timer, jiffies + timeout);
  1145. out_unlock:
  1146. spin_unlock_irq(&tp->lock);
  1147. }
  1148. static inline void rtl8169_delete_timer(struct net_device *dev)
  1149. {
  1150. struct rtl8169_private *tp = netdev_priv(dev);
  1151. struct timer_list *timer = &tp->timer;
  1152. if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
  1153. return;
  1154. del_timer_sync(timer);
  1155. }
  1156. static inline void rtl8169_request_timer(struct net_device *dev)
  1157. {
  1158. struct rtl8169_private *tp = netdev_priv(dev);
  1159. struct timer_list *timer = &tp->timer;
  1160. if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
  1161. return;
  1162. mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
  1163. }
  1164. #ifdef CONFIG_NET_POLL_CONTROLLER
  1165. /*
  1166. * Polling 'interrupt' - used by things like netconsole to send skbs
  1167. * without having to re-enable interrupts. It's not called while
  1168. * the interrupt routine is executing.
  1169. */
  1170. static void rtl8169_netpoll(struct net_device *dev)
  1171. {
  1172. struct rtl8169_private *tp = netdev_priv(dev);
  1173. struct pci_dev *pdev = tp->pci_dev;
  1174. disable_irq(pdev->irq);
  1175. rtl8169_interrupt(pdev->irq, dev);
  1176. enable_irq(pdev->irq);
  1177. }
  1178. #endif
  1179. static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
  1180. void __iomem *ioaddr)
  1181. {
  1182. iounmap(ioaddr);
  1183. pci_release_regions(pdev);
  1184. pci_disable_device(pdev);
  1185. free_netdev(dev);
  1186. }
  1187. static void rtl8169_phy_reset(struct net_device *dev,
  1188. struct rtl8169_private *tp)
  1189. {
  1190. void __iomem *ioaddr = tp->mmio_addr;
  1191. unsigned int i;
  1192. tp->phy_reset_enable(ioaddr);
  1193. for (i = 0; i < 100; i++) {
  1194. if (!tp->phy_reset_pending(ioaddr))
  1195. return;
  1196. msleep(1);
  1197. }
  1198. if (netif_msg_link(tp))
  1199. printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
  1200. }
  1201. static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
  1202. {
  1203. void __iomem *ioaddr = tp->mmio_addr;
  1204. rtl_hw_phy_config(dev);
  1205. if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
  1206. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  1207. RTL_W8(0x82, 0x01);
  1208. }
  1209. pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
  1210. if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
  1211. pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
  1212. if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
  1213. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  1214. RTL_W8(0x82, 0x01);
  1215. dprintk("Set PHY Reg 0x0bh = 0x00h\n");
  1216. mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
  1217. }
  1218. rtl8169_phy_reset(dev, tp);
  1219. /*
  1220. * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
  1221. * only 8101. Don't panic.
  1222. */
  1223. rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
  1224. if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
  1225. printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
  1226. }
  1227. static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
  1228. {
  1229. void __iomem *ioaddr = tp->mmio_addr;
  1230. u32 high;
  1231. u32 low;
  1232. low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
  1233. high = addr[4] | (addr[5] << 8);
  1234. spin_lock_irq(&tp->lock);
  1235. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1236. RTL_W32(MAC0, low);
  1237. RTL_W32(MAC4, high);
  1238. RTL_W8(Cfg9346, Cfg9346_Lock);
  1239. spin_unlock_irq(&tp->lock);
  1240. }
  1241. static int rtl_set_mac_address(struct net_device *dev, void *p)
  1242. {
  1243. struct rtl8169_private *tp = netdev_priv(dev);
  1244. struct sockaddr *addr = p;
  1245. if (!is_valid_ether_addr(addr->sa_data))
  1246. return -EADDRNOTAVAIL;
  1247. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  1248. rtl_rar_set(tp, dev->dev_addr);
  1249. return 0;
  1250. }
  1251. static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1252. {
  1253. struct rtl8169_private *tp = netdev_priv(dev);
  1254. struct mii_ioctl_data *data = if_mii(ifr);
  1255. if (!netif_running(dev))
  1256. return -ENODEV;
  1257. switch (cmd) {
  1258. case SIOCGMIIPHY:
  1259. data->phy_id = 32; /* Internal PHY */
  1260. return 0;
  1261. case SIOCGMIIREG:
  1262. data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
  1263. return 0;
  1264. case SIOCSMIIREG:
  1265. if (!capable(CAP_NET_ADMIN))
  1266. return -EPERM;
  1267. mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
  1268. return 0;
  1269. }
  1270. return -EOPNOTSUPP;
  1271. }
  1272. static const struct rtl_cfg_info {
  1273. void (*hw_start)(struct net_device *);
  1274. unsigned int region;
  1275. unsigned int align;
  1276. u16 intr_event;
  1277. u16 napi_event;
  1278. unsigned msi;
  1279. } rtl_cfg_infos [] = {
  1280. [RTL_CFG_0] = {
  1281. .hw_start = rtl_hw_start_8169,
  1282. .region = 1,
  1283. .align = 0,
  1284. .intr_event = SYSErr | LinkChg | RxOverflow |
  1285. RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
  1286. .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
  1287. .msi = 0
  1288. },
  1289. [RTL_CFG_1] = {
  1290. .hw_start = rtl_hw_start_8168,
  1291. .region = 2,
  1292. .align = 8,
  1293. .intr_event = SYSErr | LinkChg | RxOverflow |
  1294. TxErr | TxOK | RxOK | RxErr,
  1295. .napi_event = TxErr | TxOK | RxOK | RxOverflow,
  1296. .msi = RTL_FEATURE_MSI
  1297. },
  1298. [RTL_CFG_2] = {
  1299. .hw_start = rtl_hw_start_8101,
  1300. .region = 2,
  1301. .align = 8,
  1302. .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
  1303. RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
  1304. .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
  1305. .msi = RTL_FEATURE_MSI
  1306. }
  1307. };
  1308. /* Cfg9346_Unlock assumed. */
  1309. static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
  1310. const struct rtl_cfg_info *cfg)
  1311. {
  1312. unsigned msi = 0;
  1313. u8 cfg2;
  1314. cfg2 = RTL_R8(Config2) & ~MSIEnable;
  1315. if (cfg->msi) {
  1316. if (pci_enable_msi(pdev)) {
  1317. dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
  1318. } else {
  1319. cfg2 |= MSIEnable;
  1320. msi = RTL_FEATURE_MSI;
  1321. }
  1322. }
  1323. RTL_W8(Config2, cfg2);
  1324. return msi;
  1325. }
  1326. static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
  1327. {
  1328. if (tp->features & RTL_FEATURE_MSI) {
  1329. pci_disable_msi(pdev);
  1330. tp->features &= ~RTL_FEATURE_MSI;
  1331. }
  1332. }
  1333. static int __devinit
  1334. rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  1335. {
  1336. const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
  1337. const unsigned int region = cfg->region;
  1338. struct rtl8169_private *tp;
  1339. struct net_device *dev;
  1340. void __iomem *ioaddr;
  1341. unsigned int i;
  1342. int rc;
  1343. if (netif_msg_drv(&debug)) {
  1344. printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
  1345. MODULENAME, RTL8169_VERSION);
  1346. }
  1347. dev = alloc_etherdev(sizeof (*tp));
  1348. if (!dev) {
  1349. if (netif_msg_drv(&debug))
  1350. dev_err(&pdev->dev, "unable to alloc new ethernet\n");
  1351. rc = -ENOMEM;
  1352. goto out;
  1353. }
  1354. SET_NETDEV_DEV(dev, &pdev->dev);
  1355. tp = netdev_priv(dev);
  1356. tp->dev = dev;
  1357. tp->pci_dev = pdev;
  1358. tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
  1359. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  1360. rc = pci_enable_device(pdev);
  1361. if (rc < 0) {
  1362. if (netif_msg_probe(tp))
  1363. dev_err(&pdev->dev, "enable failure\n");
  1364. goto err_out_free_dev_1;
  1365. }
  1366. rc = pci_set_mwi(pdev);
  1367. if (rc < 0)
  1368. goto err_out_disable_2;
  1369. /* make sure PCI base addr 1 is MMIO */
  1370. if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
  1371. if (netif_msg_probe(tp)) {
  1372. dev_err(&pdev->dev,
  1373. "region #%d not an MMIO resource, aborting\n",
  1374. region);
  1375. }
  1376. rc = -ENODEV;
  1377. goto err_out_mwi_3;
  1378. }
  1379. /* check for weird/broken PCI region reporting */
  1380. if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
  1381. if (netif_msg_probe(tp)) {
  1382. dev_err(&pdev->dev,
  1383. "Invalid PCI region size(s), aborting\n");
  1384. }
  1385. rc = -ENODEV;
  1386. goto err_out_mwi_3;
  1387. }
  1388. rc = pci_request_regions(pdev, MODULENAME);
  1389. if (rc < 0) {
  1390. if (netif_msg_probe(tp))
  1391. dev_err(&pdev->dev, "could not request regions.\n");
  1392. goto err_out_mwi_3;
  1393. }
  1394. tp->cp_cmd = PCIMulRW | RxChkSum;
  1395. if ((sizeof(dma_addr_t) > 4) &&
  1396. !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
  1397. tp->cp_cmd |= PCIDAC;
  1398. dev->features |= NETIF_F_HIGHDMA;
  1399. } else {
  1400. rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  1401. if (rc < 0) {
  1402. if (netif_msg_probe(tp)) {
  1403. dev_err(&pdev->dev,
  1404. "DMA configuration failed.\n");
  1405. }
  1406. goto err_out_free_res_4;
  1407. }
  1408. }
  1409. pci_set_master(pdev);
  1410. /* ioremap MMIO region */
  1411. ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
  1412. if (!ioaddr) {
  1413. if (netif_msg_probe(tp))
  1414. dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
  1415. rc = -EIO;
  1416. goto err_out_free_res_4;
  1417. }
  1418. /* Unneeded ? Don't mess with Mrs. Murphy. */
  1419. rtl8169_irq_mask_and_ack(ioaddr);
  1420. /* Soft reset the chip. */
  1421. RTL_W8(ChipCmd, CmdReset);
  1422. /* Check that the chip has finished the reset. */
  1423. for (i = 0; i < 100; i++) {
  1424. if ((RTL_R8(ChipCmd) & CmdReset) == 0)
  1425. break;
  1426. msleep_interruptible(1);
  1427. }
  1428. /* Identify chip attached to board */
  1429. rtl8169_get_mac_version(tp, ioaddr);
  1430. rtl8169_print_mac_version(tp);
  1431. for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
  1432. if (tp->mac_version == rtl_chip_info[i].mac_version)
  1433. break;
  1434. }
  1435. if (i == ARRAY_SIZE(rtl_chip_info)) {
  1436. /* Unknown chip: assume array element #0, original RTL-8169 */
  1437. if (netif_msg_probe(tp)) {
  1438. dev_printk(KERN_DEBUG, &pdev->dev,
  1439. "unknown chip version, assuming %s\n",
  1440. rtl_chip_info[0].name);
  1441. }
  1442. i = 0;
  1443. }
  1444. tp->chipset = i;
  1445. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1446. RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
  1447. RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
  1448. tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
  1449. RTL_W8(Cfg9346, Cfg9346_Lock);
  1450. if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
  1451. (RTL_R8(PHYstatus) & TBI_Enable)) {
  1452. tp->set_speed = rtl8169_set_speed_tbi;
  1453. tp->get_settings = rtl8169_gset_tbi;
  1454. tp->phy_reset_enable = rtl8169_tbi_reset_enable;
  1455. tp->phy_reset_pending = rtl8169_tbi_reset_pending;
  1456. tp->link_ok = rtl8169_tbi_link_ok;
  1457. tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
  1458. } else {
  1459. tp->set_speed = rtl8169_set_speed_xmii;
  1460. tp->get_settings = rtl8169_gset_xmii;
  1461. tp->phy_reset_enable = rtl8169_xmii_reset_enable;
  1462. tp->phy_reset_pending = rtl8169_xmii_reset_pending;
  1463. tp->link_ok = rtl8169_xmii_link_ok;
  1464. dev->do_ioctl = rtl8169_ioctl;
  1465. }
  1466. /* Get MAC address. FIXME: read EEPROM */
  1467. for (i = 0; i < MAC_ADDR_LEN; i++)
  1468. dev->dev_addr[i] = RTL_R8(MAC0 + i);
  1469. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  1470. dev->open = rtl8169_open;
  1471. dev->hard_start_xmit = rtl8169_start_xmit;
  1472. dev->get_stats = rtl8169_get_stats;
  1473. SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
  1474. dev->stop = rtl8169_close;
  1475. dev->tx_timeout = rtl8169_tx_timeout;
  1476. dev->set_multicast_list = rtl_set_rx_mode;
  1477. dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
  1478. dev->irq = pdev->irq;
  1479. dev->base_addr = (unsigned long) ioaddr;
  1480. dev->change_mtu = rtl8169_change_mtu;
  1481. dev->set_mac_address = rtl_set_mac_address;
  1482. netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
  1483. #ifdef CONFIG_R8169_VLAN
  1484. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  1485. dev->vlan_rx_register = rtl8169_vlan_rx_register;
  1486. #endif
  1487. #ifdef CONFIG_NET_POLL_CONTROLLER
  1488. dev->poll_controller = rtl8169_netpoll;
  1489. #endif
  1490. tp->intr_mask = 0xffff;
  1491. tp->mmio_addr = ioaddr;
  1492. tp->align = cfg->align;
  1493. tp->hw_start = cfg->hw_start;
  1494. tp->intr_event = cfg->intr_event;
  1495. tp->napi_event = cfg->napi_event;
  1496. init_timer(&tp->timer);
  1497. tp->timer.data = (unsigned long) dev;
  1498. tp->timer.function = rtl8169_phy_timer;
  1499. spin_lock_init(&tp->lock);
  1500. rc = register_netdev(dev);
  1501. if (rc < 0)
  1502. goto err_out_msi_5;
  1503. pci_set_drvdata(pdev, dev);
  1504. if (netif_msg_probe(tp)) {
  1505. u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
  1506. printk(KERN_INFO "%s: %s at 0x%lx, "
  1507. "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
  1508. "XID %08x IRQ %d\n",
  1509. dev->name,
  1510. rtl_chip_info[tp->chipset].name,
  1511. dev->base_addr,
  1512. dev->dev_addr[0], dev->dev_addr[1],
  1513. dev->dev_addr[2], dev->dev_addr[3],
  1514. dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
  1515. }
  1516. rtl8169_init_phy(dev, tp);
  1517. out:
  1518. return rc;
  1519. err_out_msi_5:
  1520. rtl_disable_msi(pdev, tp);
  1521. iounmap(ioaddr);
  1522. err_out_free_res_4:
  1523. pci_release_regions(pdev);
  1524. err_out_mwi_3:
  1525. pci_clear_mwi(pdev);
  1526. err_out_disable_2:
  1527. pci_disable_device(pdev);
  1528. err_out_free_dev_1:
  1529. free_netdev(dev);
  1530. goto out;
  1531. }
  1532. static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
  1533. {
  1534. struct net_device *dev = pci_get_drvdata(pdev);
  1535. struct rtl8169_private *tp = netdev_priv(dev);
  1536. flush_scheduled_work();
  1537. unregister_netdev(dev);
  1538. rtl_disable_msi(pdev, tp);
  1539. rtl8169_release_board(pdev, dev, tp->mmio_addr);
  1540. pci_set_drvdata(pdev, NULL);
  1541. }
  1542. static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
  1543. struct net_device *dev)
  1544. {
  1545. unsigned int mtu = dev->mtu;
  1546. tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
  1547. }
  1548. static int rtl8169_open(struct net_device *dev)
  1549. {
  1550. struct rtl8169_private *tp = netdev_priv(dev);
  1551. struct pci_dev *pdev = tp->pci_dev;
  1552. int retval = -ENOMEM;
  1553. rtl8169_set_rxbufsize(tp, dev);
  1554. /*
  1555. * Rx and Tx desscriptors needs 256 bytes alignment.
  1556. * pci_alloc_consistent provides more.
  1557. */
  1558. tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
  1559. &tp->TxPhyAddr);
  1560. if (!tp->TxDescArray)
  1561. goto out;
  1562. tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
  1563. &tp->RxPhyAddr);
  1564. if (!tp->RxDescArray)
  1565. goto err_free_tx_0;
  1566. retval = rtl8169_init_ring(dev);
  1567. if (retval < 0)
  1568. goto err_free_rx_1;
  1569. INIT_DELAYED_WORK(&tp->task, NULL);
  1570. smp_mb();
  1571. retval = request_irq(dev->irq, rtl8169_interrupt,
  1572. (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
  1573. dev->name, dev);
  1574. if (retval < 0)
  1575. goto err_release_ring_2;
  1576. napi_enable(&tp->napi);
  1577. rtl_hw_start(dev);
  1578. rtl8169_request_timer(dev);
  1579. rtl8169_check_link_status(dev, tp, tp->mmio_addr);
  1580. out:
  1581. return retval;
  1582. err_release_ring_2:
  1583. rtl8169_rx_clear(tp);
  1584. err_free_rx_1:
  1585. pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
  1586. tp->RxPhyAddr);
  1587. err_free_tx_0:
  1588. pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
  1589. tp->TxPhyAddr);
  1590. goto out;
  1591. }
  1592. static void rtl8169_hw_reset(void __iomem *ioaddr)
  1593. {
  1594. /* Disable interrupts */
  1595. rtl8169_irq_mask_and_ack(ioaddr);
  1596. /* Reset the chipset */
  1597. RTL_W8(ChipCmd, CmdReset);
  1598. /* PCI commit */
  1599. RTL_R8(ChipCmd);
  1600. }
  1601. static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
  1602. {
  1603. void __iomem *ioaddr = tp->mmio_addr;
  1604. u32 cfg = rtl8169_rx_config;
  1605. cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
  1606. RTL_W32(RxConfig, cfg);
  1607. /* Set DMA burst size and Interframe Gap Time */
  1608. RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
  1609. (InterFrameGap << TxInterFrameGapShift));
  1610. }
  1611. static void rtl_hw_start(struct net_device *dev)
  1612. {
  1613. struct rtl8169_private *tp = netdev_priv(dev);
  1614. void __iomem *ioaddr = tp->mmio_addr;
  1615. unsigned int i;
  1616. /* Soft reset the chip. */
  1617. RTL_W8(ChipCmd, CmdReset);
  1618. /* Check that the chip has finished the reset. */
  1619. for (i = 0; i < 100; i++) {
  1620. if ((RTL_R8(ChipCmd) & CmdReset) == 0)
  1621. break;
  1622. msleep_interruptible(1);
  1623. }
  1624. tp->hw_start(dev);
  1625. netif_start_queue(dev);
  1626. }
  1627. static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
  1628. void __iomem *ioaddr)
  1629. {
  1630. /*
  1631. * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
  1632. * register to be written before TxDescAddrLow to work.
  1633. * Switching from MMIO to I/O access fixes the issue as well.
  1634. */
  1635. RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
  1636. RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
  1637. RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
  1638. RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
  1639. }
  1640. static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
  1641. {
  1642. u16 cmd;
  1643. cmd = RTL_R16(CPlusCmd);
  1644. RTL_W16(CPlusCmd, cmd);
  1645. return cmd;
  1646. }
  1647. static void rtl_set_rx_max_size(void __iomem *ioaddr)
  1648. {
  1649. /* Low hurts. Let's disable the filtering. */
  1650. RTL_W16(RxMaxSize, 16383);
  1651. }
  1652. static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
  1653. {
  1654. struct {
  1655. u32 mac_version;
  1656. u32 clk;
  1657. u32 val;
  1658. } cfg2_info [] = {
  1659. { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
  1660. { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
  1661. { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
  1662. { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
  1663. }, *p = cfg2_info;
  1664. unsigned int i;
  1665. u32 clk;
  1666. clk = RTL_R8(Config2) & PCI_Clock_66MHz;
  1667. for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
  1668. if ((p->mac_version == mac_version) && (p->clk == clk)) {
  1669. RTL_W32(0x7c, p->val);
  1670. break;
  1671. }
  1672. }
  1673. }
  1674. static void rtl_hw_start_8169(struct net_device *dev)
  1675. {
  1676. struct rtl8169_private *tp = netdev_priv(dev);
  1677. void __iomem *ioaddr = tp->mmio_addr;
  1678. struct pci_dev *pdev = tp->pci_dev;
  1679. if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
  1680. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
  1681. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
  1682. }
  1683. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1684. if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
  1685. (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
  1686. (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
  1687. (tp->mac_version == RTL_GIGA_MAC_VER_04))
  1688. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  1689. RTL_W8(EarlyTxThres, EarlyTxThld);
  1690. rtl_set_rx_max_size(ioaddr);
  1691. if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
  1692. (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
  1693. (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
  1694. (tp->mac_version == RTL_GIGA_MAC_VER_04))
  1695. rtl_set_rx_tx_config_registers(tp);
  1696. tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
  1697. if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
  1698. (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
  1699. dprintk("Set MAC Reg C+CR Offset 0xE0. "
  1700. "Bit-3 and bit-14 MUST be 1\n");
  1701. tp->cp_cmd |= (1 << 14);
  1702. }
  1703. RTL_W16(CPlusCmd, tp->cp_cmd);
  1704. rtl8169_set_magic_reg(ioaddr, tp->mac_version);
  1705. /*
  1706. * Undocumented corner. Supposedly:
  1707. * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
  1708. */
  1709. RTL_W16(IntrMitigate, 0x0000);
  1710. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  1711. if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
  1712. (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
  1713. (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
  1714. (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
  1715. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  1716. rtl_set_rx_tx_config_registers(tp);
  1717. }
  1718. RTL_W8(Cfg9346, Cfg9346_Lock);
  1719. /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
  1720. RTL_R8(IntrMask);
  1721. RTL_W32(RxMissed, 0);
  1722. rtl_set_rx_mode(dev);
  1723. /* no early-rx interrupts */
  1724. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
  1725. /* Enable all known interrupts by setting the interrupt mask. */
  1726. RTL_W16(IntrMask, tp->intr_event);
  1727. }
  1728. static void rtl_hw_start_8168(struct net_device *dev)
  1729. {
  1730. struct rtl8169_private *tp = netdev_priv(dev);
  1731. void __iomem *ioaddr = tp->mmio_addr;
  1732. struct pci_dev *pdev = tp->pci_dev;
  1733. u8 ctl;
  1734. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1735. RTL_W8(EarlyTxThres, EarlyTxThld);
  1736. rtl_set_rx_max_size(ioaddr);
  1737. rtl_set_rx_tx_config_registers(tp);
  1738. tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
  1739. RTL_W16(CPlusCmd, tp->cp_cmd);
  1740. /* Tx performance tweak. */
  1741. pci_read_config_byte(pdev, 0x69, &ctl);
  1742. ctl = (ctl & ~0x70) | 0x50;
  1743. pci_write_config_byte(pdev, 0x69, ctl);
  1744. RTL_W16(IntrMitigate, 0x5151);
  1745. /* Work around for RxFIFO overflow. */
  1746. if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
  1747. tp->intr_event |= RxFIFOOver | PCSTimeout;
  1748. tp->intr_event &= ~RxOverflow;
  1749. }
  1750. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  1751. RTL_W8(Cfg9346, Cfg9346_Lock);
  1752. RTL_R8(IntrMask);
  1753. RTL_W32(RxMissed, 0);
  1754. rtl_set_rx_mode(dev);
  1755. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  1756. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
  1757. RTL_W16(IntrMask, tp->intr_event);
  1758. }
  1759. static void rtl_hw_start_8101(struct net_device *dev)
  1760. {
  1761. struct rtl8169_private *tp = netdev_priv(dev);
  1762. void __iomem *ioaddr = tp->mmio_addr;
  1763. struct pci_dev *pdev = tp->pci_dev;
  1764. if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
  1765. (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
  1766. pci_write_config_word(pdev, 0x68, 0x00);
  1767. pci_write_config_word(pdev, 0x69, 0x08);
  1768. }
  1769. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1770. RTL_W8(EarlyTxThres, EarlyTxThld);
  1771. rtl_set_rx_max_size(ioaddr);
  1772. tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
  1773. RTL_W16(CPlusCmd, tp->cp_cmd);
  1774. RTL_W16(IntrMitigate, 0x0000);
  1775. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  1776. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  1777. rtl_set_rx_tx_config_registers(tp);
  1778. RTL_W8(Cfg9346, Cfg9346_Lock);
  1779. RTL_R8(IntrMask);
  1780. RTL_W32(RxMissed, 0);
  1781. rtl_set_rx_mode(dev);
  1782. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  1783. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
  1784. RTL_W16(IntrMask, tp->intr_event);
  1785. }
  1786. static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
  1787. {
  1788. struct rtl8169_private *tp = netdev_priv(dev);
  1789. int ret = 0;
  1790. if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
  1791. return -EINVAL;
  1792. dev->mtu = new_mtu;
  1793. if (!netif_running(dev))
  1794. goto out;
  1795. rtl8169_down(dev);
  1796. rtl8169_set_rxbufsize(tp, dev);
  1797. ret = rtl8169_init_ring(dev);
  1798. if (ret < 0)
  1799. goto out;
  1800. napi_enable(&tp->napi);
  1801. rtl_hw_start(dev);
  1802. rtl8169_request_timer(dev);
  1803. out:
  1804. return ret;
  1805. }
  1806. static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
  1807. {
  1808. desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
  1809. desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
  1810. }
  1811. static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
  1812. struct sk_buff **sk_buff, struct RxDesc *desc)
  1813. {
  1814. struct pci_dev *pdev = tp->pci_dev;
  1815. pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
  1816. PCI_DMA_FROMDEVICE);
  1817. dev_kfree_skb(*sk_buff);
  1818. *sk_buff = NULL;
  1819. rtl8169_make_unusable_by_asic(desc);
  1820. }
  1821. static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
  1822. {
  1823. u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
  1824. desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
  1825. }
  1826. static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
  1827. u32 rx_buf_sz)
  1828. {
  1829. desc->addr = cpu_to_le64(mapping);
  1830. wmb();
  1831. rtl8169_mark_to_asic(desc, rx_buf_sz);
  1832. }
  1833. static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
  1834. struct net_device *dev,
  1835. struct RxDesc *desc, int rx_buf_sz,
  1836. unsigned int align)
  1837. {
  1838. struct sk_buff *skb;
  1839. dma_addr_t mapping;
  1840. unsigned int pad;
  1841. pad = align ? align : NET_IP_ALIGN;
  1842. skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
  1843. if (!skb)
  1844. goto err_out;
  1845. skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
  1846. mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
  1847. PCI_DMA_FROMDEVICE);
  1848. rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
  1849. out:
  1850. return skb;
  1851. err_out:
  1852. rtl8169_make_unusable_by_asic(desc);
  1853. goto out;
  1854. }
  1855. static void rtl8169_rx_clear(struct rtl8169_private *tp)
  1856. {
  1857. unsigned int i;
  1858. for (i = 0; i < NUM_RX_DESC; i++) {
  1859. if (tp->Rx_skbuff[i]) {
  1860. rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
  1861. tp->RxDescArray + i);
  1862. }
  1863. }
  1864. }
  1865. static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
  1866. u32 start, u32 end)
  1867. {
  1868. u32 cur;
  1869. for (cur = start; end - cur != 0; cur++) {
  1870. struct sk_buff *skb;
  1871. unsigned int i = cur % NUM_RX_DESC;
  1872. WARN_ON((s32)(end - cur) < 0);
  1873. if (tp->Rx_skbuff[i])
  1874. continue;
  1875. skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
  1876. tp->RxDescArray + i,
  1877. tp->rx_buf_sz, tp->align);
  1878. if (!skb)
  1879. break;
  1880. tp->Rx_skbuff[i] = skb;
  1881. }
  1882. return cur - start;
  1883. }
  1884. static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
  1885. {
  1886. desc->opts1 |= cpu_to_le32(RingEnd);
  1887. }
  1888. static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
  1889. {
  1890. tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
  1891. }
  1892. static int rtl8169_init_ring(struct net_device *dev)
  1893. {
  1894. struct rtl8169_private *tp = netdev_priv(dev);
  1895. rtl8169_init_ring_indexes(tp);
  1896. memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
  1897. memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
  1898. if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
  1899. goto err_out;
  1900. rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
  1901. return 0;
  1902. err_out:
  1903. rtl8169_rx_clear(tp);
  1904. return -ENOMEM;
  1905. }
  1906. static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
  1907. struct TxDesc *desc)
  1908. {
  1909. unsigned int len = tx_skb->len;
  1910. pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
  1911. desc->opts1 = 0x00;
  1912. desc->opts2 = 0x00;
  1913. desc->addr = 0x00;
  1914. tx_skb->len = 0;
  1915. }
  1916. static void rtl8169_tx_clear(struct rtl8169_private *tp)
  1917. {
  1918. unsigned int i;
  1919. for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
  1920. unsigned int entry = i % NUM_TX_DESC;
  1921. struct ring_info *tx_skb = tp->tx_skb + entry;
  1922. unsigned int len = tx_skb->len;
  1923. if (len) {
  1924. struct sk_buff *skb = tx_skb->skb;
  1925. rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
  1926. tp->TxDescArray + entry);
  1927. if (skb) {
  1928. dev_kfree_skb(skb);
  1929. tx_skb->skb = NULL;
  1930. }
  1931. tp->dev->stats.tx_dropped++;
  1932. }
  1933. }
  1934. tp->cur_tx = tp->dirty_tx = 0;
  1935. }
  1936. static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
  1937. {
  1938. struct rtl8169_private *tp = netdev_priv(dev);
  1939. PREPARE_DELAYED_WORK(&tp->task, task);
  1940. schedule_delayed_work(&tp->task, 4);
  1941. }
  1942. static void rtl8169_wait_for_quiescence(struct net_device *dev)
  1943. {
  1944. struct rtl8169_private *tp = netdev_priv(dev);
  1945. void __iomem *ioaddr = tp->mmio_addr;
  1946. synchronize_irq(dev->irq);
  1947. /* Wait for any pending NAPI task to complete */
  1948. napi_disable(&tp->napi);
  1949. rtl8169_irq_mask_and_ack(ioaddr);
  1950. tp->intr_mask = 0xffff;
  1951. RTL_W16(IntrMask, tp->intr_event);
  1952. napi_enable(&tp->napi);
  1953. }
  1954. static void rtl8169_reinit_task(struct work_struct *work)
  1955. {
  1956. struct rtl8169_private *tp =
  1957. container_of(work, struct rtl8169_private, task.work);
  1958. struct net_device *dev = tp->dev;
  1959. int ret;
  1960. rtnl_lock();
  1961. if (!netif_running(dev))
  1962. goto out_unlock;
  1963. rtl8169_wait_for_quiescence(dev);
  1964. rtl8169_close(dev);
  1965. ret = rtl8169_open(dev);
  1966. if (unlikely(ret < 0)) {
  1967. if (net_ratelimit() && netif_msg_drv(tp)) {
  1968. printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
  1969. " Rescheduling.\n", dev->name, ret);
  1970. }
  1971. rtl8169_schedule_work(dev, rtl8169_reinit_task);
  1972. }
  1973. out_unlock:
  1974. rtnl_unlock();
  1975. }
  1976. static void rtl8169_reset_task(struct work_struct *work)
  1977. {
  1978. struct rtl8169_private *tp =
  1979. container_of(work, struct rtl8169_private, task.work);
  1980. struct net_device *dev = tp->dev;
  1981. rtnl_lock();
  1982. if (!netif_running(dev))
  1983. goto out_unlock;
  1984. rtl8169_wait_for_quiescence(dev);
  1985. rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
  1986. rtl8169_tx_clear(tp);
  1987. if (tp->dirty_rx == tp->cur_rx) {
  1988. rtl8169_init_ring_indexes(tp);
  1989. rtl_hw_start(dev);
  1990. netif_wake_queue(dev);
  1991. rtl8169_check_link_status(dev, tp, tp->mmio_addr);
  1992. } else {
  1993. if (net_ratelimit() && netif_msg_intr(tp)) {
  1994. printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
  1995. dev->name);
  1996. }
  1997. rtl8169_schedule_work(dev, rtl8169_reset_task);
  1998. }
  1999. out_unlock:
  2000. rtnl_unlock();
  2001. }
  2002. static void rtl8169_tx_timeout(struct net_device *dev)
  2003. {
  2004. struct rtl8169_private *tp = netdev_priv(dev);
  2005. rtl8169_hw_reset(tp->mmio_addr);
  2006. /* Let's wait a bit while any (async) irq lands on */
  2007. rtl8169_schedule_work(dev, rtl8169_reset_task);
  2008. }
  2009. static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
  2010. u32 opts1)
  2011. {
  2012. struct skb_shared_info *info = skb_shinfo(skb);
  2013. unsigned int cur_frag, entry;
  2014. struct TxDesc * uninitialized_var(txd);
  2015. entry = tp->cur_tx;
  2016. for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
  2017. skb_frag_t *frag = info->frags + cur_frag;
  2018. dma_addr_t mapping;
  2019. u32 status, len;
  2020. void *addr;
  2021. entry = (entry + 1) % NUM_TX_DESC;
  2022. txd = tp->TxDescArray + entry;
  2023. len = frag->size;
  2024. addr = ((void *) page_address(frag->page)) + frag->page_offset;
  2025. mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
  2026. /* anti gcc 2.95.3 bugware (sic) */
  2027. status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
  2028. txd->opts1 = cpu_to_le32(status);
  2029. txd->addr = cpu_to_le64(mapping);
  2030. tp->tx_skb[entry].len = len;
  2031. }
  2032. if (cur_frag) {
  2033. tp->tx_skb[entry].skb = skb;
  2034. txd->opts1 |= cpu_to_le32(LastFrag);
  2035. }
  2036. return cur_frag;
  2037. }
  2038. static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
  2039. {
  2040. if (dev->features & NETIF_F_TSO) {
  2041. u32 mss = skb_shinfo(skb)->gso_size;
  2042. if (mss)
  2043. return LargeSend | ((mss & MSSMask) << MSSShift);
  2044. }
  2045. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  2046. const struct iphdr *ip = ip_hdr(skb);
  2047. if (ip->protocol == IPPROTO_TCP)
  2048. return IPCS | TCPCS;
  2049. else if (ip->protocol == IPPROTO_UDP)
  2050. return IPCS | UDPCS;
  2051. WARN_ON(1); /* we need a WARN() */
  2052. }
  2053. return 0;
  2054. }
  2055. static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
  2056. {
  2057. struct rtl8169_private *tp = netdev_priv(dev);
  2058. unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
  2059. struct TxDesc *txd = tp->TxDescArray + entry;
  2060. void __iomem *ioaddr = tp->mmio_addr;
  2061. dma_addr_t mapping;
  2062. u32 status, len;
  2063. u32 opts1;
  2064. int ret = NETDEV_TX_OK;
  2065. if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
  2066. if (netif_msg_drv(tp)) {
  2067. printk(KERN_ERR
  2068. "%s: BUG! Tx Ring full when queue awake!\n",
  2069. dev->name);
  2070. }
  2071. goto err_stop;
  2072. }
  2073. if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
  2074. goto err_stop;
  2075. opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
  2076. frags = rtl8169_xmit_frags(tp, skb, opts1);
  2077. if (frags) {
  2078. len = skb_headlen(skb);
  2079. opts1 |= FirstFrag;
  2080. } else {
  2081. len = skb->len;
  2082. if (unlikely(len < ETH_ZLEN)) {
  2083. if (skb_padto(skb, ETH_ZLEN))
  2084. goto err_update_stats;
  2085. len = ETH_ZLEN;
  2086. }
  2087. opts1 |= FirstFrag | LastFrag;
  2088. tp->tx_skb[entry].skb = skb;
  2089. }
  2090. mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  2091. tp->tx_skb[entry].len = len;
  2092. txd->addr = cpu_to_le64(mapping);
  2093. txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
  2094. wmb();
  2095. /* anti gcc 2.95.3 bugware (sic) */
  2096. status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
  2097. txd->opts1 = cpu_to_le32(status);
  2098. dev->trans_start = jiffies;
  2099. tp->cur_tx += frags + 1;
  2100. smp_wmb();
  2101. RTL_W8(TxPoll, NPQ); /* set polling bit */
  2102. if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
  2103. netif_stop_queue(dev);
  2104. smp_rmb();
  2105. if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
  2106. netif_wake_queue(dev);
  2107. }
  2108. out:
  2109. return ret;
  2110. err_stop:
  2111. netif_stop_queue(dev);
  2112. ret = NETDEV_TX_BUSY;
  2113. err_update_stats:
  2114. dev->stats.tx_dropped++;
  2115. goto out;
  2116. }
  2117. static void rtl8169_pcierr_interrupt(struct net_device *dev)
  2118. {
  2119. struct rtl8169_private *tp = netdev_priv(dev);
  2120. struct pci_dev *pdev = tp->pci_dev;
  2121. void __iomem *ioaddr = tp->mmio_addr;
  2122. u16 pci_status, pci_cmd;
  2123. pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
  2124. pci_read_config_word(pdev, PCI_STATUS, &pci_status);
  2125. if (netif_msg_intr(tp)) {
  2126. printk(KERN_ERR
  2127. "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
  2128. dev->name, pci_cmd, pci_status);
  2129. }
  2130. /*
  2131. * The recovery sequence below admits a very elaborated explanation:
  2132. * - it seems to work;
  2133. * - I did not see what else could be done;
  2134. * - it makes iop3xx happy.
  2135. *
  2136. * Feel free to adjust to your needs.
  2137. */
  2138. if (pdev->broken_parity_status)
  2139. pci_cmd &= ~PCI_COMMAND_PARITY;
  2140. else
  2141. pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
  2142. pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
  2143. pci_write_config_word(pdev, PCI_STATUS,
  2144. pci_status & (PCI_STATUS_DETECTED_PARITY |
  2145. PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
  2146. PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
  2147. /* The infamous DAC f*ckup only happens at boot time */
  2148. if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
  2149. if (netif_msg_intr(tp))
  2150. printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
  2151. tp->cp_cmd &= ~PCIDAC;
  2152. RTL_W16(CPlusCmd, tp->cp_cmd);
  2153. dev->features &= ~NETIF_F_HIGHDMA;
  2154. }
  2155. rtl8169_hw_reset(ioaddr);
  2156. rtl8169_schedule_work(dev, rtl8169_reinit_task);
  2157. }
  2158. static void rtl8169_tx_interrupt(struct net_device *dev,
  2159. struct rtl8169_private *tp,
  2160. void __iomem *ioaddr)
  2161. {
  2162. unsigned int dirty_tx, tx_left;
  2163. dirty_tx = tp->dirty_tx;
  2164. smp_rmb();
  2165. tx_left = tp->cur_tx - dirty_tx;
  2166. while (tx_left > 0) {
  2167. unsigned int entry = dirty_tx % NUM_TX_DESC;
  2168. struct ring_info *tx_skb = tp->tx_skb + entry;
  2169. u32 len = tx_skb->len;
  2170. u32 status;
  2171. rmb();
  2172. status = le32_to_cpu(tp->TxDescArray[entry].opts1);
  2173. if (status & DescOwn)
  2174. break;
  2175. dev->stats.tx_bytes += len;
  2176. dev->stats.tx_packets++;
  2177. rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
  2178. if (status & LastFrag) {
  2179. dev_kfree_skb_irq(tx_skb->skb);
  2180. tx_skb->skb = NULL;
  2181. }
  2182. dirty_tx++;
  2183. tx_left--;
  2184. }
  2185. if (tp->dirty_tx != dirty_tx) {
  2186. tp->dirty_tx = dirty_tx;
  2187. smp_wmb();
  2188. if (netif_queue_stopped(dev) &&
  2189. (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
  2190. netif_wake_queue(dev);
  2191. }
  2192. /*
  2193. * 8168 hack: TxPoll requests are lost when the Tx packets are
  2194. * too close. Let's kick an extra TxPoll request when a burst
  2195. * of start_xmit activity is detected (if it is not detected,
  2196. * it is slow enough). -- FR
  2197. */
  2198. smp_rmb();
  2199. if (tp->cur_tx != dirty_tx)
  2200. RTL_W8(TxPoll, NPQ);
  2201. }
  2202. }
  2203. static inline int rtl8169_fragmented_frame(u32 status)
  2204. {
  2205. return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
  2206. }
  2207. static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
  2208. {
  2209. u32 opts1 = le32_to_cpu(desc->opts1);
  2210. u32 status = opts1 & RxProtoMask;
  2211. if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
  2212. ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
  2213. ((status == RxProtoIP) && !(opts1 & IPFail)))
  2214. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2215. else
  2216. skb->ip_summed = CHECKSUM_NONE;
  2217. }
  2218. static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
  2219. struct rtl8169_private *tp, int pkt_size,
  2220. dma_addr_t addr)
  2221. {
  2222. struct sk_buff *skb;
  2223. bool done = false;
  2224. if (pkt_size >= rx_copybreak)
  2225. goto out;
  2226. skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
  2227. if (!skb)
  2228. goto out;
  2229. pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
  2230. PCI_DMA_FROMDEVICE);
  2231. skb_reserve(skb, NET_IP_ALIGN);
  2232. skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
  2233. *sk_buff = skb;
  2234. done = true;
  2235. out:
  2236. return done;
  2237. }
  2238. static int rtl8169_rx_interrupt(struct net_device *dev,
  2239. struct rtl8169_private *tp,
  2240. void __iomem *ioaddr, u32 budget)
  2241. {
  2242. unsigned int cur_rx, rx_left;
  2243. unsigned int delta, count;
  2244. cur_rx = tp->cur_rx;
  2245. rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
  2246. rx_left = min(rx_left, budget);
  2247. for (; rx_left > 0; rx_left--, cur_rx++) {
  2248. unsigned int entry = cur_rx % NUM_RX_DESC;
  2249. struct RxDesc *desc = tp->RxDescArray + entry;
  2250. u32 status;
  2251. rmb();
  2252. status = le32_to_cpu(desc->opts1);
  2253. if (status & DescOwn)
  2254. break;
  2255. if (unlikely(status & RxRES)) {
  2256. if (netif_msg_rx_err(tp)) {
  2257. printk(KERN_INFO
  2258. "%s: Rx ERROR. status = %08x\n",
  2259. dev->name, status);
  2260. }
  2261. dev->stats.rx_errors++;
  2262. if (status & (RxRWT | RxRUNT))
  2263. dev->stats.rx_length_errors++;
  2264. if (status & RxCRC)
  2265. dev->stats.rx_crc_errors++;
  2266. if (status & RxFOVF) {
  2267. rtl8169_schedule_work(dev, rtl8169_reset_task);
  2268. dev->stats.rx_fifo_errors++;
  2269. }
  2270. rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
  2271. } else {
  2272. struct sk_buff *skb = tp->Rx_skbuff[entry];
  2273. dma_addr_t addr = le64_to_cpu(desc->addr);
  2274. int pkt_size = (status & 0x00001FFF) - 4;
  2275. struct pci_dev *pdev = tp->pci_dev;
  2276. /*
  2277. * The driver does not support incoming fragmented
  2278. * frames. They are seen as a symptom of over-mtu
  2279. * sized frames.
  2280. */
  2281. if (unlikely(rtl8169_fragmented_frame(status))) {
  2282. dev->stats.rx_dropped++;
  2283. dev->stats.rx_length_errors++;
  2284. rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
  2285. continue;
  2286. }
  2287. rtl8169_rx_csum(skb, desc);
  2288. if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
  2289. pci_dma_sync_single_for_device(pdev, addr,
  2290. pkt_size, PCI_DMA_FROMDEVICE);
  2291. rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
  2292. } else {
  2293. pci_unmap_single(pdev, addr, pkt_size,
  2294. PCI_DMA_FROMDEVICE);
  2295. tp->Rx_skbuff[entry] = NULL;
  2296. }
  2297. skb_put(skb, pkt_size);
  2298. skb->protocol = eth_type_trans(skb, dev);
  2299. if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
  2300. netif_receive_skb(skb);
  2301. dev->last_rx = jiffies;
  2302. dev->stats.rx_bytes += pkt_size;
  2303. dev->stats.rx_packets++;
  2304. }
  2305. /* Work around for AMD plateform. */
  2306. if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
  2307. (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
  2308. desc->opts2 = 0;
  2309. cur_rx++;
  2310. }
  2311. }
  2312. count = cur_rx - tp->cur_rx;
  2313. tp->cur_rx = cur_rx;
  2314. delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
  2315. if (!delta && count && netif_msg_intr(tp))
  2316. printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
  2317. tp->dirty_rx += delta;
  2318. /*
  2319. * FIXME: until there is periodic timer to try and refill the ring,
  2320. * a temporary shortage may definitely kill the Rx process.
  2321. * - disable the asic to try and avoid an overflow and kick it again
  2322. * after refill ?
  2323. * - how do others driver handle this condition (Uh oh...).
  2324. */
  2325. if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
  2326. printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
  2327. return count;
  2328. }
  2329. static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
  2330. {
  2331. struct net_device *dev = dev_instance;
  2332. struct rtl8169_private *tp = netdev_priv(dev);
  2333. void __iomem *ioaddr = tp->mmio_addr;
  2334. int handled = 0;
  2335. int status;
  2336. status = RTL_R16(IntrStatus);
  2337. /* hotplug/major error/no more work/shared irq */
  2338. if ((status == 0xffff) || !status)
  2339. goto out;
  2340. handled = 1;
  2341. if (unlikely(!netif_running(dev))) {
  2342. rtl8169_asic_down(ioaddr);
  2343. goto out;
  2344. }
  2345. status &= tp->intr_mask;
  2346. RTL_W16(IntrStatus,
  2347. (status & RxFIFOOver) ? (status | RxOverflow) : status);
  2348. if (!(status & tp->intr_event))
  2349. goto out;
  2350. /* Work around for rx fifo overflow */
  2351. if (unlikely(status & RxFIFOOver) &&
  2352. (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
  2353. netif_stop_queue(dev);
  2354. rtl8169_tx_timeout(dev);
  2355. goto out;
  2356. }
  2357. if (unlikely(status & SYSErr)) {
  2358. rtl8169_pcierr_interrupt(dev);
  2359. goto out;
  2360. }
  2361. if (status & LinkChg)
  2362. rtl8169_check_link_status(dev, tp, ioaddr);
  2363. if (status & tp->napi_event) {
  2364. RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
  2365. tp->intr_mask = ~tp->napi_event;
  2366. if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
  2367. __netif_rx_schedule(dev, &tp->napi);
  2368. else if (netif_msg_intr(tp)) {
  2369. printk(KERN_INFO "%s: interrupt %04x in poll\n",
  2370. dev->name, status);
  2371. }
  2372. }
  2373. out:
  2374. return IRQ_RETVAL(handled);
  2375. }
  2376. static int rtl8169_poll(struct napi_struct *napi, int budget)
  2377. {
  2378. struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
  2379. struct net_device *dev = tp->dev;
  2380. void __iomem *ioaddr = tp->mmio_addr;
  2381. int work_done;
  2382. work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
  2383. rtl8169_tx_interrupt(dev, tp, ioaddr);
  2384. if (work_done < budget) {
  2385. netif_rx_complete(dev, napi);
  2386. tp->intr_mask = 0xffff;
  2387. /*
  2388. * 20040426: the barrier is not strictly required but the
  2389. * behavior of the irq handler could be less predictable
  2390. * without it. Btw, the lack of flush for the posted pci
  2391. * write is safe - FR
  2392. */
  2393. smp_wmb();
  2394. RTL_W16(IntrMask, tp->intr_event);
  2395. }
  2396. return work_done;
  2397. }
  2398. static void rtl8169_down(struct net_device *dev)
  2399. {
  2400. struct rtl8169_private *tp = netdev_priv(dev);
  2401. void __iomem *ioaddr = tp->mmio_addr;
  2402. unsigned int intrmask;
  2403. rtl8169_delete_timer(dev);
  2404. netif_stop_queue(dev);
  2405. napi_disable(&tp->napi);
  2406. core_down:
  2407. spin_lock_irq(&tp->lock);
  2408. rtl8169_asic_down(ioaddr);
  2409. /* Update the error counts. */
  2410. dev->stats.rx_missed_errors += RTL_R32(RxMissed);
  2411. RTL_W32(RxMissed, 0);
  2412. spin_unlock_irq(&tp->lock);
  2413. synchronize_irq(dev->irq);
  2414. /* Give a racing hard_start_xmit a few cycles to complete. */
  2415. synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
  2416. /*
  2417. * And now for the 50k$ question: are IRQ disabled or not ?
  2418. *
  2419. * Two paths lead here:
  2420. * 1) dev->close
  2421. * -> netif_running() is available to sync the current code and the
  2422. * IRQ handler. See rtl8169_interrupt for details.
  2423. * 2) dev->change_mtu
  2424. * -> rtl8169_poll can not be issued again and re-enable the
  2425. * interruptions. Let's simply issue the IRQ down sequence again.
  2426. *
  2427. * No loop if hotpluged or major error (0xffff).
  2428. */
  2429. intrmask = RTL_R16(IntrMask);
  2430. if (intrmask && (intrmask != 0xffff))
  2431. goto core_down;
  2432. rtl8169_tx_clear(tp);
  2433. rtl8169_rx_clear(tp);
  2434. }
  2435. static int rtl8169_close(struct net_device *dev)
  2436. {
  2437. struct rtl8169_private *tp = netdev_priv(dev);
  2438. struct pci_dev *pdev = tp->pci_dev;
  2439. rtl8169_down(dev);
  2440. free_irq(dev->irq, dev);
  2441. pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
  2442. tp->RxPhyAddr);
  2443. pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
  2444. tp->TxPhyAddr);
  2445. tp->TxDescArray = NULL;
  2446. tp->RxDescArray = NULL;
  2447. return 0;
  2448. }
  2449. static void rtl_set_rx_mode(struct net_device *dev)
  2450. {
  2451. struct rtl8169_private *tp = netdev_priv(dev);
  2452. void __iomem *ioaddr = tp->mmio_addr;
  2453. unsigned long flags;
  2454. u32 mc_filter[2]; /* Multicast hash filter */
  2455. int rx_mode;
  2456. u32 tmp = 0;
  2457. if (dev->flags & IFF_PROMISC) {
  2458. /* Unconditionally log net taps. */
  2459. if (netif_msg_link(tp)) {
  2460. printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
  2461. dev->name);
  2462. }
  2463. rx_mode =
  2464. AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
  2465. AcceptAllPhys;
  2466. mc_filter[1] = mc_filter[0] = 0xffffffff;
  2467. } else if ((dev->mc_count > multicast_filter_limit)
  2468. || (dev->flags & IFF_ALLMULTI)) {
  2469. /* Too many to filter perfectly -- accept all multicasts. */
  2470. rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
  2471. mc_filter[1] = mc_filter[0] = 0xffffffff;
  2472. } else {
  2473. struct dev_mc_list *mclist;
  2474. unsigned int i;
  2475. rx_mode = AcceptBroadcast | AcceptMyPhys;
  2476. mc_filter[1] = mc_filter[0] = 0;
  2477. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  2478. i++, mclist = mclist->next) {
  2479. int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
  2480. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  2481. rx_mode |= AcceptMulticast;
  2482. }
  2483. }
  2484. spin_lock_irqsave(&tp->lock, flags);
  2485. tmp = rtl8169_rx_config | rx_mode |
  2486. (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
  2487. if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
  2488. u32 data = mc_filter[0];
  2489. mc_filter[0] = swab32(mc_filter[1]);
  2490. mc_filter[1] = swab32(data);
  2491. }
  2492. RTL_W32(MAR0 + 0, mc_filter[0]);
  2493. RTL_W32(MAR0 + 4, mc_filter[1]);
  2494. RTL_W32(RxConfig, tmp);
  2495. spin_unlock_irqrestore(&tp->lock, flags);
  2496. }
  2497. /**
  2498. * rtl8169_get_stats - Get rtl8169 read/write statistics
  2499. * @dev: The Ethernet Device to get statistics for
  2500. *
  2501. * Get TX/RX statistics for rtl8169
  2502. */
  2503. static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
  2504. {
  2505. struct rtl8169_private *tp = netdev_priv(dev);
  2506. void __iomem *ioaddr = tp->mmio_addr;
  2507. unsigned long flags;
  2508. if (netif_running(dev)) {
  2509. spin_lock_irqsave(&tp->lock, flags);
  2510. dev->stats.rx_missed_errors += RTL_R32(RxMissed);
  2511. RTL_W32(RxMissed, 0);
  2512. spin_unlock_irqrestore(&tp->lock, flags);
  2513. }
  2514. return &dev->stats;
  2515. }
  2516. #ifdef CONFIG_PM
  2517. static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
  2518. {
  2519. struct net_device *dev = pci_get_drvdata(pdev);
  2520. struct rtl8169_private *tp = netdev_priv(dev);
  2521. void __iomem *ioaddr = tp->mmio_addr;
  2522. if (!netif_running(dev))
  2523. goto out_pci_suspend;
  2524. netif_device_detach(dev);
  2525. netif_stop_queue(dev);
  2526. spin_lock_irq(&tp->lock);
  2527. rtl8169_asic_down(ioaddr);
  2528. dev->stats.rx_missed_errors += RTL_R32(RxMissed);
  2529. RTL_W32(RxMissed, 0);
  2530. spin_unlock_irq(&tp->lock);
  2531. out_pci_suspend:
  2532. pci_save_state(pdev);
  2533. pci_enable_wake(pdev, pci_choose_state(pdev, state),
  2534. (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
  2535. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  2536. return 0;
  2537. }
  2538. static int rtl8169_resume(struct pci_dev *pdev)
  2539. {
  2540. struct net_device *dev = pci_get_drvdata(pdev);
  2541. pci_set_power_state(pdev, PCI_D0);
  2542. pci_restore_state(pdev);
  2543. pci_enable_wake(pdev, PCI_D0, 0);
  2544. if (!netif_running(dev))
  2545. goto out;
  2546. netif_device_attach(dev);
  2547. rtl8169_schedule_work(dev, rtl8169_reset_task);
  2548. out:
  2549. return 0;
  2550. }
  2551. #endif /* CONFIG_PM */
  2552. static struct pci_driver rtl8169_pci_driver = {
  2553. .name = MODULENAME,
  2554. .id_table = rtl8169_pci_tbl,
  2555. .probe = rtl8169_init_one,
  2556. .remove = __devexit_p(rtl8169_remove_one),
  2557. #ifdef CONFIG_PM
  2558. .suspend = rtl8169_suspend,
  2559. .resume = rtl8169_resume,
  2560. #endif
  2561. };
  2562. static int __init rtl8169_init_module(void)
  2563. {
  2564. return pci_register_driver(&rtl8169_pci_driver);
  2565. }
  2566. static void __exit rtl8169_cleanup_module(void)
  2567. {
  2568. pci_unregister_driver(&rtl8169_pci_driver);
  2569. }
  2570. module_init(rtl8169_init_module);
  2571. module_exit(rtl8169_cleanup_module);