niu.c 202 KB

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  1. /* niu.c: Neptune ethernet driver.
  2. *
  3. * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
  4. */
  5. #include <linux/module.h>
  6. #include <linux/init.h>
  7. #include <linux/pci.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/netdevice.h>
  10. #include <linux/ethtool.h>
  11. #include <linux/etherdevice.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/delay.h>
  14. #include <linux/bitops.h>
  15. #include <linux/mii.h>
  16. #include <linux/if_ether.h>
  17. #include <linux/if_vlan.h>
  18. #include <linux/ip.h>
  19. #include <linux/in.h>
  20. #include <linux/ipv6.h>
  21. #include <linux/log2.h>
  22. #include <linux/jiffies.h>
  23. #include <linux/crc32.h>
  24. #include <linux/io.h>
  25. #ifdef CONFIG_SPARC64
  26. #include <linux/of_device.h>
  27. #endif
  28. #include "niu.h"
  29. #define DRV_MODULE_NAME "niu"
  30. #define PFX DRV_MODULE_NAME ": "
  31. #define DRV_MODULE_VERSION "0.9"
  32. #define DRV_MODULE_RELDATE "May 4, 2008"
  33. static char version[] __devinitdata =
  34. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  35. MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  36. MODULE_DESCRIPTION("NIU ethernet driver");
  37. MODULE_LICENSE("GPL");
  38. MODULE_VERSION(DRV_MODULE_VERSION);
  39. #ifndef DMA_44BIT_MASK
  40. #define DMA_44BIT_MASK 0x00000fffffffffffULL
  41. #endif
  42. #ifndef readq
  43. static u64 readq(void __iomem *reg)
  44. {
  45. return (((u64)readl(reg + 0x4UL) << 32) |
  46. (u64)readl(reg));
  47. }
  48. static void writeq(u64 val, void __iomem *reg)
  49. {
  50. writel(val & 0xffffffff, reg);
  51. writel(val >> 32, reg + 0x4UL);
  52. }
  53. #endif
  54. static struct pci_device_id niu_pci_tbl[] = {
  55. {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  56. {}
  57. };
  58. MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  59. #define NIU_TX_TIMEOUT (5 * HZ)
  60. #define nr64(reg) readq(np->regs + (reg))
  61. #define nw64(reg, val) writeq((val), np->regs + (reg))
  62. #define nr64_mac(reg) readq(np->mac_regs + (reg))
  63. #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
  64. #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
  65. #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
  66. #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
  67. #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
  68. #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
  69. #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
  70. #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  71. static int niu_debug;
  72. static int debug = -1;
  73. module_param(debug, int, 0);
  74. MODULE_PARM_DESC(debug, "NIU debug level");
  75. #define niudbg(TYPE, f, a...) \
  76. do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
  77. printk(KERN_DEBUG PFX f, ## a); \
  78. } while (0)
  79. #define niuinfo(TYPE, f, a...) \
  80. do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
  81. printk(KERN_INFO PFX f, ## a); \
  82. } while (0)
  83. #define niuwarn(TYPE, f, a...) \
  84. do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
  85. printk(KERN_WARNING PFX f, ## a); \
  86. } while (0)
  87. #define niu_lock_parent(np, flags) \
  88. spin_lock_irqsave(&np->parent->lock, flags)
  89. #define niu_unlock_parent(np, flags) \
  90. spin_unlock_irqrestore(&np->parent->lock, flags)
  91. static int serdes_init_10g_serdes(struct niu *np);
  92. static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
  93. u64 bits, int limit, int delay)
  94. {
  95. while (--limit >= 0) {
  96. u64 val = nr64_mac(reg);
  97. if (!(val & bits))
  98. break;
  99. udelay(delay);
  100. }
  101. if (limit < 0)
  102. return -ENODEV;
  103. return 0;
  104. }
  105. static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
  106. u64 bits, int limit, int delay,
  107. const char *reg_name)
  108. {
  109. int err;
  110. nw64_mac(reg, bits);
  111. err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
  112. if (err)
  113. dev_err(np->device, PFX "%s: bits (%llx) of register %s "
  114. "would not clear, val[%llx]\n",
  115. np->dev->name, (unsigned long long) bits, reg_name,
  116. (unsigned long long) nr64_mac(reg));
  117. return err;
  118. }
  119. #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
  120. ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
  121. __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
  122. })
  123. static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
  124. u64 bits, int limit, int delay)
  125. {
  126. while (--limit >= 0) {
  127. u64 val = nr64_ipp(reg);
  128. if (!(val & bits))
  129. break;
  130. udelay(delay);
  131. }
  132. if (limit < 0)
  133. return -ENODEV;
  134. return 0;
  135. }
  136. static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
  137. u64 bits, int limit, int delay,
  138. const char *reg_name)
  139. {
  140. int err;
  141. u64 val;
  142. val = nr64_ipp(reg);
  143. val |= bits;
  144. nw64_ipp(reg, val);
  145. err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
  146. if (err)
  147. dev_err(np->device, PFX "%s: bits (%llx) of register %s "
  148. "would not clear, val[%llx]\n",
  149. np->dev->name, (unsigned long long) bits, reg_name,
  150. (unsigned long long) nr64_ipp(reg));
  151. return err;
  152. }
  153. #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
  154. ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
  155. __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
  156. })
  157. static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
  158. u64 bits, int limit, int delay)
  159. {
  160. while (--limit >= 0) {
  161. u64 val = nr64(reg);
  162. if (!(val & bits))
  163. break;
  164. udelay(delay);
  165. }
  166. if (limit < 0)
  167. return -ENODEV;
  168. return 0;
  169. }
  170. #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
  171. ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
  172. __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
  173. })
  174. static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
  175. u64 bits, int limit, int delay,
  176. const char *reg_name)
  177. {
  178. int err;
  179. nw64(reg, bits);
  180. err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
  181. if (err)
  182. dev_err(np->device, PFX "%s: bits (%llx) of register %s "
  183. "would not clear, val[%llx]\n",
  184. np->dev->name, (unsigned long long) bits, reg_name,
  185. (unsigned long long) nr64(reg));
  186. return err;
  187. }
  188. #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
  189. ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
  190. __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
  191. })
  192. static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
  193. {
  194. u64 val = (u64) lp->timer;
  195. if (on)
  196. val |= LDG_IMGMT_ARM;
  197. nw64(LDG_IMGMT(lp->ldg_num), val);
  198. }
  199. static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
  200. {
  201. unsigned long mask_reg, bits;
  202. u64 val;
  203. if (ldn < 0 || ldn > LDN_MAX)
  204. return -EINVAL;
  205. if (ldn < 64) {
  206. mask_reg = LD_IM0(ldn);
  207. bits = LD_IM0_MASK;
  208. } else {
  209. mask_reg = LD_IM1(ldn - 64);
  210. bits = LD_IM1_MASK;
  211. }
  212. val = nr64(mask_reg);
  213. if (on)
  214. val &= ~bits;
  215. else
  216. val |= bits;
  217. nw64(mask_reg, val);
  218. return 0;
  219. }
  220. static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
  221. {
  222. struct niu_parent *parent = np->parent;
  223. int i;
  224. for (i = 0; i <= LDN_MAX; i++) {
  225. int err;
  226. if (parent->ldg_map[i] != lp->ldg_num)
  227. continue;
  228. err = niu_ldn_irq_enable(np, i, on);
  229. if (err)
  230. return err;
  231. }
  232. return 0;
  233. }
  234. static int niu_enable_interrupts(struct niu *np, int on)
  235. {
  236. int i;
  237. for (i = 0; i < np->num_ldg; i++) {
  238. struct niu_ldg *lp = &np->ldg[i];
  239. int err;
  240. err = niu_enable_ldn_in_ldg(np, lp, on);
  241. if (err)
  242. return err;
  243. }
  244. for (i = 0; i < np->num_ldg; i++)
  245. niu_ldg_rearm(np, &np->ldg[i], on);
  246. return 0;
  247. }
  248. static u32 phy_encode(u32 type, int port)
  249. {
  250. return (type << (port * 2));
  251. }
  252. static u32 phy_decode(u32 val, int port)
  253. {
  254. return (val >> (port * 2)) & PORT_TYPE_MASK;
  255. }
  256. static int mdio_wait(struct niu *np)
  257. {
  258. int limit = 1000;
  259. u64 val;
  260. while (--limit > 0) {
  261. val = nr64(MIF_FRAME_OUTPUT);
  262. if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
  263. return val & MIF_FRAME_OUTPUT_DATA;
  264. udelay(10);
  265. }
  266. return -ENODEV;
  267. }
  268. static int mdio_read(struct niu *np, int port, int dev, int reg)
  269. {
  270. int err;
  271. nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
  272. err = mdio_wait(np);
  273. if (err < 0)
  274. return err;
  275. nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
  276. return mdio_wait(np);
  277. }
  278. static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
  279. {
  280. int err;
  281. nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
  282. err = mdio_wait(np);
  283. if (err < 0)
  284. return err;
  285. nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
  286. err = mdio_wait(np);
  287. if (err < 0)
  288. return err;
  289. return 0;
  290. }
  291. static int mii_read(struct niu *np, int port, int reg)
  292. {
  293. nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
  294. return mdio_wait(np);
  295. }
  296. static int mii_write(struct niu *np, int port, int reg, int data)
  297. {
  298. int err;
  299. nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
  300. err = mdio_wait(np);
  301. if (err < 0)
  302. return err;
  303. return 0;
  304. }
  305. static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
  306. {
  307. int err;
  308. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  309. ESR2_TI_PLL_TX_CFG_L(channel),
  310. val & 0xffff);
  311. if (!err)
  312. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  313. ESR2_TI_PLL_TX_CFG_H(channel),
  314. val >> 16);
  315. return err;
  316. }
  317. static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
  318. {
  319. int err;
  320. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  321. ESR2_TI_PLL_RX_CFG_L(channel),
  322. val & 0xffff);
  323. if (!err)
  324. err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  325. ESR2_TI_PLL_RX_CFG_H(channel),
  326. val >> 16);
  327. return err;
  328. }
  329. /* Mode is always 10G fiber. */
  330. static int serdes_init_niu(struct niu *np)
  331. {
  332. struct niu_link_config *lp = &np->link_config;
  333. u32 tx_cfg, rx_cfg;
  334. unsigned long i;
  335. tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
  336. rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
  337. PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
  338. PLL_RX_CFG_EQ_LP_ADAPTIVE);
  339. if (lp->loopback_mode == LOOPBACK_PHY) {
  340. u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
  341. mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
  342. ESR2_TI_PLL_TEST_CFG_L, test_cfg);
  343. tx_cfg |= PLL_TX_CFG_ENTEST;
  344. rx_cfg |= PLL_RX_CFG_ENTEST;
  345. }
  346. /* Initialize all 4 lanes of the SERDES. */
  347. for (i = 0; i < 4; i++) {
  348. int err = esr2_set_tx_cfg(np, i, tx_cfg);
  349. if (err)
  350. return err;
  351. }
  352. for (i = 0; i < 4; i++) {
  353. int err = esr2_set_rx_cfg(np, i, rx_cfg);
  354. if (err)
  355. return err;
  356. }
  357. return 0;
  358. }
  359. static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
  360. {
  361. int err;
  362. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
  363. if (err >= 0) {
  364. *val = (err & 0xffff);
  365. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
  366. ESR_RXTX_CTRL_H(chan));
  367. if (err >= 0)
  368. *val |= ((err & 0xffff) << 16);
  369. err = 0;
  370. }
  371. return err;
  372. }
  373. static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
  374. {
  375. int err;
  376. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
  377. ESR_GLUE_CTRL0_L(chan));
  378. if (err >= 0) {
  379. *val = (err & 0xffff);
  380. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
  381. ESR_GLUE_CTRL0_H(chan));
  382. if (err >= 0) {
  383. *val |= ((err & 0xffff) << 16);
  384. err = 0;
  385. }
  386. }
  387. return err;
  388. }
  389. static int esr_read_reset(struct niu *np, u32 *val)
  390. {
  391. int err;
  392. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
  393. ESR_RXTX_RESET_CTRL_L);
  394. if (err >= 0) {
  395. *val = (err & 0xffff);
  396. err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
  397. ESR_RXTX_RESET_CTRL_H);
  398. if (err >= 0) {
  399. *val |= ((err & 0xffff) << 16);
  400. err = 0;
  401. }
  402. }
  403. return err;
  404. }
  405. static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
  406. {
  407. int err;
  408. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  409. ESR_RXTX_CTRL_L(chan), val & 0xffff);
  410. if (!err)
  411. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  412. ESR_RXTX_CTRL_H(chan), (val >> 16));
  413. return err;
  414. }
  415. static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
  416. {
  417. int err;
  418. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  419. ESR_GLUE_CTRL0_L(chan), val & 0xffff);
  420. if (!err)
  421. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  422. ESR_GLUE_CTRL0_H(chan), (val >> 16));
  423. return err;
  424. }
  425. static int esr_reset(struct niu *np)
  426. {
  427. u32 reset;
  428. int err;
  429. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  430. ESR_RXTX_RESET_CTRL_L, 0x0000);
  431. if (err)
  432. return err;
  433. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  434. ESR_RXTX_RESET_CTRL_H, 0xffff);
  435. if (err)
  436. return err;
  437. udelay(200);
  438. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  439. ESR_RXTX_RESET_CTRL_L, 0xffff);
  440. if (err)
  441. return err;
  442. udelay(200);
  443. err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
  444. ESR_RXTX_RESET_CTRL_H, 0x0000);
  445. if (err)
  446. return err;
  447. udelay(200);
  448. err = esr_read_reset(np, &reset);
  449. if (err)
  450. return err;
  451. if (reset != 0) {
  452. dev_err(np->device, PFX "Port %u ESR_RESET "
  453. "did not clear [%08x]\n",
  454. np->port, reset);
  455. return -ENODEV;
  456. }
  457. return 0;
  458. }
  459. static int serdes_init_10g(struct niu *np)
  460. {
  461. struct niu_link_config *lp = &np->link_config;
  462. unsigned long ctrl_reg, test_cfg_reg, i;
  463. u64 ctrl_val, test_cfg_val, sig, mask, val;
  464. int err;
  465. switch (np->port) {
  466. case 0:
  467. ctrl_reg = ENET_SERDES_0_CTRL_CFG;
  468. test_cfg_reg = ENET_SERDES_0_TEST_CFG;
  469. break;
  470. case 1:
  471. ctrl_reg = ENET_SERDES_1_CTRL_CFG;
  472. test_cfg_reg = ENET_SERDES_1_TEST_CFG;
  473. break;
  474. default:
  475. return -EINVAL;
  476. }
  477. ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
  478. ENET_SERDES_CTRL_SDET_1 |
  479. ENET_SERDES_CTRL_SDET_2 |
  480. ENET_SERDES_CTRL_SDET_3 |
  481. (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
  482. (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
  483. (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
  484. (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
  485. (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
  486. (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
  487. (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
  488. (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
  489. test_cfg_val = 0;
  490. if (lp->loopback_mode == LOOPBACK_PHY) {
  491. test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
  492. ENET_SERDES_TEST_MD_0_SHIFT) |
  493. (ENET_TEST_MD_PAD_LOOPBACK <<
  494. ENET_SERDES_TEST_MD_1_SHIFT) |
  495. (ENET_TEST_MD_PAD_LOOPBACK <<
  496. ENET_SERDES_TEST_MD_2_SHIFT) |
  497. (ENET_TEST_MD_PAD_LOOPBACK <<
  498. ENET_SERDES_TEST_MD_3_SHIFT));
  499. }
  500. nw64(ctrl_reg, ctrl_val);
  501. nw64(test_cfg_reg, test_cfg_val);
  502. /* Initialize all 4 lanes of the SERDES. */
  503. for (i = 0; i < 4; i++) {
  504. u32 rxtx_ctrl, glue0;
  505. err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
  506. if (err)
  507. return err;
  508. err = esr_read_glue0(np, i, &glue0);
  509. if (err)
  510. return err;
  511. rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
  512. rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
  513. (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
  514. glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
  515. ESR_GLUE_CTRL0_THCNT |
  516. ESR_GLUE_CTRL0_BLTIME);
  517. glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
  518. (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
  519. (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
  520. (BLTIME_300_CYCLES <<
  521. ESR_GLUE_CTRL0_BLTIME_SHIFT));
  522. err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
  523. if (err)
  524. return err;
  525. err = esr_write_glue0(np, i, glue0);
  526. if (err)
  527. return err;
  528. }
  529. err = esr_reset(np);
  530. if (err)
  531. return err;
  532. sig = nr64(ESR_INT_SIGNALS);
  533. switch (np->port) {
  534. case 0:
  535. mask = ESR_INT_SIGNALS_P0_BITS;
  536. val = (ESR_INT_SRDY0_P0 |
  537. ESR_INT_DET0_P0 |
  538. ESR_INT_XSRDY_P0 |
  539. ESR_INT_XDP_P0_CH3 |
  540. ESR_INT_XDP_P0_CH2 |
  541. ESR_INT_XDP_P0_CH1 |
  542. ESR_INT_XDP_P0_CH0);
  543. break;
  544. case 1:
  545. mask = ESR_INT_SIGNALS_P1_BITS;
  546. val = (ESR_INT_SRDY0_P1 |
  547. ESR_INT_DET0_P1 |
  548. ESR_INT_XSRDY_P1 |
  549. ESR_INT_XDP_P1_CH3 |
  550. ESR_INT_XDP_P1_CH2 |
  551. ESR_INT_XDP_P1_CH1 |
  552. ESR_INT_XDP_P1_CH0);
  553. break;
  554. default:
  555. return -EINVAL;
  556. }
  557. if ((sig & mask) != val) {
  558. if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
  559. np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
  560. return 0;
  561. }
  562. dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
  563. "[%08x]\n", np->port, (int) (sig & mask), (int) val);
  564. return -ENODEV;
  565. }
  566. if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
  567. np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
  568. return 0;
  569. }
  570. static int serdes_init_1g(struct niu *np)
  571. {
  572. u64 val;
  573. val = nr64(ENET_SERDES_1_PLL_CFG);
  574. val &= ~ENET_SERDES_PLL_FBDIV2;
  575. switch (np->port) {
  576. case 0:
  577. val |= ENET_SERDES_PLL_HRATE0;
  578. break;
  579. case 1:
  580. val |= ENET_SERDES_PLL_HRATE1;
  581. break;
  582. case 2:
  583. val |= ENET_SERDES_PLL_HRATE2;
  584. break;
  585. case 3:
  586. val |= ENET_SERDES_PLL_HRATE3;
  587. break;
  588. default:
  589. return -EINVAL;
  590. }
  591. nw64(ENET_SERDES_1_PLL_CFG, val);
  592. return 0;
  593. }
  594. static int serdes_init_1g_serdes(struct niu *np)
  595. {
  596. struct niu_link_config *lp = &np->link_config;
  597. unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
  598. u64 ctrl_val, test_cfg_val, sig, mask, val;
  599. int err;
  600. u64 reset_val, val_rd;
  601. val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
  602. ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
  603. ENET_SERDES_PLL_FBDIV0;
  604. switch (np->port) {
  605. case 0:
  606. reset_val = ENET_SERDES_RESET_0;
  607. ctrl_reg = ENET_SERDES_0_CTRL_CFG;
  608. test_cfg_reg = ENET_SERDES_0_TEST_CFG;
  609. pll_cfg = ENET_SERDES_0_PLL_CFG;
  610. break;
  611. case 1:
  612. reset_val = ENET_SERDES_RESET_1;
  613. ctrl_reg = ENET_SERDES_1_CTRL_CFG;
  614. test_cfg_reg = ENET_SERDES_1_TEST_CFG;
  615. pll_cfg = ENET_SERDES_1_PLL_CFG;
  616. break;
  617. default:
  618. return -EINVAL;
  619. }
  620. ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
  621. ENET_SERDES_CTRL_SDET_1 |
  622. ENET_SERDES_CTRL_SDET_2 |
  623. ENET_SERDES_CTRL_SDET_3 |
  624. (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
  625. (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
  626. (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
  627. (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
  628. (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
  629. (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
  630. (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
  631. (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
  632. test_cfg_val = 0;
  633. if (lp->loopback_mode == LOOPBACK_PHY) {
  634. test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
  635. ENET_SERDES_TEST_MD_0_SHIFT) |
  636. (ENET_TEST_MD_PAD_LOOPBACK <<
  637. ENET_SERDES_TEST_MD_1_SHIFT) |
  638. (ENET_TEST_MD_PAD_LOOPBACK <<
  639. ENET_SERDES_TEST_MD_2_SHIFT) |
  640. (ENET_TEST_MD_PAD_LOOPBACK <<
  641. ENET_SERDES_TEST_MD_3_SHIFT));
  642. }
  643. nw64(ENET_SERDES_RESET, reset_val);
  644. mdelay(20);
  645. val_rd = nr64(ENET_SERDES_RESET);
  646. val_rd &= ~reset_val;
  647. nw64(pll_cfg, val);
  648. nw64(ctrl_reg, ctrl_val);
  649. nw64(test_cfg_reg, test_cfg_val);
  650. nw64(ENET_SERDES_RESET, val_rd);
  651. mdelay(2000);
  652. /* Initialize all 4 lanes of the SERDES. */
  653. for (i = 0; i < 4; i++) {
  654. u32 rxtx_ctrl, glue0;
  655. err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
  656. if (err)
  657. return err;
  658. err = esr_read_glue0(np, i, &glue0);
  659. if (err)
  660. return err;
  661. rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
  662. rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
  663. (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
  664. glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
  665. ESR_GLUE_CTRL0_THCNT |
  666. ESR_GLUE_CTRL0_BLTIME);
  667. glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
  668. (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
  669. (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
  670. (BLTIME_300_CYCLES <<
  671. ESR_GLUE_CTRL0_BLTIME_SHIFT));
  672. err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
  673. if (err)
  674. return err;
  675. err = esr_write_glue0(np, i, glue0);
  676. if (err)
  677. return err;
  678. }
  679. sig = nr64(ESR_INT_SIGNALS);
  680. switch (np->port) {
  681. case 0:
  682. val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
  683. mask = val;
  684. break;
  685. case 1:
  686. val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
  687. mask = val;
  688. break;
  689. default:
  690. return -EINVAL;
  691. }
  692. if ((sig & mask) != val) {
  693. dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
  694. "[%08x]\n", np->port, (int) (sig & mask), (int) val);
  695. return -ENODEV;
  696. }
  697. return 0;
  698. }
  699. static int link_status_1g_serdes(struct niu *np, int *link_up_p)
  700. {
  701. struct niu_link_config *lp = &np->link_config;
  702. int link_up;
  703. u64 val;
  704. u16 current_speed;
  705. unsigned long flags;
  706. u8 current_duplex;
  707. link_up = 0;
  708. current_speed = SPEED_INVALID;
  709. current_duplex = DUPLEX_INVALID;
  710. spin_lock_irqsave(&np->lock, flags);
  711. val = nr64_pcs(PCS_MII_STAT);
  712. if (val & PCS_MII_STAT_LINK_STATUS) {
  713. link_up = 1;
  714. current_speed = SPEED_1000;
  715. current_duplex = DUPLEX_FULL;
  716. }
  717. lp->active_speed = current_speed;
  718. lp->active_duplex = current_duplex;
  719. spin_unlock_irqrestore(&np->lock, flags);
  720. *link_up_p = link_up;
  721. return 0;
  722. }
  723. static int link_status_10g_serdes(struct niu *np, int *link_up_p)
  724. {
  725. unsigned long flags;
  726. struct niu_link_config *lp = &np->link_config;
  727. int link_up = 0;
  728. int link_ok = 1;
  729. u64 val, val2;
  730. u16 current_speed;
  731. u8 current_duplex;
  732. if (!(np->flags & NIU_FLAGS_10G))
  733. return link_status_1g_serdes(np, link_up_p);
  734. current_speed = SPEED_INVALID;
  735. current_duplex = DUPLEX_INVALID;
  736. spin_lock_irqsave(&np->lock, flags);
  737. val = nr64_xpcs(XPCS_STATUS(0));
  738. val2 = nr64_mac(XMAC_INTER2);
  739. if (val2 & 0x01000000)
  740. link_ok = 0;
  741. if ((val & 0x1000ULL) && link_ok) {
  742. link_up = 1;
  743. current_speed = SPEED_10000;
  744. current_duplex = DUPLEX_FULL;
  745. }
  746. lp->active_speed = current_speed;
  747. lp->active_duplex = current_duplex;
  748. spin_unlock_irqrestore(&np->lock, flags);
  749. *link_up_p = link_up;
  750. return 0;
  751. }
  752. static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
  753. {
  754. struct niu_link_config *lp = &np->link_config;
  755. u16 current_speed, bmsr;
  756. unsigned long flags;
  757. u8 current_duplex;
  758. int err, link_up;
  759. link_up = 0;
  760. current_speed = SPEED_INVALID;
  761. current_duplex = DUPLEX_INVALID;
  762. spin_lock_irqsave(&np->lock, flags);
  763. err = -EINVAL;
  764. err = mii_read(np, np->phy_addr, MII_BMSR);
  765. if (err < 0)
  766. goto out;
  767. bmsr = err;
  768. if (bmsr & BMSR_LSTATUS) {
  769. u16 adv, lpa, common, estat;
  770. err = mii_read(np, np->phy_addr, MII_ADVERTISE);
  771. if (err < 0)
  772. goto out;
  773. adv = err;
  774. err = mii_read(np, np->phy_addr, MII_LPA);
  775. if (err < 0)
  776. goto out;
  777. lpa = err;
  778. common = adv & lpa;
  779. err = mii_read(np, np->phy_addr, MII_ESTATUS);
  780. if (err < 0)
  781. goto out;
  782. estat = err;
  783. link_up = 1;
  784. current_speed = SPEED_1000;
  785. current_duplex = DUPLEX_FULL;
  786. }
  787. lp->active_speed = current_speed;
  788. lp->active_duplex = current_duplex;
  789. err = 0;
  790. out:
  791. spin_unlock_irqrestore(&np->lock, flags);
  792. *link_up_p = link_up;
  793. return err;
  794. }
  795. static int bcm8704_reset(struct niu *np)
  796. {
  797. int err, limit;
  798. err = mdio_read(np, np->phy_addr,
  799. BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
  800. if (err < 0)
  801. return err;
  802. err |= BMCR_RESET;
  803. err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
  804. MII_BMCR, err);
  805. if (err)
  806. return err;
  807. limit = 1000;
  808. while (--limit >= 0) {
  809. err = mdio_read(np, np->phy_addr,
  810. BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
  811. if (err < 0)
  812. return err;
  813. if (!(err & BMCR_RESET))
  814. break;
  815. }
  816. if (limit < 0) {
  817. dev_err(np->device, PFX "Port %u PHY will not reset "
  818. "(bmcr=%04x)\n", np->port, (err & 0xffff));
  819. return -ENODEV;
  820. }
  821. return 0;
  822. }
  823. /* When written, certain PHY registers need to be read back twice
  824. * in order for the bits to settle properly.
  825. */
  826. static int bcm8704_user_dev3_readback(struct niu *np, int reg)
  827. {
  828. int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
  829. if (err < 0)
  830. return err;
  831. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
  832. if (err < 0)
  833. return err;
  834. return 0;
  835. }
  836. static int bcm8706_init_user_dev3(struct niu *np)
  837. {
  838. int err;
  839. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  840. BCM8704_USER_OPT_DIGITAL_CTRL);
  841. if (err < 0)
  842. return err;
  843. err &= ~USER_ODIG_CTRL_GPIOS;
  844. err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
  845. err |= USER_ODIG_CTRL_RESV2;
  846. err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  847. BCM8704_USER_OPT_DIGITAL_CTRL, err);
  848. if (err)
  849. return err;
  850. mdelay(1000);
  851. return 0;
  852. }
  853. static int bcm8704_init_user_dev3(struct niu *np)
  854. {
  855. int err;
  856. err = mdio_write(np, np->phy_addr,
  857. BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
  858. (USER_CONTROL_OPTXRST_LVL |
  859. USER_CONTROL_OPBIASFLT_LVL |
  860. USER_CONTROL_OBTMPFLT_LVL |
  861. USER_CONTROL_OPPRFLT_LVL |
  862. USER_CONTROL_OPTXFLT_LVL |
  863. USER_CONTROL_OPRXLOS_LVL |
  864. USER_CONTROL_OPRXFLT_LVL |
  865. USER_CONTROL_OPTXON_LVL |
  866. (0x3f << USER_CONTROL_RES1_SHIFT)));
  867. if (err)
  868. return err;
  869. err = mdio_write(np, np->phy_addr,
  870. BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
  871. (USER_PMD_TX_CTL_XFP_CLKEN |
  872. (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
  873. (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
  874. USER_PMD_TX_CTL_TSCK_LPWREN));
  875. if (err)
  876. return err;
  877. err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
  878. if (err)
  879. return err;
  880. err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
  881. if (err)
  882. return err;
  883. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  884. BCM8704_USER_OPT_DIGITAL_CTRL);
  885. if (err < 0)
  886. return err;
  887. err &= ~USER_ODIG_CTRL_GPIOS;
  888. err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
  889. err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  890. BCM8704_USER_OPT_DIGITAL_CTRL, err);
  891. if (err)
  892. return err;
  893. mdelay(1000);
  894. return 0;
  895. }
  896. static int mrvl88x2011_act_led(struct niu *np, int val)
  897. {
  898. int err;
  899. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
  900. MRVL88X2011_LED_8_TO_11_CTL);
  901. if (err < 0)
  902. return err;
  903. err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
  904. err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
  905. return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
  906. MRVL88X2011_LED_8_TO_11_CTL, err);
  907. }
  908. static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
  909. {
  910. int err;
  911. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
  912. MRVL88X2011_LED_BLINK_CTL);
  913. if (err >= 0) {
  914. err &= ~MRVL88X2011_LED_BLKRATE_MASK;
  915. err |= (rate << 4);
  916. err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
  917. MRVL88X2011_LED_BLINK_CTL, err);
  918. }
  919. return err;
  920. }
  921. static int xcvr_init_10g_mrvl88x2011(struct niu *np)
  922. {
  923. int err;
  924. /* Set LED functions */
  925. err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
  926. if (err)
  927. return err;
  928. /* led activity */
  929. err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
  930. if (err)
  931. return err;
  932. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
  933. MRVL88X2011_GENERAL_CTL);
  934. if (err < 0)
  935. return err;
  936. err |= MRVL88X2011_ENA_XFPREFCLK;
  937. err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
  938. MRVL88X2011_GENERAL_CTL, err);
  939. if (err < 0)
  940. return err;
  941. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
  942. MRVL88X2011_PMA_PMD_CTL_1);
  943. if (err < 0)
  944. return err;
  945. if (np->link_config.loopback_mode == LOOPBACK_MAC)
  946. err |= MRVL88X2011_LOOPBACK;
  947. else
  948. err &= ~MRVL88X2011_LOOPBACK;
  949. err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
  950. MRVL88X2011_PMA_PMD_CTL_1, err);
  951. if (err < 0)
  952. return err;
  953. /* Enable PMD */
  954. return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
  955. MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
  956. }
  957. static int xcvr_diag_bcm870x(struct niu *np)
  958. {
  959. u16 analog_stat0, tx_alarm_status;
  960. int err = 0;
  961. #if 1
  962. err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
  963. MII_STAT1000);
  964. if (err < 0)
  965. return err;
  966. pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
  967. np->port, err);
  968. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
  969. if (err < 0)
  970. return err;
  971. pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
  972. np->port, err);
  973. err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
  974. MII_NWAYTEST);
  975. if (err < 0)
  976. return err;
  977. pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
  978. np->port, err);
  979. #endif
  980. /* XXX dig this out it might not be so useful XXX */
  981. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  982. BCM8704_USER_ANALOG_STATUS0);
  983. if (err < 0)
  984. return err;
  985. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  986. BCM8704_USER_ANALOG_STATUS0);
  987. if (err < 0)
  988. return err;
  989. analog_stat0 = err;
  990. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  991. BCM8704_USER_TX_ALARM_STATUS);
  992. if (err < 0)
  993. return err;
  994. err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
  995. BCM8704_USER_TX_ALARM_STATUS);
  996. if (err < 0)
  997. return err;
  998. tx_alarm_status = err;
  999. if (analog_stat0 != 0x03fc) {
  1000. if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
  1001. pr_info(PFX "Port %u cable not connected "
  1002. "or bad cable.\n", np->port);
  1003. } else if (analog_stat0 == 0x639c) {
  1004. pr_info(PFX "Port %u optical module is bad "
  1005. "or missing.\n", np->port);
  1006. }
  1007. }
  1008. return 0;
  1009. }
  1010. static int xcvr_10g_set_lb_bcm870x(struct niu *np)
  1011. {
  1012. struct niu_link_config *lp = &np->link_config;
  1013. int err;
  1014. err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
  1015. MII_BMCR);
  1016. if (err < 0)
  1017. return err;
  1018. err &= ~BMCR_LOOPBACK;
  1019. if (lp->loopback_mode == LOOPBACK_MAC)
  1020. err |= BMCR_LOOPBACK;
  1021. err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
  1022. MII_BMCR, err);
  1023. if (err)
  1024. return err;
  1025. return 0;
  1026. }
  1027. static int xcvr_init_10g_bcm8706(struct niu *np)
  1028. {
  1029. int err = 0;
  1030. u64 val;
  1031. if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
  1032. (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
  1033. return err;
  1034. val = nr64_mac(XMAC_CONFIG);
  1035. val &= ~XMAC_CONFIG_LED_POLARITY;
  1036. val |= XMAC_CONFIG_FORCE_LED_ON;
  1037. nw64_mac(XMAC_CONFIG, val);
  1038. val = nr64(MIF_CONFIG);
  1039. val |= MIF_CONFIG_INDIRECT_MODE;
  1040. nw64(MIF_CONFIG, val);
  1041. err = bcm8704_reset(np);
  1042. if (err)
  1043. return err;
  1044. err = xcvr_10g_set_lb_bcm870x(np);
  1045. if (err)
  1046. return err;
  1047. err = bcm8706_init_user_dev3(np);
  1048. if (err)
  1049. return err;
  1050. err = xcvr_diag_bcm870x(np);
  1051. if (err)
  1052. return err;
  1053. return 0;
  1054. }
  1055. static int xcvr_init_10g_bcm8704(struct niu *np)
  1056. {
  1057. int err;
  1058. err = bcm8704_reset(np);
  1059. if (err)
  1060. return err;
  1061. err = bcm8704_init_user_dev3(np);
  1062. if (err)
  1063. return err;
  1064. err = xcvr_10g_set_lb_bcm870x(np);
  1065. if (err)
  1066. return err;
  1067. err = xcvr_diag_bcm870x(np);
  1068. if (err)
  1069. return err;
  1070. return 0;
  1071. }
  1072. static int xcvr_init_10g(struct niu *np)
  1073. {
  1074. int phy_id, err;
  1075. u64 val;
  1076. val = nr64_mac(XMAC_CONFIG);
  1077. val &= ~XMAC_CONFIG_LED_POLARITY;
  1078. val |= XMAC_CONFIG_FORCE_LED_ON;
  1079. nw64_mac(XMAC_CONFIG, val);
  1080. /* XXX shared resource, lock parent XXX */
  1081. val = nr64(MIF_CONFIG);
  1082. val |= MIF_CONFIG_INDIRECT_MODE;
  1083. nw64(MIF_CONFIG, val);
  1084. phy_id = phy_decode(np->parent->port_phy, np->port);
  1085. phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
  1086. /* handle different phy types */
  1087. switch (phy_id & NIU_PHY_ID_MASK) {
  1088. case NIU_PHY_ID_MRVL88X2011:
  1089. err = xcvr_init_10g_mrvl88x2011(np);
  1090. break;
  1091. default: /* bcom 8704 */
  1092. err = xcvr_init_10g_bcm8704(np);
  1093. break;
  1094. }
  1095. return 0;
  1096. }
  1097. static int mii_reset(struct niu *np)
  1098. {
  1099. int limit, err;
  1100. err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
  1101. if (err)
  1102. return err;
  1103. limit = 1000;
  1104. while (--limit >= 0) {
  1105. udelay(500);
  1106. err = mii_read(np, np->phy_addr, MII_BMCR);
  1107. if (err < 0)
  1108. return err;
  1109. if (!(err & BMCR_RESET))
  1110. break;
  1111. }
  1112. if (limit < 0) {
  1113. dev_err(np->device, PFX "Port %u MII would not reset, "
  1114. "bmcr[%04x]\n", np->port, err);
  1115. return -ENODEV;
  1116. }
  1117. return 0;
  1118. }
  1119. static int xcvr_init_1g_rgmii(struct niu *np)
  1120. {
  1121. int err;
  1122. u64 val;
  1123. u16 bmcr, bmsr, estat;
  1124. val = nr64(MIF_CONFIG);
  1125. val &= ~MIF_CONFIG_INDIRECT_MODE;
  1126. nw64(MIF_CONFIG, val);
  1127. err = mii_reset(np);
  1128. if (err)
  1129. return err;
  1130. err = mii_read(np, np->phy_addr, MII_BMSR);
  1131. if (err < 0)
  1132. return err;
  1133. bmsr = err;
  1134. estat = 0;
  1135. if (bmsr & BMSR_ESTATEN) {
  1136. err = mii_read(np, np->phy_addr, MII_ESTATUS);
  1137. if (err < 0)
  1138. return err;
  1139. estat = err;
  1140. }
  1141. bmcr = 0;
  1142. err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
  1143. if (err)
  1144. return err;
  1145. if (bmsr & BMSR_ESTATEN) {
  1146. u16 ctrl1000 = 0;
  1147. if (estat & ESTATUS_1000_TFULL)
  1148. ctrl1000 |= ADVERTISE_1000FULL;
  1149. err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
  1150. if (err)
  1151. return err;
  1152. }
  1153. bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
  1154. err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
  1155. if (err)
  1156. return err;
  1157. err = mii_read(np, np->phy_addr, MII_BMCR);
  1158. if (err < 0)
  1159. return err;
  1160. bmcr = mii_read(np, np->phy_addr, MII_BMCR);
  1161. err = mii_read(np, np->phy_addr, MII_BMSR);
  1162. if (err < 0)
  1163. return err;
  1164. return 0;
  1165. }
  1166. static int mii_init_common(struct niu *np)
  1167. {
  1168. struct niu_link_config *lp = &np->link_config;
  1169. u16 bmcr, bmsr, adv, estat;
  1170. int err;
  1171. err = mii_reset(np);
  1172. if (err)
  1173. return err;
  1174. err = mii_read(np, np->phy_addr, MII_BMSR);
  1175. if (err < 0)
  1176. return err;
  1177. bmsr = err;
  1178. estat = 0;
  1179. if (bmsr & BMSR_ESTATEN) {
  1180. err = mii_read(np, np->phy_addr, MII_ESTATUS);
  1181. if (err < 0)
  1182. return err;
  1183. estat = err;
  1184. }
  1185. bmcr = 0;
  1186. err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
  1187. if (err)
  1188. return err;
  1189. if (lp->loopback_mode == LOOPBACK_MAC) {
  1190. bmcr |= BMCR_LOOPBACK;
  1191. if (lp->active_speed == SPEED_1000)
  1192. bmcr |= BMCR_SPEED1000;
  1193. if (lp->active_duplex == DUPLEX_FULL)
  1194. bmcr |= BMCR_FULLDPLX;
  1195. }
  1196. if (lp->loopback_mode == LOOPBACK_PHY) {
  1197. u16 aux;
  1198. aux = (BCM5464R_AUX_CTL_EXT_LB |
  1199. BCM5464R_AUX_CTL_WRITE_1);
  1200. err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
  1201. if (err)
  1202. return err;
  1203. }
  1204. /* XXX configurable XXX */
  1205. /* XXX for now don't advertise half-duplex or asym pause... XXX */
  1206. adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
  1207. if (bmsr & BMSR_10FULL)
  1208. adv |= ADVERTISE_10FULL;
  1209. if (bmsr & BMSR_100FULL)
  1210. adv |= ADVERTISE_100FULL;
  1211. err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
  1212. if (err)
  1213. return err;
  1214. if (bmsr & BMSR_ESTATEN) {
  1215. u16 ctrl1000 = 0;
  1216. if (estat & ESTATUS_1000_TFULL)
  1217. ctrl1000 |= ADVERTISE_1000FULL;
  1218. err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
  1219. if (err)
  1220. return err;
  1221. }
  1222. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  1223. err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
  1224. if (err)
  1225. return err;
  1226. err = mii_read(np, np->phy_addr, MII_BMCR);
  1227. if (err < 0)
  1228. return err;
  1229. err = mii_read(np, np->phy_addr, MII_BMSR);
  1230. if (err < 0)
  1231. return err;
  1232. #if 0
  1233. pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
  1234. np->port, bmcr, bmsr);
  1235. #endif
  1236. return 0;
  1237. }
  1238. static int xcvr_init_1g(struct niu *np)
  1239. {
  1240. u64 val;
  1241. /* XXX shared resource, lock parent XXX */
  1242. val = nr64(MIF_CONFIG);
  1243. val &= ~MIF_CONFIG_INDIRECT_MODE;
  1244. nw64(MIF_CONFIG, val);
  1245. return mii_init_common(np);
  1246. }
  1247. static int niu_xcvr_init(struct niu *np)
  1248. {
  1249. const struct niu_phy_ops *ops = np->phy_ops;
  1250. int err;
  1251. err = 0;
  1252. if (ops->xcvr_init)
  1253. err = ops->xcvr_init(np);
  1254. return err;
  1255. }
  1256. static int niu_serdes_init(struct niu *np)
  1257. {
  1258. const struct niu_phy_ops *ops = np->phy_ops;
  1259. int err;
  1260. err = 0;
  1261. if (ops->serdes_init)
  1262. err = ops->serdes_init(np);
  1263. return err;
  1264. }
  1265. static void niu_init_xif(struct niu *);
  1266. static void niu_handle_led(struct niu *, int status);
  1267. static int niu_link_status_common(struct niu *np, int link_up)
  1268. {
  1269. struct niu_link_config *lp = &np->link_config;
  1270. struct net_device *dev = np->dev;
  1271. unsigned long flags;
  1272. if (!netif_carrier_ok(dev) && link_up) {
  1273. niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
  1274. dev->name,
  1275. (lp->active_speed == SPEED_10000 ?
  1276. "10Gb/sec" :
  1277. (lp->active_speed == SPEED_1000 ?
  1278. "1Gb/sec" :
  1279. (lp->active_speed == SPEED_100 ?
  1280. "100Mbit/sec" : "10Mbit/sec"))),
  1281. (lp->active_duplex == DUPLEX_FULL ?
  1282. "full" : "half"));
  1283. spin_lock_irqsave(&np->lock, flags);
  1284. niu_init_xif(np);
  1285. niu_handle_led(np, 1);
  1286. spin_unlock_irqrestore(&np->lock, flags);
  1287. netif_carrier_on(dev);
  1288. } else if (netif_carrier_ok(dev) && !link_up) {
  1289. niuwarn(LINK, "%s: Link is down\n", dev->name);
  1290. spin_lock_irqsave(&np->lock, flags);
  1291. niu_handle_led(np, 0);
  1292. spin_unlock_irqrestore(&np->lock, flags);
  1293. netif_carrier_off(dev);
  1294. }
  1295. return 0;
  1296. }
  1297. static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
  1298. {
  1299. int err, link_up, pma_status, pcs_status;
  1300. link_up = 0;
  1301. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
  1302. MRVL88X2011_10G_PMD_STATUS_2);
  1303. if (err < 0)
  1304. goto out;
  1305. /* Check PMA/PMD Register: 1.0001.2 == 1 */
  1306. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
  1307. MRVL88X2011_PMA_PMD_STATUS_1);
  1308. if (err < 0)
  1309. goto out;
  1310. pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
  1311. /* Check PMC Register : 3.0001.2 == 1: read twice */
  1312. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
  1313. MRVL88X2011_PMA_PMD_STATUS_1);
  1314. if (err < 0)
  1315. goto out;
  1316. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
  1317. MRVL88X2011_PMA_PMD_STATUS_1);
  1318. if (err < 0)
  1319. goto out;
  1320. pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
  1321. /* Check XGXS Register : 4.0018.[0-3,12] */
  1322. err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
  1323. MRVL88X2011_10G_XGXS_LANE_STAT);
  1324. if (err < 0)
  1325. goto out;
  1326. if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
  1327. PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
  1328. PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
  1329. 0x800))
  1330. link_up = (pma_status && pcs_status) ? 1 : 0;
  1331. np->link_config.active_speed = SPEED_10000;
  1332. np->link_config.active_duplex = DUPLEX_FULL;
  1333. err = 0;
  1334. out:
  1335. mrvl88x2011_act_led(np, (link_up ?
  1336. MRVL88X2011_LED_CTL_PCS_ACT :
  1337. MRVL88X2011_LED_CTL_OFF));
  1338. *link_up_p = link_up;
  1339. return err;
  1340. }
  1341. static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
  1342. {
  1343. int err, link_up;
  1344. link_up = 0;
  1345. err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
  1346. BCM8704_PMD_RCV_SIGDET);
  1347. if (err < 0)
  1348. goto out;
  1349. if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
  1350. err = 0;
  1351. goto out;
  1352. }
  1353. err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
  1354. BCM8704_PCS_10G_R_STATUS);
  1355. if (err < 0)
  1356. goto out;
  1357. if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
  1358. err = 0;
  1359. goto out;
  1360. }
  1361. err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
  1362. BCM8704_PHYXS_XGXS_LANE_STAT);
  1363. if (err < 0)
  1364. goto out;
  1365. if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
  1366. PHYXS_XGXS_LANE_STAT_MAGIC |
  1367. PHYXS_XGXS_LANE_STAT_PATTEST |
  1368. PHYXS_XGXS_LANE_STAT_LANE3 |
  1369. PHYXS_XGXS_LANE_STAT_LANE2 |
  1370. PHYXS_XGXS_LANE_STAT_LANE1 |
  1371. PHYXS_XGXS_LANE_STAT_LANE0)) {
  1372. err = 0;
  1373. np->link_config.active_speed = SPEED_INVALID;
  1374. np->link_config.active_duplex = DUPLEX_INVALID;
  1375. goto out;
  1376. }
  1377. link_up = 1;
  1378. np->link_config.active_speed = SPEED_10000;
  1379. np->link_config.active_duplex = DUPLEX_FULL;
  1380. err = 0;
  1381. out:
  1382. *link_up_p = link_up;
  1383. if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
  1384. err = 0;
  1385. return err;
  1386. }
  1387. static int link_status_10g_bcom(struct niu *np, int *link_up_p)
  1388. {
  1389. int err, link_up;
  1390. link_up = 0;
  1391. err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
  1392. BCM8704_PMD_RCV_SIGDET);
  1393. if (err < 0)
  1394. goto out;
  1395. if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
  1396. err = 0;
  1397. goto out;
  1398. }
  1399. err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
  1400. BCM8704_PCS_10G_R_STATUS);
  1401. if (err < 0)
  1402. goto out;
  1403. if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
  1404. err = 0;
  1405. goto out;
  1406. }
  1407. err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
  1408. BCM8704_PHYXS_XGXS_LANE_STAT);
  1409. if (err < 0)
  1410. goto out;
  1411. if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
  1412. PHYXS_XGXS_LANE_STAT_MAGIC |
  1413. PHYXS_XGXS_LANE_STAT_LANE3 |
  1414. PHYXS_XGXS_LANE_STAT_LANE2 |
  1415. PHYXS_XGXS_LANE_STAT_LANE1 |
  1416. PHYXS_XGXS_LANE_STAT_LANE0)) {
  1417. err = 0;
  1418. goto out;
  1419. }
  1420. link_up = 1;
  1421. np->link_config.active_speed = SPEED_10000;
  1422. np->link_config.active_duplex = DUPLEX_FULL;
  1423. err = 0;
  1424. out:
  1425. *link_up_p = link_up;
  1426. return err;
  1427. }
  1428. static int link_status_10g(struct niu *np, int *link_up_p)
  1429. {
  1430. unsigned long flags;
  1431. int err = -EINVAL;
  1432. spin_lock_irqsave(&np->lock, flags);
  1433. if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
  1434. int phy_id;
  1435. phy_id = phy_decode(np->parent->port_phy, np->port);
  1436. phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
  1437. /* handle different phy types */
  1438. switch (phy_id & NIU_PHY_ID_MASK) {
  1439. case NIU_PHY_ID_MRVL88X2011:
  1440. err = link_status_10g_mrvl(np, link_up_p);
  1441. break;
  1442. default: /* bcom 8704 */
  1443. err = link_status_10g_bcom(np, link_up_p);
  1444. break;
  1445. }
  1446. }
  1447. spin_unlock_irqrestore(&np->lock, flags);
  1448. return err;
  1449. }
  1450. static int niu_10g_phy_present(struct niu *np)
  1451. {
  1452. u64 sig, mask, val;
  1453. sig = nr64(ESR_INT_SIGNALS);
  1454. switch (np->port) {
  1455. case 0:
  1456. mask = ESR_INT_SIGNALS_P0_BITS;
  1457. val = (ESR_INT_SRDY0_P0 |
  1458. ESR_INT_DET0_P0 |
  1459. ESR_INT_XSRDY_P0 |
  1460. ESR_INT_XDP_P0_CH3 |
  1461. ESR_INT_XDP_P0_CH2 |
  1462. ESR_INT_XDP_P0_CH1 |
  1463. ESR_INT_XDP_P0_CH0);
  1464. break;
  1465. case 1:
  1466. mask = ESR_INT_SIGNALS_P1_BITS;
  1467. val = (ESR_INT_SRDY0_P1 |
  1468. ESR_INT_DET0_P1 |
  1469. ESR_INT_XSRDY_P1 |
  1470. ESR_INT_XDP_P1_CH3 |
  1471. ESR_INT_XDP_P1_CH2 |
  1472. ESR_INT_XDP_P1_CH1 |
  1473. ESR_INT_XDP_P1_CH0);
  1474. break;
  1475. default:
  1476. return 0;
  1477. }
  1478. if ((sig & mask) != val)
  1479. return 0;
  1480. return 1;
  1481. }
  1482. static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
  1483. {
  1484. unsigned long flags;
  1485. int err = 0;
  1486. int phy_present;
  1487. int phy_present_prev;
  1488. spin_lock_irqsave(&np->lock, flags);
  1489. if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
  1490. phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
  1491. 1 : 0;
  1492. phy_present = niu_10g_phy_present(np);
  1493. if (phy_present != phy_present_prev) {
  1494. /* state change */
  1495. if (phy_present) {
  1496. np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
  1497. if (np->phy_ops->xcvr_init)
  1498. err = np->phy_ops->xcvr_init(np);
  1499. if (err) {
  1500. /* debounce */
  1501. np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
  1502. }
  1503. } else {
  1504. np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
  1505. *link_up_p = 0;
  1506. niuwarn(LINK, "%s: Hotplug PHY Removed\n",
  1507. np->dev->name);
  1508. }
  1509. }
  1510. if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT)
  1511. err = link_status_10g_bcm8706(np, link_up_p);
  1512. }
  1513. spin_unlock_irqrestore(&np->lock, flags);
  1514. return err;
  1515. }
  1516. static int link_status_1g(struct niu *np, int *link_up_p)
  1517. {
  1518. struct niu_link_config *lp = &np->link_config;
  1519. u16 current_speed, bmsr;
  1520. unsigned long flags;
  1521. u8 current_duplex;
  1522. int err, link_up;
  1523. link_up = 0;
  1524. current_speed = SPEED_INVALID;
  1525. current_duplex = DUPLEX_INVALID;
  1526. spin_lock_irqsave(&np->lock, flags);
  1527. err = -EINVAL;
  1528. if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
  1529. goto out;
  1530. err = mii_read(np, np->phy_addr, MII_BMSR);
  1531. if (err < 0)
  1532. goto out;
  1533. bmsr = err;
  1534. if (bmsr & BMSR_LSTATUS) {
  1535. u16 adv, lpa, common, estat;
  1536. err = mii_read(np, np->phy_addr, MII_ADVERTISE);
  1537. if (err < 0)
  1538. goto out;
  1539. adv = err;
  1540. err = mii_read(np, np->phy_addr, MII_LPA);
  1541. if (err < 0)
  1542. goto out;
  1543. lpa = err;
  1544. common = adv & lpa;
  1545. err = mii_read(np, np->phy_addr, MII_ESTATUS);
  1546. if (err < 0)
  1547. goto out;
  1548. estat = err;
  1549. link_up = 1;
  1550. if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
  1551. current_speed = SPEED_1000;
  1552. if (estat & ESTATUS_1000_TFULL)
  1553. current_duplex = DUPLEX_FULL;
  1554. else
  1555. current_duplex = DUPLEX_HALF;
  1556. } else {
  1557. if (common & ADVERTISE_100BASE4) {
  1558. current_speed = SPEED_100;
  1559. current_duplex = DUPLEX_HALF;
  1560. } else if (common & ADVERTISE_100FULL) {
  1561. current_speed = SPEED_100;
  1562. current_duplex = DUPLEX_FULL;
  1563. } else if (common & ADVERTISE_100HALF) {
  1564. current_speed = SPEED_100;
  1565. current_duplex = DUPLEX_HALF;
  1566. } else if (common & ADVERTISE_10FULL) {
  1567. current_speed = SPEED_10;
  1568. current_duplex = DUPLEX_FULL;
  1569. } else if (common & ADVERTISE_10HALF) {
  1570. current_speed = SPEED_10;
  1571. current_duplex = DUPLEX_HALF;
  1572. } else
  1573. link_up = 0;
  1574. }
  1575. }
  1576. lp->active_speed = current_speed;
  1577. lp->active_duplex = current_duplex;
  1578. err = 0;
  1579. out:
  1580. spin_unlock_irqrestore(&np->lock, flags);
  1581. *link_up_p = link_up;
  1582. return err;
  1583. }
  1584. static int niu_link_status(struct niu *np, int *link_up_p)
  1585. {
  1586. const struct niu_phy_ops *ops = np->phy_ops;
  1587. int err;
  1588. err = 0;
  1589. if (ops->link_status)
  1590. err = ops->link_status(np, link_up_p);
  1591. return err;
  1592. }
  1593. static void niu_timer(unsigned long __opaque)
  1594. {
  1595. struct niu *np = (struct niu *) __opaque;
  1596. unsigned long off;
  1597. int err, link_up;
  1598. err = niu_link_status(np, &link_up);
  1599. if (!err)
  1600. niu_link_status_common(np, link_up);
  1601. if (netif_carrier_ok(np->dev))
  1602. off = 5 * HZ;
  1603. else
  1604. off = 1 * HZ;
  1605. np->timer.expires = jiffies + off;
  1606. add_timer(&np->timer);
  1607. }
  1608. static const struct niu_phy_ops phy_ops_10g_serdes = {
  1609. .serdes_init = serdes_init_10g_serdes,
  1610. .link_status = link_status_10g_serdes,
  1611. };
  1612. static const struct niu_phy_ops phy_ops_1g_rgmii = {
  1613. .xcvr_init = xcvr_init_1g_rgmii,
  1614. .link_status = link_status_1g_rgmii,
  1615. };
  1616. static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
  1617. .serdes_init = serdes_init_niu,
  1618. .xcvr_init = xcvr_init_10g,
  1619. .link_status = link_status_10g,
  1620. };
  1621. static const struct niu_phy_ops phy_ops_10g_fiber = {
  1622. .serdes_init = serdes_init_10g,
  1623. .xcvr_init = xcvr_init_10g,
  1624. .link_status = link_status_10g,
  1625. };
  1626. static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
  1627. .serdes_init = serdes_init_10g,
  1628. .xcvr_init = xcvr_init_10g_bcm8706,
  1629. .link_status = link_status_10g_hotplug,
  1630. };
  1631. static const struct niu_phy_ops phy_ops_10g_copper = {
  1632. .serdes_init = serdes_init_10g,
  1633. .link_status = link_status_10g, /* XXX */
  1634. };
  1635. static const struct niu_phy_ops phy_ops_1g_fiber = {
  1636. .serdes_init = serdes_init_1g,
  1637. .xcvr_init = xcvr_init_1g,
  1638. .link_status = link_status_1g,
  1639. };
  1640. static const struct niu_phy_ops phy_ops_1g_copper = {
  1641. .xcvr_init = xcvr_init_1g,
  1642. .link_status = link_status_1g,
  1643. };
  1644. struct niu_phy_template {
  1645. const struct niu_phy_ops *ops;
  1646. u32 phy_addr_base;
  1647. };
  1648. static const struct niu_phy_template phy_template_niu = {
  1649. .ops = &phy_ops_10g_fiber_niu,
  1650. .phy_addr_base = 16,
  1651. };
  1652. static const struct niu_phy_template phy_template_10g_fiber = {
  1653. .ops = &phy_ops_10g_fiber,
  1654. .phy_addr_base = 8,
  1655. };
  1656. static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
  1657. .ops = &phy_ops_10g_fiber_hotplug,
  1658. .phy_addr_base = 8,
  1659. };
  1660. static const struct niu_phy_template phy_template_10g_copper = {
  1661. .ops = &phy_ops_10g_copper,
  1662. .phy_addr_base = 10,
  1663. };
  1664. static const struct niu_phy_template phy_template_1g_fiber = {
  1665. .ops = &phy_ops_1g_fiber,
  1666. .phy_addr_base = 0,
  1667. };
  1668. static const struct niu_phy_template phy_template_1g_copper = {
  1669. .ops = &phy_ops_1g_copper,
  1670. .phy_addr_base = 0,
  1671. };
  1672. static const struct niu_phy_template phy_template_1g_rgmii = {
  1673. .ops = &phy_ops_1g_rgmii,
  1674. .phy_addr_base = 0,
  1675. };
  1676. static const struct niu_phy_template phy_template_10g_serdes = {
  1677. .ops = &phy_ops_10g_serdes,
  1678. .phy_addr_base = 0,
  1679. };
  1680. static int niu_atca_port_num[4] = {
  1681. 0, 0, 11, 10
  1682. };
  1683. static int serdes_init_10g_serdes(struct niu *np)
  1684. {
  1685. struct niu_link_config *lp = &np->link_config;
  1686. unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
  1687. u64 ctrl_val, test_cfg_val, sig, mask, val;
  1688. int err;
  1689. u64 reset_val;
  1690. switch (np->port) {
  1691. case 0:
  1692. reset_val = ENET_SERDES_RESET_0;
  1693. ctrl_reg = ENET_SERDES_0_CTRL_CFG;
  1694. test_cfg_reg = ENET_SERDES_0_TEST_CFG;
  1695. pll_cfg = ENET_SERDES_0_PLL_CFG;
  1696. break;
  1697. case 1:
  1698. reset_val = ENET_SERDES_RESET_1;
  1699. ctrl_reg = ENET_SERDES_1_CTRL_CFG;
  1700. test_cfg_reg = ENET_SERDES_1_TEST_CFG;
  1701. pll_cfg = ENET_SERDES_1_PLL_CFG;
  1702. break;
  1703. default:
  1704. return -EINVAL;
  1705. }
  1706. ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
  1707. ENET_SERDES_CTRL_SDET_1 |
  1708. ENET_SERDES_CTRL_SDET_2 |
  1709. ENET_SERDES_CTRL_SDET_3 |
  1710. (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
  1711. (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
  1712. (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
  1713. (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
  1714. (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
  1715. (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
  1716. (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
  1717. (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
  1718. test_cfg_val = 0;
  1719. if (lp->loopback_mode == LOOPBACK_PHY) {
  1720. test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
  1721. ENET_SERDES_TEST_MD_0_SHIFT) |
  1722. (ENET_TEST_MD_PAD_LOOPBACK <<
  1723. ENET_SERDES_TEST_MD_1_SHIFT) |
  1724. (ENET_TEST_MD_PAD_LOOPBACK <<
  1725. ENET_SERDES_TEST_MD_2_SHIFT) |
  1726. (ENET_TEST_MD_PAD_LOOPBACK <<
  1727. ENET_SERDES_TEST_MD_3_SHIFT));
  1728. }
  1729. esr_reset(np);
  1730. nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
  1731. nw64(ctrl_reg, ctrl_val);
  1732. nw64(test_cfg_reg, test_cfg_val);
  1733. /* Initialize all 4 lanes of the SERDES. */
  1734. for (i = 0; i < 4; i++) {
  1735. u32 rxtx_ctrl, glue0;
  1736. err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
  1737. if (err)
  1738. return err;
  1739. err = esr_read_glue0(np, i, &glue0);
  1740. if (err)
  1741. return err;
  1742. rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
  1743. rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
  1744. (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
  1745. glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
  1746. ESR_GLUE_CTRL0_THCNT |
  1747. ESR_GLUE_CTRL0_BLTIME);
  1748. glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
  1749. (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
  1750. (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
  1751. (BLTIME_300_CYCLES <<
  1752. ESR_GLUE_CTRL0_BLTIME_SHIFT));
  1753. err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
  1754. if (err)
  1755. return err;
  1756. err = esr_write_glue0(np, i, glue0);
  1757. if (err)
  1758. return err;
  1759. }
  1760. sig = nr64(ESR_INT_SIGNALS);
  1761. switch (np->port) {
  1762. case 0:
  1763. mask = ESR_INT_SIGNALS_P0_BITS;
  1764. val = (ESR_INT_SRDY0_P0 |
  1765. ESR_INT_DET0_P0 |
  1766. ESR_INT_XSRDY_P0 |
  1767. ESR_INT_XDP_P0_CH3 |
  1768. ESR_INT_XDP_P0_CH2 |
  1769. ESR_INT_XDP_P0_CH1 |
  1770. ESR_INT_XDP_P0_CH0);
  1771. break;
  1772. case 1:
  1773. mask = ESR_INT_SIGNALS_P1_BITS;
  1774. val = (ESR_INT_SRDY0_P1 |
  1775. ESR_INT_DET0_P1 |
  1776. ESR_INT_XSRDY_P1 |
  1777. ESR_INT_XDP_P1_CH3 |
  1778. ESR_INT_XDP_P1_CH2 |
  1779. ESR_INT_XDP_P1_CH1 |
  1780. ESR_INT_XDP_P1_CH0);
  1781. break;
  1782. default:
  1783. return -EINVAL;
  1784. }
  1785. if ((sig & mask) != val) {
  1786. int err;
  1787. err = serdes_init_1g_serdes(np);
  1788. if (!err) {
  1789. np->flags &= ~NIU_FLAGS_10G;
  1790. np->mac_xcvr = MAC_XCVR_PCS;
  1791. } else {
  1792. dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
  1793. np->port);
  1794. return -ENODEV;
  1795. }
  1796. }
  1797. return 0;
  1798. }
  1799. static int niu_determine_phy_disposition(struct niu *np)
  1800. {
  1801. struct niu_parent *parent = np->parent;
  1802. u8 plat_type = parent->plat_type;
  1803. const struct niu_phy_template *tp;
  1804. u32 phy_addr_off = 0;
  1805. if (plat_type == PLAT_TYPE_NIU) {
  1806. tp = &phy_template_niu;
  1807. phy_addr_off += np->port;
  1808. } else {
  1809. switch (np->flags &
  1810. (NIU_FLAGS_10G |
  1811. NIU_FLAGS_FIBER |
  1812. NIU_FLAGS_XCVR_SERDES)) {
  1813. case 0:
  1814. /* 1G copper */
  1815. tp = &phy_template_1g_copper;
  1816. if (plat_type == PLAT_TYPE_VF_P0)
  1817. phy_addr_off = 10;
  1818. else if (plat_type == PLAT_TYPE_VF_P1)
  1819. phy_addr_off = 26;
  1820. phy_addr_off += (np->port ^ 0x3);
  1821. break;
  1822. case NIU_FLAGS_10G:
  1823. /* 10G copper */
  1824. tp = &phy_template_1g_copper;
  1825. break;
  1826. case NIU_FLAGS_FIBER:
  1827. /* 1G fiber */
  1828. tp = &phy_template_1g_fiber;
  1829. break;
  1830. case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
  1831. /* 10G fiber */
  1832. tp = &phy_template_10g_fiber;
  1833. if (plat_type == PLAT_TYPE_VF_P0 ||
  1834. plat_type == PLAT_TYPE_VF_P1)
  1835. phy_addr_off = 8;
  1836. phy_addr_off += np->port;
  1837. if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
  1838. tp = &phy_template_10g_fiber_hotplug;
  1839. if (np->port == 0)
  1840. phy_addr_off = 8;
  1841. if (np->port == 1)
  1842. phy_addr_off = 12;
  1843. }
  1844. break;
  1845. case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
  1846. case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
  1847. case NIU_FLAGS_XCVR_SERDES:
  1848. switch(np->port) {
  1849. case 0:
  1850. case 1:
  1851. tp = &phy_template_10g_serdes;
  1852. break;
  1853. case 2:
  1854. case 3:
  1855. tp = &phy_template_1g_rgmii;
  1856. break;
  1857. default:
  1858. return -EINVAL;
  1859. break;
  1860. }
  1861. phy_addr_off = niu_atca_port_num[np->port];
  1862. break;
  1863. default:
  1864. return -EINVAL;
  1865. }
  1866. }
  1867. np->phy_ops = tp->ops;
  1868. np->phy_addr = tp->phy_addr_base + phy_addr_off;
  1869. return 0;
  1870. }
  1871. static int niu_init_link(struct niu *np)
  1872. {
  1873. struct niu_parent *parent = np->parent;
  1874. int err, ignore;
  1875. if (parent->plat_type == PLAT_TYPE_NIU) {
  1876. err = niu_xcvr_init(np);
  1877. if (err)
  1878. return err;
  1879. msleep(200);
  1880. }
  1881. err = niu_serdes_init(np);
  1882. if (err)
  1883. return err;
  1884. msleep(200);
  1885. err = niu_xcvr_init(np);
  1886. if (!err)
  1887. niu_link_status(np, &ignore);
  1888. return 0;
  1889. }
  1890. static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
  1891. {
  1892. u16 reg0 = addr[4] << 8 | addr[5];
  1893. u16 reg1 = addr[2] << 8 | addr[3];
  1894. u16 reg2 = addr[0] << 8 | addr[1];
  1895. if (np->flags & NIU_FLAGS_XMAC) {
  1896. nw64_mac(XMAC_ADDR0, reg0);
  1897. nw64_mac(XMAC_ADDR1, reg1);
  1898. nw64_mac(XMAC_ADDR2, reg2);
  1899. } else {
  1900. nw64_mac(BMAC_ADDR0, reg0);
  1901. nw64_mac(BMAC_ADDR1, reg1);
  1902. nw64_mac(BMAC_ADDR2, reg2);
  1903. }
  1904. }
  1905. static int niu_num_alt_addr(struct niu *np)
  1906. {
  1907. if (np->flags & NIU_FLAGS_XMAC)
  1908. return XMAC_NUM_ALT_ADDR;
  1909. else
  1910. return BMAC_NUM_ALT_ADDR;
  1911. }
  1912. static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
  1913. {
  1914. u16 reg0 = addr[4] << 8 | addr[5];
  1915. u16 reg1 = addr[2] << 8 | addr[3];
  1916. u16 reg2 = addr[0] << 8 | addr[1];
  1917. if (index >= niu_num_alt_addr(np))
  1918. return -EINVAL;
  1919. if (np->flags & NIU_FLAGS_XMAC) {
  1920. nw64_mac(XMAC_ALT_ADDR0(index), reg0);
  1921. nw64_mac(XMAC_ALT_ADDR1(index), reg1);
  1922. nw64_mac(XMAC_ALT_ADDR2(index), reg2);
  1923. } else {
  1924. nw64_mac(BMAC_ALT_ADDR0(index), reg0);
  1925. nw64_mac(BMAC_ALT_ADDR1(index), reg1);
  1926. nw64_mac(BMAC_ALT_ADDR2(index), reg2);
  1927. }
  1928. return 0;
  1929. }
  1930. static int niu_enable_alt_mac(struct niu *np, int index, int on)
  1931. {
  1932. unsigned long reg;
  1933. u64 val, mask;
  1934. if (index >= niu_num_alt_addr(np))
  1935. return -EINVAL;
  1936. if (np->flags & NIU_FLAGS_XMAC) {
  1937. reg = XMAC_ADDR_CMPEN;
  1938. mask = 1 << index;
  1939. } else {
  1940. reg = BMAC_ADDR_CMPEN;
  1941. mask = 1 << (index + 1);
  1942. }
  1943. val = nr64_mac(reg);
  1944. if (on)
  1945. val |= mask;
  1946. else
  1947. val &= ~mask;
  1948. nw64_mac(reg, val);
  1949. return 0;
  1950. }
  1951. static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
  1952. int num, int mac_pref)
  1953. {
  1954. u64 val = nr64_mac(reg);
  1955. val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
  1956. val |= num;
  1957. if (mac_pref)
  1958. val |= HOST_INFO_MPR;
  1959. nw64_mac(reg, val);
  1960. }
  1961. static int __set_rdc_table_num(struct niu *np,
  1962. int xmac_index, int bmac_index,
  1963. int rdc_table_num, int mac_pref)
  1964. {
  1965. unsigned long reg;
  1966. if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
  1967. return -EINVAL;
  1968. if (np->flags & NIU_FLAGS_XMAC)
  1969. reg = XMAC_HOST_INFO(xmac_index);
  1970. else
  1971. reg = BMAC_HOST_INFO(bmac_index);
  1972. __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
  1973. return 0;
  1974. }
  1975. static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
  1976. int mac_pref)
  1977. {
  1978. return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
  1979. }
  1980. static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
  1981. int mac_pref)
  1982. {
  1983. return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
  1984. }
  1985. static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
  1986. int table_num, int mac_pref)
  1987. {
  1988. if (idx >= niu_num_alt_addr(np))
  1989. return -EINVAL;
  1990. return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
  1991. }
  1992. static u64 vlan_entry_set_parity(u64 reg_val)
  1993. {
  1994. u64 port01_mask;
  1995. u64 port23_mask;
  1996. port01_mask = 0x00ff;
  1997. port23_mask = 0xff00;
  1998. if (hweight64(reg_val & port01_mask) & 1)
  1999. reg_val |= ENET_VLAN_TBL_PARITY0;
  2000. else
  2001. reg_val &= ~ENET_VLAN_TBL_PARITY0;
  2002. if (hweight64(reg_val & port23_mask) & 1)
  2003. reg_val |= ENET_VLAN_TBL_PARITY1;
  2004. else
  2005. reg_val &= ~ENET_VLAN_TBL_PARITY1;
  2006. return reg_val;
  2007. }
  2008. static void vlan_tbl_write(struct niu *np, unsigned long index,
  2009. int port, int vpr, int rdc_table)
  2010. {
  2011. u64 reg_val = nr64(ENET_VLAN_TBL(index));
  2012. reg_val &= ~((ENET_VLAN_TBL_VPR |
  2013. ENET_VLAN_TBL_VLANRDCTBLN) <<
  2014. ENET_VLAN_TBL_SHIFT(port));
  2015. if (vpr)
  2016. reg_val |= (ENET_VLAN_TBL_VPR <<
  2017. ENET_VLAN_TBL_SHIFT(port));
  2018. reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
  2019. reg_val = vlan_entry_set_parity(reg_val);
  2020. nw64(ENET_VLAN_TBL(index), reg_val);
  2021. }
  2022. static void vlan_tbl_clear(struct niu *np)
  2023. {
  2024. int i;
  2025. for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
  2026. nw64(ENET_VLAN_TBL(i), 0);
  2027. }
  2028. static int tcam_wait_bit(struct niu *np, u64 bit)
  2029. {
  2030. int limit = 1000;
  2031. while (--limit > 0) {
  2032. if (nr64(TCAM_CTL) & bit)
  2033. break;
  2034. udelay(1);
  2035. }
  2036. if (limit < 0)
  2037. return -ENODEV;
  2038. return 0;
  2039. }
  2040. static int tcam_flush(struct niu *np, int index)
  2041. {
  2042. nw64(TCAM_KEY_0, 0x00);
  2043. nw64(TCAM_KEY_MASK_0, 0xff);
  2044. nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
  2045. return tcam_wait_bit(np, TCAM_CTL_STAT);
  2046. }
  2047. #if 0
  2048. static int tcam_read(struct niu *np, int index,
  2049. u64 *key, u64 *mask)
  2050. {
  2051. int err;
  2052. nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
  2053. err = tcam_wait_bit(np, TCAM_CTL_STAT);
  2054. if (!err) {
  2055. key[0] = nr64(TCAM_KEY_0);
  2056. key[1] = nr64(TCAM_KEY_1);
  2057. key[2] = nr64(TCAM_KEY_2);
  2058. key[3] = nr64(TCAM_KEY_3);
  2059. mask[0] = nr64(TCAM_KEY_MASK_0);
  2060. mask[1] = nr64(TCAM_KEY_MASK_1);
  2061. mask[2] = nr64(TCAM_KEY_MASK_2);
  2062. mask[3] = nr64(TCAM_KEY_MASK_3);
  2063. }
  2064. return err;
  2065. }
  2066. #endif
  2067. static int tcam_write(struct niu *np, int index,
  2068. u64 *key, u64 *mask)
  2069. {
  2070. nw64(TCAM_KEY_0, key[0]);
  2071. nw64(TCAM_KEY_1, key[1]);
  2072. nw64(TCAM_KEY_2, key[2]);
  2073. nw64(TCAM_KEY_3, key[3]);
  2074. nw64(TCAM_KEY_MASK_0, mask[0]);
  2075. nw64(TCAM_KEY_MASK_1, mask[1]);
  2076. nw64(TCAM_KEY_MASK_2, mask[2]);
  2077. nw64(TCAM_KEY_MASK_3, mask[3]);
  2078. nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
  2079. return tcam_wait_bit(np, TCAM_CTL_STAT);
  2080. }
  2081. #if 0
  2082. static int tcam_assoc_read(struct niu *np, int index, u64 *data)
  2083. {
  2084. int err;
  2085. nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
  2086. err = tcam_wait_bit(np, TCAM_CTL_STAT);
  2087. if (!err)
  2088. *data = nr64(TCAM_KEY_1);
  2089. return err;
  2090. }
  2091. #endif
  2092. static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
  2093. {
  2094. nw64(TCAM_KEY_1, assoc_data);
  2095. nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
  2096. return tcam_wait_bit(np, TCAM_CTL_STAT);
  2097. }
  2098. static void tcam_enable(struct niu *np, int on)
  2099. {
  2100. u64 val = nr64(FFLP_CFG_1);
  2101. if (on)
  2102. val &= ~FFLP_CFG_1_TCAM_DIS;
  2103. else
  2104. val |= FFLP_CFG_1_TCAM_DIS;
  2105. nw64(FFLP_CFG_1, val);
  2106. }
  2107. static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
  2108. {
  2109. u64 val = nr64(FFLP_CFG_1);
  2110. val &= ~(FFLP_CFG_1_FFLPINITDONE |
  2111. FFLP_CFG_1_CAMLAT |
  2112. FFLP_CFG_1_CAMRATIO);
  2113. val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
  2114. val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
  2115. nw64(FFLP_CFG_1, val);
  2116. val = nr64(FFLP_CFG_1);
  2117. val |= FFLP_CFG_1_FFLPINITDONE;
  2118. nw64(FFLP_CFG_1, val);
  2119. }
  2120. static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
  2121. int on)
  2122. {
  2123. unsigned long reg;
  2124. u64 val;
  2125. if (class < CLASS_CODE_ETHERTYPE1 ||
  2126. class > CLASS_CODE_ETHERTYPE2)
  2127. return -EINVAL;
  2128. reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
  2129. val = nr64(reg);
  2130. if (on)
  2131. val |= L2_CLS_VLD;
  2132. else
  2133. val &= ~L2_CLS_VLD;
  2134. nw64(reg, val);
  2135. return 0;
  2136. }
  2137. #if 0
  2138. static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
  2139. u64 ether_type)
  2140. {
  2141. unsigned long reg;
  2142. u64 val;
  2143. if (class < CLASS_CODE_ETHERTYPE1 ||
  2144. class > CLASS_CODE_ETHERTYPE2 ||
  2145. (ether_type & ~(u64)0xffff) != 0)
  2146. return -EINVAL;
  2147. reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
  2148. val = nr64(reg);
  2149. val &= ~L2_CLS_ETYPE;
  2150. val |= (ether_type << L2_CLS_ETYPE_SHIFT);
  2151. nw64(reg, val);
  2152. return 0;
  2153. }
  2154. #endif
  2155. static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
  2156. int on)
  2157. {
  2158. unsigned long reg;
  2159. u64 val;
  2160. if (class < CLASS_CODE_USER_PROG1 ||
  2161. class > CLASS_CODE_USER_PROG4)
  2162. return -EINVAL;
  2163. reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
  2164. val = nr64(reg);
  2165. if (on)
  2166. val |= L3_CLS_VALID;
  2167. else
  2168. val &= ~L3_CLS_VALID;
  2169. nw64(reg, val);
  2170. return 0;
  2171. }
  2172. #if 0
  2173. static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
  2174. int ipv6, u64 protocol_id,
  2175. u64 tos_mask, u64 tos_val)
  2176. {
  2177. unsigned long reg;
  2178. u64 val;
  2179. if (class < CLASS_CODE_USER_PROG1 ||
  2180. class > CLASS_CODE_USER_PROG4 ||
  2181. (protocol_id & ~(u64)0xff) != 0 ||
  2182. (tos_mask & ~(u64)0xff) != 0 ||
  2183. (tos_val & ~(u64)0xff) != 0)
  2184. return -EINVAL;
  2185. reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
  2186. val = nr64(reg);
  2187. val &= ~(L3_CLS_IPVER | L3_CLS_PID |
  2188. L3_CLS_TOSMASK | L3_CLS_TOS);
  2189. if (ipv6)
  2190. val |= L3_CLS_IPVER;
  2191. val |= (protocol_id << L3_CLS_PID_SHIFT);
  2192. val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
  2193. val |= (tos_val << L3_CLS_TOS_SHIFT);
  2194. nw64(reg, val);
  2195. return 0;
  2196. }
  2197. #endif
  2198. static int tcam_early_init(struct niu *np)
  2199. {
  2200. unsigned long i;
  2201. int err;
  2202. tcam_enable(np, 0);
  2203. tcam_set_lat_and_ratio(np,
  2204. DEFAULT_TCAM_LATENCY,
  2205. DEFAULT_TCAM_ACCESS_RATIO);
  2206. for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
  2207. err = tcam_user_eth_class_enable(np, i, 0);
  2208. if (err)
  2209. return err;
  2210. }
  2211. for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
  2212. err = tcam_user_ip_class_enable(np, i, 0);
  2213. if (err)
  2214. return err;
  2215. }
  2216. return 0;
  2217. }
  2218. static int tcam_flush_all(struct niu *np)
  2219. {
  2220. unsigned long i;
  2221. for (i = 0; i < np->parent->tcam_num_entries; i++) {
  2222. int err = tcam_flush(np, i);
  2223. if (err)
  2224. return err;
  2225. }
  2226. return 0;
  2227. }
  2228. static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
  2229. {
  2230. return ((u64)index | (num_entries == 1 ?
  2231. HASH_TBL_ADDR_AUTOINC : 0));
  2232. }
  2233. #if 0
  2234. static int hash_read(struct niu *np, unsigned long partition,
  2235. unsigned long index, unsigned long num_entries,
  2236. u64 *data)
  2237. {
  2238. u64 val = hash_addr_regval(index, num_entries);
  2239. unsigned long i;
  2240. if (partition >= FCRAM_NUM_PARTITIONS ||
  2241. index + num_entries > FCRAM_SIZE)
  2242. return -EINVAL;
  2243. nw64(HASH_TBL_ADDR(partition), val);
  2244. for (i = 0; i < num_entries; i++)
  2245. data[i] = nr64(HASH_TBL_DATA(partition));
  2246. return 0;
  2247. }
  2248. #endif
  2249. static int hash_write(struct niu *np, unsigned long partition,
  2250. unsigned long index, unsigned long num_entries,
  2251. u64 *data)
  2252. {
  2253. u64 val = hash_addr_regval(index, num_entries);
  2254. unsigned long i;
  2255. if (partition >= FCRAM_NUM_PARTITIONS ||
  2256. index + (num_entries * 8) > FCRAM_SIZE)
  2257. return -EINVAL;
  2258. nw64(HASH_TBL_ADDR(partition), val);
  2259. for (i = 0; i < num_entries; i++)
  2260. nw64(HASH_TBL_DATA(partition), data[i]);
  2261. return 0;
  2262. }
  2263. static void fflp_reset(struct niu *np)
  2264. {
  2265. u64 val;
  2266. nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
  2267. udelay(10);
  2268. nw64(FFLP_CFG_1, 0);
  2269. val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
  2270. nw64(FFLP_CFG_1, val);
  2271. }
  2272. static void fflp_set_timings(struct niu *np)
  2273. {
  2274. u64 val = nr64(FFLP_CFG_1);
  2275. val &= ~FFLP_CFG_1_FFLPINITDONE;
  2276. val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
  2277. nw64(FFLP_CFG_1, val);
  2278. val = nr64(FFLP_CFG_1);
  2279. val |= FFLP_CFG_1_FFLPINITDONE;
  2280. nw64(FFLP_CFG_1, val);
  2281. val = nr64(FCRAM_REF_TMR);
  2282. val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
  2283. val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
  2284. val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
  2285. nw64(FCRAM_REF_TMR, val);
  2286. }
  2287. static int fflp_set_partition(struct niu *np, u64 partition,
  2288. u64 mask, u64 base, int enable)
  2289. {
  2290. unsigned long reg;
  2291. u64 val;
  2292. if (partition >= FCRAM_NUM_PARTITIONS ||
  2293. (mask & ~(u64)0x1f) != 0 ||
  2294. (base & ~(u64)0x1f) != 0)
  2295. return -EINVAL;
  2296. reg = FLW_PRT_SEL(partition);
  2297. val = nr64(reg);
  2298. val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
  2299. val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
  2300. val |= (base << FLW_PRT_SEL_BASE_SHIFT);
  2301. if (enable)
  2302. val |= FLW_PRT_SEL_EXT;
  2303. nw64(reg, val);
  2304. return 0;
  2305. }
  2306. static int fflp_disable_all_partitions(struct niu *np)
  2307. {
  2308. unsigned long i;
  2309. for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
  2310. int err = fflp_set_partition(np, 0, 0, 0, 0);
  2311. if (err)
  2312. return err;
  2313. }
  2314. return 0;
  2315. }
  2316. static void fflp_llcsnap_enable(struct niu *np, int on)
  2317. {
  2318. u64 val = nr64(FFLP_CFG_1);
  2319. if (on)
  2320. val |= FFLP_CFG_1_LLCSNAP;
  2321. else
  2322. val &= ~FFLP_CFG_1_LLCSNAP;
  2323. nw64(FFLP_CFG_1, val);
  2324. }
  2325. static void fflp_errors_enable(struct niu *np, int on)
  2326. {
  2327. u64 val = nr64(FFLP_CFG_1);
  2328. if (on)
  2329. val &= ~FFLP_CFG_1_ERRORDIS;
  2330. else
  2331. val |= FFLP_CFG_1_ERRORDIS;
  2332. nw64(FFLP_CFG_1, val);
  2333. }
  2334. static int fflp_hash_clear(struct niu *np)
  2335. {
  2336. struct fcram_hash_ipv4 ent;
  2337. unsigned long i;
  2338. /* IPV4 hash entry with valid bit clear, rest is don't care. */
  2339. memset(&ent, 0, sizeof(ent));
  2340. ent.header = HASH_HEADER_EXT;
  2341. for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
  2342. int err = hash_write(np, 0, i, 1, (u64 *) &ent);
  2343. if (err)
  2344. return err;
  2345. }
  2346. return 0;
  2347. }
  2348. static int fflp_early_init(struct niu *np)
  2349. {
  2350. struct niu_parent *parent;
  2351. unsigned long flags;
  2352. int err;
  2353. niu_lock_parent(np, flags);
  2354. parent = np->parent;
  2355. err = 0;
  2356. if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
  2357. niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
  2358. np->port);
  2359. if (np->parent->plat_type != PLAT_TYPE_NIU) {
  2360. fflp_reset(np);
  2361. fflp_set_timings(np);
  2362. err = fflp_disable_all_partitions(np);
  2363. if (err) {
  2364. niudbg(PROBE, "fflp_disable_all_partitions "
  2365. "failed, err=%d\n", err);
  2366. goto out;
  2367. }
  2368. }
  2369. err = tcam_early_init(np);
  2370. if (err) {
  2371. niudbg(PROBE, "tcam_early_init failed, err=%d\n",
  2372. err);
  2373. goto out;
  2374. }
  2375. fflp_llcsnap_enable(np, 1);
  2376. fflp_errors_enable(np, 0);
  2377. nw64(H1POLY, 0);
  2378. nw64(H2POLY, 0);
  2379. err = tcam_flush_all(np);
  2380. if (err) {
  2381. niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
  2382. err);
  2383. goto out;
  2384. }
  2385. if (np->parent->plat_type != PLAT_TYPE_NIU) {
  2386. err = fflp_hash_clear(np);
  2387. if (err) {
  2388. niudbg(PROBE, "fflp_hash_clear failed, "
  2389. "err=%d\n", err);
  2390. goto out;
  2391. }
  2392. }
  2393. vlan_tbl_clear(np);
  2394. niudbg(PROBE, "fflp_early_init: Success\n");
  2395. parent->flags |= PARENT_FLGS_CLS_HWINIT;
  2396. }
  2397. out:
  2398. niu_unlock_parent(np, flags);
  2399. return err;
  2400. }
  2401. static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
  2402. {
  2403. if (class_code < CLASS_CODE_USER_PROG1 ||
  2404. class_code > CLASS_CODE_SCTP_IPV6)
  2405. return -EINVAL;
  2406. nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
  2407. return 0;
  2408. }
  2409. static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
  2410. {
  2411. if (class_code < CLASS_CODE_USER_PROG1 ||
  2412. class_code > CLASS_CODE_SCTP_IPV6)
  2413. return -EINVAL;
  2414. nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
  2415. return 0;
  2416. }
  2417. static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
  2418. u32 offset, u32 size)
  2419. {
  2420. int i = skb_shinfo(skb)->nr_frags;
  2421. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2422. frag->page = page;
  2423. frag->page_offset = offset;
  2424. frag->size = size;
  2425. skb->len += size;
  2426. skb->data_len += size;
  2427. skb->truesize += size;
  2428. skb_shinfo(skb)->nr_frags = i + 1;
  2429. }
  2430. static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
  2431. {
  2432. a >>= PAGE_SHIFT;
  2433. a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
  2434. return (a & (MAX_RBR_RING_SIZE - 1));
  2435. }
  2436. static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
  2437. struct page ***link)
  2438. {
  2439. unsigned int h = niu_hash_rxaddr(rp, addr);
  2440. struct page *p, **pp;
  2441. addr &= PAGE_MASK;
  2442. pp = &rp->rxhash[h];
  2443. for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
  2444. if (p->index == addr) {
  2445. *link = pp;
  2446. break;
  2447. }
  2448. }
  2449. return p;
  2450. }
  2451. static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
  2452. {
  2453. unsigned int h = niu_hash_rxaddr(rp, base);
  2454. page->index = base;
  2455. page->mapping = (struct address_space *) rp->rxhash[h];
  2456. rp->rxhash[h] = page;
  2457. }
  2458. static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
  2459. gfp_t mask, int start_index)
  2460. {
  2461. struct page *page;
  2462. u64 addr;
  2463. int i;
  2464. page = alloc_page(mask);
  2465. if (!page)
  2466. return -ENOMEM;
  2467. addr = np->ops->map_page(np->device, page, 0,
  2468. PAGE_SIZE, DMA_FROM_DEVICE);
  2469. niu_hash_page(rp, page, addr);
  2470. if (rp->rbr_blocks_per_page > 1)
  2471. atomic_add(rp->rbr_blocks_per_page - 1,
  2472. &compound_head(page)->_count);
  2473. for (i = 0; i < rp->rbr_blocks_per_page; i++) {
  2474. __le32 *rbr = &rp->rbr[start_index + i];
  2475. *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
  2476. addr += rp->rbr_block_size;
  2477. }
  2478. return 0;
  2479. }
  2480. static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
  2481. {
  2482. int index = rp->rbr_index;
  2483. rp->rbr_pending++;
  2484. if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
  2485. int err = niu_rbr_add_page(np, rp, mask, index);
  2486. if (unlikely(err)) {
  2487. rp->rbr_pending--;
  2488. return;
  2489. }
  2490. rp->rbr_index += rp->rbr_blocks_per_page;
  2491. BUG_ON(rp->rbr_index > rp->rbr_table_size);
  2492. if (rp->rbr_index == rp->rbr_table_size)
  2493. rp->rbr_index = 0;
  2494. if (rp->rbr_pending >= rp->rbr_kick_thresh) {
  2495. nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
  2496. rp->rbr_pending = 0;
  2497. }
  2498. }
  2499. }
  2500. static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
  2501. {
  2502. unsigned int index = rp->rcr_index;
  2503. int num_rcr = 0;
  2504. rp->rx_dropped++;
  2505. while (1) {
  2506. struct page *page, **link;
  2507. u64 addr, val;
  2508. u32 rcr_size;
  2509. num_rcr++;
  2510. val = le64_to_cpup(&rp->rcr[index]);
  2511. addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
  2512. RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
  2513. page = niu_find_rxpage(rp, addr, &link);
  2514. rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
  2515. RCR_ENTRY_PKTBUFSZ_SHIFT];
  2516. if ((page->index + PAGE_SIZE) - rcr_size == addr) {
  2517. *link = (struct page *) page->mapping;
  2518. np->ops->unmap_page(np->device, page->index,
  2519. PAGE_SIZE, DMA_FROM_DEVICE);
  2520. page->index = 0;
  2521. page->mapping = NULL;
  2522. __free_page(page);
  2523. rp->rbr_refill_pending++;
  2524. }
  2525. index = NEXT_RCR(rp, index);
  2526. if (!(val & RCR_ENTRY_MULTI))
  2527. break;
  2528. }
  2529. rp->rcr_index = index;
  2530. return num_rcr;
  2531. }
  2532. static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
  2533. {
  2534. unsigned int index = rp->rcr_index;
  2535. struct sk_buff *skb;
  2536. int len, num_rcr;
  2537. skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
  2538. if (unlikely(!skb))
  2539. return niu_rx_pkt_ignore(np, rp);
  2540. num_rcr = 0;
  2541. while (1) {
  2542. struct page *page, **link;
  2543. u32 rcr_size, append_size;
  2544. u64 addr, val, off;
  2545. num_rcr++;
  2546. val = le64_to_cpup(&rp->rcr[index]);
  2547. len = (val & RCR_ENTRY_L2_LEN) >>
  2548. RCR_ENTRY_L2_LEN_SHIFT;
  2549. len -= ETH_FCS_LEN;
  2550. addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
  2551. RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
  2552. page = niu_find_rxpage(rp, addr, &link);
  2553. rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
  2554. RCR_ENTRY_PKTBUFSZ_SHIFT];
  2555. off = addr & ~PAGE_MASK;
  2556. append_size = rcr_size;
  2557. if (num_rcr == 1) {
  2558. int ptype;
  2559. off += 2;
  2560. append_size -= 2;
  2561. ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
  2562. if ((ptype == RCR_PKT_TYPE_TCP ||
  2563. ptype == RCR_PKT_TYPE_UDP) &&
  2564. !(val & (RCR_ENTRY_NOPORT |
  2565. RCR_ENTRY_ERROR)))
  2566. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2567. else
  2568. skb->ip_summed = CHECKSUM_NONE;
  2569. }
  2570. if (!(val & RCR_ENTRY_MULTI))
  2571. append_size = len - skb->len;
  2572. niu_rx_skb_append(skb, page, off, append_size);
  2573. if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
  2574. *link = (struct page *) page->mapping;
  2575. np->ops->unmap_page(np->device, page->index,
  2576. PAGE_SIZE, DMA_FROM_DEVICE);
  2577. page->index = 0;
  2578. page->mapping = NULL;
  2579. rp->rbr_refill_pending++;
  2580. } else
  2581. get_page(page);
  2582. index = NEXT_RCR(rp, index);
  2583. if (!(val & RCR_ENTRY_MULTI))
  2584. break;
  2585. }
  2586. rp->rcr_index = index;
  2587. skb_reserve(skb, NET_IP_ALIGN);
  2588. __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
  2589. rp->rx_packets++;
  2590. rp->rx_bytes += skb->len;
  2591. skb->protocol = eth_type_trans(skb, np->dev);
  2592. netif_receive_skb(skb);
  2593. np->dev->last_rx = jiffies;
  2594. return num_rcr;
  2595. }
  2596. static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
  2597. {
  2598. int blocks_per_page = rp->rbr_blocks_per_page;
  2599. int err, index = rp->rbr_index;
  2600. err = 0;
  2601. while (index < (rp->rbr_table_size - blocks_per_page)) {
  2602. err = niu_rbr_add_page(np, rp, mask, index);
  2603. if (err)
  2604. break;
  2605. index += blocks_per_page;
  2606. }
  2607. rp->rbr_index = index;
  2608. return err;
  2609. }
  2610. static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
  2611. {
  2612. int i;
  2613. for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
  2614. struct page *page;
  2615. page = rp->rxhash[i];
  2616. while (page) {
  2617. struct page *next = (struct page *) page->mapping;
  2618. u64 base = page->index;
  2619. np->ops->unmap_page(np->device, base, PAGE_SIZE,
  2620. DMA_FROM_DEVICE);
  2621. page->index = 0;
  2622. page->mapping = NULL;
  2623. __free_page(page);
  2624. page = next;
  2625. }
  2626. }
  2627. for (i = 0; i < rp->rbr_table_size; i++)
  2628. rp->rbr[i] = cpu_to_le32(0);
  2629. rp->rbr_index = 0;
  2630. }
  2631. static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
  2632. {
  2633. struct tx_buff_info *tb = &rp->tx_buffs[idx];
  2634. struct sk_buff *skb = tb->skb;
  2635. struct tx_pkt_hdr *tp;
  2636. u64 tx_flags;
  2637. int i, len;
  2638. tp = (struct tx_pkt_hdr *) skb->data;
  2639. tx_flags = le64_to_cpup(&tp->flags);
  2640. rp->tx_packets++;
  2641. rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
  2642. ((tx_flags & TXHDR_PAD) / 2));
  2643. len = skb_headlen(skb);
  2644. np->ops->unmap_single(np->device, tb->mapping,
  2645. len, DMA_TO_DEVICE);
  2646. if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
  2647. rp->mark_pending--;
  2648. tb->skb = NULL;
  2649. do {
  2650. idx = NEXT_TX(rp, idx);
  2651. len -= MAX_TX_DESC_LEN;
  2652. } while (len > 0);
  2653. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2654. tb = &rp->tx_buffs[idx];
  2655. BUG_ON(tb->skb != NULL);
  2656. np->ops->unmap_page(np->device, tb->mapping,
  2657. skb_shinfo(skb)->frags[i].size,
  2658. DMA_TO_DEVICE);
  2659. idx = NEXT_TX(rp, idx);
  2660. }
  2661. dev_kfree_skb(skb);
  2662. return idx;
  2663. }
  2664. #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
  2665. static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
  2666. {
  2667. struct netdev_queue *txq;
  2668. u16 pkt_cnt, tmp;
  2669. int cons, index;
  2670. u64 cs;
  2671. index = (rp - np->tx_rings);
  2672. txq = netdev_get_tx_queue(np->dev, index);
  2673. cs = rp->tx_cs;
  2674. if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
  2675. goto out;
  2676. tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
  2677. pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
  2678. (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
  2679. rp->last_pkt_cnt = tmp;
  2680. cons = rp->cons;
  2681. niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
  2682. np->dev->name, pkt_cnt, cons);
  2683. while (pkt_cnt--)
  2684. cons = release_tx_packet(np, rp, cons);
  2685. rp->cons = cons;
  2686. smp_mb();
  2687. out:
  2688. if (unlikely(netif_tx_queue_stopped(txq) &&
  2689. (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
  2690. __netif_tx_lock(txq, smp_processor_id());
  2691. if (netif_tx_queue_stopped(txq) &&
  2692. (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
  2693. netif_tx_wake_queue(txq);
  2694. __netif_tx_unlock(txq);
  2695. }
  2696. }
  2697. static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
  2698. {
  2699. int qlen, rcr_done = 0, work_done = 0;
  2700. struct rxdma_mailbox *mbox = rp->mbox;
  2701. u64 stat;
  2702. #if 1
  2703. stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
  2704. qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
  2705. #else
  2706. stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
  2707. qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
  2708. #endif
  2709. mbox->rx_dma_ctl_stat = 0;
  2710. mbox->rcrstat_a = 0;
  2711. niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
  2712. np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
  2713. rcr_done = work_done = 0;
  2714. qlen = min(qlen, budget);
  2715. while (work_done < qlen) {
  2716. rcr_done += niu_process_rx_pkt(np, rp);
  2717. work_done++;
  2718. }
  2719. if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
  2720. unsigned int i;
  2721. for (i = 0; i < rp->rbr_refill_pending; i++)
  2722. niu_rbr_refill(np, rp, GFP_ATOMIC);
  2723. rp->rbr_refill_pending = 0;
  2724. }
  2725. stat = (RX_DMA_CTL_STAT_MEX |
  2726. ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
  2727. ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
  2728. nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
  2729. return work_done;
  2730. }
  2731. static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
  2732. {
  2733. u64 v0 = lp->v0;
  2734. u32 tx_vec = (v0 >> 32);
  2735. u32 rx_vec = (v0 & 0xffffffff);
  2736. int i, work_done = 0;
  2737. niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
  2738. np->dev->name, (unsigned long long) v0);
  2739. for (i = 0; i < np->num_tx_rings; i++) {
  2740. struct tx_ring_info *rp = &np->tx_rings[i];
  2741. if (tx_vec & (1 << rp->tx_channel))
  2742. niu_tx_work(np, rp);
  2743. nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
  2744. }
  2745. for (i = 0; i < np->num_rx_rings; i++) {
  2746. struct rx_ring_info *rp = &np->rx_rings[i];
  2747. if (rx_vec & (1 << rp->rx_channel)) {
  2748. int this_work_done;
  2749. this_work_done = niu_rx_work(np, rp,
  2750. budget);
  2751. budget -= this_work_done;
  2752. work_done += this_work_done;
  2753. }
  2754. nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
  2755. }
  2756. return work_done;
  2757. }
  2758. static int niu_poll(struct napi_struct *napi, int budget)
  2759. {
  2760. struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
  2761. struct niu *np = lp->np;
  2762. int work_done;
  2763. work_done = niu_poll_core(np, lp, budget);
  2764. if (work_done < budget) {
  2765. netif_rx_complete(np->dev, napi);
  2766. niu_ldg_rearm(np, lp, 1);
  2767. }
  2768. return work_done;
  2769. }
  2770. static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
  2771. u64 stat)
  2772. {
  2773. dev_err(np->device, PFX "%s: RX channel %u errors ( ",
  2774. np->dev->name, rp->rx_channel);
  2775. if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
  2776. printk("RBR_TMOUT ");
  2777. if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
  2778. printk("RSP_CNT ");
  2779. if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
  2780. printk("BYTE_EN_BUS ");
  2781. if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
  2782. printk("RSP_DAT ");
  2783. if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
  2784. printk("RCR_ACK ");
  2785. if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
  2786. printk("RCR_SHA_PAR ");
  2787. if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
  2788. printk("RBR_PRE_PAR ");
  2789. if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
  2790. printk("CONFIG ");
  2791. if (stat & RX_DMA_CTL_STAT_RCRINCON)
  2792. printk("RCRINCON ");
  2793. if (stat & RX_DMA_CTL_STAT_RCRFULL)
  2794. printk("RCRFULL ");
  2795. if (stat & RX_DMA_CTL_STAT_RBRFULL)
  2796. printk("RBRFULL ");
  2797. if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
  2798. printk("RBRLOGPAGE ");
  2799. if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
  2800. printk("CFIGLOGPAGE ");
  2801. if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
  2802. printk("DC_FIDO ");
  2803. printk(")\n");
  2804. }
  2805. static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
  2806. {
  2807. u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
  2808. int err = 0;
  2809. if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
  2810. RX_DMA_CTL_STAT_PORT_FATAL))
  2811. err = -EINVAL;
  2812. if (err) {
  2813. dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
  2814. np->dev->name, rp->rx_channel,
  2815. (unsigned long long) stat);
  2816. niu_log_rxchan_errors(np, rp, stat);
  2817. }
  2818. nw64(RX_DMA_CTL_STAT(rp->rx_channel),
  2819. stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
  2820. return err;
  2821. }
  2822. static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
  2823. u64 cs)
  2824. {
  2825. dev_err(np->device, PFX "%s: TX channel %u errors ( ",
  2826. np->dev->name, rp->tx_channel);
  2827. if (cs & TX_CS_MBOX_ERR)
  2828. printk("MBOX ");
  2829. if (cs & TX_CS_PKT_SIZE_ERR)
  2830. printk("PKT_SIZE ");
  2831. if (cs & TX_CS_TX_RING_OFLOW)
  2832. printk("TX_RING_OFLOW ");
  2833. if (cs & TX_CS_PREF_BUF_PAR_ERR)
  2834. printk("PREF_BUF_PAR ");
  2835. if (cs & TX_CS_NACK_PREF)
  2836. printk("NACK_PREF ");
  2837. if (cs & TX_CS_NACK_PKT_RD)
  2838. printk("NACK_PKT_RD ");
  2839. if (cs & TX_CS_CONF_PART_ERR)
  2840. printk("CONF_PART ");
  2841. if (cs & TX_CS_PKT_PRT_ERR)
  2842. printk("PKT_PTR ");
  2843. printk(")\n");
  2844. }
  2845. static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
  2846. {
  2847. u64 cs, logh, logl;
  2848. cs = nr64(TX_CS(rp->tx_channel));
  2849. logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
  2850. logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
  2851. dev_err(np->device, PFX "%s: TX channel %u error, "
  2852. "cs[%llx] logh[%llx] logl[%llx]\n",
  2853. np->dev->name, rp->tx_channel,
  2854. (unsigned long long) cs,
  2855. (unsigned long long) logh,
  2856. (unsigned long long) logl);
  2857. niu_log_txchan_errors(np, rp, cs);
  2858. return -ENODEV;
  2859. }
  2860. static int niu_mif_interrupt(struct niu *np)
  2861. {
  2862. u64 mif_status = nr64(MIF_STATUS);
  2863. int phy_mdint = 0;
  2864. if (np->flags & NIU_FLAGS_XMAC) {
  2865. u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
  2866. if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
  2867. phy_mdint = 1;
  2868. }
  2869. dev_err(np->device, PFX "%s: MIF interrupt, "
  2870. "stat[%llx] phy_mdint(%d)\n",
  2871. np->dev->name, (unsigned long long) mif_status, phy_mdint);
  2872. return -ENODEV;
  2873. }
  2874. static void niu_xmac_interrupt(struct niu *np)
  2875. {
  2876. struct niu_xmac_stats *mp = &np->mac_stats.xmac;
  2877. u64 val;
  2878. val = nr64_mac(XTXMAC_STATUS);
  2879. if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
  2880. mp->tx_frames += TXMAC_FRM_CNT_COUNT;
  2881. if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
  2882. mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
  2883. if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
  2884. mp->tx_fifo_errors++;
  2885. if (val & XTXMAC_STATUS_TXMAC_OFLOW)
  2886. mp->tx_overflow_errors++;
  2887. if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
  2888. mp->tx_max_pkt_size_errors++;
  2889. if (val & XTXMAC_STATUS_TXMAC_UFLOW)
  2890. mp->tx_underflow_errors++;
  2891. val = nr64_mac(XRXMAC_STATUS);
  2892. if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
  2893. mp->rx_local_faults++;
  2894. if (val & XRXMAC_STATUS_RFLT_DET)
  2895. mp->rx_remote_faults++;
  2896. if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
  2897. mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
  2898. if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
  2899. mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
  2900. if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
  2901. mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
  2902. if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
  2903. mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
  2904. if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
  2905. mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
  2906. if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
  2907. mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
  2908. if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
  2909. mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
  2910. if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
  2911. mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
  2912. if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
  2913. mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
  2914. if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
  2915. mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
  2916. if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
  2917. mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
  2918. if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
  2919. mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
  2920. if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
  2921. mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
  2922. if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
  2923. mp->rx_octets += RXMAC_BT_CNT_COUNT;
  2924. if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
  2925. mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
  2926. if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
  2927. mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
  2928. if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
  2929. mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
  2930. if (val & XRXMAC_STATUS_RXUFLOW)
  2931. mp->rx_underflows++;
  2932. if (val & XRXMAC_STATUS_RXOFLOW)
  2933. mp->rx_overflows++;
  2934. val = nr64_mac(XMAC_FC_STAT);
  2935. if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
  2936. mp->pause_off_state++;
  2937. if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
  2938. mp->pause_on_state++;
  2939. if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
  2940. mp->pause_received++;
  2941. }
  2942. static void niu_bmac_interrupt(struct niu *np)
  2943. {
  2944. struct niu_bmac_stats *mp = &np->mac_stats.bmac;
  2945. u64 val;
  2946. val = nr64_mac(BTXMAC_STATUS);
  2947. if (val & BTXMAC_STATUS_UNDERRUN)
  2948. mp->tx_underflow_errors++;
  2949. if (val & BTXMAC_STATUS_MAX_PKT_ERR)
  2950. mp->tx_max_pkt_size_errors++;
  2951. if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
  2952. mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
  2953. if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
  2954. mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
  2955. val = nr64_mac(BRXMAC_STATUS);
  2956. if (val & BRXMAC_STATUS_OVERFLOW)
  2957. mp->rx_overflows++;
  2958. if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
  2959. mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
  2960. if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
  2961. mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
  2962. if (val & BRXMAC_STATUS_CRC_ERR_EXP)
  2963. mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
  2964. if (val & BRXMAC_STATUS_LEN_ERR_EXP)
  2965. mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
  2966. val = nr64_mac(BMAC_CTRL_STATUS);
  2967. if (val & BMAC_CTRL_STATUS_NOPAUSE)
  2968. mp->pause_off_state++;
  2969. if (val & BMAC_CTRL_STATUS_PAUSE)
  2970. mp->pause_on_state++;
  2971. if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
  2972. mp->pause_received++;
  2973. }
  2974. static int niu_mac_interrupt(struct niu *np)
  2975. {
  2976. if (np->flags & NIU_FLAGS_XMAC)
  2977. niu_xmac_interrupt(np);
  2978. else
  2979. niu_bmac_interrupt(np);
  2980. return 0;
  2981. }
  2982. static void niu_log_device_error(struct niu *np, u64 stat)
  2983. {
  2984. dev_err(np->device, PFX "%s: Core device errors ( ",
  2985. np->dev->name);
  2986. if (stat & SYS_ERR_MASK_META2)
  2987. printk("META2 ");
  2988. if (stat & SYS_ERR_MASK_META1)
  2989. printk("META1 ");
  2990. if (stat & SYS_ERR_MASK_PEU)
  2991. printk("PEU ");
  2992. if (stat & SYS_ERR_MASK_TXC)
  2993. printk("TXC ");
  2994. if (stat & SYS_ERR_MASK_RDMC)
  2995. printk("RDMC ");
  2996. if (stat & SYS_ERR_MASK_TDMC)
  2997. printk("TDMC ");
  2998. if (stat & SYS_ERR_MASK_ZCP)
  2999. printk("ZCP ");
  3000. if (stat & SYS_ERR_MASK_FFLP)
  3001. printk("FFLP ");
  3002. if (stat & SYS_ERR_MASK_IPP)
  3003. printk("IPP ");
  3004. if (stat & SYS_ERR_MASK_MAC)
  3005. printk("MAC ");
  3006. if (stat & SYS_ERR_MASK_SMX)
  3007. printk("SMX ");
  3008. printk(")\n");
  3009. }
  3010. static int niu_device_error(struct niu *np)
  3011. {
  3012. u64 stat = nr64(SYS_ERR_STAT);
  3013. dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
  3014. np->dev->name, (unsigned long long) stat);
  3015. niu_log_device_error(np, stat);
  3016. return -ENODEV;
  3017. }
  3018. static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
  3019. u64 v0, u64 v1, u64 v2)
  3020. {
  3021. int i, err = 0;
  3022. lp->v0 = v0;
  3023. lp->v1 = v1;
  3024. lp->v2 = v2;
  3025. if (v1 & 0x00000000ffffffffULL) {
  3026. u32 rx_vec = (v1 & 0xffffffff);
  3027. for (i = 0; i < np->num_rx_rings; i++) {
  3028. struct rx_ring_info *rp = &np->rx_rings[i];
  3029. if (rx_vec & (1 << rp->rx_channel)) {
  3030. int r = niu_rx_error(np, rp);
  3031. if (r) {
  3032. err = r;
  3033. } else {
  3034. if (!v0)
  3035. nw64(RX_DMA_CTL_STAT(rp->rx_channel),
  3036. RX_DMA_CTL_STAT_MEX);
  3037. }
  3038. }
  3039. }
  3040. }
  3041. if (v1 & 0x7fffffff00000000ULL) {
  3042. u32 tx_vec = (v1 >> 32) & 0x7fffffff;
  3043. for (i = 0; i < np->num_tx_rings; i++) {
  3044. struct tx_ring_info *rp = &np->tx_rings[i];
  3045. if (tx_vec & (1 << rp->tx_channel)) {
  3046. int r = niu_tx_error(np, rp);
  3047. if (r)
  3048. err = r;
  3049. }
  3050. }
  3051. }
  3052. if ((v0 | v1) & 0x8000000000000000ULL) {
  3053. int r = niu_mif_interrupt(np);
  3054. if (r)
  3055. err = r;
  3056. }
  3057. if (v2) {
  3058. if (v2 & 0x01ef) {
  3059. int r = niu_mac_interrupt(np);
  3060. if (r)
  3061. err = r;
  3062. }
  3063. if (v2 & 0x0210) {
  3064. int r = niu_device_error(np);
  3065. if (r)
  3066. err = r;
  3067. }
  3068. }
  3069. if (err)
  3070. niu_enable_interrupts(np, 0);
  3071. return err;
  3072. }
  3073. static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
  3074. int ldn)
  3075. {
  3076. struct rxdma_mailbox *mbox = rp->mbox;
  3077. u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
  3078. stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
  3079. RX_DMA_CTL_STAT_RCRTO);
  3080. nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
  3081. niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
  3082. np->dev->name, (unsigned long long) stat);
  3083. }
  3084. static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
  3085. int ldn)
  3086. {
  3087. rp->tx_cs = nr64(TX_CS(rp->tx_channel));
  3088. niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
  3089. np->dev->name, (unsigned long long) rp->tx_cs);
  3090. }
  3091. static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
  3092. {
  3093. struct niu_parent *parent = np->parent;
  3094. u32 rx_vec, tx_vec;
  3095. int i;
  3096. tx_vec = (v0 >> 32);
  3097. rx_vec = (v0 & 0xffffffff);
  3098. for (i = 0; i < np->num_rx_rings; i++) {
  3099. struct rx_ring_info *rp = &np->rx_rings[i];
  3100. int ldn = LDN_RXDMA(rp->rx_channel);
  3101. if (parent->ldg_map[ldn] != ldg)
  3102. continue;
  3103. nw64(LD_IM0(ldn), LD_IM0_MASK);
  3104. if (rx_vec & (1 << rp->rx_channel))
  3105. niu_rxchan_intr(np, rp, ldn);
  3106. }
  3107. for (i = 0; i < np->num_tx_rings; i++) {
  3108. struct tx_ring_info *rp = &np->tx_rings[i];
  3109. int ldn = LDN_TXDMA(rp->tx_channel);
  3110. if (parent->ldg_map[ldn] != ldg)
  3111. continue;
  3112. nw64(LD_IM0(ldn), LD_IM0_MASK);
  3113. if (tx_vec & (1 << rp->tx_channel))
  3114. niu_txchan_intr(np, rp, ldn);
  3115. }
  3116. }
  3117. static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
  3118. u64 v0, u64 v1, u64 v2)
  3119. {
  3120. if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
  3121. lp->v0 = v0;
  3122. lp->v1 = v1;
  3123. lp->v2 = v2;
  3124. __niu_fastpath_interrupt(np, lp->ldg_num, v0);
  3125. __netif_rx_schedule(np->dev, &lp->napi);
  3126. }
  3127. }
  3128. static irqreturn_t niu_interrupt(int irq, void *dev_id)
  3129. {
  3130. struct niu_ldg *lp = dev_id;
  3131. struct niu *np = lp->np;
  3132. int ldg = lp->ldg_num;
  3133. unsigned long flags;
  3134. u64 v0, v1, v2;
  3135. if (netif_msg_intr(np))
  3136. printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
  3137. lp, ldg);
  3138. spin_lock_irqsave(&np->lock, flags);
  3139. v0 = nr64(LDSV0(ldg));
  3140. v1 = nr64(LDSV1(ldg));
  3141. v2 = nr64(LDSV2(ldg));
  3142. if (netif_msg_intr(np))
  3143. printk("v0[%llx] v1[%llx] v2[%llx]\n",
  3144. (unsigned long long) v0,
  3145. (unsigned long long) v1,
  3146. (unsigned long long) v2);
  3147. if (unlikely(!v0 && !v1 && !v2)) {
  3148. spin_unlock_irqrestore(&np->lock, flags);
  3149. return IRQ_NONE;
  3150. }
  3151. if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
  3152. int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
  3153. if (err)
  3154. goto out;
  3155. }
  3156. if (likely(v0 & ~((u64)1 << LDN_MIF)))
  3157. niu_schedule_napi(np, lp, v0, v1, v2);
  3158. else
  3159. niu_ldg_rearm(np, lp, 1);
  3160. out:
  3161. spin_unlock_irqrestore(&np->lock, flags);
  3162. return IRQ_HANDLED;
  3163. }
  3164. static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
  3165. {
  3166. if (rp->mbox) {
  3167. np->ops->free_coherent(np->device,
  3168. sizeof(struct rxdma_mailbox),
  3169. rp->mbox, rp->mbox_dma);
  3170. rp->mbox = NULL;
  3171. }
  3172. if (rp->rcr) {
  3173. np->ops->free_coherent(np->device,
  3174. MAX_RCR_RING_SIZE * sizeof(__le64),
  3175. rp->rcr, rp->rcr_dma);
  3176. rp->rcr = NULL;
  3177. rp->rcr_table_size = 0;
  3178. rp->rcr_index = 0;
  3179. }
  3180. if (rp->rbr) {
  3181. niu_rbr_free(np, rp);
  3182. np->ops->free_coherent(np->device,
  3183. MAX_RBR_RING_SIZE * sizeof(__le32),
  3184. rp->rbr, rp->rbr_dma);
  3185. rp->rbr = NULL;
  3186. rp->rbr_table_size = 0;
  3187. rp->rbr_index = 0;
  3188. }
  3189. kfree(rp->rxhash);
  3190. rp->rxhash = NULL;
  3191. }
  3192. static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
  3193. {
  3194. if (rp->mbox) {
  3195. np->ops->free_coherent(np->device,
  3196. sizeof(struct txdma_mailbox),
  3197. rp->mbox, rp->mbox_dma);
  3198. rp->mbox = NULL;
  3199. }
  3200. if (rp->descr) {
  3201. int i;
  3202. for (i = 0; i < MAX_TX_RING_SIZE; i++) {
  3203. if (rp->tx_buffs[i].skb)
  3204. (void) release_tx_packet(np, rp, i);
  3205. }
  3206. np->ops->free_coherent(np->device,
  3207. MAX_TX_RING_SIZE * sizeof(__le64),
  3208. rp->descr, rp->descr_dma);
  3209. rp->descr = NULL;
  3210. rp->pending = 0;
  3211. rp->prod = 0;
  3212. rp->cons = 0;
  3213. rp->wrap_bit = 0;
  3214. }
  3215. }
  3216. static void niu_free_channels(struct niu *np)
  3217. {
  3218. int i;
  3219. if (np->rx_rings) {
  3220. for (i = 0; i < np->num_rx_rings; i++) {
  3221. struct rx_ring_info *rp = &np->rx_rings[i];
  3222. niu_free_rx_ring_info(np, rp);
  3223. }
  3224. kfree(np->rx_rings);
  3225. np->rx_rings = NULL;
  3226. np->num_rx_rings = 0;
  3227. }
  3228. if (np->tx_rings) {
  3229. for (i = 0; i < np->num_tx_rings; i++) {
  3230. struct tx_ring_info *rp = &np->tx_rings[i];
  3231. niu_free_tx_ring_info(np, rp);
  3232. }
  3233. kfree(np->tx_rings);
  3234. np->tx_rings = NULL;
  3235. np->num_tx_rings = 0;
  3236. }
  3237. }
  3238. static int niu_alloc_rx_ring_info(struct niu *np,
  3239. struct rx_ring_info *rp)
  3240. {
  3241. BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
  3242. rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
  3243. GFP_KERNEL);
  3244. if (!rp->rxhash)
  3245. return -ENOMEM;
  3246. rp->mbox = np->ops->alloc_coherent(np->device,
  3247. sizeof(struct rxdma_mailbox),
  3248. &rp->mbox_dma, GFP_KERNEL);
  3249. if (!rp->mbox)
  3250. return -ENOMEM;
  3251. if ((unsigned long)rp->mbox & (64UL - 1)) {
  3252. dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
  3253. "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
  3254. return -EINVAL;
  3255. }
  3256. rp->rcr = np->ops->alloc_coherent(np->device,
  3257. MAX_RCR_RING_SIZE * sizeof(__le64),
  3258. &rp->rcr_dma, GFP_KERNEL);
  3259. if (!rp->rcr)
  3260. return -ENOMEM;
  3261. if ((unsigned long)rp->rcr & (64UL - 1)) {
  3262. dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
  3263. "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
  3264. return -EINVAL;
  3265. }
  3266. rp->rcr_table_size = MAX_RCR_RING_SIZE;
  3267. rp->rcr_index = 0;
  3268. rp->rbr = np->ops->alloc_coherent(np->device,
  3269. MAX_RBR_RING_SIZE * sizeof(__le32),
  3270. &rp->rbr_dma, GFP_KERNEL);
  3271. if (!rp->rbr)
  3272. return -ENOMEM;
  3273. if ((unsigned long)rp->rbr & (64UL - 1)) {
  3274. dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
  3275. "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
  3276. return -EINVAL;
  3277. }
  3278. rp->rbr_table_size = MAX_RBR_RING_SIZE;
  3279. rp->rbr_index = 0;
  3280. rp->rbr_pending = 0;
  3281. return 0;
  3282. }
  3283. static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
  3284. {
  3285. int mtu = np->dev->mtu;
  3286. /* These values are recommended by the HW designers for fair
  3287. * utilization of DRR amongst the rings.
  3288. */
  3289. rp->max_burst = mtu + 32;
  3290. if (rp->max_burst > 4096)
  3291. rp->max_burst = 4096;
  3292. }
  3293. static int niu_alloc_tx_ring_info(struct niu *np,
  3294. struct tx_ring_info *rp)
  3295. {
  3296. BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
  3297. rp->mbox = np->ops->alloc_coherent(np->device,
  3298. sizeof(struct txdma_mailbox),
  3299. &rp->mbox_dma, GFP_KERNEL);
  3300. if (!rp->mbox)
  3301. return -ENOMEM;
  3302. if ((unsigned long)rp->mbox & (64UL - 1)) {
  3303. dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
  3304. "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
  3305. return -EINVAL;
  3306. }
  3307. rp->descr = np->ops->alloc_coherent(np->device,
  3308. MAX_TX_RING_SIZE * sizeof(__le64),
  3309. &rp->descr_dma, GFP_KERNEL);
  3310. if (!rp->descr)
  3311. return -ENOMEM;
  3312. if ((unsigned long)rp->descr & (64UL - 1)) {
  3313. dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
  3314. "TXDMA descr table %p\n", np->dev->name, rp->descr);
  3315. return -EINVAL;
  3316. }
  3317. rp->pending = MAX_TX_RING_SIZE;
  3318. rp->prod = 0;
  3319. rp->cons = 0;
  3320. rp->wrap_bit = 0;
  3321. /* XXX make these configurable... XXX */
  3322. rp->mark_freq = rp->pending / 4;
  3323. niu_set_max_burst(np, rp);
  3324. return 0;
  3325. }
  3326. static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
  3327. {
  3328. u16 bss;
  3329. bss = min(PAGE_SHIFT, 15);
  3330. rp->rbr_block_size = 1 << bss;
  3331. rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
  3332. rp->rbr_sizes[0] = 256;
  3333. rp->rbr_sizes[1] = 1024;
  3334. if (np->dev->mtu > ETH_DATA_LEN) {
  3335. switch (PAGE_SIZE) {
  3336. case 4 * 1024:
  3337. rp->rbr_sizes[2] = 4096;
  3338. break;
  3339. default:
  3340. rp->rbr_sizes[2] = 8192;
  3341. break;
  3342. }
  3343. } else {
  3344. rp->rbr_sizes[2] = 2048;
  3345. }
  3346. rp->rbr_sizes[3] = rp->rbr_block_size;
  3347. }
  3348. static int niu_alloc_channels(struct niu *np)
  3349. {
  3350. struct niu_parent *parent = np->parent;
  3351. int first_rx_channel, first_tx_channel;
  3352. int i, port, err;
  3353. port = np->port;
  3354. first_rx_channel = first_tx_channel = 0;
  3355. for (i = 0; i < port; i++) {
  3356. first_rx_channel += parent->rxchan_per_port[i];
  3357. first_tx_channel += parent->txchan_per_port[i];
  3358. }
  3359. np->num_rx_rings = parent->rxchan_per_port[port];
  3360. np->num_tx_rings = parent->txchan_per_port[port];
  3361. np->dev->real_num_tx_queues = np->num_tx_rings;
  3362. np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
  3363. GFP_KERNEL);
  3364. err = -ENOMEM;
  3365. if (!np->rx_rings)
  3366. goto out_err;
  3367. for (i = 0; i < np->num_rx_rings; i++) {
  3368. struct rx_ring_info *rp = &np->rx_rings[i];
  3369. rp->np = np;
  3370. rp->rx_channel = first_rx_channel + i;
  3371. err = niu_alloc_rx_ring_info(np, rp);
  3372. if (err)
  3373. goto out_err;
  3374. niu_size_rbr(np, rp);
  3375. /* XXX better defaults, configurable, etc... XXX */
  3376. rp->nonsyn_window = 64;
  3377. rp->nonsyn_threshold = rp->rcr_table_size - 64;
  3378. rp->syn_window = 64;
  3379. rp->syn_threshold = rp->rcr_table_size - 64;
  3380. rp->rcr_pkt_threshold = 16;
  3381. rp->rcr_timeout = 8;
  3382. rp->rbr_kick_thresh = RBR_REFILL_MIN;
  3383. if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
  3384. rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
  3385. err = niu_rbr_fill(np, rp, GFP_KERNEL);
  3386. if (err)
  3387. return err;
  3388. }
  3389. np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
  3390. GFP_KERNEL);
  3391. err = -ENOMEM;
  3392. if (!np->tx_rings)
  3393. goto out_err;
  3394. for (i = 0; i < np->num_tx_rings; i++) {
  3395. struct tx_ring_info *rp = &np->tx_rings[i];
  3396. rp->np = np;
  3397. rp->tx_channel = first_tx_channel + i;
  3398. err = niu_alloc_tx_ring_info(np, rp);
  3399. if (err)
  3400. goto out_err;
  3401. }
  3402. return 0;
  3403. out_err:
  3404. niu_free_channels(np);
  3405. return err;
  3406. }
  3407. static int niu_tx_cs_sng_poll(struct niu *np, int channel)
  3408. {
  3409. int limit = 1000;
  3410. while (--limit > 0) {
  3411. u64 val = nr64(TX_CS(channel));
  3412. if (val & TX_CS_SNG_STATE)
  3413. return 0;
  3414. }
  3415. return -ENODEV;
  3416. }
  3417. static int niu_tx_channel_stop(struct niu *np, int channel)
  3418. {
  3419. u64 val = nr64(TX_CS(channel));
  3420. val |= TX_CS_STOP_N_GO;
  3421. nw64(TX_CS(channel), val);
  3422. return niu_tx_cs_sng_poll(np, channel);
  3423. }
  3424. static int niu_tx_cs_reset_poll(struct niu *np, int channel)
  3425. {
  3426. int limit = 1000;
  3427. while (--limit > 0) {
  3428. u64 val = nr64(TX_CS(channel));
  3429. if (!(val & TX_CS_RST))
  3430. return 0;
  3431. }
  3432. return -ENODEV;
  3433. }
  3434. static int niu_tx_channel_reset(struct niu *np, int channel)
  3435. {
  3436. u64 val = nr64(TX_CS(channel));
  3437. int err;
  3438. val |= TX_CS_RST;
  3439. nw64(TX_CS(channel), val);
  3440. err = niu_tx_cs_reset_poll(np, channel);
  3441. if (!err)
  3442. nw64(TX_RING_KICK(channel), 0);
  3443. return err;
  3444. }
  3445. static int niu_tx_channel_lpage_init(struct niu *np, int channel)
  3446. {
  3447. u64 val;
  3448. nw64(TX_LOG_MASK1(channel), 0);
  3449. nw64(TX_LOG_VAL1(channel), 0);
  3450. nw64(TX_LOG_MASK2(channel), 0);
  3451. nw64(TX_LOG_VAL2(channel), 0);
  3452. nw64(TX_LOG_PAGE_RELO1(channel), 0);
  3453. nw64(TX_LOG_PAGE_RELO2(channel), 0);
  3454. nw64(TX_LOG_PAGE_HDL(channel), 0);
  3455. val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
  3456. val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
  3457. nw64(TX_LOG_PAGE_VLD(channel), val);
  3458. /* XXX TXDMA 32bit mode? XXX */
  3459. return 0;
  3460. }
  3461. static void niu_txc_enable_port(struct niu *np, int on)
  3462. {
  3463. unsigned long flags;
  3464. u64 val, mask;
  3465. niu_lock_parent(np, flags);
  3466. val = nr64(TXC_CONTROL);
  3467. mask = (u64)1 << np->port;
  3468. if (on) {
  3469. val |= TXC_CONTROL_ENABLE | mask;
  3470. } else {
  3471. val &= ~mask;
  3472. if ((val & ~TXC_CONTROL_ENABLE) == 0)
  3473. val &= ~TXC_CONTROL_ENABLE;
  3474. }
  3475. nw64(TXC_CONTROL, val);
  3476. niu_unlock_parent(np, flags);
  3477. }
  3478. static void niu_txc_set_imask(struct niu *np, u64 imask)
  3479. {
  3480. unsigned long flags;
  3481. u64 val;
  3482. niu_lock_parent(np, flags);
  3483. val = nr64(TXC_INT_MASK);
  3484. val &= ~TXC_INT_MASK_VAL(np->port);
  3485. val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
  3486. niu_unlock_parent(np, flags);
  3487. }
  3488. static void niu_txc_port_dma_enable(struct niu *np, int on)
  3489. {
  3490. u64 val = 0;
  3491. if (on) {
  3492. int i;
  3493. for (i = 0; i < np->num_tx_rings; i++)
  3494. val |= (1 << np->tx_rings[i].tx_channel);
  3495. }
  3496. nw64(TXC_PORT_DMA(np->port), val);
  3497. }
  3498. static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
  3499. {
  3500. int err, channel = rp->tx_channel;
  3501. u64 val, ring_len;
  3502. err = niu_tx_channel_stop(np, channel);
  3503. if (err)
  3504. return err;
  3505. err = niu_tx_channel_reset(np, channel);
  3506. if (err)
  3507. return err;
  3508. err = niu_tx_channel_lpage_init(np, channel);
  3509. if (err)
  3510. return err;
  3511. nw64(TXC_DMA_MAX(channel), rp->max_burst);
  3512. nw64(TX_ENT_MSK(channel), 0);
  3513. if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
  3514. TX_RNG_CFIG_STADDR)) {
  3515. dev_err(np->device, PFX "%s: TX ring channel %d "
  3516. "DMA addr (%llx) is not aligned.\n",
  3517. np->dev->name, channel,
  3518. (unsigned long long) rp->descr_dma);
  3519. return -EINVAL;
  3520. }
  3521. /* The length field in TX_RNG_CFIG is measured in 64-byte
  3522. * blocks. rp->pending is the number of TX descriptors in
  3523. * our ring, 8 bytes each, thus we divide by 8 bytes more
  3524. * to get the proper value the chip wants.
  3525. */
  3526. ring_len = (rp->pending / 8);
  3527. val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
  3528. rp->descr_dma);
  3529. nw64(TX_RNG_CFIG(channel), val);
  3530. if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
  3531. ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
  3532. dev_err(np->device, PFX "%s: TX ring channel %d "
  3533. "MBOX addr (%llx) is has illegal bits.\n",
  3534. np->dev->name, channel,
  3535. (unsigned long long) rp->mbox_dma);
  3536. return -EINVAL;
  3537. }
  3538. nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
  3539. nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
  3540. nw64(TX_CS(channel), 0);
  3541. rp->last_pkt_cnt = 0;
  3542. return 0;
  3543. }
  3544. static void niu_init_rdc_groups(struct niu *np)
  3545. {
  3546. struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
  3547. int i, first_table_num = tp->first_table_num;
  3548. for (i = 0; i < tp->num_tables; i++) {
  3549. struct rdc_table *tbl = &tp->tables[i];
  3550. int this_table = first_table_num + i;
  3551. int slot;
  3552. for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
  3553. nw64(RDC_TBL(this_table, slot),
  3554. tbl->rxdma_channel[slot]);
  3555. }
  3556. nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
  3557. }
  3558. static void niu_init_drr_weight(struct niu *np)
  3559. {
  3560. int type = phy_decode(np->parent->port_phy, np->port);
  3561. u64 val;
  3562. switch (type) {
  3563. case PORT_TYPE_10G:
  3564. val = PT_DRR_WEIGHT_DEFAULT_10G;
  3565. break;
  3566. case PORT_TYPE_1G:
  3567. default:
  3568. val = PT_DRR_WEIGHT_DEFAULT_1G;
  3569. break;
  3570. }
  3571. nw64(PT_DRR_WT(np->port), val);
  3572. }
  3573. static int niu_init_hostinfo(struct niu *np)
  3574. {
  3575. struct niu_parent *parent = np->parent;
  3576. struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
  3577. int i, err, num_alt = niu_num_alt_addr(np);
  3578. int first_rdc_table = tp->first_table_num;
  3579. err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
  3580. if (err)
  3581. return err;
  3582. err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
  3583. if (err)
  3584. return err;
  3585. for (i = 0; i < num_alt; i++) {
  3586. err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
  3587. if (err)
  3588. return err;
  3589. }
  3590. return 0;
  3591. }
  3592. static int niu_rx_channel_reset(struct niu *np, int channel)
  3593. {
  3594. return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
  3595. RXDMA_CFIG1_RST, 1000, 10,
  3596. "RXDMA_CFIG1");
  3597. }
  3598. static int niu_rx_channel_lpage_init(struct niu *np, int channel)
  3599. {
  3600. u64 val;
  3601. nw64(RX_LOG_MASK1(channel), 0);
  3602. nw64(RX_LOG_VAL1(channel), 0);
  3603. nw64(RX_LOG_MASK2(channel), 0);
  3604. nw64(RX_LOG_VAL2(channel), 0);
  3605. nw64(RX_LOG_PAGE_RELO1(channel), 0);
  3606. nw64(RX_LOG_PAGE_RELO2(channel), 0);
  3607. nw64(RX_LOG_PAGE_HDL(channel), 0);
  3608. val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
  3609. val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
  3610. nw64(RX_LOG_PAGE_VLD(channel), val);
  3611. return 0;
  3612. }
  3613. static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
  3614. {
  3615. u64 val;
  3616. val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
  3617. ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
  3618. ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
  3619. ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
  3620. nw64(RDC_RED_PARA(rp->rx_channel), val);
  3621. }
  3622. static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
  3623. {
  3624. u64 val = 0;
  3625. switch (rp->rbr_block_size) {
  3626. case 4 * 1024:
  3627. val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
  3628. break;
  3629. case 8 * 1024:
  3630. val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
  3631. break;
  3632. case 16 * 1024:
  3633. val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
  3634. break;
  3635. case 32 * 1024:
  3636. val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
  3637. break;
  3638. default:
  3639. return -EINVAL;
  3640. }
  3641. val |= RBR_CFIG_B_VLD2;
  3642. switch (rp->rbr_sizes[2]) {
  3643. case 2 * 1024:
  3644. val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
  3645. break;
  3646. case 4 * 1024:
  3647. val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
  3648. break;
  3649. case 8 * 1024:
  3650. val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
  3651. break;
  3652. case 16 * 1024:
  3653. val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
  3654. break;
  3655. default:
  3656. return -EINVAL;
  3657. }
  3658. val |= RBR_CFIG_B_VLD1;
  3659. switch (rp->rbr_sizes[1]) {
  3660. case 1 * 1024:
  3661. val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
  3662. break;
  3663. case 2 * 1024:
  3664. val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
  3665. break;
  3666. case 4 * 1024:
  3667. val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
  3668. break;
  3669. case 8 * 1024:
  3670. val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
  3671. break;
  3672. default:
  3673. return -EINVAL;
  3674. }
  3675. val |= RBR_CFIG_B_VLD0;
  3676. switch (rp->rbr_sizes[0]) {
  3677. case 256:
  3678. val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
  3679. break;
  3680. case 512:
  3681. val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
  3682. break;
  3683. case 1 * 1024:
  3684. val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
  3685. break;
  3686. case 2 * 1024:
  3687. val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
  3688. break;
  3689. default:
  3690. return -EINVAL;
  3691. }
  3692. *ret = val;
  3693. return 0;
  3694. }
  3695. static int niu_enable_rx_channel(struct niu *np, int channel, int on)
  3696. {
  3697. u64 val = nr64(RXDMA_CFIG1(channel));
  3698. int limit;
  3699. if (on)
  3700. val |= RXDMA_CFIG1_EN;
  3701. else
  3702. val &= ~RXDMA_CFIG1_EN;
  3703. nw64(RXDMA_CFIG1(channel), val);
  3704. limit = 1000;
  3705. while (--limit > 0) {
  3706. if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
  3707. break;
  3708. udelay(10);
  3709. }
  3710. if (limit <= 0)
  3711. return -ENODEV;
  3712. return 0;
  3713. }
  3714. static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
  3715. {
  3716. int err, channel = rp->rx_channel;
  3717. u64 val;
  3718. err = niu_rx_channel_reset(np, channel);
  3719. if (err)
  3720. return err;
  3721. err = niu_rx_channel_lpage_init(np, channel);
  3722. if (err)
  3723. return err;
  3724. niu_rx_channel_wred_init(np, rp);
  3725. nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
  3726. nw64(RX_DMA_CTL_STAT(channel),
  3727. (RX_DMA_CTL_STAT_MEX |
  3728. RX_DMA_CTL_STAT_RCRTHRES |
  3729. RX_DMA_CTL_STAT_RCRTO |
  3730. RX_DMA_CTL_STAT_RBR_EMPTY));
  3731. nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
  3732. nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
  3733. nw64(RBR_CFIG_A(channel),
  3734. ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
  3735. (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
  3736. err = niu_compute_rbr_cfig_b(rp, &val);
  3737. if (err)
  3738. return err;
  3739. nw64(RBR_CFIG_B(channel), val);
  3740. nw64(RCRCFIG_A(channel),
  3741. ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
  3742. (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
  3743. nw64(RCRCFIG_B(channel),
  3744. ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
  3745. RCRCFIG_B_ENTOUT |
  3746. ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
  3747. err = niu_enable_rx_channel(np, channel, 1);
  3748. if (err)
  3749. return err;
  3750. nw64(RBR_KICK(channel), rp->rbr_index);
  3751. val = nr64(RX_DMA_CTL_STAT(channel));
  3752. val |= RX_DMA_CTL_STAT_RBR_EMPTY;
  3753. nw64(RX_DMA_CTL_STAT(channel), val);
  3754. return 0;
  3755. }
  3756. static int niu_init_rx_channels(struct niu *np)
  3757. {
  3758. unsigned long flags;
  3759. u64 seed = jiffies_64;
  3760. int err, i;
  3761. niu_lock_parent(np, flags);
  3762. nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
  3763. nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
  3764. niu_unlock_parent(np, flags);
  3765. /* XXX RXDMA 32bit mode? XXX */
  3766. niu_init_rdc_groups(np);
  3767. niu_init_drr_weight(np);
  3768. err = niu_init_hostinfo(np);
  3769. if (err)
  3770. return err;
  3771. for (i = 0; i < np->num_rx_rings; i++) {
  3772. struct rx_ring_info *rp = &np->rx_rings[i];
  3773. err = niu_init_one_rx_channel(np, rp);
  3774. if (err)
  3775. return err;
  3776. }
  3777. return 0;
  3778. }
  3779. static int niu_set_ip_frag_rule(struct niu *np)
  3780. {
  3781. struct niu_parent *parent = np->parent;
  3782. struct niu_classifier *cp = &np->clas;
  3783. struct niu_tcam_entry *tp;
  3784. int index, err;
  3785. /* XXX fix this allocation scheme XXX */
  3786. index = cp->tcam_index;
  3787. tp = &parent->tcam[index];
  3788. /* Note that the noport bit is the same in both ipv4 and
  3789. * ipv6 format TCAM entries.
  3790. */
  3791. memset(tp, 0, sizeof(*tp));
  3792. tp->key[1] = TCAM_V4KEY1_NOPORT;
  3793. tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
  3794. tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
  3795. ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
  3796. err = tcam_write(np, index, tp->key, tp->key_mask);
  3797. if (err)
  3798. return err;
  3799. err = tcam_assoc_write(np, index, tp->assoc_data);
  3800. if (err)
  3801. return err;
  3802. return 0;
  3803. }
  3804. static int niu_init_classifier_hw(struct niu *np)
  3805. {
  3806. struct niu_parent *parent = np->parent;
  3807. struct niu_classifier *cp = &np->clas;
  3808. int i, err;
  3809. nw64(H1POLY, cp->h1_init);
  3810. nw64(H2POLY, cp->h2_init);
  3811. err = niu_init_hostinfo(np);
  3812. if (err)
  3813. return err;
  3814. for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
  3815. struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
  3816. vlan_tbl_write(np, i, np->port,
  3817. vp->vlan_pref, vp->rdc_num);
  3818. }
  3819. for (i = 0; i < cp->num_alt_mac_mappings; i++) {
  3820. struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
  3821. err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
  3822. ap->rdc_num, ap->mac_pref);
  3823. if (err)
  3824. return err;
  3825. }
  3826. for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
  3827. int index = i - CLASS_CODE_USER_PROG1;
  3828. err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
  3829. if (err)
  3830. return err;
  3831. err = niu_set_flow_key(np, i, parent->flow_key[index]);
  3832. if (err)
  3833. return err;
  3834. }
  3835. err = niu_set_ip_frag_rule(np);
  3836. if (err)
  3837. return err;
  3838. tcam_enable(np, 1);
  3839. return 0;
  3840. }
  3841. static int niu_zcp_write(struct niu *np, int index, u64 *data)
  3842. {
  3843. nw64(ZCP_RAM_DATA0, data[0]);
  3844. nw64(ZCP_RAM_DATA1, data[1]);
  3845. nw64(ZCP_RAM_DATA2, data[2]);
  3846. nw64(ZCP_RAM_DATA3, data[3]);
  3847. nw64(ZCP_RAM_DATA4, data[4]);
  3848. nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
  3849. nw64(ZCP_RAM_ACC,
  3850. (ZCP_RAM_ACC_WRITE |
  3851. (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
  3852. (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
  3853. return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
  3854. 1000, 100);
  3855. }
  3856. static int niu_zcp_read(struct niu *np, int index, u64 *data)
  3857. {
  3858. int err;
  3859. err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
  3860. 1000, 100);
  3861. if (err) {
  3862. dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
  3863. "ZCP_RAM_ACC[%llx]\n", np->dev->name,
  3864. (unsigned long long) nr64(ZCP_RAM_ACC));
  3865. return err;
  3866. }
  3867. nw64(ZCP_RAM_ACC,
  3868. (ZCP_RAM_ACC_READ |
  3869. (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
  3870. (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
  3871. err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
  3872. 1000, 100);
  3873. if (err) {
  3874. dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
  3875. "ZCP_RAM_ACC[%llx]\n", np->dev->name,
  3876. (unsigned long long) nr64(ZCP_RAM_ACC));
  3877. return err;
  3878. }
  3879. data[0] = nr64(ZCP_RAM_DATA0);
  3880. data[1] = nr64(ZCP_RAM_DATA1);
  3881. data[2] = nr64(ZCP_RAM_DATA2);
  3882. data[3] = nr64(ZCP_RAM_DATA3);
  3883. data[4] = nr64(ZCP_RAM_DATA4);
  3884. return 0;
  3885. }
  3886. static void niu_zcp_cfifo_reset(struct niu *np)
  3887. {
  3888. u64 val = nr64(RESET_CFIFO);
  3889. val |= RESET_CFIFO_RST(np->port);
  3890. nw64(RESET_CFIFO, val);
  3891. udelay(10);
  3892. val &= ~RESET_CFIFO_RST(np->port);
  3893. nw64(RESET_CFIFO, val);
  3894. }
  3895. static int niu_init_zcp(struct niu *np)
  3896. {
  3897. u64 data[5], rbuf[5];
  3898. int i, max, err;
  3899. if (np->parent->plat_type != PLAT_TYPE_NIU) {
  3900. if (np->port == 0 || np->port == 1)
  3901. max = ATLAS_P0_P1_CFIFO_ENTRIES;
  3902. else
  3903. max = ATLAS_P2_P3_CFIFO_ENTRIES;
  3904. } else
  3905. max = NIU_CFIFO_ENTRIES;
  3906. data[0] = 0;
  3907. data[1] = 0;
  3908. data[2] = 0;
  3909. data[3] = 0;
  3910. data[4] = 0;
  3911. for (i = 0; i < max; i++) {
  3912. err = niu_zcp_write(np, i, data);
  3913. if (err)
  3914. return err;
  3915. err = niu_zcp_read(np, i, rbuf);
  3916. if (err)
  3917. return err;
  3918. }
  3919. niu_zcp_cfifo_reset(np);
  3920. nw64(CFIFO_ECC(np->port), 0);
  3921. nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
  3922. (void) nr64(ZCP_INT_STAT);
  3923. nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
  3924. return 0;
  3925. }
  3926. static void niu_ipp_write(struct niu *np, int index, u64 *data)
  3927. {
  3928. u64 val = nr64_ipp(IPP_CFIG);
  3929. nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
  3930. nw64_ipp(IPP_DFIFO_WR_PTR, index);
  3931. nw64_ipp(IPP_DFIFO_WR0, data[0]);
  3932. nw64_ipp(IPP_DFIFO_WR1, data[1]);
  3933. nw64_ipp(IPP_DFIFO_WR2, data[2]);
  3934. nw64_ipp(IPP_DFIFO_WR3, data[3]);
  3935. nw64_ipp(IPP_DFIFO_WR4, data[4]);
  3936. nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
  3937. }
  3938. static void niu_ipp_read(struct niu *np, int index, u64 *data)
  3939. {
  3940. nw64_ipp(IPP_DFIFO_RD_PTR, index);
  3941. data[0] = nr64_ipp(IPP_DFIFO_RD0);
  3942. data[1] = nr64_ipp(IPP_DFIFO_RD1);
  3943. data[2] = nr64_ipp(IPP_DFIFO_RD2);
  3944. data[3] = nr64_ipp(IPP_DFIFO_RD3);
  3945. data[4] = nr64_ipp(IPP_DFIFO_RD4);
  3946. }
  3947. static int niu_ipp_reset(struct niu *np)
  3948. {
  3949. return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
  3950. 1000, 100, "IPP_CFIG");
  3951. }
  3952. static int niu_init_ipp(struct niu *np)
  3953. {
  3954. u64 data[5], rbuf[5], val;
  3955. int i, max, err;
  3956. if (np->parent->plat_type != PLAT_TYPE_NIU) {
  3957. if (np->port == 0 || np->port == 1)
  3958. max = ATLAS_P0_P1_DFIFO_ENTRIES;
  3959. else
  3960. max = ATLAS_P2_P3_DFIFO_ENTRIES;
  3961. } else
  3962. max = NIU_DFIFO_ENTRIES;
  3963. data[0] = 0;
  3964. data[1] = 0;
  3965. data[2] = 0;
  3966. data[3] = 0;
  3967. data[4] = 0;
  3968. for (i = 0; i < max; i++) {
  3969. niu_ipp_write(np, i, data);
  3970. niu_ipp_read(np, i, rbuf);
  3971. }
  3972. (void) nr64_ipp(IPP_INT_STAT);
  3973. (void) nr64_ipp(IPP_INT_STAT);
  3974. err = niu_ipp_reset(np);
  3975. if (err)
  3976. return err;
  3977. (void) nr64_ipp(IPP_PKT_DIS);
  3978. (void) nr64_ipp(IPP_BAD_CS_CNT);
  3979. (void) nr64_ipp(IPP_ECC);
  3980. (void) nr64_ipp(IPP_INT_STAT);
  3981. nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
  3982. val = nr64_ipp(IPP_CFIG);
  3983. val &= ~IPP_CFIG_IP_MAX_PKT;
  3984. val |= (IPP_CFIG_IPP_ENABLE |
  3985. IPP_CFIG_DFIFO_ECC_EN |
  3986. IPP_CFIG_DROP_BAD_CRC |
  3987. IPP_CFIG_CKSUM_EN |
  3988. (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
  3989. nw64_ipp(IPP_CFIG, val);
  3990. return 0;
  3991. }
  3992. static void niu_handle_led(struct niu *np, int status)
  3993. {
  3994. u64 val;
  3995. val = nr64_mac(XMAC_CONFIG);
  3996. if ((np->flags & NIU_FLAGS_10G) != 0 &&
  3997. (np->flags & NIU_FLAGS_FIBER) != 0) {
  3998. if (status) {
  3999. val |= XMAC_CONFIG_LED_POLARITY;
  4000. val &= ~XMAC_CONFIG_FORCE_LED_ON;
  4001. } else {
  4002. val |= XMAC_CONFIG_FORCE_LED_ON;
  4003. val &= ~XMAC_CONFIG_LED_POLARITY;
  4004. }
  4005. }
  4006. nw64_mac(XMAC_CONFIG, val);
  4007. }
  4008. static void niu_init_xif_xmac(struct niu *np)
  4009. {
  4010. struct niu_link_config *lp = &np->link_config;
  4011. u64 val;
  4012. if (np->flags & NIU_FLAGS_XCVR_SERDES) {
  4013. val = nr64(MIF_CONFIG);
  4014. val |= MIF_CONFIG_ATCA_GE;
  4015. nw64(MIF_CONFIG, val);
  4016. }
  4017. val = nr64_mac(XMAC_CONFIG);
  4018. val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
  4019. val |= XMAC_CONFIG_TX_OUTPUT_EN;
  4020. if (lp->loopback_mode == LOOPBACK_MAC) {
  4021. val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
  4022. val |= XMAC_CONFIG_LOOPBACK;
  4023. } else {
  4024. val &= ~XMAC_CONFIG_LOOPBACK;
  4025. }
  4026. if (np->flags & NIU_FLAGS_10G) {
  4027. val &= ~XMAC_CONFIG_LFS_DISABLE;
  4028. } else {
  4029. val |= XMAC_CONFIG_LFS_DISABLE;
  4030. if (!(np->flags & NIU_FLAGS_FIBER) &&
  4031. !(np->flags & NIU_FLAGS_XCVR_SERDES))
  4032. val |= XMAC_CONFIG_1G_PCS_BYPASS;
  4033. else
  4034. val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
  4035. }
  4036. val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
  4037. if (lp->active_speed == SPEED_100)
  4038. val |= XMAC_CONFIG_SEL_CLK_25MHZ;
  4039. else
  4040. val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
  4041. nw64_mac(XMAC_CONFIG, val);
  4042. val = nr64_mac(XMAC_CONFIG);
  4043. val &= ~XMAC_CONFIG_MODE_MASK;
  4044. if (np->flags & NIU_FLAGS_10G) {
  4045. val |= XMAC_CONFIG_MODE_XGMII;
  4046. } else {
  4047. if (lp->active_speed == SPEED_100)
  4048. val |= XMAC_CONFIG_MODE_MII;
  4049. else
  4050. val |= XMAC_CONFIG_MODE_GMII;
  4051. }
  4052. nw64_mac(XMAC_CONFIG, val);
  4053. }
  4054. static void niu_init_xif_bmac(struct niu *np)
  4055. {
  4056. struct niu_link_config *lp = &np->link_config;
  4057. u64 val;
  4058. val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
  4059. if (lp->loopback_mode == LOOPBACK_MAC)
  4060. val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
  4061. else
  4062. val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
  4063. if (lp->active_speed == SPEED_1000)
  4064. val |= BMAC_XIF_CONFIG_GMII_MODE;
  4065. else
  4066. val &= ~BMAC_XIF_CONFIG_GMII_MODE;
  4067. val &= ~(BMAC_XIF_CONFIG_LINK_LED |
  4068. BMAC_XIF_CONFIG_LED_POLARITY);
  4069. if (!(np->flags & NIU_FLAGS_10G) &&
  4070. !(np->flags & NIU_FLAGS_FIBER) &&
  4071. lp->active_speed == SPEED_100)
  4072. val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
  4073. else
  4074. val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
  4075. nw64_mac(BMAC_XIF_CONFIG, val);
  4076. }
  4077. static void niu_init_xif(struct niu *np)
  4078. {
  4079. if (np->flags & NIU_FLAGS_XMAC)
  4080. niu_init_xif_xmac(np);
  4081. else
  4082. niu_init_xif_bmac(np);
  4083. }
  4084. static void niu_pcs_mii_reset(struct niu *np)
  4085. {
  4086. int limit = 1000;
  4087. u64 val = nr64_pcs(PCS_MII_CTL);
  4088. val |= PCS_MII_CTL_RST;
  4089. nw64_pcs(PCS_MII_CTL, val);
  4090. while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
  4091. udelay(100);
  4092. val = nr64_pcs(PCS_MII_CTL);
  4093. }
  4094. }
  4095. static void niu_xpcs_reset(struct niu *np)
  4096. {
  4097. int limit = 1000;
  4098. u64 val = nr64_xpcs(XPCS_CONTROL1);
  4099. val |= XPCS_CONTROL1_RESET;
  4100. nw64_xpcs(XPCS_CONTROL1, val);
  4101. while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
  4102. udelay(100);
  4103. val = nr64_xpcs(XPCS_CONTROL1);
  4104. }
  4105. }
  4106. static int niu_init_pcs(struct niu *np)
  4107. {
  4108. struct niu_link_config *lp = &np->link_config;
  4109. u64 val;
  4110. switch (np->flags & (NIU_FLAGS_10G |
  4111. NIU_FLAGS_FIBER |
  4112. NIU_FLAGS_XCVR_SERDES)) {
  4113. case NIU_FLAGS_FIBER:
  4114. /* 1G fiber */
  4115. nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
  4116. nw64_pcs(PCS_DPATH_MODE, 0);
  4117. niu_pcs_mii_reset(np);
  4118. break;
  4119. case NIU_FLAGS_10G:
  4120. case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
  4121. case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
  4122. /* 10G SERDES */
  4123. if (!(np->flags & NIU_FLAGS_XMAC))
  4124. return -EINVAL;
  4125. /* 10G copper or fiber */
  4126. val = nr64_mac(XMAC_CONFIG);
  4127. val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
  4128. nw64_mac(XMAC_CONFIG, val);
  4129. niu_xpcs_reset(np);
  4130. val = nr64_xpcs(XPCS_CONTROL1);
  4131. if (lp->loopback_mode == LOOPBACK_PHY)
  4132. val |= XPCS_CONTROL1_LOOPBACK;
  4133. else
  4134. val &= ~XPCS_CONTROL1_LOOPBACK;
  4135. nw64_xpcs(XPCS_CONTROL1, val);
  4136. nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
  4137. (void) nr64_xpcs(XPCS_SYMERR_CNT01);
  4138. (void) nr64_xpcs(XPCS_SYMERR_CNT23);
  4139. break;
  4140. case NIU_FLAGS_XCVR_SERDES:
  4141. /* 1G SERDES */
  4142. niu_pcs_mii_reset(np);
  4143. nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
  4144. nw64_pcs(PCS_DPATH_MODE, 0);
  4145. break;
  4146. case 0:
  4147. /* 1G copper */
  4148. case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
  4149. /* 1G RGMII FIBER */
  4150. nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
  4151. niu_pcs_mii_reset(np);
  4152. break;
  4153. default:
  4154. return -EINVAL;
  4155. }
  4156. return 0;
  4157. }
  4158. static int niu_reset_tx_xmac(struct niu *np)
  4159. {
  4160. return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
  4161. (XTXMAC_SW_RST_REG_RS |
  4162. XTXMAC_SW_RST_SOFT_RST),
  4163. 1000, 100, "XTXMAC_SW_RST");
  4164. }
  4165. static int niu_reset_tx_bmac(struct niu *np)
  4166. {
  4167. int limit;
  4168. nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
  4169. limit = 1000;
  4170. while (--limit >= 0) {
  4171. if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
  4172. break;
  4173. udelay(100);
  4174. }
  4175. if (limit < 0) {
  4176. dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
  4177. "BTXMAC_SW_RST[%llx]\n",
  4178. np->port,
  4179. (unsigned long long) nr64_mac(BTXMAC_SW_RST));
  4180. return -ENODEV;
  4181. }
  4182. return 0;
  4183. }
  4184. static int niu_reset_tx_mac(struct niu *np)
  4185. {
  4186. if (np->flags & NIU_FLAGS_XMAC)
  4187. return niu_reset_tx_xmac(np);
  4188. else
  4189. return niu_reset_tx_bmac(np);
  4190. }
  4191. static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
  4192. {
  4193. u64 val;
  4194. val = nr64_mac(XMAC_MIN);
  4195. val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
  4196. XMAC_MIN_RX_MIN_PKT_SIZE);
  4197. val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
  4198. val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
  4199. nw64_mac(XMAC_MIN, val);
  4200. nw64_mac(XMAC_MAX, max);
  4201. nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
  4202. val = nr64_mac(XMAC_IPG);
  4203. if (np->flags & NIU_FLAGS_10G) {
  4204. val &= ~XMAC_IPG_IPG_XGMII;
  4205. val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
  4206. } else {
  4207. val &= ~XMAC_IPG_IPG_MII_GMII;
  4208. val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
  4209. }
  4210. nw64_mac(XMAC_IPG, val);
  4211. val = nr64_mac(XMAC_CONFIG);
  4212. val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
  4213. XMAC_CONFIG_STRETCH_MODE |
  4214. XMAC_CONFIG_VAR_MIN_IPG_EN |
  4215. XMAC_CONFIG_TX_ENABLE);
  4216. nw64_mac(XMAC_CONFIG, val);
  4217. nw64_mac(TXMAC_FRM_CNT, 0);
  4218. nw64_mac(TXMAC_BYTE_CNT, 0);
  4219. }
  4220. static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
  4221. {
  4222. u64 val;
  4223. nw64_mac(BMAC_MIN_FRAME, min);
  4224. nw64_mac(BMAC_MAX_FRAME, max);
  4225. nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
  4226. nw64_mac(BMAC_CTRL_TYPE, 0x8808);
  4227. nw64_mac(BMAC_PREAMBLE_SIZE, 7);
  4228. val = nr64_mac(BTXMAC_CONFIG);
  4229. val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
  4230. BTXMAC_CONFIG_ENABLE);
  4231. nw64_mac(BTXMAC_CONFIG, val);
  4232. }
  4233. static void niu_init_tx_mac(struct niu *np)
  4234. {
  4235. u64 min, max;
  4236. min = 64;
  4237. if (np->dev->mtu > ETH_DATA_LEN)
  4238. max = 9216;
  4239. else
  4240. max = 1522;
  4241. /* The XMAC_MIN register only accepts values for TX min which
  4242. * have the low 3 bits cleared.
  4243. */
  4244. BUILD_BUG_ON(min & 0x7);
  4245. if (np->flags & NIU_FLAGS_XMAC)
  4246. niu_init_tx_xmac(np, min, max);
  4247. else
  4248. niu_init_tx_bmac(np, min, max);
  4249. }
  4250. static int niu_reset_rx_xmac(struct niu *np)
  4251. {
  4252. int limit;
  4253. nw64_mac(XRXMAC_SW_RST,
  4254. XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
  4255. limit = 1000;
  4256. while (--limit >= 0) {
  4257. if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
  4258. XRXMAC_SW_RST_SOFT_RST)))
  4259. break;
  4260. udelay(100);
  4261. }
  4262. if (limit < 0) {
  4263. dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
  4264. "XRXMAC_SW_RST[%llx]\n",
  4265. np->port,
  4266. (unsigned long long) nr64_mac(XRXMAC_SW_RST));
  4267. return -ENODEV;
  4268. }
  4269. return 0;
  4270. }
  4271. static int niu_reset_rx_bmac(struct niu *np)
  4272. {
  4273. int limit;
  4274. nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
  4275. limit = 1000;
  4276. while (--limit >= 0) {
  4277. if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
  4278. break;
  4279. udelay(100);
  4280. }
  4281. if (limit < 0) {
  4282. dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
  4283. "BRXMAC_SW_RST[%llx]\n",
  4284. np->port,
  4285. (unsigned long long) nr64_mac(BRXMAC_SW_RST));
  4286. return -ENODEV;
  4287. }
  4288. return 0;
  4289. }
  4290. static int niu_reset_rx_mac(struct niu *np)
  4291. {
  4292. if (np->flags & NIU_FLAGS_XMAC)
  4293. return niu_reset_rx_xmac(np);
  4294. else
  4295. return niu_reset_rx_bmac(np);
  4296. }
  4297. static void niu_init_rx_xmac(struct niu *np)
  4298. {
  4299. struct niu_parent *parent = np->parent;
  4300. struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
  4301. int first_rdc_table = tp->first_table_num;
  4302. unsigned long i;
  4303. u64 val;
  4304. nw64_mac(XMAC_ADD_FILT0, 0);
  4305. nw64_mac(XMAC_ADD_FILT1, 0);
  4306. nw64_mac(XMAC_ADD_FILT2, 0);
  4307. nw64_mac(XMAC_ADD_FILT12_MASK, 0);
  4308. nw64_mac(XMAC_ADD_FILT00_MASK, 0);
  4309. for (i = 0; i < MAC_NUM_HASH; i++)
  4310. nw64_mac(XMAC_HASH_TBL(i), 0);
  4311. nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
  4312. niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
  4313. niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
  4314. val = nr64_mac(XMAC_CONFIG);
  4315. val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
  4316. XMAC_CONFIG_PROMISCUOUS |
  4317. XMAC_CONFIG_PROMISC_GROUP |
  4318. XMAC_CONFIG_ERR_CHK_DIS |
  4319. XMAC_CONFIG_RX_CRC_CHK_DIS |
  4320. XMAC_CONFIG_RESERVED_MULTICAST |
  4321. XMAC_CONFIG_RX_CODEV_CHK_DIS |
  4322. XMAC_CONFIG_ADDR_FILTER_EN |
  4323. XMAC_CONFIG_RCV_PAUSE_ENABLE |
  4324. XMAC_CONFIG_STRIP_CRC |
  4325. XMAC_CONFIG_PASS_FLOW_CTRL |
  4326. XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
  4327. val |= (XMAC_CONFIG_HASH_FILTER_EN);
  4328. nw64_mac(XMAC_CONFIG, val);
  4329. nw64_mac(RXMAC_BT_CNT, 0);
  4330. nw64_mac(RXMAC_BC_FRM_CNT, 0);
  4331. nw64_mac(RXMAC_MC_FRM_CNT, 0);
  4332. nw64_mac(RXMAC_FRAG_CNT, 0);
  4333. nw64_mac(RXMAC_HIST_CNT1, 0);
  4334. nw64_mac(RXMAC_HIST_CNT2, 0);
  4335. nw64_mac(RXMAC_HIST_CNT3, 0);
  4336. nw64_mac(RXMAC_HIST_CNT4, 0);
  4337. nw64_mac(RXMAC_HIST_CNT5, 0);
  4338. nw64_mac(RXMAC_HIST_CNT6, 0);
  4339. nw64_mac(RXMAC_HIST_CNT7, 0);
  4340. nw64_mac(RXMAC_MPSZER_CNT, 0);
  4341. nw64_mac(RXMAC_CRC_ER_CNT, 0);
  4342. nw64_mac(RXMAC_CD_VIO_CNT, 0);
  4343. nw64_mac(LINK_FAULT_CNT, 0);
  4344. }
  4345. static void niu_init_rx_bmac(struct niu *np)
  4346. {
  4347. struct niu_parent *parent = np->parent;
  4348. struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
  4349. int first_rdc_table = tp->first_table_num;
  4350. unsigned long i;
  4351. u64 val;
  4352. nw64_mac(BMAC_ADD_FILT0, 0);
  4353. nw64_mac(BMAC_ADD_FILT1, 0);
  4354. nw64_mac(BMAC_ADD_FILT2, 0);
  4355. nw64_mac(BMAC_ADD_FILT12_MASK, 0);
  4356. nw64_mac(BMAC_ADD_FILT00_MASK, 0);
  4357. for (i = 0; i < MAC_NUM_HASH; i++)
  4358. nw64_mac(BMAC_HASH_TBL(i), 0);
  4359. niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
  4360. niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
  4361. nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
  4362. val = nr64_mac(BRXMAC_CONFIG);
  4363. val &= ~(BRXMAC_CONFIG_ENABLE |
  4364. BRXMAC_CONFIG_STRIP_PAD |
  4365. BRXMAC_CONFIG_STRIP_FCS |
  4366. BRXMAC_CONFIG_PROMISC |
  4367. BRXMAC_CONFIG_PROMISC_GRP |
  4368. BRXMAC_CONFIG_ADDR_FILT_EN |
  4369. BRXMAC_CONFIG_DISCARD_DIS);
  4370. val |= (BRXMAC_CONFIG_HASH_FILT_EN);
  4371. nw64_mac(BRXMAC_CONFIG, val);
  4372. val = nr64_mac(BMAC_ADDR_CMPEN);
  4373. val |= BMAC_ADDR_CMPEN_EN0;
  4374. nw64_mac(BMAC_ADDR_CMPEN, val);
  4375. }
  4376. static void niu_init_rx_mac(struct niu *np)
  4377. {
  4378. niu_set_primary_mac(np, np->dev->dev_addr);
  4379. if (np->flags & NIU_FLAGS_XMAC)
  4380. niu_init_rx_xmac(np);
  4381. else
  4382. niu_init_rx_bmac(np);
  4383. }
  4384. static void niu_enable_tx_xmac(struct niu *np, int on)
  4385. {
  4386. u64 val = nr64_mac(XMAC_CONFIG);
  4387. if (on)
  4388. val |= XMAC_CONFIG_TX_ENABLE;
  4389. else
  4390. val &= ~XMAC_CONFIG_TX_ENABLE;
  4391. nw64_mac(XMAC_CONFIG, val);
  4392. }
  4393. static void niu_enable_tx_bmac(struct niu *np, int on)
  4394. {
  4395. u64 val = nr64_mac(BTXMAC_CONFIG);
  4396. if (on)
  4397. val |= BTXMAC_CONFIG_ENABLE;
  4398. else
  4399. val &= ~BTXMAC_CONFIG_ENABLE;
  4400. nw64_mac(BTXMAC_CONFIG, val);
  4401. }
  4402. static void niu_enable_tx_mac(struct niu *np, int on)
  4403. {
  4404. if (np->flags & NIU_FLAGS_XMAC)
  4405. niu_enable_tx_xmac(np, on);
  4406. else
  4407. niu_enable_tx_bmac(np, on);
  4408. }
  4409. static void niu_enable_rx_xmac(struct niu *np, int on)
  4410. {
  4411. u64 val = nr64_mac(XMAC_CONFIG);
  4412. val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
  4413. XMAC_CONFIG_PROMISCUOUS);
  4414. if (np->flags & NIU_FLAGS_MCAST)
  4415. val |= XMAC_CONFIG_HASH_FILTER_EN;
  4416. if (np->flags & NIU_FLAGS_PROMISC)
  4417. val |= XMAC_CONFIG_PROMISCUOUS;
  4418. if (on)
  4419. val |= XMAC_CONFIG_RX_MAC_ENABLE;
  4420. else
  4421. val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
  4422. nw64_mac(XMAC_CONFIG, val);
  4423. }
  4424. static void niu_enable_rx_bmac(struct niu *np, int on)
  4425. {
  4426. u64 val = nr64_mac(BRXMAC_CONFIG);
  4427. val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
  4428. BRXMAC_CONFIG_PROMISC);
  4429. if (np->flags & NIU_FLAGS_MCAST)
  4430. val |= BRXMAC_CONFIG_HASH_FILT_EN;
  4431. if (np->flags & NIU_FLAGS_PROMISC)
  4432. val |= BRXMAC_CONFIG_PROMISC;
  4433. if (on)
  4434. val |= BRXMAC_CONFIG_ENABLE;
  4435. else
  4436. val &= ~BRXMAC_CONFIG_ENABLE;
  4437. nw64_mac(BRXMAC_CONFIG, val);
  4438. }
  4439. static void niu_enable_rx_mac(struct niu *np, int on)
  4440. {
  4441. if (np->flags & NIU_FLAGS_XMAC)
  4442. niu_enable_rx_xmac(np, on);
  4443. else
  4444. niu_enable_rx_bmac(np, on);
  4445. }
  4446. static int niu_init_mac(struct niu *np)
  4447. {
  4448. int err;
  4449. niu_init_xif(np);
  4450. err = niu_init_pcs(np);
  4451. if (err)
  4452. return err;
  4453. err = niu_reset_tx_mac(np);
  4454. if (err)
  4455. return err;
  4456. niu_init_tx_mac(np);
  4457. err = niu_reset_rx_mac(np);
  4458. if (err)
  4459. return err;
  4460. niu_init_rx_mac(np);
  4461. /* This looks hookey but the RX MAC reset we just did will
  4462. * undo some of the state we setup in niu_init_tx_mac() so we
  4463. * have to call it again. In particular, the RX MAC reset will
  4464. * set the XMAC_MAX register back to it's default value.
  4465. */
  4466. niu_init_tx_mac(np);
  4467. niu_enable_tx_mac(np, 1);
  4468. niu_enable_rx_mac(np, 1);
  4469. return 0;
  4470. }
  4471. static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
  4472. {
  4473. (void) niu_tx_channel_stop(np, rp->tx_channel);
  4474. }
  4475. static void niu_stop_tx_channels(struct niu *np)
  4476. {
  4477. int i;
  4478. for (i = 0; i < np->num_tx_rings; i++) {
  4479. struct tx_ring_info *rp = &np->tx_rings[i];
  4480. niu_stop_one_tx_channel(np, rp);
  4481. }
  4482. }
  4483. static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
  4484. {
  4485. (void) niu_tx_channel_reset(np, rp->tx_channel);
  4486. }
  4487. static void niu_reset_tx_channels(struct niu *np)
  4488. {
  4489. int i;
  4490. for (i = 0; i < np->num_tx_rings; i++) {
  4491. struct tx_ring_info *rp = &np->tx_rings[i];
  4492. niu_reset_one_tx_channel(np, rp);
  4493. }
  4494. }
  4495. static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
  4496. {
  4497. (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
  4498. }
  4499. static void niu_stop_rx_channels(struct niu *np)
  4500. {
  4501. int i;
  4502. for (i = 0; i < np->num_rx_rings; i++) {
  4503. struct rx_ring_info *rp = &np->rx_rings[i];
  4504. niu_stop_one_rx_channel(np, rp);
  4505. }
  4506. }
  4507. static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
  4508. {
  4509. int channel = rp->rx_channel;
  4510. (void) niu_rx_channel_reset(np, channel);
  4511. nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
  4512. nw64(RX_DMA_CTL_STAT(channel), 0);
  4513. (void) niu_enable_rx_channel(np, channel, 0);
  4514. }
  4515. static void niu_reset_rx_channels(struct niu *np)
  4516. {
  4517. int i;
  4518. for (i = 0; i < np->num_rx_rings; i++) {
  4519. struct rx_ring_info *rp = &np->rx_rings[i];
  4520. niu_reset_one_rx_channel(np, rp);
  4521. }
  4522. }
  4523. static void niu_disable_ipp(struct niu *np)
  4524. {
  4525. u64 rd, wr, val;
  4526. int limit;
  4527. rd = nr64_ipp(IPP_DFIFO_RD_PTR);
  4528. wr = nr64_ipp(IPP_DFIFO_WR_PTR);
  4529. limit = 100;
  4530. while (--limit >= 0 && (rd != wr)) {
  4531. rd = nr64_ipp(IPP_DFIFO_RD_PTR);
  4532. wr = nr64_ipp(IPP_DFIFO_WR_PTR);
  4533. }
  4534. if (limit < 0 &&
  4535. (rd != 0 && wr != 1)) {
  4536. dev_err(np->device, PFX "%s: IPP would not quiesce, "
  4537. "rd_ptr[%llx] wr_ptr[%llx]\n",
  4538. np->dev->name,
  4539. (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
  4540. (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
  4541. }
  4542. val = nr64_ipp(IPP_CFIG);
  4543. val &= ~(IPP_CFIG_IPP_ENABLE |
  4544. IPP_CFIG_DFIFO_ECC_EN |
  4545. IPP_CFIG_DROP_BAD_CRC |
  4546. IPP_CFIG_CKSUM_EN);
  4547. nw64_ipp(IPP_CFIG, val);
  4548. (void) niu_ipp_reset(np);
  4549. }
  4550. static int niu_init_hw(struct niu *np)
  4551. {
  4552. int i, err;
  4553. niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
  4554. niu_txc_enable_port(np, 1);
  4555. niu_txc_port_dma_enable(np, 1);
  4556. niu_txc_set_imask(np, 0);
  4557. niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
  4558. for (i = 0; i < np->num_tx_rings; i++) {
  4559. struct tx_ring_info *rp = &np->tx_rings[i];
  4560. err = niu_init_one_tx_channel(np, rp);
  4561. if (err)
  4562. return err;
  4563. }
  4564. niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
  4565. err = niu_init_rx_channels(np);
  4566. if (err)
  4567. goto out_uninit_tx_channels;
  4568. niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
  4569. err = niu_init_classifier_hw(np);
  4570. if (err)
  4571. goto out_uninit_rx_channels;
  4572. niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
  4573. err = niu_init_zcp(np);
  4574. if (err)
  4575. goto out_uninit_rx_channels;
  4576. niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
  4577. err = niu_init_ipp(np);
  4578. if (err)
  4579. goto out_uninit_rx_channels;
  4580. niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
  4581. err = niu_init_mac(np);
  4582. if (err)
  4583. goto out_uninit_ipp;
  4584. return 0;
  4585. out_uninit_ipp:
  4586. niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
  4587. niu_disable_ipp(np);
  4588. out_uninit_rx_channels:
  4589. niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
  4590. niu_stop_rx_channels(np);
  4591. niu_reset_rx_channels(np);
  4592. out_uninit_tx_channels:
  4593. niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
  4594. niu_stop_tx_channels(np);
  4595. niu_reset_tx_channels(np);
  4596. return err;
  4597. }
  4598. static void niu_stop_hw(struct niu *np)
  4599. {
  4600. niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
  4601. niu_enable_interrupts(np, 0);
  4602. niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
  4603. niu_enable_rx_mac(np, 0);
  4604. niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
  4605. niu_disable_ipp(np);
  4606. niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
  4607. niu_stop_tx_channels(np);
  4608. niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
  4609. niu_stop_rx_channels(np);
  4610. niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
  4611. niu_reset_tx_channels(np);
  4612. niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
  4613. niu_reset_rx_channels(np);
  4614. }
  4615. static int niu_request_irq(struct niu *np)
  4616. {
  4617. int i, j, err;
  4618. err = 0;
  4619. for (i = 0; i < np->num_ldg; i++) {
  4620. struct niu_ldg *lp = &np->ldg[i];
  4621. err = request_irq(lp->irq, niu_interrupt,
  4622. IRQF_SHARED | IRQF_SAMPLE_RANDOM,
  4623. np->dev->name, lp);
  4624. if (err)
  4625. goto out_free_irqs;
  4626. }
  4627. return 0;
  4628. out_free_irqs:
  4629. for (j = 0; j < i; j++) {
  4630. struct niu_ldg *lp = &np->ldg[j];
  4631. free_irq(lp->irq, lp);
  4632. }
  4633. return err;
  4634. }
  4635. static void niu_free_irq(struct niu *np)
  4636. {
  4637. int i;
  4638. for (i = 0; i < np->num_ldg; i++) {
  4639. struct niu_ldg *lp = &np->ldg[i];
  4640. free_irq(lp->irq, lp);
  4641. }
  4642. }
  4643. static void niu_enable_napi(struct niu *np)
  4644. {
  4645. int i;
  4646. for (i = 0; i < np->num_ldg; i++)
  4647. napi_enable(&np->ldg[i].napi);
  4648. }
  4649. static void niu_disable_napi(struct niu *np)
  4650. {
  4651. int i;
  4652. for (i = 0; i < np->num_ldg; i++)
  4653. napi_disable(&np->ldg[i].napi);
  4654. }
  4655. static int niu_open(struct net_device *dev)
  4656. {
  4657. struct niu *np = netdev_priv(dev);
  4658. int err;
  4659. netif_carrier_off(dev);
  4660. err = niu_alloc_channels(np);
  4661. if (err)
  4662. goto out_err;
  4663. err = niu_enable_interrupts(np, 0);
  4664. if (err)
  4665. goto out_free_channels;
  4666. err = niu_request_irq(np);
  4667. if (err)
  4668. goto out_free_channels;
  4669. niu_enable_napi(np);
  4670. spin_lock_irq(&np->lock);
  4671. err = niu_init_hw(np);
  4672. if (!err) {
  4673. init_timer(&np->timer);
  4674. np->timer.expires = jiffies + HZ;
  4675. np->timer.data = (unsigned long) np;
  4676. np->timer.function = niu_timer;
  4677. err = niu_enable_interrupts(np, 1);
  4678. if (err)
  4679. niu_stop_hw(np);
  4680. }
  4681. spin_unlock_irq(&np->lock);
  4682. if (err) {
  4683. niu_disable_napi(np);
  4684. goto out_free_irq;
  4685. }
  4686. netif_tx_start_all_queues(dev);
  4687. if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
  4688. netif_carrier_on(dev);
  4689. add_timer(&np->timer);
  4690. return 0;
  4691. out_free_irq:
  4692. niu_free_irq(np);
  4693. out_free_channels:
  4694. niu_free_channels(np);
  4695. out_err:
  4696. return err;
  4697. }
  4698. static void niu_full_shutdown(struct niu *np, struct net_device *dev)
  4699. {
  4700. cancel_work_sync(&np->reset_task);
  4701. niu_disable_napi(np);
  4702. netif_tx_stop_all_queues(dev);
  4703. del_timer_sync(&np->timer);
  4704. spin_lock_irq(&np->lock);
  4705. niu_stop_hw(np);
  4706. spin_unlock_irq(&np->lock);
  4707. }
  4708. static int niu_close(struct net_device *dev)
  4709. {
  4710. struct niu *np = netdev_priv(dev);
  4711. niu_full_shutdown(np, dev);
  4712. niu_free_irq(np);
  4713. niu_free_channels(np);
  4714. niu_handle_led(np, 0);
  4715. return 0;
  4716. }
  4717. static void niu_sync_xmac_stats(struct niu *np)
  4718. {
  4719. struct niu_xmac_stats *mp = &np->mac_stats.xmac;
  4720. mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
  4721. mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
  4722. mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
  4723. mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
  4724. mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
  4725. mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
  4726. mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
  4727. mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
  4728. mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
  4729. mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
  4730. mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
  4731. mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
  4732. mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
  4733. mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
  4734. mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
  4735. mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
  4736. mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
  4737. mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
  4738. }
  4739. static void niu_sync_bmac_stats(struct niu *np)
  4740. {
  4741. struct niu_bmac_stats *mp = &np->mac_stats.bmac;
  4742. mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
  4743. mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
  4744. mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
  4745. mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
  4746. mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
  4747. mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
  4748. }
  4749. static void niu_sync_mac_stats(struct niu *np)
  4750. {
  4751. if (np->flags & NIU_FLAGS_XMAC)
  4752. niu_sync_xmac_stats(np);
  4753. else
  4754. niu_sync_bmac_stats(np);
  4755. }
  4756. static void niu_get_rx_stats(struct niu *np)
  4757. {
  4758. unsigned long pkts, dropped, errors, bytes;
  4759. int i;
  4760. pkts = dropped = errors = bytes = 0;
  4761. for (i = 0; i < np->num_rx_rings; i++) {
  4762. struct rx_ring_info *rp = &np->rx_rings[i];
  4763. pkts += rp->rx_packets;
  4764. bytes += rp->rx_bytes;
  4765. dropped += rp->rx_dropped;
  4766. errors += rp->rx_errors;
  4767. }
  4768. np->net_stats.rx_packets = pkts;
  4769. np->net_stats.rx_bytes = bytes;
  4770. np->net_stats.rx_dropped = dropped;
  4771. np->net_stats.rx_errors = errors;
  4772. }
  4773. static void niu_get_tx_stats(struct niu *np)
  4774. {
  4775. unsigned long pkts, errors, bytes;
  4776. int i;
  4777. pkts = errors = bytes = 0;
  4778. for (i = 0; i < np->num_tx_rings; i++) {
  4779. struct tx_ring_info *rp = &np->tx_rings[i];
  4780. pkts += rp->tx_packets;
  4781. bytes += rp->tx_bytes;
  4782. errors += rp->tx_errors;
  4783. }
  4784. np->net_stats.tx_packets = pkts;
  4785. np->net_stats.tx_bytes = bytes;
  4786. np->net_stats.tx_errors = errors;
  4787. }
  4788. static struct net_device_stats *niu_get_stats(struct net_device *dev)
  4789. {
  4790. struct niu *np = netdev_priv(dev);
  4791. niu_get_rx_stats(np);
  4792. niu_get_tx_stats(np);
  4793. return &np->net_stats;
  4794. }
  4795. static void niu_load_hash_xmac(struct niu *np, u16 *hash)
  4796. {
  4797. int i;
  4798. for (i = 0; i < 16; i++)
  4799. nw64_mac(XMAC_HASH_TBL(i), hash[i]);
  4800. }
  4801. static void niu_load_hash_bmac(struct niu *np, u16 *hash)
  4802. {
  4803. int i;
  4804. for (i = 0; i < 16; i++)
  4805. nw64_mac(BMAC_HASH_TBL(i), hash[i]);
  4806. }
  4807. static void niu_load_hash(struct niu *np, u16 *hash)
  4808. {
  4809. if (np->flags & NIU_FLAGS_XMAC)
  4810. niu_load_hash_xmac(np, hash);
  4811. else
  4812. niu_load_hash_bmac(np, hash);
  4813. }
  4814. static void niu_set_rx_mode(struct net_device *dev)
  4815. {
  4816. struct niu *np = netdev_priv(dev);
  4817. int i, alt_cnt, err;
  4818. struct dev_addr_list *addr;
  4819. unsigned long flags;
  4820. u16 hash[16] = { 0, };
  4821. spin_lock_irqsave(&np->lock, flags);
  4822. niu_enable_rx_mac(np, 0);
  4823. np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
  4824. if (dev->flags & IFF_PROMISC)
  4825. np->flags |= NIU_FLAGS_PROMISC;
  4826. if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
  4827. np->flags |= NIU_FLAGS_MCAST;
  4828. alt_cnt = dev->uc_count;
  4829. if (alt_cnt > niu_num_alt_addr(np)) {
  4830. alt_cnt = 0;
  4831. np->flags |= NIU_FLAGS_PROMISC;
  4832. }
  4833. if (alt_cnt) {
  4834. int index = 0;
  4835. for (addr = dev->uc_list; addr; addr = addr->next) {
  4836. err = niu_set_alt_mac(np, index,
  4837. addr->da_addr);
  4838. if (err)
  4839. printk(KERN_WARNING PFX "%s: Error %d "
  4840. "adding alt mac %d\n",
  4841. dev->name, err, index);
  4842. err = niu_enable_alt_mac(np, index, 1);
  4843. if (err)
  4844. printk(KERN_WARNING PFX "%s: Error %d "
  4845. "enabling alt mac %d\n",
  4846. dev->name, err, index);
  4847. index++;
  4848. }
  4849. } else {
  4850. int alt_start;
  4851. if (np->flags & NIU_FLAGS_XMAC)
  4852. alt_start = 0;
  4853. else
  4854. alt_start = 1;
  4855. for (i = alt_start; i < niu_num_alt_addr(np); i++) {
  4856. err = niu_enable_alt_mac(np, i, 0);
  4857. if (err)
  4858. printk(KERN_WARNING PFX "%s: Error %d "
  4859. "disabling alt mac %d\n",
  4860. dev->name, err, i);
  4861. }
  4862. }
  4863. if (dev->flags & IFF_ALLMULTI) {
  4864. for (i = 0; i < 16; i++)
  4865. hash[i] = 0xffff;
  4866. } else if (dev->mc_count > 0) {
  4867. for (addr = dev->mc_list; addr; addr = addr->next) {
  4868. u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
  4869. crc >>= 24;
  4870. hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
  4871. }
  4872. }
  4873. if (np->flags & NIU_FLAGS_MCAST)
  4874. niu_load_hash(np, hash);
  4875. niu_enable_rx_mac(np, 1);
  4876. spin_unlock_irqrestore(&np->lock, flags);
  4877. }
  4878. static int niu_set_mac_addr(struct net_device *dev, void *p)
  4879. {
  4880. struct niu *np = netdev_priv(dev);
  4881. struct sockaddr *addr = p;
  4882. unsigned long flags;
  4883. if (!is_valid_ether_addr(addr->sa_data))
  4884. return -EINVAL;
  4885. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  4886. if (!netif_running(dev))
  4887. return 0;
  4888. spin_lock_irqsave(&np->lock, flags);
  4889. niu_enable_rx_mac(np, 0);
  4890. niu_set_primary_mac(np, dev->dev_addr);
  4891. niu_enable_rx_mac(np, 1);
  4892. spin_unlock_irqrestore(&np->lock, flags);
  4893. return 0;
  4894. }
  4895. static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  4896. {
  4897. return -EOPNOTSUPP;
  4898. }
  4899. static void niu_netif_stop(struct niu *np)
  4900. {
  4901. np->dev->trans_start = jiffies; /* prevent tx timeout */
  4902. niu_disable_napi(np);
  4903. netif_tx_disable(np->dev);
  4904. }
  4905. static void niu_netif_start(struct niu *np)
  4906. {
  4907. /* NOTE: unconditional netif_wake_queue is only appropriate
  4908. * so long as all callers are assured to have free tx slots
  4909. * (such as after niu_init_hw).
  4910. */
  4911. netif_tx_wake_all_queues(np->dev);
  4912. niu_enable_napi(np);
  4913. niu_enable_interrupts(np, 1);
  4914. }
  4915. static void niu_reset_task(struct work_struct *work)
  4916. {
  4917. struct niu *np = container_of(work, struct niu, reset_task);
  4918. unsigned long flags;
  4919. int err;
  4920. spin_lock_irqsave(&np->lock, flags);
  4921. if (!netif_running(np->dev)) {
  4922. spin_unlock_irqrestore(&np->lock, flags);
  4923. return;
  4924. }
  4925. spin_unlock_irqrestore(&np->lock, flags);
  4926. del_timer_sync(&np->timer);
  4927. niu_netif_stop(np);
  4928. spin_lock_irqsave(&np->lock, flags);
  4929. niu_stop_hw(np);
  4930. err = niu_init_hw(np);
  4931. if (!err) {
  4932. np->timer.expires = jiffies + HZ;
  4933. add_timer(&np->timer);
  4934. niu_netif_start(np);
  4935. }
  4936. spin_unlock_irqrestore(&np->lock, flags);
  4937. }
  4938. static void niu_tx_timeout(struct net_device *dev)
  4939. {
  4940. struct niu *np = netdev_priv(dev);
  4941. dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
  4942. dev->name);
  4943. schedule_work(&np->reset_task);
  4944. }
  4945. static void niu_set_txd(struct tx_ring_info *rp, int index,
  4946. u64 mapping, u64 len, u64 mark,
  4947. u64 n_frags)
  4948. {
  4949. __le64 *desc = &rp->descr[index];
  4950. *desc = cpu_to_le64(mark |
  4951. (n_frags << TX_DESC_NUM_PTR_SHIFT) |
  4952. (len << TX_DESC_TR_LEN_SHIFT) |
  4953. (mapping & TX_DESC_SAD));
  4954. }
  4955. static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
  4956. u64 pad_bytes, u64 len)
  4957. {
  4958. u16 eth_proto, eth_proto_inner;
  4959. u64 csum_bits, l3off, ihl, ret;
  4960. u8 ip_proto;
  4961. int ipv6;
  4962. eth_proto = be16_to_cpu(ehdr->h_proto);
  4963. eth_proto_inner = eth_proto;
  4964. if (eth_proto == ETH_P_8021Q) {
  4965. struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
  4966. __be16 val = vp->h_vlan_encapsulated_proto;
  4967. eth_proto_inner = be16_to_cpu(val);
  4968. }
  4969. ipv6 = ihl = 0;
  4970. switch (skb->protocol) {
  4971. case __constant_htons(ETH_P_IP):
  4972. ip_proto = ip_hdr(skb)->protocol;
  4973. ihl = ip_hdr(skb)->ihl;
  4974. break;
  4975. case __constant_htons(ETH_P_IPV6):
  4976. ip_proto = ipv6_hdr(skb)->nexthdr;
  4977. ihl = (40 >> 2);
  4978. ipv6 = 1;
  4979. break;
  4980. default:
  4981. ip_proto = ihl = 0;
  4982. break;
  4983. }
  4984. csum_bits = TXHDR_CSUM_NONE;
  4985. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  4986. u64 start, stuff;
  4987. csum_bits = (ip_proto == IPPROTO_TCP ?
  4988. TXHDR_CSUM_TCP :
  4989. (ip_proto == IPPROTO_UDP ?
  4990. TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
  4991. start = skb_transport_offset(skb) -
  4992. (pad_bytes + sizeof(struct tx_pkt_hdr));
  4993. stuff = start + skb->csum_offset;
  4994. csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
  4995. csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
  4996. }
  4997. l3off = skb_network_offset(skb) -
  4998. (pad_bytes + sizeof(struct tx_pkt_hdr));
  4999. ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
  5000. (len << TXHDR_LEN_SHIFT) |
  5001. ((l3off / 2) << TXHDR_L3START_SHIFT) |
  5002. (ihl << TXHDR_IHL_SHIFT) |
  5003. ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
  5004. ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
  5005. (ipv6 ? TXHDR_IP_VER : 0) |
  5006. csum_bits);
  5007. return ret;
  5008. }
  5009. static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
  5010. {
  5011. struct niu *np = netdev_priv(dev);
  5012. unsigned long align, headroom;
  5013. struct netdev_queue *txq;
  5014. struct tx_ring_info *rp;
  5015. struct tx_pkt_hdr *tp;
  5016. unsigned int len, nfg;
  5017. struct ethhdr *ehdr;
  5018. int prod, i, tlen;
  5019. u64 mapping, mrk;
  5020. i = skb_get_queue_mapping(skb);
  5021. rp = &np->tx_rings[i];
  5022. txq = netdev_get_tx_queue(dev, i);
  5023. if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
  5024. netif_tx_stop_queue(txq);
  5025. dev_err(np->device, PFX "%s: BUG! Tx ring full when "
  5026. "queue awake!\n", dev->name);
  5027. rp->tx_errors++;
  5028. return NETDEV_TX_BUSY;
  5029. }
  5030. if (skb->len < ETH_ZLEN) {
  5031. unsigned int pad_bytes = ETH_ZLEN - skb->len;
  5032. if (skb_pad(skb, pad_bytes))
  5033. goto out;
  5034. skb_put(skb, pad_bytes);
  5035. }
  5036. len = sizeof(struct tx_pkt_hdr) + 15;
  5037. if (skb_headroom(skb) < len) {
  5038. struct sk_buff *skb_new;
  5039. skb_new = skb_realloc_headroom(skb, len);
  5040. if (!skb_new) {
  5041. rp->tx_errors++;
  5042. goto out_drop;
  5043. }
  5044. kfree_skb(skb);
  5045. skb = skb_new;
  5046. } else
  5047. skb_orphan(skb);
  5048. align = ((unsigned long) skb->data & (16 - 1));
  5049. headroom = align + sizeof(struct tx_pkt_hdr);
  5050. ehdr = (struct ethhdr *) skb->data;
  5051. tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
  5052. len = skb->len - sizeof(struct tx_pkt_hdr);
  5053. tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
  5054. tp->resv = 0;
  5055. len = skb_headlen(skb);
  5056. mapping = np->ops->map_single(np->device, skb->data,
  5057. len, DMA_TO_DEVICE);
  5058. prod = rp->prod;
  5059. rp->tx_buffs[prod].skb = skb;
  5060. rp->tx_buffs[prod].mapping = mapping;
  5061. mrk = TX_DESC_SOP;
  5062. if (++rp->mark_counter == rp->mark_freq) {
  5063. rp->mark_counter = 0;
  5064. mrk |= TX_DESC_MARK;
  5065. rp->mark_pending++;
  5066. }
  5067. tlen = len;
  5068. nfg = skb_shinfo(skb)->nr_frags;
  5069. while (tlen > 0) {
  5070. tlen -= MAX_TX_DESC_LEN;
  5071. nfg++;
  5072. }
  5073. while (len > 0) {
  5074. unsigned int this_len = len;
  5075. if (this_len > MAX_TX_DESC_LEN)
  5076. this_len = MAX_TX_DESC_LEN;
  5077. niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
  5078. mrk = nfg = 0;
  5079. prod = NEXT_TX(rp, prod);
  5080. mapping += this_len;
  5081. len -= this_len;
  5082. }
  5083. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  5084. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  5085. len = frag->size;
  5086. mapping = np->ops->map_page(np->device, frag->page,
  5087. frag->page_offset, len,
  5088. DMA_TO_DEVICE);
  5089. rp->tx_buffs[prod].skb = NULL;
  5090. rp->tx_buffs[prod].mapping = mapping;
  5091. niu_set_txd(rp, prod, mapping, len, 0, 0);
  5092. prod = NEXT_TX(rp, prod);
  5093. }
  5094. if (prod < rp->prod)
  5095. rp->wrap_bit ^= TX_RING_KICK_WRAP;
  5096. rp->prod = prod;
  5097. nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
  5098. if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
  5099. netif_tx_stop_queue(txq);
  5100. if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
  5101. netif_tx_wake_queue(txq);
  5102. }
  5103. dev->trans_start = jiffies;
  5104. out:
  5105. return NETDEV_TX_OK;
  5106. out_drop:
  5107. rp->tx_errors++;
  5108. kfree_skb(skb);
  5109. goto out;
  5110. }
  5111. static int niu_change_mtu(struct net_device *dev, int new_mtu)
  5112. {
  5113. struct niu *np = netdev_priv(dev);
  5114. int err, orig_jumbo, new_jumbo;
  5115. if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
  5116. return -EINVAL;
  5117. orig_jumbo = (dev->mtu > ETH_DATA_LEN);
  5118. new_jumbo = (new_mtu > ETH_DATA_LEN);
  5119. dev->mtu = new_mtu;
  5120. if (!netif_running(dev) ||
  5121. (orig_jumbo == new_jumbo))
  5122. return 0;
  5123. niu_full_shutdown(np, dev);
  5124. niu_free_channels(np);
  5125. niu_enable_napi(np);
  5126. err = niu_alloc_channels(np);
  5127. if (err)
  5128. return err;
  5129. spin_lock_irq(&np->lock);
  5130. err = niu_init_hw(np);
  5131. if (!err) {
  5132. init_timer(&np->timer);
  5133. np->timer.expires = jiffies + HZ;
  5134. np->timer.data = (unsigned long) np;
  5135. np->timer.function = niu_timer;
  5136. err = niu_enable_interrupts(np, 1);
  5137. if (err)
  5138. niu_stop_hw(np);
  5139. }
  5140. spin_unlock_irq(&np->lock);
  5141. if (!err) {
  5142. netif_tx_start_all_queues(dev);
  5143. if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
  5144. netif_carrier_on(dev);
  5145. add_timer(&np->timer);
  5146. }
  5147. return err;
  5148. }
  5149. static void niu_get_drvinfo(struct net_device *dev,
  5150. struct ethtool_drvinfo *info)
  5151. {
  5152. struct niu *np = netdev_priv(dev);
  5153. struct niu_vpd *vpd = &np->vpd;
  5154. strcpy(info->driver, DRV_MODULE_NAME);
  5155. strcpy(info->version, DRV_MODULE_VERSION);
  5156. sprintf(info->fw_version, "%d.%d",
  5157. vpd->fcode_major, vpd->fcode_minor);
  5158. if (np->parent->plat_type != PLAT_TYPE_NIU)
  5159. strcpy(info->bus_info, pci_name(np->pdev));
  5160. }
  5161. static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  5162. {
  5163. struct niu *np = netdev_priv(dev);
  5164. struct niu_link_config *lp;
  5165. lp = &np->link_config;
  5166. memset(cmd, 0, sizeof(*cmd));
  5167. cmd->phy_address = np->phy_addr;
  5168. cmd->supported = lp->supported;
  5169. cmd->advertising = lp->advertising;
  5170. cmd->autoneg = lp->autoneg;
  5171. cmd->speed = lp->active_speed;
  5172. cmd->duplex = lp->active_duplex;
  5173. return 0;
  5174. }
  5175. static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  5176. {
  5177. return -EINVAL;
  5178. }
  5179. static u32 niu_get_msglevel(struct net_device *dev)
  5180. {
  5181. struct niu *np = netdev_priv(dev);
  5182. return np->msg_enable;
  5183. }
  5184. static void niu_set_msglevel(struct net_device *dev, u32 value)
  5185. {
  5186. struct niu *np = netdev_priv(dev);
  5187. np->msg_enable = value;
  5188. }
  5189. static int niu_get_eeprom_len(struct net_device *dev)
  5190. {
  5191. struct niu *np = netdev_priv(dev);
  5192. return np->eeprom_len;
  5193. }
  5194. static int niu_get_eeprom(struct net_device *dev,
  5195. struct ethtool_eeprom *eeprom, u8 *data)
  5196. {
  5197. struct niu *np = netdev_priv(dev);
  5198. u32 offset, len, val;
  5199. offset = eeprom->offset;
  5200. len = eeprom->len;
  5201. if (offset + len < offset)
  5202. return -EINVAL;
  5203. if (offset >= np->eeprom_len)
  5204. return -EINVAL;
  5205. if (offset + len > np->eeprom_len)
  5206. len = eeprom->len = np->eeprom_len - offset;
  5207. if (offset & 3) {
  5208. u32 b_offset, b_count;
  5209. b_offset = offset & 3;
  5210. b_count = 4 - b_offset;
  5211. if (b_count > len)
  5212. b_count = len;
  5213. val = nr64(ESPC_NCR((offset - b_offset) / 4));
  5214. memcpy(data, ((char *)&val) + b_offset, b_count);
  5215. data += b_count;
  5216. len -= b_count;
  5217. offset += b_count;
  5218. }
  5219. while (len >= 4) {
  5220. val = nr64(ESPC_NCR(offset / 4));
  5221. memcpy(data, &val, 4);
  5222. data += 4;
  5223. len -= 4;
  5224. offset += 4;
  5225. }
  5226. if (len) {
  5227. val = nr64(ESPC_NCR(offset / 4));
  5228. memcpy(data, &val, len);
  5229. }
  5230. return 0;
  5231. }
  5232. static int niu_ethflow_to_class(int flow_type, u64 *class)
  5233. {
  5234. switch (flow_type) {
  5235. case TCP_V4_FLOW:
  5236. *class = CLASS_CODE_TCP_IPV4;
  5237. break;
  5238. case UDP_V4_FLOW:
  5239. *class = CLASS_CODE_UDP_IPV4;
  5240. break;
  5241. case AH_ESP_V4_FLOW:
  5242. *class = CLASS_CODE_AH_ESP_IPV4;
  5243. break;
  5244. case SCTP_V4_FLOW:
  5245. *class = CLASS_CODE_SCTP_IPV4;
  5246. break;
  5247. case TCP_V6_FLOW:
  5248. *class = CLASS_CODE_TCP_IPV6;
  5249. break;
  5250. case UDP_V6_FLOW:
  5251. *class = CLASS_CODE_UDP_IPV6;
  5252. break;
  5253. case AH_ESP_V6_FLOW:
  5254. *class = CLASS_CODE_AH_ESP_IPV6;
  5255. break;
  5256. case SCTP_V6_FLOW:
  5257. *class = CLASS_CODE_SCTP_IPV6;
  5258. break;
  5259. default:
  5260. return 0;
  5261. }
  5262. return 1;
  5263. }
  5264. static u64 niu_flowkey_to_ethflow(u64 flow_key)
  5265. {
  5266. u64 ethflow = 0;
  5267. if (flow_key & FLOW_KEY_PORT)
  5268. ethflow |= RXH_DEV_PORT;
  5269. if (flow_key & FLOW_KEY_L2DA)
  5270. ethflow |= RXH_L2DA;
  5271. if (flow_key & FLOW_KEY_VLAN)
  5272. ethflow |= RXH_VLAN;
  5273. if (flow_key & FLOW_KEY_IPSA)
  5274. ethflow |= RXH_IP_SRC;
  5275. if (flow_key & FLOW_KEY_IPDA)
  5276. ethflow |= RXH_IP_DST;
  5277. if (flow_key & FLOW_KEY_PROTO)
  5278. ethflow |= RXH_L3_PROTO;
  5279. if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
  5280. ethflow |= RXH_L4_B_0_1;
  5281. if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
  5282. ethflow |= RXH_L4_B_2_3;
  5283. return ethflow;
  5284. }
  5285. static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
  5286. {
  5287. u64 key = 0;
  5288. if (ethflow & RXH_DEV_PORT)
  5289. key |= FLOW_KEY_PORT;
  5290. if (ethflow & RXH_L2DA)
  5291. key |= FLOW_KEY_L2DA;
  5292. if (ethflow & RXH_VLAN)
  5293. key |= FLOW_KEY_VLAN;
  5294. if (ethflow & RXH_IP_SRC)
  5295. key |= FLOW_KEY_IPSA;
  5296. if (ethflow & RXH_IP_DST)
  5297. key |= FLOW_KEY_IPDA;
  5298. if (ethflow & RXH_L3_PROTO)
  5299. key |= FLOW_KEY_PROTO;
  5300. if (ethflow & RXH_L4_B_0_1)
  5301. key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
  5302. if (ethflow & RXH_L4_B_2_3)
  5303. key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
  5304. *flow_key = key;
  5305. return 1;
  5306. }
  5307. static int niu_get_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
  5308. {
  5309. struct niu *np = netdev_priv(dev);
  5310. u64 class;
  5311. cmd->data = 0;
  5312. if (!niu_ethflow_to_class(cmd->flow_type, &class))
  5313. return -EINVAL;
  5314. if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
  5315. TCAM_KEY_DISC)
  5316. cmd->data = RXH_DISCARD;
  5317. else
  5318. cmd->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
  5319. CLASS_CODE_USER_PROG1]);
  5320. return 0;
  5321. }
  5322. static int niu_set_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
  5323. {
  5324. struct niu *np = netdev_priv(dev);
  5325. u64 class;
  5326. u64 flow_key = 0;
  5327. unsigned long flags;
  5328. if (!niu_ethflow_to_class(cmd->flow_type, &class))
  5329. return -EINVAL;
  5330. if (class < CLASS_CODE_USER_PROG1 ||
  5331. class > CLASS_CODE_SCTP_IPV6)
  5332. return -EINVAL;
  5333. if (cmd->data & RXH_DISCARD) {
  5334. niu_lock_parent(np, flags);
  5335. flow_key = np->parent->tcam_key[class -
  5336. CLASS_CODE_USER_PROG1];
  5337. flow_key |= TCAM_KEY_DISC;
  5338. nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
  5339. np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
  5340. niu_unlock_parent(np, flags);
  5341. return 0;
  5342. } else {
  5343. /* Discard was set before, but is not set now */
  5344. if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
  5345. TCAM_KEY_DISC) {
  5346. niu_lock_parent(np, flags);
  5347. flow_key = np->parent->tcam_key[class -
  5348. CLASS_CODE_USER_PROG1];
  5349. flow_key &= ~TCAM_KEY_DISC;
  5350. nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
  5351. flow_key);
  5352. np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
  5353. flow_key;
  5354. niu_unlock_parent(np, flags);
  5355. }
  5356. }
  5357. if (!niu_ethflow_to_flowkey(cmd->data, &flow_key))
  5358. return -EINVAL;
  5359. niu_lock_parent(np, flags);
  5360. nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
  5361. np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
  5362. niu_unlock_parent(np, flags);
  5363. return 0;
  5364. }
  5365. static const struct {
  5366. const char string[ETH_GSTRING_LEN];
  5367. } niu_xmac_stat_keys[] = {
  5368. { "tx_frames" },
  5369. { "tx_bytes" },
  5370. { "tx_fifo_errors" },
  5371. { "tx_overflow_errors" },
  5372. { "tx_max_pkt_size_errors" },
  5373. { "tx_underflow_errors" },
  5374. { "rx_local_faults" },
  5375. { "rx_remote_faults" },
  5376. { "rx_link_faults" },
  5377. { "rx_align_errors" },
  5378. { "rx_frags" },
  5379. { "rx_mcasts" },
  5380. { "rx_bcasts" },
  5381. { "rx_hist_cnt1" },
  5382. { "rx_hist_cnt2" },
  5383. { "rx_hist_cnt3" },
  5384. { "rx_hist_cnt4" },
  5385. { "rx_hist_cnt5" },
  5386. { "rx_hist_cnt6" },
  5387. { "rx_hist_cnt7" },
  5388. { "rx_octets" },
  5389. { "rx_code_violations" },
  5390. { "rx_len_errors" },
  5391. { "rx_crc_errors" },
  5392. { "rx_underflows" },
  5393. { "rx_overflows" },
  5394. { "pause_off_state" },
  5395. { "pause_on_state" },
  5396. { "pause_received" },
  5397. };
  5398. #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
  5399. static const struct {
  5400. const char string[ETH_GSTRING_LEN];
  5401. } niu_bmac_stat_keys[] = {
  5402. { "tx_underflow_errors" },
  5403. { "tx_max_pkt_size_errors" },
  5404. { "tx_bytes" },
  5405. { "tx_frames" },
  5406. { "rx_overflows" },
  5407. { "rx_frames" },
  5408. { "rx_align_errors" },
  5409. { "rx_crc_errors" },
  5410. { "rx_len_errors" },
  5411. { "pause_off_state" },
  5412. { "pause_on_state" },
  5413. { "pause_received" },
  5414. };
  5415. #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
  5416. static const struct {
  5417. const char string[ETH_GSTRING_LEN];
  5418. } niu_rxchan_stat_keys[] = {
  5419. { "rx_channel" },
  5420. { "rx_packets" },
  5421. { "rx_bytes" },
  5422. { "rx_dropped" },
  5423. { "rx_errors" },
  5424. };
  5425. #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
  5426. static const struct {
  5427. const char string[ETH_GSTRING_LEN];
  5428. } niu_txchan_stat_keys[] = {
  5429. { "tx_channel" },
  5430. { "tx_packets" },
  5431. { "tx_bytes" },
  5432. { "tx_errors" },
  5433. };
  5434. #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
  5435. static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  5436. {
  5437. struct niu *np = netdev_priv(dev);
  5438. int i;
  5439. if (stringset != ETH_SS_STATS)
  5440. return;
  5441. if (np->flags & NIU_FLAGS_XMAC) {
  5442. memcpy(data, niu_xmac_stat_keys,
  5443. sizeof(niu_xmac_stat_keys));
  5444. data += sizeof(niu_xmac_stat_keys);
  5445. } else {
  5446. memcpy(data, niu_bmac_stat_keys,
  5447. sizeof(niu_bmac_stat_keys));
  5448. data += sizeof(niu_bmac_stat_keys);
  5449. }
  5450. for (i = 0; i < np->num_rx_rings; i++) {
  5451. memcpy(data, niu_rxchan_stat_keys,
  5452. sizeof(niu_rxchan_stat_keys));
  5453. data += sizeof(niu_rxchan_stat_keys);
  5454. }
  5455. for (i = 0; i < np->num_tx_rings; i++) {
  5456. memcpy(data, niu_txchan_stat_keys,
  5457. sizeof(niu_txchan_stat_keys));
  5458. data += sizeof(niu_txchan_stat_keys);
  5459. }
  5460. }
  5461. static int niu_get_stats_count(struct net_device *dev)
  5462. {
  5463. struct niu *np = netdev_priv(dev);
  5464. return ((np->flags & NIU_FLAGS_XMAC ?
  5465. NUM_XMAC_STAT_KEYS :
  5466. NUM_BMAC_STAT_KEYS) +
  5467. (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
  5468. (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
  5469. }
  5470. static void niu_get_ethtool_stats(struct net_device *dev,
  5471. struct ethtool_stats *stats, u64 *data)
  5472. {
  5473. struct niu *np = netdev_priv(dev);
  5474. int i;
  5475. niu_sync_mac_stats(np);
  5476. if (np->flags & NIU_FLAGS_XMAC) {
  5477. memcpy(data, &np->mac_stats.xmac,
  5478. sizeof(struct niu_xmac_stats));
  5479. data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
  5480. } else {
  5481. memcpy(data, &np->mac_stats.bmac,
  5482. sizeof(struct niu_bmac_stats));
  5483. data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
  5484. }
  5485. for (i = 0; i < np->num_rx_rings; i++) {
  5486. struct rx_ring_info *rp = &np->rx_rings[i];
  5487. data[0] = rp->rx_channel;
  5488. data[1] = rp->rx_packets;
  5489. data[2] = rp->rx_bytes;
  5490. data[3] = rp->rx_dropped;
  5491. data[4] = rp->rx_errors;
  5492. data += 5;
  5493. }
  5494. for (i = 0; i < np->num_tx_rings; i++) {
  5495. struct tx_ring_info *rp = &np->tx_rings[i];
  5496. data[0] = rp->tx_channel;
  5497. data[1] = rp->tx_packets;
  5498. data[2] = rp->tx_bytes;
  5499. data[3] = rp->tx_errors;
  5500. data += 4;
  5501. }
  5502. }
  5503. static u64 niu_led_state_save(struct niu *np)
  5504. {
  5505. if (np->flags & NIU_FLAGS_XMAC)
  5506. return nr64_mac(XMAC_CONFIG);
  5507. else
  5508. return nr64_mac(BMAC_XIF_CONFIG);
  5509. }
  5510. static void niu_led_state_restore(struct niu *np, u64 val)
  5511. {
  5512. if (np->flags & NIU_FLAGS_XMAC)
  5513. nw64_mac(XMAC_CONFIG, val);
  5514. else
  5515. nw64_mac(BMAC_XIF_CONFIG, val);
  5516. }
  5517. static void niu_force_led(struct niu *np, int on)
  5518. {
  5519. u64 val, reg, bit;
  5520. if (np->flags & NIU_FLAGS_XMAC) {
  5521. reg = XMAC_CONFIG;
  5522. bit = XMAC_CONFIG_FORCE_LED_ON;
  5523. } else {
  5524. reg = BMAC_XIF_CONFIG;
  5525. bit = BMAC_XIF_CONFIG_LINK_LED;
  5526. }
  5527. val = nr64_mac(reg);
  5528. if (on)
  5529. val |= bit;
  5530. else
  5531. val &= ~bit;
  5532. nw64_mac(reg, val);
  5533. }
  5534. static int niu_phys_id(struct net_device *dev, u32 data)
  5535. {
  5536. struct niu *np = netdev_priv(dev);
  5537. u64 orig_led_state;
  5538. int i;
  5539. if (!netif_running(dev))
  5540. return -EAGAIN;
  5541. if (data == 0)
  5542. data = 2;
  5543. orig_led_state = niu_led_state_save(np);
  5544. for (i = 0; i < (data * 2); i++) {
  5545. int on = ((i % 2) == 0);
  5546. niu_force_led(np, on);
  5547. if (msleep_interruptible(500))
  5548. break;
  5549. }
  5550. niu_led_state_restore(np, orig_led_state);
  5551. return 0;
  5552. }
  5553. static const struct ethtool_ops niu_ethtool_ops = {
  5554. .get_drvinfo = niu_get_drvinfo,
  5555. .get_link = ethtool_op_get_link,
  5556. .get_msglevel = niu_get_msglevel,
  5557. .set_msglevel = niu_set_msglevel,
  5558. .get_eeprom_len = niu_get_eeprom_len,
  5559. .get_eeprom = niu_get_eeprom,
  5560. .get_settings = niu_get_settings,
  5561. .set_settings = niu_set_settings,
  5562. .get_strings = niu_get_strings,
  5563. .get_stats_count = niu_get_stats_count,
  5564. .get_ethtool_stats = niu_get_ethtool_stats,
  5565. .phys_id = niu_phys_id,
  5566. .get_rxhash = niu_get_hash_opts,
  5567. .set_rxhash = niu_set_hash_opts,
  5568. };
  5569. static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
  5570. int ldg, int ldn)
  5571. {
  5572. if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
  5573. return -EINVAL;
  5574. if (ldn < 0 || ldn > LDN_MAX)
  5575. return -EINVAL;
  5576. parent->ldg_map[ldn] = ldg;
  5577. if (np->parent->plat_type == PLAT_TYPE_NIU) {
  5578. /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
  5579. * the firmware, and we're not supposed to change them.
  5580. * Validate the mapping, because if it's wrong we probably
  5581. * won't get any interrupts and that's painful to debug.
  5582. */
  5583. if (nr64(LDG_NUM(ldn)) != ldg) {
  5584. dev_err(np->device, PFX "Port %u, mis-matched "
  5585. "LDG assignment "
  5586. "for ldn %d, should be %d is %llu\n",
  5587. np->port, ldn, ldg,
  5588. (unsigned long long) nr64(LDG_NUM(ldn)));
  5589. return -EINVAL;
  5590. }
  5591. } else
  5592. nw64(LDG_NUM(ldn), ldg);
  5593. return 0;
  5594. }
  5595. static int niu_set_ldg_timer_res(struct niu *np, int res)
  5596. {
  5597. if (res < 0 || res > LDG_TIMER_RES_VAL)
  5598. return -EINVAL;
  5599. nw64(LDG_TIMER_RES, res);
  5600. return 0;
  5601. }
  5602. static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
  5603. {
  5604. if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
  5605. (func < 0 || func > 3) ||
  5606. (vector < 0 || vector > 0x1f))
  5607. return -EINVAL;
  5608. nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
  5609. return 0;
  5610. }
  5611. static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
  5612. {
  5613. u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
  5614. (addr << ESPC_PIO_STAT_ADDR_SHIFT));
  5615. int limit;
  5616. if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
  5617. return -EINVAL;
  5618. frame = frame_base;
  5619. nw64(ESPC_PIO_STAT, frame);
  5620. limit = 64;
  5621. do {
  5622. udelay(5);
  5623. frame = nr64(ESPC_PIO_STAT);
  5624. if (frame & ESPC_PIO_STAT_READ_END)
  5625. break;
  5626. } while (limit--);
  5627. if (!(frame & ESPC_PIO_STAT_READ_END)) {
  5628. dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
  5629. (unsigned long long) frame);
  5630. return -ENODEV;
  5631. }
  5632. frame = frame_base;
  5633. nw64(ESPC_PIO_STAT, frame);
  5634. limit = 64;
  5635. do {
  5636. udelay(5);
  5637. frame = nr64(ESPC_PIO_STAT);
  5638. if (frame & ESPC_PIO_STAT_READ_END)
  5639. break;
  5640. } while (limit--);
  5641. if (!(frame & ESPC_PIO_STAT_READ_END)) {
  5642. dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
  5643. (unsigned long long) frame);
  5644. return -ENODEV;
  5645. }
  5646. frame = nr64(ESPC_PIO_STAT);
  5647. return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
  5648. }
  5649. static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
  5650. {
  5651. int err = niu_pci_eeprom_read(np, off);
  5652. u16 val;
  5653. if (err < 0)
  5654. return err;
  5655. val = (err << 8);
  5656. err = niu_pci_eeprom_read(np, off + 1);
  5657. if (err < 0)
  5658. return err;
  5659. val |= (err & 0xff);
  5660. return val;
  5661. }
  5662. static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
  5663. {
  5664. int err = niu_pci_eeprom_read(np, off);
  5665. u16 val;
  5666. if (err < 0)
  5667. return err;
  5668. val = (err & 0xff);
  5669. err = niu_pci_eeprom_read(np, off + 1);
  5670. if (err < 0)
  5671. return err;
  5672. val |= (err & 0xff) << 8;
  5673. return val;
  5674. }
  5675. static int __devinit niu_pci_vpd_get_propname(struct niu *np,
  5676. u32 off,
  5677. char *namebuf,
  5678. int namebuf_len)
  5679. {
  5680. int i;
  5681. for (i = 0; i < namebuf_len; i++) {
  5682. int err = niu_pci_eeprom_read(np, off + i);
  5683. if (err < 0)
  5684. return err;
  5685. *namebuf++ = err;
  5686. if (!err)
  5687. break;
  5688. }
  5689. if (i >= namebuf_len)
  5690. return -EINVAL;
  5691. return i + 1;
  5692. }
  5693. static void __devinit niu_vpd_parse_version(struct niu *np)
  5694. {
  5695. struct niu_vpd *vpd = &np->vpd;
  5696. int len = strlen(vpd->version) + 1;
  5697. const char *s = vpd->version;
  5698. int i;
  5699. for (i = 0; i < len - 5; i++) {
  5700. if (!strncmp(s + i, "FCode ", 5))
  5701. break;
  5702. }
  5703. if (i >= len - 5)
  5704. return;
  5705. s += i + 5;
  5706. sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
  5707. niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
  5708. vpd->fcode_major, vpd->fcode_minor);
  5709. if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
  5710. (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
  5711. vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
  5712. np->flags |= NIU_FLAGS_VPD_VALID;
  5713. }
  5714. /* ESPC_PIO_EN_ENABLE must be set */
  5715. static int __devinit niu_pci_vpd_scan_props(struct niu *np,
  5716. u32 start, u32 end)
  5717. {
  5718. unsigned int found_mask = 0;
  5719. #define FOUND_MASK_MODEL 0x00000001
  5720. #define FOUND_MASK_BMODEL 0x00000002
  5721. #define FOUND_MASK_VERS 0x00000004
  5722. #define FOUND_MASK_MAC 0x00000008
  5723. #define FOUND_MASK_NMAC 0x00000010
  5724. #define FOUND_MASK_PHY 0x00000020
  5725. #define FOUND_MASK_ALL 0x0000003f
  5726. niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
  5727. start, end);
  5728. while (start < end) {
  5729. int len, err, instance, type, prop_len;
  5730. char namebuf[64];
  5731. u8 *prop_buf;
  5732. int max_len;
  5733. if (found_mask == FOUND_MASK_ALL) {
  5734. niu_vpd_parse_version(np);
  5735. return 1;
  5736. }
  5737. err = niu_pci_eeprom_read(np, start + 2);
  5738. if (err < 0)
  5739. return err;
  5740. len = err;
  5741. start += 3;
  5742. instance = niu_pci_eeprom_read(np, start);
  5743. type = niu_pci_eeprom_read(np, start + 3);
  5744. prop_len = niu_pci_eeprom_read(np, start + 4);
  5745. err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
  5746. if (err < 0)
  5747. return err;
  5748. prop_buf = NULL;
  5749. max_len = 0;
  5750. if (!strcmp(namebuf, "model")) {
  5751. prop_buf = np->vpd.model;
  5752. max_len = NIU_VPD_MODEL_MAX;
  5753. found_mask |= FOUND_MASK_MODEL;
  5754. } else if (!strcmp(namebuf, "board-model")) {
  5755. prop_buf = np->vpd.board_model;
  5756. max_len = NIU_VPD_BD_MODEL_MAX;
  5757. found_mask |= FOUND_MASK_BMODEL;
  5758. } else if (!strcmp(namebuf, "version")) {
  5759. prop_buf = np->vpd.version;
  5760. max_len = NIU_VPD_VERSION_MAX;
  5761. found_mask |= FOUND_MASK_VERS;
  5762. } else if (!strcmp(namebuf, "local-mac-address")) {
  5763. prop_buf = np->vpd.local_mac;
  5764. max_len = ETH_ALEN;
  5765. found_mask |= FOUND_MASK_MAC;
  5766. } else if (!strcmp(namebuf, "num-mac-addresses")) {
  5767. prop_buf = &np->vpd.mac_num;
  5768. max_len = 1;
  5769. found_mask |= FOUND_MASK_NMAC;
  5770. } else if (!strcmp(namebuf, "phy-type")) {
  5771. prop_buf = np->vpd.phy_type;
  5772. max_len = NIU_VPD_PHY_TYPE_MAX;
  5773. found_mask |= FOUND_MASK_PHY;
  5774. }
  5775. if (max_len && prop_len > max_len) {
  5776. dev_err(np->device, PFX "Property '%s' length (%d) is "
  5777. "too long.\n", namebuf, prop_len);
  5778. return -EINVAL;
  5779. }
  5780. if (prop_buf) {
  5781. u32 off = start + 5 + err;
  5782. int i;
  5783. niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
  5784. "len[%d]\n", namebuf, prop_len);
  5785. for (i = 0; i < prop_len; i++)
  5786. *prop_buf++ = niu_pci_eeprom_read(np, off + i);
  5787. }
  5788. start += len;
  5789. }
  5790. return 0;
  5791. }
  5792. /* ESPC_PIO_EN_ENABLE must be set */
  5793. static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
  5794. {
  5795. u32 offset;
  5796. int err;
  5797. err = niu_pci_eeprom_read16_swp(np, start + 1);
  5798. if (err < 0)
  5799. return;
  5800. offset = err + 3;
  5801. while (start + offset < ESPC_EEPROM_SIZE) {
  5802. u32 here = start + offset;
  5803. u32 end;
  5804. err = niu_pci_eeprom_read(np, here);
  5805. if (err != 0x90)
  5806. return;
  5807. err = niu_pci_eeprom_read16_swp(np, here + 1);
  5808. if (err < 0)
  5809. return;
  5810. here = start + offset + 3;
  5811. end = start + offset + err;
  5812. offset += err;
  5813. err = niu_pci_vpd_scan_props(np, here, end);
  5814. if (err < 0 || err == 1)
  5815. return;
  5816. }
  5817. }
  5818. /* ESPC_PIO_EN_ENABLE must be set */
  5819. static u32 __devinit niu_pci_vpd_offset(struct niu *np)
  5820. {
  5821. u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
  5822. int err;
  5823. while (start < end) {
  5824. ret = start;
  5825. /* ROM header signature? */
  5826. err = niu_pci_eeprom_read16(np, start + 0);
  5827. if (err != 0x55aa)
  5828. return 0;
  5829. /* Apply offset to PCI data structure. */
  5830. err = niu_pci_eeprom_read16(np, start + 23);
  5831. if (err < 0)
  5832. return 0;
  5833. start += err;
  5834. /* Check for "PCIR" signature. */
  5835. err = niu_pci_eeprom_read16(np, start + 0);
  5836. if (err != 0x5043)
  5837. return 0;
  5838. err = niu_pci_eeprom_read16(np, start + 2);
  5839. if (err != 0x4952)
  5840. return 0;
  5841. /* Check for OBP image type. */
  5842. err = niu_pci_eeprom_read(np, start + 20);
  5843. if (err < 0)
  5844. return 0;
  5845. if (err != 0x01) {
  5846. err = niu_pci_eeprom_read(np, ret + 2);
  5847. if (err < 0)
  5848. return 0;
  5849. start = ret + (err * 512);
  5850. continue;
  5851. }
  5852. err = niu_pci_eeprom_read16_swp(np, start + 8);
  5853. if (err < 0)
  5854. return err;
  5855. ret += err;
  5856. err = niu_pci_eeprom_read(np, ret + 0);
  5857. if (err != 0x82)
  5858. return 0;
  5859. return ret;
  5860. }
  5861. return 0;
  5862. }
  5863. static int __devinit niu_phy_type_prop_decode(struct niu *np,
  5864. const char *phy_prop)
  5865. {
  5866. if (!strcmp(phy_prop, "mif")) {
  5867. /* 1G copper, MII */
  5868. np->flags &= ~(NIU_FLAGS_FIBER |
  5869. NIU_FLAGS_10G);
  5870. np->mac_xcvr = MAC_XCVR_MII;
  5871. } else if (!strcmp(phy_prop, "xgf")) {
  5872. /* 10G fiber, XPCS */
  5873. np->flags |= (NIU_FLAGS_10G |
  5874. NIU_FLAGS_FIBER);
  5875. np->mac_xcvr = MAC_XCVR_XPCS;
  5876. } else if (!strcmp(phy_prop, "pcs")) {
  5877. /* 1G fiber, PCS */
  5878. np->flags &= ~NIU_FLAGS_10G;
  5879. np->flags |= NIU_FLAGS_FIBER;
  5880. np->mac_xcvr = MAC_XCVR_PCS;
  5881. } else if (!strcmp(phy_prop, "xgc")) {
  5882. /* 10G copper, XPCS */
  5883. np->flags |= NIU_FLAGS_10G;
  5884. np->flags &= ~NIU_FLAGS_FIBER;
  5885. np->mac_xcvr = MAC_XCVR_XPCS;
  5886. } else {
  5887. return -EINVAL;
  5888. }
  5889. return 0;
  5890. }
  5891. static int niu_pci_vpd_get_nports(struct niu *np)
  5892. {
  5893. int ports = 0;
  5894. if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
  5895. (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
  5896. (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
  5897. (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
  5898. (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
  5899. ports = 4;
  5900. } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
  5901. (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
  5902. (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
  5903. (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
  5904. ports = 2;
  5905. }
  5906. return ports;
  5907. }
  5908. static void __devinit niu_pci_vpd_validate(struct niu *np)
  5909. {
  5910. struct net_device *dev = np->dev;
  5911. struct niu_vpd *vpd = &np->vpd;
  5912. u8 val8;
  5913. if (!is_valid_ether_addr(&vpd->local_mac[0])) {
  5914. dev_err(np->device, PFX "VPD MAC invalid, "
  5915. "falling back to SPROM.\n");
  5916. np->flags &= ~NIU_FLAGS_VPD_VALID;
  5917. return;
  5918. }
  5919. if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
  5920. !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
  5921. np->flags |= NIU_FLAGS_10G;
  5922. np->flags &= ~NIU_FLAGS_FIBER;
  5923. np->flags |= NIU_FLAGS_XCVR_SERDES;
  5924. np->mac_xcvr = MAC_XCVR_PCS;
  5925. if (np->port > 1) {
  5926. np->flags |= NIU_FLAGS_FIBER;
  5927. np->flags &= ~NIU_FLAGS_10G;
  5928. }
  5929. if (np->flags & NIU_FLAGS_10G)
  5930. np->mac_xcvr = MAC_XCVR_XPCS;
  5931. } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
  5932. np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
  5933. NIU_FLAGS_HOTPLUG_PHY);
  5934. } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
  5935. dev_err(np->device, PFX "Illegal phy string [%s].\n",
  5936. np->vpd.phy_type);
  5937. dev_err(np->device, PFX "Falling back to SPROM.\n");
  5938. np->flags &= ~NIU_FLAGS_VPD_VALID;
  5939. return;
  5940. }
  5941. memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
  5942. val8 = dev->perm_addr[5];
  5943. dev->perm_addr[5] += np->port;
  5944. if (dev->perm_addr[5] < val8)
  5945. dev->perm_addr[4]++;
  5946. memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
  5947. }
  5948. static int __devinit niu_pci_probe_sprom(struct niu *np)
  5949. {
  5950. struct net_device *dev = np->dev;
  5951. int len, i;
  5952. u64 val, sum;
  5953. u8 val8;
  5954. val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
  5955. val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
  5956. len = val / 4;
  5957. np->eeprom_len = len;
  5958. niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
  5959. sum = 0;
  5960. for (i = 0; i < len; i++) {
  5961. val = nr64(ESPC_NCR(i));
  5962. sum += (val >> 0) & 0xff;
  5963. sum += (val >> 8) & 0xff;
  5964. sum += (val >> 16) & 0xff;
  5965. sum += (val >> 24) & 0xff;
  5966. }
  5967. niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
  5968. if ((sum & 0xff) != 0xab) {
  5969. dev_err(np->device, PFX "Bad SPROM checksum "
  5970. "(%x, should be 0xab)\n", (int) (sum & 0xff));
  5971. return -EINVAL;
  5972. }
  5973. val = nr64(ESPC_PHY_TYPE);
  5974. switch (np->port) {
  5975. case 0:
  5976. val8 = (val & ESPC_PHY_TYPE_PORT0) >>
  5977. ESPC_PHY_TYPE_PORT0_SHIFT;
  5978. break;
  5979. case 1:
  5980. val8 = (val & ESPC_PHY_TYPE_PORT1) >>
  5981. ESPC_PHY_TYPE_PORT1_SHIFT;
  5982. break;
  5983. case 2:
  5984. val8 = (val & ESPC_PHY_TYPE_PORT2) >>
  5985. ESPC_PHY_TYPE_PORT2_SHIFT;
  5986. break;
  5987. case 3:
  5988. val8 = (val & ESPC_PHY_TYPE_PORT3) >>
  5989. ESPC_PHY_TYPE_PORT3_SHIFT;
  5990. break;
  5991. default:
  5992. dev_err(np->device, PFX "Bogus port number %u\n",
  5993. np->port);
  5994. return -EINVAL;
  5995. }
  5996. niudbg(PROBE, "SPROM: PHY type %x\n", val8);
  5997. switch (val8) {
  5998. case ESPC_PHY_TYPE_1G_COPPER:
  5999. /* 1G copper, MII */
  6000. np->flags &= ~(NIU_FLAGS_FIBER |
  6001. NIU_FLAGS_10G);
  6002. np->mac_xcvr = MAC_XCVR_MII;
  6003. break;
  6004. case ESPC_PHY_TYPE_1G_FIBER:
  6005. /* 1G fiber, PCS */
  6006. np->flags &= ~NIU_FLAGS_10G;
  6007. np->flags |= NIU_FLAGS_FIBER;
  6008. np->mac_xcvr = MAC_XCVR_PCS;
  6009. break;
  6010. case ESPC_PHY_TYPE_10G_COPPER:
  6011. /* 10G copper, XPCS */
  6012. np->flags |= NIU_FLAGS_10G;
  6013. np->flags &= ~NIU_FLAGS_FIBER;
  6014. np->mac_xcvr = MAC_XCVR_XPCS;
  6015. break;
  6016. case ESPC_PHY_TYPE_10G_FIBER:
  6017. /* 10G fiber, XPCS */
  6018. np->flags |= (NIU_FLAGS_10G |
  6019. NIU_FLAGS_FIBER);
  6020. np->mac_xcvr = MAC_XCVR_XPCS;
  6021. break;
  6022. default:
  6023. dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
  6024. return -EINVAL;
  6025. }
  6026. val = nr64(ESPC_MAC_ADDR0);
  6027. niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
  6028. (unsigned long long) val);
  6029. dev->perm_addr[0] = (val >> 0) & 0xff;
  6030. dev->perm_addr[1] = (val >> 8) & 0xff;
  6031. dev->perm_addr[2] = (val >> 16) & 0xff;
  6032. dev->perm_addr[3] = (val >> 24) & 0xff;
  6033. val = nr64(ESPC_MAC_ADDR1);
  6034. niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
  6035. (unsigned long long) val);
  6036. dev->perm_addr[4] = (val >> 0) & 0xff;
  6037. dev->perm_addr[5] = (val >> 8) & 0xff;
  6038. if (!is_valid_ether_addr(&dev->perm_addr[0])) {
  6039. dev_err(np->device, PFX "SPROM MAC address invalid\n");
  6040. dev_err(np->device, PFX "[ \n");
  6041. for (i = 0; i < 6; i++)
  6042. printk("%02x ", dev->perm_addr[i]);
  6043. printk("]\n");
  6044. return -EINVAL;
  6045. }
  6046. val8 = dev->perm_addr[5];
  6047. dev->perm_addr[5] += np->port;
  6048. if (dev->perm_addr[5] < val8)
  6049. dev->perm_addr[4]++;
  6050. memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
  6051. val = nr64(ESPC_MOD_STR_LEN);
  6052. niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
  6053. (unsigned long long) val);
  6054. if (val >= 8 * 4)
  6055. return -EINVAL;
  6056. for (i = 0; i < val; i += 4) {
  6057. u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
  6058. np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
  6059. np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
  6060. np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
  6061. np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
  6062. }
  6063. np->vpd.model[val] = '\0';
  6064. val = nr64(ESPC_BD_MOD_STR_LEN);
  6065. niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
  6066. (unsigned long long) val);
  6067. if (val >= 4 * 4)
  6068. return -EINVAL;
  6069. for (i = 0; i < val; i += 4) {
  6070. u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
  6071. np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
  6072. np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
  6073. np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
  6074. np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
  6075. }
  6076. np->vpd.board_model[val] = '\0';
  6077. np->vpd.mac_num =
  6078. nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
  6079. niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
  6080. np->vpd.mac_num);
  6081. return 0;
  6082. }
  6083. static int __devinit niu_get_and_validate_port(struct niu *np)
  6084. {
  6085. struct niu_parent *parent = np->parent;
  6086. if (np->port <= 1)
  6087. np->flags |= NIU_FLAGS_XMAC;
  6088. if (!parent->num_ports) {
  6089. if (parent->plat_type == PLAT_TYPE_NIU) {
  6090. parent->num_ports = 2;
  6091. } else {
  6092. parent->num_ports = niu_pci_vpd_get_nports(np);
  6093. if (!parent->num_ports) {
  6094. /* Fall back to SPROM as last resort.
  6095. * This will fail on most cards.
  6096. */
  6097. parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
  6098. ESPC_NUM_PORTS_MACS_VAL;
  6099. /* All of the current probing methods fail on
  6100. * Maramba on-board parts.
  6101. */
  6102. if (!parent->num_ports)
  6103. parent->num_ports = 4;
  6104. }
  6105. }
  6106. }
  6107. niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
  6108. np->port, parent->num_ports);
  6109. if (np->port >= parent->num_ports)
  6110. return -ENODEV;
  6111. return 0;
  6112. }
  6113. static int __devinit phy_record(struct niu_parent *parent,
  6114. struct phy_probe_info *p,
  6115. int dev_id_1, int dev_id_2, u8 phy_port,
  6116. int type)
  6117. {
  6118. u32 id = (dev_id_1 << 16) | dev_id_2;
  6119. u8 idx;
  6120. if (dev_id_1 < 0 || dev_id_2 < 0)
  6121. return 0;
  6122. if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
  6123. if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
  6124. ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
  6125. ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
  6126. return 0;
  6127. } else {
  6128. if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
  6129. return 0;
  6130. }
  6131. pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
  6132. parent->index, id,
  6133. (type == PHY_TYPE_PMA_PMD ?
  6134. "PMA/PMD" :
  6135. (type == PHY_TYPE_PCS ?
  6136. "PCS" : "MII")),
  6137. phy_port);
  6138. if (p->cur[type] >= NIU_MAX_PORTS) {
  6139. printk(KERN_ERR PFX "Too many PHY ports.\n");
  6140. return -EINVAL;
  6141. }
  6142. idx = p->cur[type];
  6143. p->phy_id[type][idx] = id;
  6144. p->phy_port[type][idx] = phy_port;
  6145. p->cur[type] = idx + 1;
  6146. return 0;
  6147. }
  6148. static int __devinit port_has_10g(struct phy_probe_info *p, int port)
  6149. {
  6150. int i;
  6151. for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
  6152. if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
  6153. return 1;
  6154. }
  6155. for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
  6156. if (p->phy_port[PHY_TYPE_PCS][i] == port)
  6157. return 1;
  6158. }
  6159. return 0;
  6160. }
  6161. static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
  6162. {
  6163. int port, cnt;
  6164. cnt = 0;
  6165. *lowest = 32;
  6166. for (port = 8; port < 32; port++) {
  6167. if (port_has_10g(p, port)) {
  6168. if (!cnt)
  6169. *lowest = port;
  6170. cnt++;
  6171. }
  6172. }
  6173. return cnt;
  6174. }
  6175. static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
  6176. {
  6177. *lowest = 32;
  6178. if (p->cur[PHY_TYPE_MII])
  6179. *lowest = p->phy_port[PHY_TYPE_MII][0];
  6180. return p->cur[PHY_TYPE_MII];
  6181. }
  6182. static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
  6183. {
  6184. int num_ports = parent->num_ports;
  6185. int i;
  6186. for (i = 0; i < num_ports; i++) {
  6187. parent->rxchan_per_port[i] = (16 / num_ports);
  6188. parent->txchan_per_port[i] = (16 / num_ports);
  6189. pr_info(PFX "niu%d: Port %u [%u RX chans] "
  6190. "[%u TX chans]\n",
  6191. parent->index, i,
  6192. parent->rxchan_per_port[i],
  6193. parent->txchan_per_port[i]);
  6194. }
  6195. }
  6196. static void __devinit niu_divide_channels(struct niu_parent *parent,
  6197. int num_10g, int num_1g)
  6198. {
  6199. int num_ports = parent->num_ports;
  6200. int rx_chans_per_10g, rx_chans_per_1g;
  6201. int tx_chans_per_10g, tx_chans_per_1g;
  6202. int i, tot_rx, tot_tx;
  6203. if (!num_10g || !num_1g) {
  6204. rx_chans_per_10g = rx_chans_per_1g =
  6205. (NIU_NUM_RXCHAN / num_ports);
  6206. tx_chans_per_10g = tx_chans_per_1g =
  6207. (NIU_NUM_TXCHAN / num_ports);
  6208. } else {
  6209. rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
  6210. rx_chans_per_10g = (NIU_NUM_RXCHAN -
  6211. (rx_chans_per_1g * num_1g)) /
  6212. num_10g;
  6213. tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
  6214. tx_chans_per_10g = (NIU_NUM_TXCHAN -
  6215. (tx_chans_per_1g * num_1g)) /
  6216. num_10g;
  6217. }
  6218. tot_rx = tot_tx = 0;
  6219. for (i = 0; i < num_ports; i++) {
  6220. int type = phy_decode(parent->port_phy, i);
  6221. if (type == PORT_TYPE_10G) {
  6222. parent->rxchan_per_port[i] = rx_chans_per_10g;
  6223. parent->txchan_per_port[i] = tx_chans_per_10g;
  6224. } else {
  6225. parent->rxchan_per_port[i] = rx_chans_per_1g;
  6226. parent->txchan_per_port[i] = tx_chans_per_1g;
  6227. }
  6228. pr_info(PFX "niu%d: Port %u [%u RX chans] "
  6229. "[%u TX chans]\n",
  6230. parent->index, i,
  6231. parent->rxchan_per_port[i],
  6232. parent->txchan_per_port[i]);
  6233. tot_rx += parent->rxchan_per_port[i];
  6234. tot_tx += parent->txchan_per_port[i];
  6235. }
  6236. if (tot_rx > NIU_NUM_RXCHAN) {
  6237. printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
  6238. "resetting to one per port.\n",
  6239. parent->index, tot_rx);
  6240. for (i = 0; i < num_ports; i++)
  6241. parent->rxchan_per_port[i] = 1;
  6242. }
  6243. if (tot_tx > NIU_NUM_TXCHAN) {
  6244. printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
  6245. "resetting to one per port.\n",
  6246. parent->index, tot_tx);
  6247. for (i = 0; i < num_ports; i++)
  6248. parent->txchan_per_port[i] = 1;
  6249. }
  6250. if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
  6251. printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
  6252. "RX[%d] TX[%d]\n",
  6253. parent->index, tot_rx, tot_tx);
  6254. }
  6255. }
  6256. static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
  6257. int num_10g, int num_1g)
  6258. {
  6259. int i, num_ports = parent->num_ports;
  6260. int rdc_group, rdc_groups_per_port;
  6261. int rdc_channel_base;
  6262. rdc_group = 0;
  6263. rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
  6264. rdc_channel_base = 0;
  6265. for (i = 0; i < num_ports; i++) {
  6266. struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
  6267. int grp, num_channels = parent->rxchan_per_port[i];
  6268. int this_channel_offset;
  6269. tp->first_table_num = rdc_group;
  6270. tp->num_tables = rdc_groups_per_port;
  6271. this_channel_offset = 0;
  6272. for (grp = 0; grp < tp->num_tables; grp++) {
  6273. struct rdc_table *rt = &tp->tables[grp];
  6274. int slot;
  6275. pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
  6276. parent->index, i, tp->first_table_num + grp);
  6277. for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
  6278. rt->rxdma_channel[slot] =
  6279. rdc_channel_base + this_channel_offset;
  6280. printk("%d ", rt->rxdma_channel[slot]);
  6281. if (++this_channel_offset == num_channels)
  6282. this_channel_offset = 0;
  6283. }
  6284. printk("]\n");
  6285. }
  6286. parent->rdc_default[i] = rdc_channel_base;
  6287. rdc_channel_base += num_channels;
  6288. rdc_group += rdc_groups_per_port;
  6289. }
  6290. }
  6291. static int __devinit fill_phy_probe_info(struct niu *np,
  6292. struct niu_parent *parent,
  6293. struct phy_probe_info *info)
  6294. {
  6295. unsigned long flags;
  6296. int port, err;
  6297. memset(info, 0, sizeof(*info));
  6298. /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
  6299. niu_lock_parent(np, flags);
  6300. err = 0;
  6301. for (port = 8; port < 32; port++) {
  6302. int dev_id_1, dev_id_2;
  6303. dev_id_1 = mdio_read(np, port,
  6304. NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
  6305. dev_id_2 = mdio_read(np, port,
  6306. NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
  6307. err = phy_record(parent, info, dev_id_1, dev_id_2, port,
  6308. PHY_TYPE_PMA_PMD);
  6309. if (err)
  6310. break;
  6311. dev_id_1 = mdio_read(np, port,
  6312. NIU_PCS_DEV_ADDR, MII_PHYSID1);
  6313. dev_id_2 = mdio_read(np, port,
  6314. NIU_PCS_DEV_ADDR, MII_PHYSID2);
  6315. err = phy_record(parent, info, dev_id_1, dev_id_2, port,
  6316. PHY_TYPE_PCS);
  6317. if (err)
  6318. break;
  6319. dev_id_1 = mii_read(np, port, MII_PHYSID1);
  6320. dev_id_2 = mii_read(np, port, MII_PHYSID2);
  6321. err = phy_record(parent, info, dev_id_1, dev_id_2, port,
  6322. PHY_TYPE_MII);
  6323. if (err)
  6324. break;
  6325. }
  6326. niu_unlock_parent(np, flags);
  6327. return err;
  6328. }
  6329. static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
  6330. {
  6331. struct phy_probe_info *info = &parent->phy_probe_info;
  6332. int lowest_10g, lowest_1g;
  6333. int num_10g, num_1g;
  6334. u32 val;
  6335. int err;
  6336. if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
  6337. !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
  6338. num_10g = 0;
  6339. num_1g = 2;
  6340. parent->plat_type = PLAT_TYPE_ATCA_CP3220;
  6341. parent->num_ports = 4;
  6342. val = (phy_encode(PORT_TYPE_1G, 0) |
  6343. phy_encode(PORT_TYPE_1G, 1) |
  6344. phy_encode(PORT_TYPE_1G, 2) |
  6345. phy_encode(PORT_TYPE_1G, 3));
  6346. } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
  6347. num_10g = 2;
  6348. num_1g = 0;
  6349. parent->num_ports = 2;
  6350. val = (phy_encode(PORT_TYPE_10G, 0) |
  6351. phy_encode(PORT_TYPE_10G, 1));
  6352. } else {
  6353. err = fill_phy_probe_info(np, parent, info);
  6354. if (err)
  6355. return err;
  6356. num_10g = count_10g_ports(info, &lowest_10g);
  6357. num_1g = count_1g_ports(info, &lowest_1g);
  6358. switch ((num_10g << 4) | num_1g) {
  6359. case 0x24:
  6360. if (lowest_1g == 10)
  6361. parent->plat_type = PLAT_TYPE_VF_P0;
  6362. else if (lowest_1g == 26)
  6363. parent->plat_type = PLAT_TYPE_VF_P1;
  6364. else
  6365. goto unknown_vg_1g_port;
  6366. /* fallthru */
  6367. case 0x22:
  6368. val = (phy_encode(PORT_TYPE_10G, 0) |
  6369. phy_encode(PORT_TYPE_10G, 1) |
  6370. phy_encode(PORT_TYPE_1G, 2) |
  6371. phy_encode(PORT_TYPE_1G, 3));
  6372. break;
  6373. case 0x20:
  6374. val = (phy_encode(PORT_TYPE_10G, 0) |
  6375. phy_encode(PORT_TYPE_10G, 1));
  6376. break;
  6377. case 0x10:
  6378. val = phy_encode(PORT_TYPE_10G, np->port);
  6379. break;
  6380. case 0x14:
  6381. if (lowest_1g == 10)
  6382. parent->plat_type = PLAT_TYPE_VF_P0;
  6383. else if (lowest_1g == 26)
  6384. parent->plat_type = PLAT_TYPE_VF_P1;
  6385. else
  6386. goto unknown_vg_1g_port;
  6387. /* fallthru */
  6388. case 0x13:
  6389. if ((lowest_10g & 0x7) == 0)
  6390. val = (phy_encode(PORT_TYPE_10G, 0) |
  6391. phy_encode(PORT_TYPE_1G, 1) |
  6392. phy_encode(PORT_TYPE_1G, 2) |
  6393. phy_encode(PORT_TYPE_1G, 3));
  6394. else
  6395. val = (phy_encode(PORT_TYPE_1G, 0) |
  6396. phy_encode(PORT_TYPE_10G, 1) |
  6397. phy_encode(PORT_TYPE_1G, 2) |
  6398. phy_encode(PORT_TYPE_1G, 3));
  6399. break;
  6400. case 0x04:
  6401. if (lowest_1g == 10)
  6402. parent->plat_type = PLAT_TYPE_VF_P0;
  6403. else if (lowest_1g == 26)
  6404. parent->plat_type = PLAT_TYPE_VF_P1;
  6405. else
  6406. goto unknown_vg_1g_port;
  6407. val = (phy_encode(PORT_TYPE_1G, 0) |
  6408. phy_encode(PORT_TYPE_1G, 1) |
  6409. phy_encode(PORT_TYPE_1G, 2) |
  6410. phy_encode(PORT_TYPE_1G, 3));
  6411. break;
  6412. default:
  6413. printk(KERN_ERR PFX "Unsupported port config "
  6414. "10G[%d] 1G[%d]\n",
  6415. num_10g, num_1g);
  6416. return -EINVAL;
  6417. }
  6418. }
  6419. parent->port_phy = val;
  6420. if (parent->plat_type == PLAT_TYPE_NIU)
  6421. niu_n2_divide_channels(parent);
  6422. else
  6423. niu_divide_channels(parent, num_10g, num_1g);
  6424. niu_divide_rdc_groups(parent, num_10g, num_1g);
  6425. return 0;
  6426. unknown_vg_1g_port:
  6427. printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
  6428. lowest_1g);
  6429. return -EINVAL;
  6430. }
  6431. static int __devinit niu_probe_ports(struct niu *np)
  6432. {
  6433. struct niu_parent *parent = np->parent;
  6434. int err, i;
  6435. niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
  6436. parent->port_phy);
  6437. if (parent->port_phy == PORT_PHY_UNKNOWN) {
  6438. err = walk_phys(np, parent);
  6439. if (err)
  6440. return err;
  6441. niu_set_ldg_timer_res(np, 2);
  6442. for (i = 0; i <= LDN_MAX; i++)
  6443. niu_ldn_irq_enable(np, i, 0);
  6444. }
  6445. if (parent->port_phy == PORT_PHY_INVALID)
  6446. return -EINVAL;
  6447. return 0;
  6448. }
  6449. static int __devinit niu_classifier_swstate_init(struct niu *np)
  6450. {
  6451. struct niu_classifier *cp = &np->clas;
  6452. niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
  6453. np->parent->tcam_num_entries);
  6454. cp->tcam_index = (u16) np->port;
  6455. cp->h1_init = 0xffffffff;
  6456. cp->h2_init = 0xffff;
  6457. return fflp_early_init(np);
  6458. }
  6459. static void __devinit niu_link_config_init(struct niu *np)
  6460. {
  6461. struct niu_link_config *lp = &np->link_config;
  6462. lp->advertising = (ADVERTISED_10baseT_Half |
  6463. ADVERTISED_10baseT_Full |
  6464. ADVERTISED_100baseT_Half |
  6465. ADVERTISED_100baseT_Full |
  6466. ADVERTISED_1000baseT_Half |
  6467. ADVERTISED_1000baseT_Full |
  6468. ADVERTISED_10000baseT_Full |
  6469. ADVERTISED_Autoneg);
  6470. lp->speed = lp->active_speed = SPEED_INVALID;
  6471. lp->duplex = lp->active_duplex = DUPLEX_INVALID;
  6472. #if 0
  6473. lp->loopback_mode = LOOPBACK_MAC;
  6474. lp->active_speed = SPEED_10000;
  6475. lp->active_duplex = DUPLEX_FULL;
  6476. #else
  6477. lp->loopback_mode = LOOPBACK_DISABLED;
  6478. #endif
  6479. }
  6480. static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
  6481. {
  6482. switch (np->port) {
  6483. case 0:
  6484. np->mac_regs = np->regs + XMAC_PORT0_OFF;
  6485. np->ipp_off = 0x00000;
  6486. np->pcs_off = 0x04000;
  6487. np->xpcs_off = 0x02000;
  6488. break;
  6489. case 1:
  6490. np->mac_regs = np->regs + XMAC_PORT1_OFF;
  6491. np->ipp_off = 0x08000;
  6492. np->pcs_off = 0x0a000;
  6493. np->xpcs_off = 0x08000;
  6494. break;
  6495. case 2:
  6496. np->mac_regs = np->regs + BMAC_PORT2_OFF;
  6497. np->ipp_off = 0x04000;
  6498. np->pcs_off = 0x0e000;
  6499. np->xpcs_off = ~0UL;
  6500. break;
  6501. case 3:
  6502. np->mac_regs = np->regs + BMAC_PORT3_OFF;
  6503. np->ipp_off = 0x0c000;
  6504. np->pcs_off = 0x12000;
  6505. np->xpcs_off = ~0UL;
  6506. break;
  6507. default:
  6508. dev_err(np->device, PFX "Port %u is invalid, cannot "
  6509. "compute MAC block offset.\n", np->port);
  6510. return -EINVAL;
  6511. }
  6512. return 0;
  6513. }
  6514. static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
  6515. {
  6516. struct msix_entry msi_vec[NIU_NUM_LDG];
  6517. struct niu_parent *parent = np->parent;
  6518. struct pci_dev *pdev = np->pdev;
  6519. int i, num_irqs, err;
  6520. u8 first_ldg;
  6521. first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
  6522. for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
  6523. ldg_num_map[i] = first_ldg + i;
  6524. num_irqs = (parent->rxchan_per_port[np->port] +
  6525. parent->txchan_per_port[np->port] +
  6526. (np->port == 0 ? 3 : 1));
  6527. BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
  6528. retry:
  6529. for (i = 0; i < num_irqs; i++) {
  6530. msi_vec[i].vector = 0;
  6531. msi_vec[i].entry = i;
  6532. }
  6533. err = pci_enable_msix(pdev, msi_vec, num_irqs);
  6534. if (err < 0) {
  6535. np->flags &= ~NIU_FLAGS_MSIX;
  6536. return;
  6537. }
  6538. if (err > 0) {
  6539. num_irqs = err;
  6540. goto retry;
  6541. }
  6542. np->flags |= NIU_FLAGS_MSIX;
  6543. for (i = 0; i < num_irqs; i++)
  6544. np->ldg[i].irq = msi_vec[i].vector;
  6545. np->num_ldg = num_irqs;
  6546. }
  6547. static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
  6548. {
  6549. #ifdef CONFIG_SPARC64
  6550. struct of_device *op = np->op;
  6551. const u32 *int_prop;
  6552. int i;
  6553. int_prop = of_get_property(op->node, "interrupts", NULL);
  6554. if (!int_prop)
  6555. return -ENODEV;
  6556. for (i = 0; i < op->num_irqs; i++) {
  6557. ldg_num_map[i] = int_prop[i];
  6558. np->ldg[i].irq = op->irqs[i];
  6559. }
  6560. np->num_ldg = op->num_irqs;
  6561. return 0;
  6562. #else
  6563. return -EINVAL;
  6564. #endif
  6565. }
  6566. static int __devinit niu_ldg_init(struct niu *np)
  6567. {
  6568. struct niu_parent *parent = np->parent;
  6569. u8 ldg_num_map[NIU_NUM_LDG];
  6570. int first_chan, num_chan;
  6571. int i, err, ldg_rotor;
  6572. u8 port;
  6573. np->num_ldg = 1;
  6574. np->ldg[0].irq = np->dev->irq;
  6575. if (parent->plat_type == PLAT_TYPE_NIU) {
  6576. err = niu_n2_irq_init(np, ldg_num_map);
  6577. if (err)
  6578. return err;
  6579. } else
  6580. niu_try_msix(np, ldg_num_map);
  6581. port = np->port;
  6582. for (i = 0; i < np->num_ldg; i++) {
  6583. struct niu_ldg *lp = &np->ldg[i];
  6584. netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
  6585. lp->np = np;
  6586. lp->ldg_num = ldg_num_map[i];
  6587. lp->timer = 2; /* XXX */
  6588. /* On N2 NIU the firmware has setup the SID mappings so they go
  6589. * to the correct values that will route the LDG to the proper
  6590. * interrupt in the NCU interrupt table.
  6591. */
  6592. if (np->parent->plat_type != PLAT_TYPE_NIU) {
  6593. err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
  6594. if (err)
  6595. return err;
  6596. }
  6597. }
  6598. /* We adopt the LDG assignment ordering used by the N2 NIU
  6599. * 'interrupt' properties because that simplifies a lot of
  6600. * things. This ordering is:
  6601. *
  6602. * MAC
  6603. * MIF (if port zero)
  6604. * SYSERR (if port zero)
  6605. * RX channels
  6606. * TX channels
  6607. */
  6608. ldg_rotor = 0;
  6609. err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
  6610. LDN_MAC(port));
  6611. if (err)
  6612. return err;
  6613. ldg_rotor++;
  6614. if (ldg_rotor == np->num_ldg)
  6615. ldg_rotor = 0;
  6616. if (port == 0) {
  6617. err = niu_ldg_assign_ldn(np, parent,
  6618. ldg_num_map[ldg_rotor],
  6619. LDN_MIF);
  6620. if (err)
  6621. return err;
  6622. ldg_rotor++;
  6623. if (ldg_rotor == np->num_ldg)
  6624. ldg_rotor = 0;
  6625. err = niu_ldg_assign_ldn(np, parent,
  6626. ldg_num_map[ldg_rotor],
  6627. LDN_DEVICE_ERROR);
  6628. if (err)
  6629. return err;
  6630. ldg_rotor++;
  6631. if (ldg_rotor == np->num_ldg)
  6632. ldg_rotor = 0;
  6633. }
  6634. first_chan = 0;
  6635. for (i = 0; i < port; i++)
  6636. first_chan += parent->rxchan_per_port[port];
  6637. num_chan = parent->rxchan_per_port[port];
  6638. for (i = first_chan; i < (first_chan + num_chan); i++) {
  6639. err = niu_ldg_assign_ldn(np, parent,
  6640. ldg_num_map[ldg_rotor],
  6641. LDN_RXDMA(i));
  6642. if (err)
  6643. return err;
  6644. ldg_rotor++;
  6645. if (ldg_rotor == np->num_ldg)
  6646. ldg_rotor = 0;
  6647. }
  6648. first_chan = 0;
  6649. for (i = 0; i < port; i++)
  6650. first_chan += parent->txchan_per_port[port];
  6651. num_chan = parent->txchan_per_port[port];
  6652. for (i = first_chan; i < (first_chan + num_chan); i++) {
  6653. err = niu_ldg_assign_ldn(np, parent,
  6654. ldg_num_map[ldg_rotor],
  6655. LDN_TXDMA(i));
  6656. if (err)
  6657. return err;
  6658. ldg_rotor++;
  6659. if (ldg_rotor == np->num_ldg)
  6660. ldg_rotor = 0;
  6661. }
  6662. return 0;
  6663. }
  6664. static void __devexit niu_ldg_free(struct niu *np)
  6665. {
  6666. if (np->flags & NIU_FLAGS_MSIX)
  6667. pci_disable_msix(np->pdev);
  6668. }
  6669. static int __devinit niu_get_of_props(struct niu *np)
  6670. {
  6671. #ifdef CONFIG_SPARC64
  6672. struct net_device *dev = np->dev;
  6673. struct device_node *dp;
  6674. const char *phy_type;
  6675. const u8 *mac_addr;
  6676. const char *model;
  6677. int prop_len;
  6678. if (np->parent->plat_type == PLAT_TYPE_NIU)
  6679. dp = np->op->node;
  6680. else
  6681. dp = pci_device_to_OF_node(np->pdev);
  6682. phy_type = of_get_property(dp, "phy-type", &prop_len);
  6683. if (!phy_type) {
  6684. dev_err(np->device, PFX "%s: OF node lacks "
  6685. "phy-type property\n",
  6686. dp->full_name);
  6687. return -EINVAL;
  6688. }
  6689. if (!strcmp(phy_type, "none"))
  6690. return -ENODEV;
  6691. strcpy(np->vpd.phy_type, phy_type);
  6692. if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
  6693. dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
  6694. dp->full_name, np->vpd.phy_type);
  6695. return -EINVAL;
  6696. }
  6697. mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
  6698. if (!mac_addr) {
  6699. dev_err(np->device, PFX "%s: OF node lacks "
  6700. "local-mac-address property\n",
  6701. dp->full_name);
  6702. return -EINVAL;
  6703. }
  6704. if (prop_len != dev->addr_len) {
  6705. dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
  6706. "is wrong.\n",
  6707. dp->full_name, prop_len);
  6708. }
  6709. memcpy(dev->perm_addr, mac_addr, dev->addr_len);
  6710. if (!is_valid_ether_addr(&dev->perm_addr[0])) {
  6711. int i;
  6712. dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
  6713. dp->full_name);
  6714. dev_err(np->device, PFX "%s: [ \n",
  6715. dp->full_name);
  6716. for (i = 0; i < 6; i++)
  6717. printk("%02x ", dev->perm_addr[i]);
  6718. printk("]\n");
  6719. return -EINVAL;
  6720. }
  6721. memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
  6722. model = of_get_property(dp, "model", &prop_len);
  6723. if (model)
  6724. strcpy(np->vpd.model, model);
  6725. return 0;
  6726. #else
  6727. return -EINVAL;
  6728. #endif
  6729. }
  6730. static int __devinit niu_get_invariants(struct niu *np)
  6731. {
  6732. int err, have_props;
  6733. u32 offset;
  6734. err = niu_get_of_props(np);
  6735. if (err == -ENODEV)
  6736. return err;
  6737. have_props = !err;
  6738. err = niu_init_mac_ipp_pcs_base(np);
  6739. if (err)
  6740. return err;
  6741. if (have_props) {
  6742. err = niu_get_and_validate_port(np);
  6743. if (err)
  6744. return err;
  6745. } else {
  6746. if (np->parent->plat_type == PLAT_TYPE_NIU)
  6747. return -EINVAL;
  6748. nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
  6749. offset = niu_pci_vpd_offset(np);
  6750. niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
  6751. offset);
  6752. if (offset)
  6753. niu_pci_vpd_fetch(np, offset);
  6754. nw64(ESPC_PIO_EN, 0);
  6755. if (np->flags & NIU_FLAGS_VPD_VALID) {
  6756. niu_pci_vpd_validate(np);
  6757. err = niu_get_and_validate_port(np);
  6758. if (err)
  6759. return err;
  6760. }
  6761. if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
  6762. err = niu_get_and_validate_port(np);
  6763. if (err)
  6764. return err;
  6765. err = niu_pci_probe_sprom(np);
  6766. if (err)
  6767. return err;
  6768. }
  6769. }
  6770. err = niu_probe_ports(np);
  6771. if (err)
  6772. return err;
  6773. niu_ldg_init(np);
  6774. niu_classifier_swstate_init(np);
  6775. niu_link_config_init(np);
  6776. err = niu_determine_phy_disposition(np);
  6777. if (!err)
  6778. err = niu_init_link(np);
  6779. return err;
  6780. }
  6781. static LIST_HEAD(niu_parent_list);
  6782. static DEFINE_MUTEX(niu_parent_lock);
  6783. static int niu_parent_index;
  6784. static ssize_t show_port_phy(struct device *dev,
  6785. struct device_attribute *attr, char *buf)
  6786. {
  6787. struct platform_device *plat_dev = to_platform_device(dev);
  6788. struct niu_parent *p = plat_dev->dev.platform_data;
  6789. u32 port_phy = p->port_phy;
  6790. char *orig_buf = buf;
  6791. int i;
  6792. if (port_phy == PORT_PHY_UNKNOWN ||
  6793. port_phy == PORT_PHY_INVALID)
  6794. return 0;
  6795. for (i = 0; i < p->num_ports; i++) {
  6796. const char *type_str;
  6797. int type;
  6798. type = phy_decode(port_phy, i);
  6799. if (type == PORT_TYPE_10G)
  6800. type_str = "10G";
  6801. else
  6802. type_str = "1G";
  6803. buf += sprintf(buf,
  6804. (i == 0) ? "%s" : " %s",
  6805. type_str);
  6806. }
  6807. buf += sprintf(buf, "\n");
  6808. return buf - orig_buf;
  6809. }
  6810. static ssize_t show_plat_type(struct device *dev,
  6811. struct device_attribute *attr, char *buf)
  6812. {
  6813. struct platform_device *plat_dev = to_platform_device(dev);
  6814. struct niu_parent *p = plat_dev->dev.platform_data;
  6815. const char *type_str;
  6816. switch (p->plat_type) {
  6817. case PLAT_TYPE_ATLAS:
  6818. type_str = "atlas";
  6819. break;
  6820. case PLAT_TYPE_NIU:
  6821. type_str = "niu";
  6822. break;
  6823. case PLAT_TYPE_VF_P0:
  6824. type_str = "vf_p0";
  6825. break;
  6826. case PLAT_TYPE_VF_P1:
  6827. type_str = "vf_p1";
  6828. break;
  6829. default:
  6830. type_str = "unknown";
  6831. break;
  6832. }
  6833. return sprintf(buf, "%s\n", type_str);
  6834. }
  6835. static ssize_t __show_chan_per_port(struct device *dev,
  6836. struct device_attribute *attr, char *buf,
  6837. int rx)
  6838. {
  6839. struct platform_device *plat_dev = to_platform_device(dev);
  6840. struct niu_parent *p = plat_dev->dev.platform_data;
  6841. char *orig_buf = buf;
  6842. u8 *arr;
  6843. int i;
  6844. arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
  6845. for (i = 0; i < p->num_ports; i++) {
  6846. buf += sprintf(buf,
  6847. (i == 0) ? "%d" : " %d",
  6848. arr[i]);
  6849. }
  6850. buf += sprintf(buf, "\n");
  6851. return buf - orig_buf;
  6852. }
  6853. static ssize_t show_rxchan_per_port(struct device *dev,
  6854. struct device_attribute *attr, char *buf)
  6855. {
  6856. return __show_chan_per_port(dev, attr, buf, 1);
  6857. }
  6858. static ssize_t show_txchan_per_port(struct device *dev,
  6859. struct device_attribute *attr, char *buf)
  6860. {
  6861. return __show_chan_per_port(dev, attr, buf, 1);
  6862. }
  6863. static ssize_t show_num_ports(struct device *dev,
  6864. struct device_attribute *attr, char *buf)
  6865. {
  6866. struct platform_device *plat_dev = to_platform_device(dev);
  6867. struct niu_parent *p = plat_dev->dev.platform_data;
  6868. return sprintf(buf, "%d\n", p->num_ports);
  6869. }
  6870. static struct device_attribute niu_parent_attributes[] = {
  6871. __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
  6872. __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
  6873. __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
  6874. __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
  6875. __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
  6876. {}
  6877. };
  6878. static struct niu_parent * __devinit niu_new_parent(struct niu *np,
  6879. union niu_parent_id *id,
  6880. u8 ptype)
  6881. {
  6882. struct platform_device *plat_dev;
  6883. struct niu_parent *p;
  6884. int i;
  6885. niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
  6886. plat_dev = platform_device_register_simple("niu", niu_parent_index,
  6887. NULL, 0);
  6888. if (!plat_dev)
  6889. return NULL;
  6890. for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
  6891. int err = device_create_file(&plat_dev->dev,
  6892. &niu_parent_attributes[i]);
  6893. if (err)
  6894. goto fail_unregister;
  6895. }
  6896. p = kzalloc(sizeof(*p), GFP_KERNEL);
  6897. if (!p)
  6898. goto fail_unregister;
  6899. p->index = niu_parent_index++;
  6900. plat_dev->dev.platform_data = p;
  6901. p->plat_dev = plat_dev;
  6902. memcpy(&p->id, id, sizeof(*id));
  6903. p->plat_type = ptype;
  6904. INIT_LIST_HEAD(&p->list);
  6905. atomic_set(&p->refcnt, 0);
  6906. list_add(&p->list, &niu_parent_list);
  6907. spin_lock_init(&p->lock);
  6908. p->rxdma_clock_divider = 7500;
  6909. p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
  6910. if (p->plat_type == PLAT_TYPE_NIU)
  6911. p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
  6912. for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
  6913. int index = i - CLASS_CODE_USER_PROG1;
  6914. p->tcam_key[index] = TCAM_KEY_TSEL;
  6915. p->flow_key[index] = (FLOW_KEY_IPSA |
  6916. FLOW_KEY_IPDA |
  6917. FLOW_KEY_PROTO |
  6918. (FLOW_KEY_L4_BYTE12 <<
  6919. FLOW_KEY_L4_0_SHIFT) |
  6920. (FLOW_KEY_L4_BYTE12 <<
  6921. FLOW_KEY_L4_1_SHIFT));
  6922. }
  6923. for (i = 0; i < LDN_MAX + 1; i++)
  6924. p->ldg_map[i] = LDG_INVALID;
  6925. return p;
  6926. fail_unregister:
  6927. platform_device_unregister(plat_dev);
  6928. return NULL;
  6929. }
  6930. static struct niu_parent * __devinit niu_get_parent(struct niu *np,
  6931. union niu_parent_id *id,
  6932. u8 ptype)
  6933. {
  6934. struct niu_parent *p, *tmp;
  6935. int port = np->port;
  6936. niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
  6937. ptype, port);
  6938. mutex_lock(&niu_parent_lock);
  6939. p = NULL;
  6940. list_for_each_entry(tmp, &niu_parent_list, list) {
  6941. if (!memcmp(id, &tmp->id, sizeof(*id))) {
  6942. p = tmp;
  6943. break;
  6944. }
  6945. }
  6946. if (!p)
  6947. p = niu_new_parent(np, id, ptype);
  6948. if (p) {
  6949. char port_name[6];
  6950. int err;
  6951. sprintf(port_name, "port%d", port);
  6952. err = sysfs_create_link(&p->plat_dev->dev.kobj,
  6953. &np->device->kobj,
  6954. port_name);
  6955. if (!err) {
  6956. p->ports[port] = np;
  6957. atomic_inc(&p->refcnt);
  6958. }
  6959. }
  6960. mutex_unlock(&niu_parent_lock);
  6961. return p;
  6962. }
  6963. static void niu_put_parent(struct niu *np)
  6964. {
  6965. struct niu_parent *p = np->parent;
  6966. u8 port = np->port;
  6967. char port_name[6];
  6968. BUG_ON(!p || p->ports[port] != np);
  6969. niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
  6970. sprintf(port_name, "port%d", port);
  6971. mutex_lock(&niu_parent_lock);
  6972. sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
  6973. p->ports[port] = NULL;
  6974. np->parent = NULL;
  6975. if (atomic_dec_and_test(&p->refcnt)) {
  6976. list_del(&p->list);
  6977. platform_device_unregister(p->plat_dev);
  6978. }
  6979. mutex_unlock(&niu_parent_lock);
  6980. }
  6981. static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
  6982. u64 *handle, gfp_t flag)
  6983. {
  6984. dma_addr_t dh;
  6985. void *ret;
  6986. ret = dma_alloc_coherent(dev, size, &dh, flag);
  6987. if (ret)
  6988. *handle = dh;
  6989. return ret;
  6990. }
  6991. static void niu_pci_free_coherent(struct device *dev, size_t size,
  6992. void *cpu_addr, u64 handle)
  6993. {
  6994. dma_free_coherent(dev, size, cpu_addr, handle);
  6995. }
  6996. static u64 niu_pci_map_page(struct device *dev, struct page *page,
  6997. unsigned long offset, size_t size,
  6998. enum dma_data_direction direction)
  6999. {
  7000. return dma_map_page(dev, page, offset, size, direction);
  7001. }
  7002. static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
  7003. size_t size, enum dma_data_direction direction)
  7004. {
  7005. return dma_unmap_page(dev, dma_address, size, direction);
  7006. }
  7007. static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
  7008. size_t size,
  7009. enum dma_data_direction direction)
  7010. {
  7011. return dma_map_single(dev, cpu_addr, size, direction);
  7012. }
  7013. static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
  7014. size_t size,
  7015. enum dma_data_direction direction)
  7016. {
  7017. dma_unmap_single(dev, dma_address, size, direction);
  7018. }
  7019. static const struct niu_ops niu_pci_ops = {
  7020. .alloc_coherent = niu_pci_alloc_coherent,
  7021. .free_coherent = niu_pci_free_coherent,
  7022. .map_page = niu_pci_map_page,
  7023. .unmap_page = niu_pci_unmap_page,
  7024. .map_single = niu_pci_map_single,
  7025. .unmap_single = niu_pci_unmap_single,
  7026. };
  7027. static void __devinit niu_driver_version(void)
  7028. {
  7029. static int niu_version_printed;
  7030. if (niu_version_printed++ == 0)
  7031. pr_info("%s", version);
  7032. }
  7033. static struct net_device * __devinit niu_alloc_and_init(
  7034. struct device *gen_dev, struct pci_dev *pdev,
  7035. struct of_device *op, const struct niu_ops *ops,
  7036. u8 port)
  7037. {
  7038. struct net_device *dev;
  7039. struct niu *np;
  7040. dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
  7041. if (!dev) {
  7042. dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
  7043. return NULL;
  7044. }
  7045. SET_NETDEV_DEV(dev, gen_dev);
  7046. np = netdev_priv(dev);
  7047. np->dev = dev;
  7048. np->pdev = pdev;
  7049. np->op = op;
  7050. np->device = gen_dev;
  7051. np->ops = ops;
  7052. np->msg_enable = niu_debug;
  7053. spin_lock_init(&np->lock);
  7054. INIT_WORK(&np->reset_task, niu_reset_task);
  7055. np->port = port;
  7056. return dev;
  7057. }
  7058. static void __devinit niu_assign_netdev_ops(struct net_device *dev)
  7059. {
  7060. dev->open = niu_open;
  7061. dev->stop = niu_close;
  7062. dev->get_stats = niu_get_stats;
  7063. dev->set_multicast_list = niu_set_rx_mode;
  7064. dev->set_mac_address = niu_set_mac_addr;
  7065. dev->do_ioctl = niu_ioctl;
  7066. dev->tx_timeout = niu_tx_timeout;
  7067. dev->hard_start_xmit = niu_start_xmit;
  7068. dev->ethtool_ops = &niu_ethtool_ops;
  7069. dev->watchdog_timeo = NIU_TX_TIMEOUT;
  7070. dev->change_mtu = niu_change_mtu;
  7071. }
  7072. static void __devinit niu_device_announce(struct niu *np)
  7073. {
  7074. struct net_device *dev = np->dev;
  7075. DECLARE_MAC_BUF(mac);
  7076. pr_info("%s: NIU Ethernet %s\n",
  7077. dev->name, print_mac(mac, dev->dev_addr));
  7078. if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
  7079. pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
  7080. dev->name,
  7081. (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
  7082. (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
  7083. (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
  7084. (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
  7085. (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
  7086. np->vpd.phy_type);
  7087. } else {
  7088. pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
  7089. dev->name,
  7090. (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
  7091. (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
  7092. (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"),
  7093. (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
  7094. (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
  7095. np->vpd.phy_type);
  7096. }
  7097. }
  7098. static int __devinit niu_pci_init_one(struct pci_dev *pdev,
  7099. const struct pci_device_id *ent)
  7100. {
  7101. unsigned long niureg_base, niureg_len;
  7102. union niu_parent_id parent_id;
  7103. struct net_device *dev;
  7104. struct niu *np;
  7105. int err, pos;
  7106. u64 dma_mask;
  7107. u16 val16;
  7108. niu_driver_version();
  7109. err = pci_enable_device(pdev);
  7110. if (err) {
  7111. dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
  7112. "aborting.\n");
  7113. return err;
  7114. }
  7115. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  7116. !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  7117. dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
  7118. "base addresses, aborting.\n");
  7119. err = -ENODEV;
  7120. goto err_out_disable_pdev;
  7121. }
  7122. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  7123. if (err) {
  7124. dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
  7125. "aborting.\n");
  7126. goto err_out_disable_pdev;
  7127. }
  7128. pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
  7129. if (pos <= 0) {
  7130. dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
  7131. "aborting.\n");
  7132. goto err_out_free_res;
  7133. }
  7134. dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
  7135. &niu_pci_ops, PCI_FUNC(pdev->devfn));
  7136. if (!dev) {
  7137. err = -ENOMEM;
  7138. goto err_out_free_res;
  7139. }
  7140. np = netdev_priv(dev);
  7141. memset(&parent_id, 0, sizeof(parent_id));
  7142. parent_id.pci.domain = pci_domain_nr(pdev->bus);
  7143. parent_id.pci.bus = pdev->bus->number;
  7144. parent_id.pci.device = PCI_SLOT(pdev->devfn);
  7145. np->parent = niu_get_parent(np, &parent_id,
  7146. PLAT_TYPE_ATLAS);
  7147. if (!np->parent) {
  7148. err = -ENOMEM;
  7149. goto err_out_free_dev;
  7150. }
  7151. pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
  7152. val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
  7153. val16 |= (PCI_EXP_DEVCTL_CERE |
  7154. PCI_EXP_DEVCTL_NFERE |
  7155. PCI_EXP_DEVCTL_FERE |
  7156. PCI_EXP_DEVCTL_URRE |
  7157. PCI_EXP_DEVCTL_RELAX_EN);
  7158. pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
  7159. dma_mask = DMA_44BIT_MASK;
  7160. err = pci_set_dma_mask(pdev, dma_mask);
  7161. if (!err) {
  7162. dev->features |= NETIF_F_HIGHDMA;
  7163. err = pci_set_consistent_dma_mask(pdev, dma_mask);
  7164. if (err) {
  7165. dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
  7166. "DMA for consistent allocations, "
  7167. "aborting.\n");
  7168. goto err_out_release_parent;
  7169. }
  7170. }
  7171. if (err || dma_mask == DMA_32BIT_MASK) {
  7172. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  7173. if (err) {
  7174. dev_err(&pdev->dev, PFX "No usable DMA configuration, "
  7175. "aborting.\n");
  7176. goto err_out_release_parent;
  7177. }
  7178. }
  7179. dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
  7180. niureg_base = pci_resource_start(pdev, 0);
  7181. niureg_len = pci_resource_len(pdev, 0);
  7182. np->regs = ioremap_nocache(niureg_base, niureg_len);
  7183. if (!np->regs) {
  7184. dev_err(&pdev->dev, PFX "Cannot map device registers, "
  7185. "aborting.\n");
  7186. err = -ENOMEM;
  7187. goto err_out_release_parent;
  7188. }
  7189. pci_set_master(pdev);
  7190. pci_save_state(pdev);
  7191. dev->irq = pdev->irq;
  7192. niu_assign_netdev_ops(dev);
  7193. err = niu_get_invariants(np);
  7194. if (err) {
  7195. if (err != -ENODEV)
  7196. dev_err(&pdev->dev, PFX "Problem fetching invariants "
  7197. "of chip, aborting.\n");
  7198. goto err_out_iounmap;
  7199. }
  7200. err = register_netdev(dev);
  7201. if (err) {
  7202. dev_err(&pdev->dev, PFX "Cannot register net device, "
  7203. "aborting.\n");
  7204. goto err_out_iounmap;
  7205. }
  7206. pci_set_drvdata(pdev, dev);
  7207. niu_device_announce(np);
  7208. return 0;
  7209. err_out_iounmap:
  7210. if (np->regs) {
  7211. iounmap(np->regs);
  7212. np->regs = NULL;
  7213. }
  7214. err_out_release_parent:
  7215. niu_put_parent(np);
  7216. err_out_free_dev:
  7217. free_netdev(dev);
  7218. err_out_free_res:
  7219. pci_release_regions(pdev);
  7220. err_out_disable_pdev:
  7221. pci_disable_device(pdev);
  7222. pci_set_drvdata(pdev, NULL);
  7223. return err;
  7224. }
  7225. static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
  7226. {
  7227. struct net_device *dev = pci_get_drvdata(pdev);
  7228. if (dev) {
  7229. struct niu *np = netdev_priv(dev);
  7230. unregister_netdev(dev);
  7231. if (np->regs) {
  7232. iounmap(np->regs);
  7233. np->regs = NULL;
  7234. }
  7235. niu_ldg_free(np);
  7236. niu_put_parent(np);
  7237. free_netdev(dev);
  7238. pci_release_regions(pdev);
  7239. pci_disable_device(pdev);
  7240. pci_set_drvdata(pdev, NULL);
  7241. }
  7242. }
  7243. static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
  7244. {
  7245. struct net_device *dev = pci_get_drvdata(pdev);
  7246. struct niu *np = netdev_priv(dev);
  7247. unsigned long flags;
  7248. if (!netif_running(dev))
  7249. return 0;
  7250. flush_scheduled_work();
  7251. niu_netif_stop(np);
  7252. del_timer_sync(&np->timer);
  7253. spin_lock_irqsave(&np->lock, flags);
  7254. niu_enable_interrupts(np, 0);
  7255. spin_unlock_irqrestore(&np->lock, flags);
  7256. netif_device_detach(dev);
  7257. spin_lock_irqsave(&np->lock, flags);
  7258. niu_stop_hw(np);
  7259. spin_unlock_irqrestore(&np->lock, flags);
  7260. pci_save_state(pdev);
  7261. return 0;
  7262. }
  7263. static int niu_resume(struct pci_dev *pdev)
  7264. {
  7265. struct net_device *dev = pci_get_drvdata(pdev);
  7266. struct niu *np = netdev_priv(dev);
  7267. unsigned long flags;
  7268. int err;
  7269. if (!netif_running(dev))
  7270. return 0;
  7271. pci_restore_state(pdev);
  7272. netif_device_attach(dev);
  7273. spin_lock_irqsave(&np->lock, flags);
  7274. err = niu_init_hw(np);
  7275. if (!err) {
  7276. np->timer.expires = jiffies + HZ;
  7277. add_timer(&np->timer);
  7278. niu_netif_start(np);
  7279. }
  7280. spin_unlock_irqrestore(&np->lock, flags);
  7281. return err;
  7282. }
  7283. static struct pci_driver niu_pci_driver = {
  7284. .name = DRV_MODULE_NAME,
  7285. .id_table = niu_pci_tbl,
  7286. .probe = niu_pci_init_one,
  7287. .remove = __devexit_p(niu_pci_remove_one),
  7288. .suspend = niu_suspend,
  7289. .resume = niu_resume,
  7290. };
  7291. #ifdef CONFIG_SPARC64
  7292. static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
  7293. u64 *dma_addr, gfp_t flag)
  7294. {
  7295. unsigned long order = get_order(size);
  7296. unsigned long page = __get_free_pages(flag, order);
  7297. if (page == 0UL)
  7298. return NULL;
  7299. memset((char *)page, 0, PAGE_SIZE << order);
  7300. *dma_addr = __pa(page);
  7301. return (void *) page;
  7302. }
  7303. static void niu_phys_free_coherent(struct device *dev, size_t size,
  7304. void *cpu_addr, u64 handle)
  7305. {
  7306. unsigned long order = get_order(size);
  7307. free_pages((unsigned long) cpu_addr, order);
  7308. }
  7309. static u64 niu_phys_map_page(struct device *dev, struct page *page,
  7310. unsigned long offset, size_t size,
  7311. enum dma_data_direction direction)
  7312. {
  7313. return page_to_phys(page) + offset;
  7314. }
  7315. static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
  7316. size_t size, enum dma_data_direction direction)
  7317. {
  7318. /* Nothing to do. */
  7319. }
  7320. static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
  7321. size_t size,
  7322. enum dma_data_direction direction)
  7323. {
  7324. return __pa(cpu_addr);
  7325. }
  7326. static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
  7327. size_t size,
  7328. enum dma_data_direction direction)
  7329. {
  7330. /* Nothing to do. */
  7331. }
  7332. static const struct niu_ops niu_phys_ops = {
  7333. .alloc_coherent = niu_phys_alloc_coherent,
  7334. .free_coherent = niu_phys_free_coherent,
  7335. .map_page = niu_phys_map_page,
  7336. .unmap_page = niu_phys_unmap_page,
  7337. .map_single = niu_phys_map_single,
  7338. .unmap_single = niu_phys_unmap_single,
  7339. };
  7340. static unsigned long res_size(struct resource *r)
  7341. {
  7342. return r->end - r->start + 1UL;
  7343. }
  7344. static int __devinit niu_of_probe(struct of_device *op,
  7345. const struct of_device_id *match)
  7346. {
  7347. union niu_parent_id parent_id;
  7348. struct net_device *dev;
  7349. struct niu *np;
  7350. const u32 *reg;
  7351. int err;
  7352. niu_driver_version();
  7353. reg = of_get_property(op->node, "reg", NULL);
  7354. if (!reg) {
  7355. dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
  7356. op->node->full_name);
  7357. return -ENODEV;
  7358. }
  7359. dev = niu_alloc_and_init(&op->dev, NULL, op,
  7360. &niu_phys_ops, reg[0] & 0x1);
  7361. if (!dev) {
  7362. err = -ENOMEM;
  7363. goto err_out;
  7364. }
  7365. np = netdev_priv(dev);
  7366. memset(&parent_id, 0, sizeof(parent_id));
  7367. parent_id.of = of_get_parent(op->node);
  7368. np->parent = niu_get_parent(np, &parent_id,
  7369. PLAT_TYPE_NIU);
  7370. if (!np->parent) {
  7371. err = -ENOMEM;
  7372. goto err_out_free_dev;
  7373. }
  7374. dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
  7375. np->regs = of_ioremap(&op->resource[1], 0,
  7376. res_size(&op->resource[1]),
  7377. "niu regs");
  7378. if (!np->regs) {
  7379. dev_err(&op->dev, PFX "Cannot map device registers, "
  7380. "aborting.\n");
  7381. err = -ENOMEM;
  7382. goto err_out_release_parent;
  7383. }
  7384. np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
  7385. res_size(&op->resource[2]),
  7386. "niu vregs-1");
  7387. if (!np->vir_regs_1) {
  7388. dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
  7389. "aborting.\n");
  7390. err = -ENOMEM;
  7391. goto err_out_iounmap;
  7392. }
  7393. np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
  7394. res_size(&op->resource[3]),
  7395. "niu vregs-2");
  7396. if (!np->vir_regs_2) {
  7397. dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
  7398. "aborting.\n");
  7399. err = -ENOMEM;
  7400. goto err_out_iounmap;
  7401. }
  7402. niu_assign_netdev_ops(dev);
  7403. err = niu_get_invariants(np);
  7404. if (err) {
  7405. if (err != -ENODEV)
  7406. dev_err(&op->dev, PFX "Problem fetching invariants "
  7407. "of chip, aborting.\n");
  7408. goto err_out_iounmap;
  7409. }
  7410. err = register_netdev(dev);
  7411. if (err) {
  7412. dev_err(&op->dev, PFX "Cannot register net device, "
  7413. "aborting.\n");
  7414. goto err_out_iounmap;
  7415. }
  7416. dev_set_drvdata(&op->dev, dev);
  7417. niu_device_announce(np);
  7418. return 0;
  7419. err_out_iounmap:
  7420. if (np->vir_regs_1) {
  7421. of_iounmap(&op->resource[2], np->vir_regs_1,
  7422. res_size(&op->resource[2]));
  7423. np->vir_regs_1 = NULL;
  7424. }
  7425. if (np->vir_regs_2) {
  7426. of_iounmap(&op->resource[3], np->vir_regs_2,
  7427. res_size(&op->resource[3]));
  7428. np->vir_regs_2 = NULL;
  7429. }
  7430. if (np->regs) {
  7431. of_iounmap(&op->resource[1], np->regs,
  7432. res_size(&op->resource[1]));
  7433. np->regs = NULL;
  7434. }
  7435. err_out_release_parent:
  7436. niu_put_parent(np);
  7437. err_out_free_dev:
  7438. free_netdev(dev);
  7439. err_out:
  7440. return err;
  7441. }
  7442. static int __devexit niu_of_remove(struct of_device *op)
  7443. {
  7444. struct net_device *dev = dev_get_drvdata(&op->dev);
  7445. if (dev) {
  7446. struct niu *np = netdev_priv(dev);
  7447. unregister_netdev(dev);
  7448. if (np->vir_regs_1) {
  7449. of_iounmap(&op->resource[2], np->vir_regs_1,
  7450. res_size(&op->resource[2]));
  7451. np->vir_regs_1 = NULL;
  7452. }
  7453. if (np->vir_regs_2) {
  7454. of_iounmap(&op->resource[3], np->vir_regs_2,
  7455. res_size(&op->resource[3]));
  7456. np->vir_regs_2 = NULL;
  7457. }
  7458. if (np->regs) {
  7459. of_iounmap(&op->resource[1], np->regs,
  7460. res_size(&op->resource[1]));
  7461. np->regs = NULL;
  7462. }
  7463. niu_ldg_free(np);
  7464. niu_put_parent(np);
  7465. free_netdev(dev);
  7466. dev_set_drvdata(&op->dev, NULL);
  7467. }
  7468. return 0;
  7469. }
  7470. static struct of_device_id niu_match[] = {
  7471. {
  7472. .name = "network",
  7473. .compatible = "SUNW,niusl",
  7474. },
  7475. {},
  7476. };
  7477. MODULE_DEVICE_TABLE(of, niu_match);
  7478. static struct of_platform_driver niu_of_driver = {
  7479. .name = "niu",
  7480. .match_table = niu_match,
  7481. .probe = niu_of_probe,
  7482. .remove = __devexit_p(niu_of_remove),
  7483. };
  7484. #endif /* CONFIG_SPARC64 */
  7485. static int __init niu_init(void)
  7486. {
  7487. int err = 0;
  7488. BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
  7489. niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
  7490. #ifdef CONFIG_SPARC64
  7491. err = of_register_driver(&niu_of_driver, &of_bus_type);
  7492. #endif
  7493. if (!err) {
  7494. err = pci_register_driver(&niu_pci_driver);
  7495. #ifdef CONFIG_SPARC64
  7496. if (err)
  7497. of_unregister_driver(&niu_of_driver);
  7498. #endif
  7499. }
  7500. return err;
  7501. }
  7502. static void __exit niu_exit(void)
  7503. {
  7504. pci_unregister_driver(&niu_pci_driver);
  7505. #ifdef CONFIG_SPARC64
  7506. of_unregister_driver(&niu_of_driver);
  7507. #endif
  7508. }
  7509. module_init(niu_init);
  7510. module_exit(niu_exit);